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GET /api/1.0/patches/11445/?format=api
{ "id": 11445, "url": "http://patchwork.dpdk.org/api/1.0/patches/11445/?format=api", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/1.0/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk" }, "msgid": "<1457658611-1035-2-git-send-email-wenzhuo.lu@intel.com>", "date": "2016-03-11T01:10:07", "name": "[dpdk-dev,v8,1/5] ixgbe: select pool by MAC when using double VLAN", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6a4e444b27e63c387ef51cd05495db493e2ac01e", "submitter": { "id": 258, "url": "http://patchwork.dpdk.org/api/1.0/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/1.0/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1457658611-1035-2-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [], "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/11445/checks/", "tags": {}, "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 885105424;\n\tFri, 11 Mar 2016 02:10:22 +0100 (CET)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id E6B4D275D\n\tfor <dev@dpdk.org>; Fri, 11 Mar 2016 02:10:18 +0100 (CET)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga101.fm.intel.com with ESMTP; 10 Mar 2016 17:10:18 -0800", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby FMSMGA003.fm.intel.com with ESMTP; 10 Mar 2016 17:10:19 -0800", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id u2B1AGJi029277;\n\tFri, 11 Mar 2016 09:10:16 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid u2B1ADhk001102; Fri, 11 Mar 2016 09:10:15 +0800", "(from wenzhuol@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u2B1ADrV001098; \n\tFri, 11 Mar 2016 09:10:13 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.24,318,1455004800\"; d=\"scan'208\";a=\"667411324\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 11 Mar 2016 09:10:07 +0800", "Message-Id": "<1457658611-1035-2-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1457658611-1035-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1454051035-25757-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1457658611-1035-1-git-send-email-wenzhuo.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH v8 1/5] ixgbe: select pool by MAC when using\n\tdouble VLAN", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "On X550, as required by datasheet, E-tag packets are not expected\nwhen double VLAN are used. So modify the register PFVTCTL after\nenabling double VLAN to select pool by MAC but not MAC or E-tag.\n\nAn introduction of E-tag:\nIt's defined in IEEE802.1br. Please reference this website,\nhttp://www.ieee802.org/1/pages/802.1br.html.\n\nA brief description.\nE-tag means external tag, and it's a kind of l2 tunnel. It means a\ntag will be inserted in the l2 header. Like below,\n |31 24|23 16|15 8|7 0|\n 0| Destination MAC address |\n 4| Dest MAC address(cont.) | Src MAC address |\n 8| Source MAC address(cont.) |\n 12| E-tag Etherenet type (0x893f) | E-tag header |\n 16| E-tag header(cont.) |\n 20| VLAN Ethertype(optional) | VLAN header(optional) |\n 24| Original type | ...... |\n...| ...... |\nThe E-tag format is like below,\n |0 15|16 18|19 |20 31|\n | Ethertype - 0x893f | E-PCP |DEI| Ingress E-CID_base |\n\n |32 33|34 35|36 47|48 55 |56 63|\n | RSV | GRP |E-CID_base|Ingress_E-CID_ext| E-CID_ext |\n\nThe Ingess_E-CID_ext and E-CID_ext are always zero for endpoints\nand are effectively reserved.\n\nThe more details of E-tag is in IEEE 802.1BR. 802.1BR is used to\nreplace 802.1Qbh. 802.1BR is a standard for Bridge Port Extension.\nIt specifies the operation of Bridge Port Extenders, including\nmanagement, protocols, and algorithms. Bridge Port Extenders\noperate in support of the MAC Service by Extended Bridges.\nThe E-tag is added to l2 header to identify the VM channel and\nthe virtual port.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\nAcked-by: Shaopeng He <shaopeng.he@intel.com>\nAcked-by: Jingjing Wu <jingjing.wu@intel.com>\nTested-by: Yong Liu <yong.liu@intel.com>\n---\n drivers/net/ixgbe/ixgbe_ethdev.c | 10 ++++++++++\n 1 file changed, 10 insertions(+)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c\nindex 3e6fe86..b99e48e 100644\n--- a/drivers/net/ixgbe/ixgbe_ethdev.c\n+++ b/drivers/net/ixgbe/ixgbe_ethdev.c\n@@ -138,6 +138,8 @@\n \n #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL\n \n+#define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000\n+\n static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);\n static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);\n static int ixgbe_dev_configure(struct rte_eth_dev *dev);\n@@ -1725,6 +1727,14 @@ ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)\n \tctrl |= IXGBE_EXTENDED_VLAN;\n \tIXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);\n \n+\t/* Clear pooling mode of PFVTCTL. It's required by X550. */\n+\tif (hw->mac.type == ixgbe_mac_X550 ||\n+\t hw->mac.type == ixgbe_mac_X550EM_x) {\n+\t\tctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);\n+\t\tctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);\n+\t}\n+\n \t/*\n \t * VET EXT field in the EXVET register = 0x8100 by default\n \t * So no need to change. Same to VT field of DMATXCTL register\n", "prefixes": [ "dpdk-dev", "v8", "1/5" ] }