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{ "id": 116663, "url": "http://patchwork.dpdk.org/api/covers/116663/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/cover/20220922190345.394-1-valex@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220922190345.394-1-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220922190345.394-1-valex@nvidia.com", "date": "2022-09-22T19:03:25", "name": "[v1,00/19] net/mlx5: Add HW steering low level support", "submitter": { "id": 2858, "url": "http://patchwork.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/cover/20220922190345.394-1-valex@nvidia.com/mbox/", "series": [ { "id": 24786, "url": "http://patchwork.dpdk.org/api/series/24786/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=24786", "date": "2022-09-22T19:03:25", "name": "net/mlx5: Add HW steering low level support", "version": 1, "mbox": "http://patchwork.dpdk.org/series/24786/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/covers/116663/comments/", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8BDA6A0543;\n\tThu, 22 Sep 2022 21:04:53 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7A50440156;\n\tThu, 22 Sep 2022 21:04:53 +0200 (CEST)", "from NAM04-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam04on2065.outbound.protection.outlook.com [40.107.102.65])\n by mails.dpdk.org (Postfix) with ESMTP id 445C5400D7\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <erezsh@nvidia.com>,\n <thomas@monjalon.net>, <suanmingm@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v1 00/19] net/mlx5: Add HW steering low level support", "Date": "Thu, 22 Sep 2022 22:03:25 +0300", "Message-ID": "<20220922190345.394-1-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT082:EE_|BY5PR12MB4936:EE_", "X-MS-Office365-Filtering-Correlation-Id": "05f38cc1-42e9-4690-f5a9-08da9ccd5228", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n +mt/EbZFcBJeroejgXDdKXExaX+W2EcTWiOrHS8SqtAfR3u92BWLseHdtoLf77x1NAAySw2wjmDREKYGlo6ecLTA4q/pZVdVx002iZ/xySQSRn/ucEBxGf5Uhzz96kKlEC9dBpwPoZPZZN3f1/DKSDXE0m3lrpuPUMdoBTKPkLXky3mh/zW19yPmkzYeyoOPrQG9JHSd6qFz9jMYb4Ef6VZ33KPJZqJUBLLb/MIxw65/F9sBwNwdj32iGaq7UDNud57flI4gmmwmAPUlW/YALrvRobGu69k4PQelvC16eUYJXdQo1PN/S5DGBvopjorRAHrYWAGiG1ce6VbiRo/MunFQtVf6GKlUItyWKm83PPqYuAxtNzjvzuJAbYHMlSnUQ3o3A0g61sW4eopifF6I/NDPsto5hCfTYNsJeCpLygDhAwMtlnpBboKNn1yUc2K+UFJ1h1ABNB+KFGayvthsAg6yHRNZjeShUPpD/ebYhUmqbUNr7XJUY4ioJxNdruq2vrOSmvbjfi3GZbWG4RImSnh5wrhEe6oiU9FAFGpzle5jJAKUzXN6GRwkmZDUgXI9sdWurs40im1bBBFbhz4snzRbWeshsV0p9gTfwjcLkwiAmAvtzkhfkZAkFp+zqHRA89/EDGi9YKiIjOd0l85BmY8v/ItbdCaVBcTFTRIOc0nE3E6RAxIPgXCZuTsIiQp88UyQva8Mrf/dHkqQMhvO/widw8XbS+FpGA2nRMCfZsB5paxIcHDr2Dl8TO/A7KfF+RsI3jzbTqE+/6tbk3Hd1g==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT082.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB4936", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Mellanox ConnetX devices supports packet matching, packet modification and\nredirection. These functionalities are also referred to as flow-steering.\nTo configure a steering rule, the rule is written to the device owned\nmemory, this memory is accessed and cached by the device when processing\na packet.\n\nThe highlight of this patchset is supporting HW Steering (HWS) which\nis the new technology supported in new ConnectX devices, HWS allows\nconfiguring steering rules directly to the HW using special HW queues\nwith minimal CPU effort.\n\nThis patchset is the internal low layer implementation for HWS used by\nthe mlx5 PMD. The mlx5dr (direct rule) is layer that bridges between the\nPMD and the HW by configuring the HW offloads based on the PMD logic\n\nThis is the initial draft to present the code to the community and it will\nbe reworked.\n\nAlex Vesker (13):\n net/mlx5: Add additional glue functions for HWS\n net/mlx5: Remove stub HWS support\n net/mlx5/hws: Add HWS command layer\n net/mlx5/hws: Add HWS pool and buddy\n net/mlx5/hws: Add HWS send layer\n net/mlx5/hws: Add HWS definer layer\n net/mlx5/hws: Add HWS context object\n net/mlx5/hws: Add HWS table object\n net/mlx5/hws: Add HWS matcher object\n net/mlx5/hws: Add HWS rule object\n net/mlx5/hws: Add HWS action object\n net/mlx5/hws: Add HWS debug layer\n net/mlx5/hws: Enable HWS\n\nBing Zhao (2):\n common/mlx5: query set capability of registers\n net/mlx5: provide the available tag registers\n\nDariusz Sosnowski (1):\n net/mlx5: add port to metadata conversion\n\nSuanming Mou (3):\n net/mlx5: split flow item translation\n net/mlx5: split flow item matcher and value translation\n net/mlx5: add hardware steering item translation function\n\n drivers/common/mlx5/linux/mlx5_glue.c | 121 +-\n drivers/common/mlx5/linux/mlx5_glue.h | 17 +\n drivers/common/mlx5/mlx5_devx_cmds.c | 30 +\n drivers/common/mlx5/mlx5_devx_cmds.h | 2 +\n drivers/common/mlx5/mlx5_prm.h | 653 ++++-\n drivers/net/mlx5/hws/meson.build | 18 +\n drivers/net/mlx5/{mlx5_dr.h => hws/mlx5dr.h} | 210 +-\n drivers/net/mlx5/hws/mlx5dr_action.c | 2217 +++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_action.h | 251 ++\n drivers/net/mlx5/hws/mlx5dr_buddy.c | 201 ++\n drivers/net/mlx5/hws/mlx5dr_buddy.h | 18 +\n drivers/net/mlx5/hws/mlx5dr_cmd.c | 957 +++++++\n drivers/net/mlx5/hws/mlx5dr_cmd.h | 232 ++\n drivers/net/mlx5/hws/mlx5dr_context.c | 222 ++\n drivers/net/mlx5/hws/mlx5dr_context.h | 40 +\n drivers/net/mlx5/hws/mlx5dr_debug.c | 459 ++++\n drivers/net/mlx5/hws/mlx5dr_debug.h | 28 +\n drivers/net/mlx5/hws/mlx5dr_definer.c | 1866 +++++++++++++\n drivers/net/mlx5/hws/mlx5dr_definer.h | 582 ++++\n drivers/net/mlx5/hws/mlx5dr_internal.h | 93 +\n drivers/net/mlx5/hws/mlx5dr_matcher.c | 920 +++++++\n drivers/net/mlx5/hws/mlx5dr_matcher.h | 76 +\n drivers/net/mlx5/hws/mlx5dr_pat_arg.c | 511 ++++\n drivers/net/mlx5/hws/mlx5dr_pat_arg.h | 76 +\n drivers/net/mlx5/hws/mlx5dr_pool.c | 672 +++++\n drivers/net/mlx5/hws/mlx5dr_pool.h | 152 +\n drivers/net/mlx5/hws/mlx5dr_rule.c | 528 ++++\n drivers/net/mlx5/hws/mlx5dr_rule.h | 50 +\n drivers/net/mlx5/hws/mlx5dr_send.c | 849 ++++++\n drivers/net/mlx5/hws/mlx5dr_send.h | 273 ++\n drivers/net/mlx5/hws/mlx5dr_table.c | 248 ++\n drivers/net/mlx5/hws/mlx5dr_table.h | 44 +\n drivers/net/mlx5/linux/mlx5_os.c | 7 +-\n drivers/net/mlx5/meson.build | 2 +-\n drivers/net/mlx5/mlx5.c | 3 +\n drivers/net/mlx5/mlx5.h | 3 +-\n drivers/net/mlx5/mlx5_defs.h | 2 +\n drivers/net/mlx5/mlx5_dr.c | 383 ---\n drivers/net/mlx5/mlx5_flow.c | 17 +\n drivers/net/mlx5/mlx5_flow.h | 128 +\n drivers/net/mlx5/mlx5_flow_dv.c | 2599 +++++++++---------\n drivers/net/mlx5/mlx5_flow_hw.c | 109 +-\n 42 files changed, 14189 insertions(+), 1680 deletions(-)\n create mode 100644 drivers/net/mlx5/hws/meson.build\n rename drivers/net/mlx5/{mlx5_dr.h => hws/mlx5dr.h} (65%)\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_action.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_action.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_buddy.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_buddy.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_cmd.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_cmd.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_context.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_context.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_debug.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_debug.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_definer.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_definer.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_internal.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_matcher.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_matcher.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_pat_arg.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_pat_arg.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_pool.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_pool.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_rule.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_rule.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_send.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_send.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_table.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_table.h\n delete mode 100644 drivers/net/mlx5/mlx5_dr.c" }