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{ "id": 118580, "url": "http://patchwork.dpdk.org/api/covers/118580/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/cover/20221019144258.16282-1-valex@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221019144258.16282-1-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221019144258.16282-1-valex@nvidia.com", "date": "2022-10-19T14:42:40", "name": "[v4,00/18] net/mlx5: Add HW steering low level support", "submitter": { "id": 2858, "url": "http://patchwork.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/cover/20221019144258.16282-1-valex@nvidia.com/mbox/", "series": [ { "id": 25310, "url": "http://patchwork.dpdk.org/api/series/25310/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25310", "date": "2022-10-19T14:42:40", "name": "net/mlx5: Add HW steering low level support", "version": 4, "mbox": "http://patchwork.dpdk.org/series/25310/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/covers/118580/comments/", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E9141A06CC;\n\tWed, 19 Oct 2022 16:43:27 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 955B142BB3;\n\tWed, 19 Oct 2022 16:43:27 +0200 (CEST)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2057.outbound.protection.outlook.com [40.107.94.57])\n by mails.dpdk.org (Postfix) with ESMTP id 6275442BB1\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=none (sender ip is\n 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=fail (p=reject sp=reject pct=100) action=oreject\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=+F3790x6yGxOeaV/ishIT4h49QTVxREFxululm6pq6Q=;\n b=AaRsjNtjid2i81sOfc3BP9dJCy53SsutZ25jb6J1lpqjRiIrOisBOqGY76H8Rxk/KrkgonqFs88aPrP6af27QWqKpQbUpIdT+r3WBHm4Can7YXn+NJRS7knXqK2UFAHFzxSe5T2L0xWBtkkQzNB/I3CwLGtur1BFtWfjgb2RSxykT+OjTCSTpS6RytPU0ZGR8ezeZqFuXgZRWqFNzwVLmSGD6AeR342hX1ZWpKF2DmVyy4hk48qg6y22q0OsRZd04zuwzS9f5GPuEOJb6xdjW3PS7lpovNwvju2iP7CE2p7mo9v5C4ggeEEqfWP3HWbVnZtBvMvQCAeGcubwx9zCsw==", "X-MS-Exchange-Authentication-Results": "spf=none (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=fail action=oreject header.from=nvidia.com;", "Received-SPF": "None (protection.outlook.com: nvidia.com does not designate\n permitted sender hosts)", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v4 00/18] net/mlx5: Add HW steering low level support", "Date": "Wed, 19 Oct 2022 17:42:40 +0300", "Message-ID": "<20221019144258.16282-1-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220922190345.394-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT052:EE_|BL3PR12MB6475:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d166f557-d7d6-4a79-b655-08dab1e04631", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n rT7rnZEtfaYHzVbCkPoEBYzTJQ293TG5yKP47XPQzyAfIRphkfyLjwIUJQDellq8XuTv8NWrYY3E4jd9u2Xa0ZjoCZ/P2dTmEFU1XFrFSvxRwa+4csOaomYPpz4h9UFq0DlcgbWRqSgTP2EcC8cTk/UKmwXBK8oirT7AP968FtBtkfZQVado7i8h+ZBz1a5EYgRIiA9FXDRsaV4luA85dy+wjx+TCFzILu6+BycudLEiullV7sZ2NG8cyPRweIZVY0Fo6m00mh8wXFoyFwVQIz/oEAbiYzf07GROg5cIcxVSq33MS+uQ5HuP5ZduKIt1JqY9Ceh1shDwoNvUkh0hvuLps7HG7suZ4cdEhpjbHZY0m+JCcwzSPWGhjN5VVSaqX1QFam9GLYU6cXfET/Ma4OcLPjP0DEUxAoQ3cLBppv9c4Ot4uBv/+QAbIGGyu2rpc+Cyd+hmoIunsUWAoAVamm9wDPkLvfi3YfAqYJB4vD6SI8MG/Qmx2XXY4r8OaX9ZSLTSnIbbkS7bITmfJWoc5oT4G72Hj9PFNdy4j8P4qqzEB/zCWCGikIHEkUuMlJZ0mos0bbVMRNLTsDYZ6JhQst22eCgXGCB3hoPmVe7z/uUYupb5nfg706HN+L/BeaZR/iU2TitmAcjucD79rXAKb3+NbbyzNAQpCpLTUk0VcHv5gxatBLBrPG8J32bS0wZVseNF8sEv79qbluRP5/QlmebIixZ4LTqrQeTbA4bgeoDqlRGQu49bWmVRIR0IYh7j2k3So0WhGrRcI38sGRXDfw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(39860400002)(346002)(376002)(136003)(396003)(451199015)(36840700001)(46966006)(40470700004)(316002)(54906003)(6636002)(110136005)(186003)(7696005)(2616005)(40460700003)(16526019)(2906002)(41300700001)(1076003)(36756003)(55016003)(26005)(5660300002)(8936002)(83380400001)(426003)(8676002)(86362001)(70586007)(6666004)(47076005)(70206006)(6286002)(4326008)(107886003)(336012)(82310400005)(356005)(7636003)(82740400003)(40480700001)(478600001)(36860700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Oct 2022 14:43:23.2612 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d166f557-d7d6-4a79-b655-08dab1e04631", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT052.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL3PR12MB6475", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Mellanox ConnetX devices supports packet matching, packet modification and\nredirection. These functionalities are also referred to as flow-steering.\nTo configure a steering rule, the rule is written to the device owned\nmemory, this memory is accessed and cached by the device when processing\na packet.\n\nThe highlight of this patchset is supporting HW Steering (HWS) which\nis the new technology supported in new ConnectX devices, HWS allows\nconfiguring steering rules directly to the HW using special HW queues\nwith minimal CPU effort.\n\nThis patchset is the internal low layer implementation for HWS used by\nthe mlx5 PMD. The mlx5dr (direct rule) is layer that bridges between the\nPMD and the HW by configuring the HW offloads based on the PMD logic\n\nv2:\nFix check patch and cosmetic changes\n\nv3:\n-Fix unsupported items\n-Fix compilation with mlx5dv dependency\n\nv4:\n-Fix compile on Windows\n\nAlex Vesker (9):\n net/mlx5: Add additional glue functions for HWS\n net/mlx5/hws: Add HWS send layer\n net/mlx5/hws: Add HWS definer layer\n net/mlx5/hws: Add HWS context object\n net/mlx5/hws: Add HWS table object\n net/mlx5/hws: Add HWS matcher object\n net/mlx5/hws: Add HWS rule object\n net/mlx5/hws: Add HWS action object\n net/mlx5/hws: Enable HWS\n\nBing Zhao (2):\n common/mlx5: query set capability of registers\n net/mlx5: provide the available tag registers\n\nDariusz Sosnowski (1):\n net/mlx5: add port to metadata conversion\n\nErez Shitrit (2):\n net/mlx5/hws: Add HWS command layer\n net/mlx5/hws: Add HWS pool and buddy\n\nHamdan Igbaria (1):\n net/mlx5/hws: Add HWS debug layer\n\nSuanming Mou (3):\n net/mlx5: split flow item translation\n net/mlx5: split flow item matcher and value translation\n net/mlx5: add hardware steering item translation function\n\n doc/guides/nics/mlx5.rst | 5 +-\n doc/guides/rel_notes/release_22_11.rst | 4 +\n drivers/common/mlx5/linux/meson.build | 2 +\n drivers/common/mlx5/linux/mlx5_glue.c | 121 +-\n drivers/common/mlx5/linux/mlx5_glue.h | 17 +\n drivers/common/mlx5/mlx5_devx_cmds.c | 30 +\n drivers/common/mlx5/mlx5_devx_cmds.h | 2 +\n drivers/common/mlx5/mlx5_prm.h | 652 ++++-\n drivers/net/mlx5/hws/meson.build | 18 +\n drivers/net/mlx5/{mlx5_dr.h => hws/mlx5dr.h} | 209 +-\n drivers/net/mlx5/hws/mlx5dr_action.c | 2222 +++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_action.h | 253 ++\n drivers/net/mlx5/hws/mlx5dr_buddy.c | 201 ++\n drivers/net/mlx5/hws/mlx5dr_buddy.h | 22 +\n drivers/net/mlx5/hws/mlx5dr_cmd.c | 948 +++++++\n drivers/net/mlx5/hws/mlx5dr_cmd.h | 230 ++\n drivers/net/mlx5/hws/mlx5dr_context.c | 223 ++\n drivers/net/mlx5/hws/mlx5dr_context.h | 40 +\n drivers/net/mlx5/hws/mlx5dr_debug.c | 462 +++\n drivers/net/mlx5/hws/mlx5dr_debug.h | 28 +\n drivers/net/mlx5/hws/mlx5dr_definer.c | 1968 +++++++++++++\n drivers/net/mlx5/hws/mlx5dr_definer.h | 585 ++++\n drivers/net/mlx5/hws/mlx5dr_internal.h | 93 +\n drivers/net/mlx5/hws/mlx5dr_matcher.c | 922 ++++++\n drivers/net/mlx5/hws/mlx5dr_matcher.h | 76 +\n drivers/net/mlx5/hws/mlx5dr_pat_arg.c | 511 ++++\n drivers/net/mlx5/hws/mlx5dr_pat_arg.h | 83 +\n drivers/net/mlx5/hws/mlx5dr_pool.c | 672 +++++\n drivers/net/mlx5/hws/mlx5dr_pool.h | 152 +\n drivers/net/mlx5/hws/mlx5dr_rule.c | 528 ++++\n drivers/net/mlx5/hws/mlx5dr_rule.h | 50 +\n drivers/net/mlx5/hws/mlx5dr_send.c | 844 ++++++\n drivers/net/mlx5/hws/mlx5dr_send.h | 275 ++\n drivers/net/mlx5/hws/mlx5dr_table.c | 248 ++\n drivers/net/mlx5/hws/mlx5dr_table.h | 44 +\n drivers/net/mlx5/linux/mlx5_os.c | 12 +-\n drivers/net/mlx5/meson.build | 7 +-\n drivers/net/mlx5/mlx5.c | 9 +-\n drivers/net/mlx5/mlx5.h | 8 +-\n drivers/net/mlx5/mlx5_defs.h | 2 +\n drivers/net/mlx5/mlx5_devx.c | 2 +-\n drivers/net/mlx5/mlx5_dr.c | 383 ---\n drivers/net/mlx5/mlx5_flow.c | 29 +-\n drivers/net/mlx5/mlx5_flow.h | 174 +-\n drivers/net/mlx5/mlx5_flow_dv.c | 2631 +++++++++---------\n drivers/net/mlx5/mlx5_flow_hw.c | 115 +-\n 46 files changed, 14386 insertions(+), 1726 deletions(-)\n create mode 100644 drivers/net/mlx5/hws/meson.build\n rename drivers/net/mlx5/{mlx5_dr.h => hws/mlx5dr.h} (66%)\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_action.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_action.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_buddy.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_buddy.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_cmd.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_cmd.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_context.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_context.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_debug.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_debug.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_definer.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_definer.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_internal.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_matcher.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_matcher.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_pat_arg.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_pat_arg.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_pool.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_pool.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_rule.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_rule.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_send.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_send.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_table.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_table.h\n delete mode 100644 drivers/net/mlx5/mlx5_dr.c" }