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{ "id": 122779, "url": "http://patchwork.dpdk.org/api/covers/122779/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/cover/20230201072815.1329101-1-valex@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201072815.1329101-1-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201072815.1329101-1-valex@nvidia.com", "date": "2023-02-01T07:27:59", "name": "[v2,00/16] net/mlx5/hws: support range and partial hash matching", "submitter": { "id": 2858, "url": "http://patchwork.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/cover/20230201072815.1329101-1-valex@nvidia.com/mbox/", "series": [ { "id": 26726, "url": "http://patchwork.dpdk.org/api/series/26726/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=26726", "date": "2023-02-01T07:28:01", "name": "net/mlx5/hws: support range and partial hash matching", "version": 2, "mbox": "http://patchwork.dpdk.org/series/26726/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/covers/122779/comments/", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D90A241B9B;\n\tWed, 1 Feb 2023 08:28:59 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7D75A427E9;\n\tWed, 1 Feb 2023 08:28:57 +0100 (CET)", "from NAM02-SN1-obe.outbound.protection.outlook.com\n (mail-sn1nam02on2066.outbound.protection.outlook.com [40.107.96.66])\n by mails.dpdk.org (Postfix) with ESMTP id 570F541611\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>", "CC": "<matan@nvidia.com>, <dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v2 00/16] net/mlx5/hws: support range and partial hash matching", "Date": "Wed, 1 Feb 2023 09:27:59 +0200", "Message-ID": "<20230201072815.1329101-1-valex@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230131093346.1261066-1-valex@nvidia.com>", "References": "<20230131093346.1261066-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT068:EE_|PH8PR12MB6892:EE_", "X-MS-Office365-Filtering-Correlation-Id": "dc5f9a67-d142-4276-0de1-08db0425f8ff", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n PA+ztWY1vsjGrvNKkk0PtBhh0lsso7IAdRL4ZQ1GJf2b12r0sB3e21605P3AtEW2dy04FgnXP2ybYa5TtMq8GGcKVyU0PLw/PinIRqjNtVRgfow1rEjV/7fPqliNk43StJeC6gu2XjyjmssCSXhaxeI37rFK1RokTawzDKxCl63uaKA5hanRBx8ikTg1uuDcgnLMlGCDzDd2AR+UESQW20zAdO6agmyg0yQgnkowAAydSXrSSseNnOqiP6hv8U2B4UU0EroCVt86wiuN2DiPUXG3UV90Opu7B5zWh3/n4M1R8+/Zma0nrMwvCSUKOgHqILspfmp8/idu44e9joFKmY6xoskBC5AF+0AsplhT7Z6Xs2FPc3EN28GmWNrmTJ5HIMyXKtCOlSjpkDXngA5x1NLsSlv2XgkArkndaOGxapGW3rpA1givI3+d7hkYrfDXw4xo4iGD/Jb5xkssHj89LKYhJyts3Ipilvcmpe8cMznvR5u8Lx6gp38dNcKYqq2hBNtL6tH+CWlEJ/LtOeB0KsXkYv4b4YqK1FxvxylRGAyt/l9C5xoIXA8BAeBwihog3eS2OSEhcGYNIM5eRLNc5xXVk86UtXiDikFBi4tl8bYp1sz4OPRSAj6mKE8WpIMEH7Y9XiCWzlADEG/RMNxtoLVTeXJFsOlTXToKJJLj0SWeqM8kpK8W5R5YW4D+XkM1b+zy3oAaiQ5JWbXdYAO0qw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(376002)(39860400002)(136003)(346002)(396003)(451199018)(36840700001)(46966006)(40470700004)(41300700001)(55016003)(6666004)(83380400001)(86362001)(40480700001)(2616005)(107886003)(82310400005)(426003)(47076005)(336012)(356005)(36860700001)(7636003)(82740400003)(316002)(8676002)(70586007)(4326008)(70206006)(54906003)(110136005)(36756003)(1076003)(40460700003)(26005)(7696005)(16526019)(478600001)(6286002)(186003)(2906002)(8936002)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Feb 2023 07:28:53.8791 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n dc5f9a67-d142-4276-0de1-08db0425f8ff", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT068.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH8PR12MB6892", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "ConnectX and BlueField devices which support HWS are capable of performing\nadvanced match, range-match and hashing operations on packet headers. This\npatch-set introduces support for (1) range matching - allows combining\nrange and exact match over provided item fields using spec, last and mask.\nA useful example for Range and exact match is matching exact IP and port\nrange. This series also introduces (2) partial hash, which allows using\nthe same matcher and performing partial hashing in case of multiple match\ntemplates are provided. The matcher create code finds the union and\nintersection fields to split the hash and match in a way the HW can\nsupport. This increases the match templates combinations possible although\nit may limit the maximum PPS. Since (1) and (2) are not fully support on\ncurrent HW the implementation is done on top of a HW like FW API using\nWQEs.\n\nv2:\n-Fix missed checkpatch comments\n\nAlex Vesker (16):\n net/mlx5/hws: support synchronous drain\n net/mlx5/hws: matcher remove AT and MT limitation\n net/mlx5/hws: support GTA WQE write using FW command\n net/mlx5/hws: add capability query for gen wqe command\n net/mlx5/hws: align RTC create command with PRM format\n net/mlx5/hws: add send FW match STE using gen WQE\n net/mlx5/hws: add send FW range STE WQE\n net/mlx5/hws: move matcher size check to function\n net/mlx5/hws: support range match\n net/mlx5/hws: redesign definer create\n net/mlx5/hws: support partial hash\n net/mlx5/hws: add range definer creation support\n net/mlx5/hws: add FW WQE rule creation logic\n net/mlx5/hws: add debug dump support for range and hash\n net/mlx5/hws: rename pattern cache object\n net/mlx5/hws: cache definer for reuse\n\n drivers/common/mlx5/mlx5_prm.h | 53 +-\n drivers/net/mlx5/hws/mlx5dr.h | 6 +-\n drivers/net/mlx5/hws/mlx5dr_cmd.c | 72 ++-\n drivers/net/mlx5/hws/mlx5dr_cmd.h | 27 +-\n drivers/net/mlx5/hws/mlx5dr_context.c | 12 +-\n drivers/net/mlx5/hws/mlx5dr_context.h | 1 +\n drivers/net/mlx5/hws/mlx5dr_debug.c | 41 +-\n drivers/net/mlx5/hws/mlx5dr_debug.h | 4 +-\n drivers/net/mlx5/hws/mlx5dr_definer.c | 750 +++++++++++++++++++++----\n drivers/net/mlx5/hws/mlx5dr_definer.h | 44 +-\n drivers/net/mlx5/hws/mlx5dr_internal.h | 2 +-\n drivers/net/mlx5/hws/mlx5dr_matcher.c | 279 ++++++---\n drivers/net/mlx5/hws/mlx5dr_matcher.h | 43 +-\n drivers/net/mlx5/hws/mlx5dr_pat_arg.c | 49 +-\n drivers/net/mlx5/hws/mlx5dr_pat_arg.h | 6 +-\n drivers/net/mlx5/hws/mlx5dr_rule.c | 193 ++++++-\n drivers/net/mlx5/hws/mlx5dr_rule.h | 2 +\n drivers/net/mlx5/hws/mlx5dr_send.c | 169 +++++-\n drivers/net/mlx5/hws/mlx5dr_send.h | 24 +-\n drivers/net/mlx5/mlx5_flow_hw.c | 2 +-\n 20 files changed, 1475 insertions(+), 304 deletions(-)" }