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helo=mail.nvidia.com;", "From": "Dmitry Kozlyuk <dkozlyuk@nvidia.com>", "To": "<dev@dpdk.org>", "Date": "Wed, 18 Aug 2021 12:07:51 +0300", "Message-ID": "<20210818090755.2419483-1-dkozlyuk@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n DRHQMAIL107.nvidia.com (10.27.9.16)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "4120b78d-57b3-49cb-a9f7-08d96227b687", "X-MS-TrafficTypeDiagnostic": "MN2PR12MB3325:", "X-Microsoft-Antispam-PRVS": "\n <MN2PR12MB3325545D783967E88F27B295B9FF9@MN2PR12MB3325.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:8273;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n XPv0jtyAYj0lnbB3JhMngs7hBdbzLAeD01pJRWGa4ZAjeWGUaD0Lcg3su4ttnTHSnJtlrEWUORCp/ibmYoR73mhoFx3r46oMCnUS4hlxzmOaUc66SBL66nLIVPI3GAn+reDZpBPBcrlYe7vaTq3dUDO2MWGxTKGXIoHlJEMYqm4lF9XgfiY9Y4Nw0KkrKyZ9SPXOQC7IaLa5t5g2U3YupfYNTDo04+yX2ZlpcNAcuTQO6+tj37xwShdrOuB299BBix/Q5RPBkfR6H5c9sdl+Tjk1BmfWg4e3IeGq21758MeYmVSTAC5yK8IkSqz7btLlHlOcefrD/VbhUcfPgoDilq87xGPV2LcYBBRWCUQae+eunMv4Pgk/hO4ZVWp0RdQNbG+jwUyyr9vet2mg1JM1ulbpcewBp+1yrrzziB8iaacvsx+lEIYR0bro6nZAHheGlS4f03ZWN0cJitCk3mV2xXp4BQytvT/68YpcIREGAC7wFp3XNsvqqwUlV5/SKbbfyoz5t7/CYCf1nnA7NeknsvJYgJZCf3TtpO65Kb1XSXzUD/6qBxiFUpPF9goDpgeqbH7nbbnriJQTeXjOcvgtqJ1Gz04+ormdv5uzFJoy5zpPtRCj/GBnm2fUorqZDCJxcYyPDqKqmxv4wZ33mXWr2dSAslpNTw9HckQEaCkYdanX895tWoh5jQmGkaav+wdT/w3b73VXnifvBwQ4kvYDardNG2sK1uEims7tzqqCbbnTvcPAofZsL+VfCQRPiX8KmgR81+UtV7IteFPaWAvdyiDl4l3xPmZLiOxJde41EMA=", "X-Forefront-Antispam-Report": "CIP:216.228.112.36; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid05.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(396003)(136003)(376002)(39860400002)(36840700001)(46966006)(966005)(5660300002)(8676002)(47076005)(2906002)(45080400002)(8936002)(478600001)(316002)(1076003)(6916009)(7696005)(70586007)(36860700001)(336012)(86362001)(186003)(55016002)(70206006)(6666004)(2616005)(83380400001)(82740400003)(7636003)(356005)(36756003)(426003)(82310400003)(6286002)(16526019)(26005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Aug 2021 09:08:15.4137 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4120b78d-57b3-49cb-a9f7-08d96227b687", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT006.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB3325", "Subject": "[dpdk-dev] [PATCH 0/4] net/mlx5: implicit mempool registration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "MLX5 hardware has its internal IOMMU where PMD registers the memory.\nOn the data path, PMD translates VA into a key consumed by the device\nIOMMU. It is impractical for the PMD to register all allocated memory\nbecause of increased lookup cost both in HW and SW. Most often mbuf\nmemory comes from mempools, so if PMD tracks them, it can almost always\nhave mbuf memory registered before an mbuf hits the PMD. This patchset\nadds such tracking in the PMD and internal API to support it.\n\nPlease see [1] for a more thorough explanation of the patch 2/4\nand how it can be useful outside of the MLX5 PMD.\n\n[1]: http://inbox.dpdk.org/dev/CH0PR12MB509112FADB778AB28AF3771DB9F99@CH0PR12MB5091.namprd12.prod.outlook.com/\n\nDmitry Kozlyuk (4):\n mempool: add event callbacks\n mempool: add non-IO flag\n common/mlx5: add mempool registration facilities\n net/mlx5: support mempool registration\n\n doc/guides/nics/mlx5.rst | 11 +\n doc/guides/rel_notes/release_21_11.rst | 9 +\n drivers/common/mlx5/mlx5_common_mp.c | 50 +++\n drivers/common/mlx5/mlx5_common_mp.h | 14 +\n drivers/common/mlx5/mlx5_common_mr.c | 564 +++++++++++++++++++++++++\n drivers/common/mlx5/mlx5_common_mr.h | 17 +\n drivers/common/mlx5/version.map | 5 +\n drivers/net/mlx5/linux/mlx5_mp_os.c | 44 ++\n drivers/net/mlx5/linux/mlx5_os.c | 4 +-\n drivers/net/mlx5/linux/mlx5_os.h | 2 +\n drivers/net/mlx5/mlx5.c | 128 ++++++\n drivers/net/mlx5/mlx5.h | 13 +\n drivers/net/mlx5/mlx5_mr.c | 27 ++\n drivers/net/mlx5/mlx5_trigger.c | 10 +-\n lib/mempool/rte_mempool.c | 153 ++++++-\n lib/mempool/rte_mempool.h | 60 +++\n lib/mempool/version.map | 8 +\n 17 files changed, 1110 insertions(+), 9 deletions(-)" }