Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/102671/?format=api
{ "id": 102671, "url": "http://patchwork.dpdk.org/api/patches/102671/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211022154600.2180938-1-fkelly@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211022154600.2180938-1-fkelly@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211022154600.2180938-1-fkelly@nvidia.com", "date": "2021-10-22T15:45:51", "name": "[01/10] common/mlx5: update PRM definitions for regex availability", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "0dca83e7020c95c8e4a3b91e1faf8a69085ececd", "submitter": { "id": 2387, "url": "http://patchwork.dpdk.org/api/people/2387/?format=api", "name": "Francis Kelly", "email": "fkelly@nvidia.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211022154600.2180938-1-fkelly@nvidia.com/mbox/", "series": [ { "id": 19921, "url": "http://patchwork.dpdk.org/api/series/19921/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=19921", "date": "2021-10-22T15:45:51", "name": "[01/10] common/mlx5: update PRM definitions for regex availability", "version": 1, "mbox": "http://patchwork.dpdk.org/series/19921/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/102671/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/102671/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8C083A0C43;\n\tFri, 22 Oct 2021 17:46:30 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 723C2411EA;\n\tFri, 22 Oct 2021 17:46:30 +0200 (CEST)", "from NAM04-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam08on2050.outbound.protection.outlook.com [40.107.100.50])\n by mails.dpdk.org (Postfix) with ESMTP id BE275411EA\n for <dev@dpdk.org>; Fri, 22 Oct 2021 17:46:28 +0200 (CEST)", "from DM6PR08CA0013.namprd08.prod.outlook.com (2603:10b6:5:80::26) by\n DM6PR12MB3291.namprd12.prod.outlook.com (2603:10b6:5:186::32) with\n Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.4608.18; Fri, 22 Oct 2021 15:46:26 +0000", "from DM6NAM11FT045.eop-nam11.prod.protection.outlook.com\n (2603:10b6:5:80:cafe::64) by DM6PR08CA0013.outlook.office365.com\n (2603:10b6:5:80::26) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18 via Frontend\n Transport; Fri, 22 Oct 2021 15:46:26 +0000", "from mail.nvidia.com (216.228.112.34) by\n DM6NAM11FT045.mail.protection.outlook.com (10.13.173.123) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4628.16 via Frontend Transport; Fri, 22 Oct 2021 15:46:26 +0000", "from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 22 Oct\n 2021 15:46:23 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=e1a1zkwI8Nuz3IbTcQpH34pgxSr+keC3A27xJz4YMwrp9UgaWhzbXPhGlbT+E9wcss+CDo/N6BhJg+6LdKTLbk3Ee9Rz8FaTwWZtdyTYGWl0zYljhF3GAqCHlE8Bc4cteMAISH1Qa2NvoV8QXZMoNd8b9vWZob8XlCXf+WGNta06ZCngkX3N4EL2BIKrg+oJevXDzGMHs1cZhcfxBxtDYBuHTlwprelX6NXt1o7mI84M8QV07uXUNuWZFCJohxycxFbPupREhXrBz9IEXwIsHd209YpBuQBK4hyA33vbEzzOduPWIqgN78TEUUN14lDsTdrXC2SEluWK0II3LmbPnw==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=5iIeprwD5yEnZjk55E6mu4Scg84a1uwQw7NladLDWTw=;\n b=Ju9rJCu7vpcmPmM54oMxDLRBtCnszAZg7D61k/gtDtl5IKGnKJApWfrzPU08sAgC7GJrmXMjjcPwbELzmzm1L2Am2FVqLUz3W+pq+0Uk/xm/3I9cQ3Zp31lFXeVWOx5fOHtIIRNthqxlSK31kB8PslUT9ax4akybwHOeCgdxnhdczt0L9EyRRwJt70V3oaKOeJOdI+l8p0M+tEwO8RB6ftsABE8UshE+3RJGfYlyQ7ZTAZearlCym9bJWUavcF7cB5rPBxKmugguX8KWFLoQ0gL85haSwIEN3giR02Nu2YiRmVDMLpEm7a3NeIeoVFGTZfUX9HdT0Naaf0+g8AvBSg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=quarantine pct=100) action=none\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=5iIeprwD5yEnZjk55E6mu4Scg84a1uwQw7NladLDWTw=;\n b=A+6JueTE6AQOQw7e3nRqJO2AVD7MrvRh8+2rRhFwyjZ0J5oE/Z2jvDxnm9aChQrbiOhmzavzNBsqEKBKhz/0PtkNz4cGTnZBERiFDjMO82dGiLty9LCuJYBQuLs/0mmHyolKdFSp3cNsFWKueVDa8jQhxtKwNcBq/N9+Tl05zeYhEK4uWHOWpNFpoqdFzgXUsK4Jr6NjQvGu3GFCVg/LRn0UYknMPXrJ7pcVe7XSf+33SDVf/mGS6cqVS/40E9QcuEbeNGxieeKJ87IZ301PZJRTRsMzPkA64WGp/5xKKEMu2KMDRlooYQtWW+sl4IE+AAzPyUNAXey109suZAiVBA==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; gmail.com; dkim=none (message not signed)\n header.d=none;gmail.com; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Francis Kelly <fkelly@nvidia.com>", "To": "<tmonjalon@nvidia.com>, Matan Azrad <matan@nvidia.com>, \"Viacheslav\n Ovsiienko\" <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>", "CC": "<jamhunter@nvidia.com>, <aagbarih@nvidia.com>, <dev@dpdk.org>, Ady Agbarih\n <adypodoman@gmail.com>", "Date": "Fri, 22 Oct 2021 15:45:51 +0000", "Message-ID": "<20211022154600.2180938-1-fkelly@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "c307478c-53bd-408d-c25c-08d995731b60", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB3291:", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB32914224B9C02FFCFF9D0107B9809@DM6PR12MB3291.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:2089;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n W1vMYsQK6UsEiAJFtJYv5gxEVR9e1rKYqvQDDqdZ0r4nVrsXTW1b2fCRKgKfAyTVr3vqnvfo+Ht/D2svrhv9kJXSqxqNu3srgOXaKI5gPVkdR1BP4d1zevsCQzti8uvjMN2JRZm4q5ZkGh9fPbAdaaTAGELkW9WeziXEEQt25YMdzGrOlI3sPFjQR/rPtqk1zRksZh/6NtMsL1SiyCHT2X+93AeMzQBGUnvZZEvcVKJWhcbknLxVtyX5zSR4F17LgCsd/0ElazSFcdNqYCRiQccwXH9yI0Ck5QkoewR92s4bWaFjAWdfOJNnBBry8Be1gcZuA8b+Rl+rrKAoLndQ9k2HggUbB6j2wCUthtob2l2EXHHS6SXoNNV19ZCBD2FpsNKf5i+XtcFaJWo1LfWfdvvrcjimGoWbo/VKpGXZCXz0tO4+qA8a7/wT4GkVNxFenXsepbVVwKD7+f/uxfTplsF/8Zu2976BMm+UZea9BoUgMlHdZoYcq2sYJCkg77RQaYB/E8Vn77zoUsDp3gsm4oUmiMpJmwqwwzTol8xcqrRQLP1fNZSE+V7rkIMUdAwo+1AtaJrGIn/VFkvDCRReTwXm2un4ljXQJ54/WlCH0vIBbpPVdgNCclJEIQ275/JbLlboJdS6HNxIMzoiUCH1R+bEcIMtktTsNJTv7o5TGpwFPrqb/boJU4+2znko1lXxH38apGKVnGpHGP3qYe9EKg==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(5660300002)(6636002)(36860700001)(1076003)(7636003)(36756003)(2906002)(86362001)(4326008)(6666004)(7696005)(6286002)(336012)(36906005)(54906003)(110136005)(15650500001)(16526019)(47076005)(83380400001)(316002)(186003)(26005)(55016002)(8676002)(82310400003)(508600001)(2616005)(356005)(426003)(70586007)(8936002)(70206006);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 Oct 2021 15:46:26.1550 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c307478c-53bd-408d-c25c-08d995731b60", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT045.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB3291", "Subject": "[dpdk-dev] [PATCH 01/10] common/mlx5: update PRM definitions for\n regex availability", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ady Agbarih <adypodoman@gmail.com>\n\nUpdate PRM hca capabilities definitions as follows:\nregexp_version field added - specifies whether BF2 or BF3\nregexp field removed\nregexp_params field moved\nregexp_log_crspace_size field removed\nregexp_mmo added - specifies if using regex mmo wqe is supported\n\nAllow regex only if both regexp_params and regexp_mmo are set,\ninstead of checking regexp_mmo only.\n\nCheck version through the new capability field regexp_version instead\nof reading crspace register.\n\nSigned-off-by: Ady Agbarih <adypodoman@gmail.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 3 ++-\n drivers/common/mlx5/mlx5_devx_cmds.h | 3 ++-\n drivers/common/mlx5/mlx5_prm.h | 12 +++++-------\n drivers/regex/mlx5/mlx5_regex.c | 11 ++---------\n drivers/regex/mlx5/mlx5_rxp_csrs.h | 2 +-\n 5 files changed, 12 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex fb7c8e986f..f0af94b31c 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -821,7 +821,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);\n \tattr->steering_format_version =\n \t\tMLX5_GET(cmd_hca_cap, hcattr, steering_format_version);\n-\tattr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);\n+\tattr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);\n+\tattr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);\n \tattr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t regexp_num_of_engines);\n \t/* Read the general_obj_types bitmap and extract the relevant bits. */\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 5e4f3b749e..69b6bed2dd 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -151,7 +151,8 @@ struct mlx5_hca_attr {\n \tuint32_t sq_ts_format:2;\n \tuint32_t steering_format_version:4;\n \tuint32_t qp_ts_format:2;\n-\tuint32_t regex:1;\n+\tuint32_t regexp_params:1;\n+\tuint32_t regexp_version:3;\n \tuint32_t reg_c_preserve:1;\n \tuint32_t ct_offload:1; /* General obj type ASO CT offload supported. */\n \tuint32_t crypto:1; /* Crypto engine is supported. */\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex eab80eaead..8b0f2f1a89 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1341,16 +1341,13 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 wqe_index_ignore_cap[0x1];\n \tu8 dynamic_qp_allocation[0x1];\n \tu8 log_max_qp[0x5];\n-\tu8 regexp[0x1];\n-\tu8 reserved_at_a1[0x3];\n+\tu8 reserved_at_a0[0x4];\n \tu8 regexp_num_of_engines[0x4];\n \tu8 reserved_at_a8[0x1];\n \tu8 reg_c_preserve[0x1];\n \tu8 reserved_at_aa[0x1];\n \tu8 log_max_srq[0x5];\n-\tu8 reserved_at_b0[0x3];\n-\tu8 regexp_log_crspace_size[0x5];\n-\tu8 reserved_at_b8[0x3];\n+\tu8 reserved_at_b0[0xb];\n \tu8 scatter_fcs_w_decap_disable[0x1];\n \tu8 reserved_at_bc[0x4];\n \tu8 reserved_at_c0[0x8];\n@@ -1506,7 +1503,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 uc[0x1];\n \tu8 rc[0x1];\n \tu8 uar_4k[0x1];\n-\tu8 reserved_at_241[0x9];\n+\tu8 reserved_at_241[0x8];\n+\tu8 regexp_params[0x1];\n \tu8 uar_sz[0x6];\n \tu8 port_selection_cap[0x1];\n \tu8 reserved_at_251[0x7];\n@@ -1523,7 +1521,7 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 max_wqe_sz_sq[0x10];\n \tu8 reserved_at_2a0[0xc];\n \tu8 regexp_mmo_sq[0x1];\n-\tu8 reserved_at_2b0[0x3];\n+\tu8 regexp_version[0x3];\n \tu8 max_wqe_sz_rq[0x10];\n \tu8 max_flow_counter_31_16[0x10];\n \tu8 max_wqe_sz_sq_dc[0x10];\ndiff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex 5aa988be6d..2124fd15f0 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -129,7 +129,6 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev)\n \tstruct mlx5_hca_attr attr;\n \tchar name[RTE_REGEXDEV_NAME_MAX_LEN];\n \tint ret;\n-\tuint32_t val;\n \n \tibv = mlx5_os_get_ibv_dev(rte_dev);\n \tif (ibv == NULL)\n@@ -146,7 +145,7 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev)\n \t\tDRV_LOG(ERR, \"Unable to read HCA capabilities.\");\n \t\trte_errno = ENOTSUP;\n \t\tgoto dev_error;\n-\t} else if (((!attr.regex) && (!attr.mmo_regex_sq_en) &&\n+\t} else if (((!attr.regexp_params) && (!attr.mmo_regex_sq_en) &&\n \t\t(!attr.mmo_regex_qp_en)) || attr.regexp_num_of_engines == 0) {\n \t\tDRV_LOG(ERR, \"Not enough capabilities to support RegEx, maybe \"\n \t\t\t\"old FW/OFED version?\");\n@@ -170,13 +169,7 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev)\n \tpriv->qp_ts_format = attr.qp_ts_format;\n \tpriv->ctx = ctx;\n \tpriv->nb_engines = 2; /* attr.regexp_num_of_engines */\n-\tret = mlx5_devx_regex_register_read(priv->ctx, 0,\n-\t\t\t\t\t MLX5_RXP_CSR_IDENTIFIER, &val);\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"CSR read failed!\");\n-\t\tgoto dev_error;\n-\t}\n-\tif (val == MLX5_RXP_BF2_IDENTIFIER)\n+\tif (attr.regexp_version == MLX5_RXP_BF2_IDENTIFIER)\n \t\tpriv->is_bf2 = 1;\n \t/* Default RXP programming mode to Shared. */\n \tpriv->prog_mode = MLX5_RXP_SHARED_PROG_MODE;\ndiff --git a/drivers/regex/mlx5/mlx5_rxp_csrs.h b/drivers/regex/mlx5/mlx5_rxp_csrs.h\nindex f3ffdfdef2..08cb6f3261 100644\n--- a/drivers/regex/mlx5/mlx5_rxp_csrs.h\n+++ b/drivers/regex/mlx5/mlx5_rxp_csrs.h\n@@ -6,7 +6,7 @@\n #define _MLX5_RXP_CSRS_H_\n \n /* BF types */\n-#define MLX5_RXP_BF2_IDENTIFIER 0x07055254ul\n+#define MLX5_RXP_BF2_IDENTIFIER 0x0\n \n /*\n * Common to all RXP implementations\n", "prefixes": [ "01/10" ] }