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{
    "id": 102676,
    "url": "http://patchwork.dpdk.org/api/patches/102676/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211022154600.2180938-4-fkelly@nvidia.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211022154600.2180938-4-fkelly@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211022154600.2180938-4-fkelly@nvidia.com",
    "date": "2021-10-22T15:45:54",
    "name": "[04/10] regex/mlx5: remove regexp register read/write",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "a851d3e127478ddb26ac0858bf62642e81fcbaf9",
    "submitter": {
        "id": 2387,
        "url": "http://patchwork.dpdk.org/api/people/2387/?format=api",
        "name": "Francis Kelly",
        "email": "fkelly@nvidia.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211022154600.2180938-4-fkelly@nvidia.com/mbox/",
    "series": [
        {
            "id": 19921,
            "url": "http://patchwork.dpdk.org/api/series/19921/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=19921",
            "date": "2021-10-22T15:45:51",
            "name": "[01/10] common/mlx5: update PRM definitions for regex availability",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/19921/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/102676/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/102676/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Francis Kelly <fkelly@nvidia.com>",
        "To": "<tmonjalon@nvidia.com>, Ori Kam <orika@nvidia.com>",
        "CC": "<jamhunter@nvidia.com>, <aagbarih@nvidia.com>, <dev@dpdk.org>, Ady Agbarih\n <adypodoman@gmail.com>",
        "Date": "Fri, 22 Oct 2021 15:45:54 +0000",
        "Message-ID": "<20211022154600.2180938-4-fkelly@nvidia.com>",
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        "Subject": "[dpdk-dev] [PATCH 04/10] regex/mlx5: remove regexp register\n read/write",
        "X-BeenThere": "dev@dpdk.org",
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    },
    "content": "From: Ady Agbarih <adypodoman@gmail.com>\n\nRemove the set/query regexp register commands from devx.\nRemove functions that used these commands.\nRemove manual rules programming.\n\nSigned-off-by: Ady Agbarih <adypodoman@gmail.com>\n---\n drivers/regex/mlx5/mlx5_regex.c      |  28 --\n drivers/regex/mlx5/mlx5_regex.h      |   4 -\n drivers/regex/mlx5/mlx5_regex_devx.c |  48 --\n drivers/regex/mlx5/mlx5_rxp.c        | 708 +--------------------------\n 4 files changed, 1 insertion(+), 787 deletions(-)",
    "diff": "diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex 4be36e40c5..f9eb3a2fab 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -68,29 +68,6 @@ mlx5_regex_close(struct rte_regexdev *dev __rte_unused)\n \treturn 0;\n }\n \n-static int\n-mlx5_regex_engines_status(struct ibv_context *ctx, int num_engines)\n-{\n-\tuint32_t fpga_ident = 0;\n-\tint err;\n-\tint i;\n-\n-\tfor (i = 0; i < num_engines; i++) {\n-\t\terr = mlx5_devx_regex_register_read(ctx, i,\n-\t\t\t\t\t\t    MLX5_RXP_CSR_IDENTIFIER,\n-\t\t\t\t\t\t    &fpga_ident);\n-\t\tfpga_ident = (fpga_ident & (0x0000FFFF));\n-\t\tif (err || fpga_ident != MLX5_RXP_IDENTIFIER) {\n-\t\t\tDRV_LOG(ERR, \"Failed setup RXP %d err %d database \"\n-\t\t\t\t\"memory 0x%x\", i, err, fpga_ident);\n-\t\t\tif (!err)\n-\t\t\t\terr = EINVAL;\n-\t\t\treturn err;\n-\t\t}\n-\t}\n-\treturn 0;\n-}\n-\n static void\n mlx5_regex_get_name(char *name, struct rte_device *dev)\n {\n@@ -163,11 +140,6 @@ mlx5_regex_dev_probe(struct rte_device *rte_dev)\n \t\trte_errno = ENOTSUP;\n \t\tgoto dev_error;\n \t}\n-\tif (mlx5_regex_engines_status(ctx, 2)) {\n-\t\tDRV_LOG(ERR, \"RegEx engine error.\");\n-\t\trte_errno = ENOMEM;\n-\t\tgoto dev_error;\n-\t}\n \tpriv = rte_zmalloc(\"mlx5 regex device private\", sizeof(*priv),\n \t\t\t   RTE_CACHE_LINE_SIZE);\n \tif (!priv) {\ndiff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex c9586ae714..09b360a1ab 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -113,10 +113,6 @@ int mlx5_regex_rules_db_import(struct rte_regexdev *dev,\n \t\t\t       const char *rule_db, uint32_t rule_db_len);\n \n /* mlx5_regex_devx.c */\n-int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,\n-\t\t\t\t   uint32_t addr, uint32_t data);\n-int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,\n-\t\t\t\t  uint32_t addr, uint32_t *data);\n int mlx5_devx_regex_database_stop(void *ctx, uint8_t engine);\n int mlx5_devx_regex_database_resume(void *ctx, uint8_t engine);\n int mlx5_devx_regex_rules_program(void *ctx, uint8_t engine, uint32_t rof_mkey,\ndiff --git a/drivers/regex/mlx5/mlx5_regex_devx.c b/drivers/regex/mlx5/mlx5_regex_devx.c\nindex d8515768c3..262f301121 100644\n--- a/drivers/regex/mlx5/mlx5_regex_devx.c\n+++ b/drivers/regex/mlx5/mlx5_regex_devx.c\n@@ -12,54 +12,6 @@\n #include \"mlx5_regex.h\"\n #include \"mlx5_regex_utils.h\"\n \n-int\n-mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,\n-\t\t\t       uint32_t addr, uint32_t data)\n-{\n-\tuint32_t out[MLX5_ST_SZ_DW(set_regexp_register_out)] = {0};\n-\tuint32_t in[MLX5_ST_SZ_DW(set_regexp_register_in)] = {0};\n-\tint ret;\n-\n-\tMLX5_SET(set_regexp_register_in, in, opcode,\n-\t\t MLX5_CMD_SET_REGEX_REGISTERS);\n-\tMLX5_SET(set_regexp_register_in, in, engine_id, engine_id);\n-\tMLX5_SET(set_regexp_register_in, in, register_address, addr);\n-\tMLX5_SET(set_regexp_register_in, in, register_data, data);\n-\n-\tret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,\n-\t\t\t\t\t  sizeof(out));\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"Set regexp register failed %d\", ret);\n-\t\trte_errno = errno;\n-\t\treturn -errno;\n-\t}\n-\treturn 0;\n-}\n-\n-int\n-mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,\n-\t\t\t      uint32_t addr, uint32_t *data)\n-{\n-\tuint32_t out[MLX5_ST_SZ_DW(query_regexp_register_out)] = {0};\n-\tuint32_t in[MLX5_ST_SZ_DW(query_regexp_register_in)] = {0};\n-\tint ret;\n-\n-\tMLX5_SET(query_regexp_register_in, in, opcode,\n-\t\t MLX5_CMD_QUERY_REGEX_REGISTERS);\n-\tMLX5_SET(query_regexp_register_in, in, engine_id, engine_id);\n-\tMLX5_SET(query_regexp_register_in, in, register_address, addr);\n-\n-\tret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,\n-\t\t\t\t\t  sizeof(out));\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"Query regexp register failed %d\", ret);\n-\t\trte_errno = errno;\n-\t\treturn -errno;\n-\t}\n-\t*data = MLX5_GET(query_regexp_register_out, out, register_data);\n-\treturn 0;\n-}\n-\n int\n mlx5_devx_regex_database_stop(void *ctx, uint8_t engine)\n {\ndiff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c\nindex 79f063a127..8f54ab018e 100644\n--- a/drivers/regex/mlx5/mlx5_rxp.c\n+++ b/drivers/regex/mlx5/mlx5_rxp.c\n@@ -28,71 +28,6 @@\n #define MLX5_REGEX_RXP_ROF2_LINE_LEN 34\n \n /* Private Declarations */\n-static int\n-rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,\n-\t\t       uint32_t address, uint32_t expected_value,\n-\t\t       uint32_t expected_mask, uint32_t timeout_ms, uint8_t id);\n-static int\n-mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id);\n-static int\n-mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id);\n-static int\n-program_rxp_rules(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n-\t\t  uint8_t id);\n-static int\n-rxp_init_eng(struct mlx5_regex_priv *priv, uint8_t id);\n-static int\n-rxp_db_setup(struct mlx5_regex_priv *priv);\n-static void\n-rxp_dump_csrs(struct ibv_context *ctx, uint8_t id);\n-static int\n-rxp_start_engine(struct ibv_context *ctx, uint8_t id);\n-static int\n-rxp_stop_engine(struct ibv_context *ctx, uint8_t id);\n-\n-static void __rte_unused\n-rxp_dump_csrs(struct ibv_context *ctx __rte_unused, uint8_t id __rte_unused)\n-{\n-\tuint32_t reg, i;\n-\n-\t/* Main CSRs*/\n-\tfor (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {\n-\t\tif (mlx5_devx_regex_register_read(ctx, id,\n-\t\t\t\t\t\t  (MLX5_RXP_CSR_WIDTH * i) +\n-\t\t\t\t\t\t  MLX5_RXP_CSR_BASE_ADDRESS,\n-\t\t\t\t\t\t  &reg)) {\n-\t\t\tDRV_LOG(ERR, \"Failed to read Main CSRs Engine %d!\", id);\n-\t\t\treturn;\n-\t\t}\n-\t\tDRV_LOG(DEBUG, \"RXP Main CSRs (Eng%d) register (%d): %08x\",\n-\t\t\tid, i, reg);\n-\t}\n-\t/* RTRU CSRs*/\n-\tfor (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {\n-\t\tif (mlx5_devx_regex_register_read(ctx, id,\n-\t\t\t\t\t\t  (MLX5_RXP_CSR_WIDTH * i) +\n-\t\t\t\t\t\t MLX5_RXP_RTRU_CSR_BASE_ADDRESS,\n-\t\t\t\t\t\t  &reg)) {\n-\t\t\tDRV_LOG(ERR, \"Failed to read RTRU CSRs Engine %d!\", id);\n-\t\t\treturn;\n-\t\t}\n-\t\tDRV_LOG(DEBUG, \"RXP RTRU CSRs (Eng%d) register (%d): %08x\",\n-\t\t\tid, i, reg);\n-\t}\n-\t/* STAT CSRs */\n-\tfor (i = 0; i < MLX5_RXP_CSR_NUM_ENTRIES; i++) {\n-\t\tif (mlx5_devx_regex_register_read(ctx, id,\n-\t\t\t\t\t\t  (MLX5_RXP_CSR_WIDTH * i) +\n-\t\t\t\t\t\tMLX5_RXP_STATS_CSR_BASE_ADDRESS,\n-\t\t\t\t\t\t  &reg)) {\n-\t\t\tDRV_LOG(ERR, \"Failed to read STAT CSRs Engine %d!\", id);\n-\t\t\treturn;\n-\t\t}\n-\t\tDRV_LOG(DEBUG, \"RXP STAT CSRs (Eng%d) register (%d): %08x\",\n-\t\t\tid, i, reg);\n-\t}\n-}\n-\n int\n mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,\n \t\t    struct rte_regexdev_info *info)\n@@ -108,614 +43,6 @@ mlx5_regex_info_get(struct rte_regexdev *dev __rte_unused,\n \treturn 0;\n }\n \n-static int\n-rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value,\n-\t\t       uint32_t address, uint32_t expected_value,\n-\t\t       uint32_t expected_mask, uint32_t timeout_ms, uint8_t id)\n-{\n-\tunsigned int i;\n-\tint ret;\n-\n-\tret = -EBUSY;\n-\tfor (i = 0; i < timeout_ms; i++) {\n-\t\tif (mlx5_devx_regex_register_read(ctx, id, address, value))\n-\t\t\treturn -1;\n-\t\tif ((*value & expected_mask) == expected_value) {\n-\t\t\tret = 0;\n-\t\t\tbreak;\n-\t\t}\n-\t\trte_delay_us(1000);\n-\t}\n-\treturn ret;\n-}\n-\n-static int\n-rxp_start_engine(struct ibv_context *ctx, uint8_t id)\n-{\n-\tuint32_t ctrl;\n-\tint ret;\n-\n-\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);\n-\tif (ret)\n-\t\treturn ret;\n-\tctrl |= MLX5_RXP_CSR_CTRL_GO;\n-\tctrl |= MLX5_RXP_CSR_CTRL_DISABLE_L2C;\n-\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);\n-\treturn ret;\n-}\n-\n-static int\n-rxp_stop_engine(struct ibv_context *ctx, uint8_t id)\n-{\n-\tuint32_t ctrl;\n-\tint ret;\n-\n-\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);\n-\tif (ret)\n-\t\treturn ret;\n-\tctrl &= ~MLX5_RXP_CSR_CTRL_GO;\n-\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);\n-\treturn ret;\n-}\n-\n-static int\n-rxp_init_rtru(struct mlx5_regex_priv *priv, uint8_t id, uint32_t init_bits)\n-{\n-\tuint32_t ctrl_value;\n-\tuint32_t poll_value;\n-\tuint32_t expected_value;\n-\tuint32_t expected_mask;\n-\tstruct ibv_context *ctx = priv->ctx;\n-\tint ret = 0;\n-\n-\t/* Read the rtru ctrl CSR. */\n-\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n-\t\t\t\t\t    &ctrl_value);\n-\tif (ret)\n-\t\treturn -1;\n-\t/* Clear any previous init modes. */\n-\tctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK);\n-\tif (ctrl_value & MLX5_RXP_RTRU_CSR_CTRL_INIT) {\n-\t\tctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);\n-\t\tmlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n-\t\t\t\t\t       ctrl_value);\n-\t}\n-\t/* Set the init_mode bits in the rtru ctrl CSR. */\n-\tctrl_value |= init_bits;\n-\tmlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n-\t\t\t\t       ctrl_value);\n-\t/* Need to sleep for a short period after pulsing the rtru init bit. */\n-\trte_delay_us(20000);\n-\t/* Poll the rtru status CSR until all the init done bits are set. */\n-\tDRV_LOG(DEBUG, \"waiting for RXP rule memory to complete init\");\n-\t/* Set the init bit in the rtru ctrl CSR. */\n-\tctrl_value |= MLX5_RXP_RTRU_CSR_CTRL_INIT;\n-\tmlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n-\t\t\t\t       ctrl_value);\n-\t/* Clear the init bit in the rtru ctrl CSR */\n-\tctrl_value &= ~MLX5_RXP_RTRU_CSR_CTRL_INIT;\n-\tmlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n-\t\t\t\t       ctrl_value);\n-\t/* Check that the following bits are set in the RTRU_CSR. */\n-\tif (init_bits == MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2) {\n-\t\t/* Must be incremental mode */\n-\t\texpected_value = MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE;\n-\t} else {\n-\t\texpected_value = MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE |\n-\t\t\tMLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE;\n-\t}\n-\tif (priv->is_bf2)\n-\t\texpected_value |= MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE;\n-\n-\n-\texpected_mask = expected_value;\n-\tret = rxp_poll_csr_for_value(ctx, &poll_value,\n-\t\t\t\t     MLX5_RXP_RTRU_CSR_STATUS,\n-\t\t\t\t     expected_value, expected_mask,\n-\t\t\t\t     MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);\n-\tif (ret)\n-\t\treturn ret;\n-\tDRV_LOG(DEBUG, \"rule memory initialise: 0x%08X\", poll_value);\n-\t/* Clear the init bit in the rtru ctrl CSR */\n-\tctrl_value &= ~(MLX5_RXP_RTRU_CSR_CTRL_INIT);\n-\tmlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n-\t\t\t\t       ctrl_value);\n-\treturn 0;\n-}\n-\n-static int\n-rxp_parse_line(char *line, uint32_t *type, uint32_t *address, uint64_t *value)\n-{\n-\tchar *cur_pos;\n-\n-\tif (*line == '\\0' || *line == '#')\n-\t\treturn  1;\n-\t*type = strtoul(line, &cur_pos, 10);\n-\tif (*cur_pos != ',' && *cur_pos != '\\0')\n-\t\treturn -1;\n-\t*address = strtoul(cur_pos+1, &cur_pos, 16);\n-\tif (*cur_pos != ',' && *cur_pos != '\\0')\n-\t\treturn -1;\n-\t*value = strtoul(cur_pos+1, &cur_pos, 16);\n-\tif (*cur_pos != ',' && *cur_pos != '\\0')\n-\t\treturn -1;\n-\treturn 0;\n-}\n-\n-static uint32_t\n-rxp_get_reg_address(uint32_t address)\n-{\n-\tuint32_t block;\n-\tuint32_t reg;\n-\n-\tblock = (address >> 16) & 0xFFFF;\n-\tif (block == 0)\n-\t\treg = MLX5_RXP_CSR_BASE_ADDRESS;\n-\telse if (block == 1)\n-\t\treg = MLX5_RXP_RTRU_CSR_BASE_ADDRESS;\n-\telse {\n-\t\tDRV_LOG(ERR, \"Invalid ROF register 0x%08X!\", address);\n-\t\t\treturn UINT32_MAX;\n-\t}\n-\treg += (address & 0xFFFF) * MLX5_RXP_CSR_WIDTH;\n-\treturn reg;\n-}\n-\n-#define MLX5_RXP_NUM_LINES_PER_BLOCK 8\n-\n-static int\n-rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n-\t\tuint8_t id)\n-{\n-\tstatic const char del[] = \"\\n\\r\";\n-\tchar *line;\n-\tchar *tmp;\n-\tuint32_t type = 0;\n-\tuint32_t address;\n-\tuint64_t val;\n-\tuint32_t reg_val;\n-\tint ret;\n-\tint skip = -1;\n-\tint last = 0;\n-\tuint32_t temp;\n-\tuint32_t tmp_addr;\n-\tuint32_t rof_rule_addr;\n-\tuint64_t tmp_write_swap[4];\n-\tstruct mlx5_rxp_rof_entry rules[8];\n-\tint i;\n-\tint db_free;\n-\tint j;\n-\n-\ttmp = rte_malloc(\"\", len, 0);\n-\tif (!tmp)\n-\t\treturn -ENOMEM;\n-\tmemcpy(tmp, buf, len);\n-\tdb_free = mlnx_update_database(priv, id);\n-\tif (db_free < 0) {\n-\t\tDRV_LOG(ERR, \"Failed to setup db memory!\");\n-\t\trte_free(tmp);\n-\t\treturn db_free;\n-\t}\n-\tfor (line = strtok(tmp, del), j = 0; line; line = strtok(NULL, del),\n-\t     j++, last = type) {\n-\t\tret = rxp_parse_line(line, &type, &address, &val);\n-\t\tif (ret != 0) {\n-\t\t\tif (ret < 0)\n-\t\t\t\tgoto parse_error;\n-\t\t\tcontinue;\n-\t\t}\n-\t\tswitch (type) {\n-\t\tcase MLX5_RXP_ROF_ENTRY_EQ:\n-\t\t\tif (skip == 0 && address == 0)\n-\t\t\t\tskip = 1;\n-\t\t\ttmp_addr = rxp_get_reg_address(address);\n-\t\t\tif (tmp_addr == UINT32_MAX)\n-\t\t\t\tgoto parse_error;\n-\t\t\tret = mlx5_devx_regex_register_read(priv->ctx, id,\n-\t\t\t\t\t\t\t    tmp_addr, &reg_val);\n-\t\t\tif (ret)\n-\t\t\t\tgoto parse_error;\n-\t\t\tif (skip == -1 && address == 0) {\n-\t\t\t\tif (val == reg_val) {\n-\t\t\t\t\tskip = 0;\n-\t\t\t\t\tcontinue;\n-\t\t\t\t}\n-\t\t\t} else if (skip == 0) {\n-\t\t\t\tif (val != reg_val) {\n-\t\t\t\t\tDRV_LOG(ERR,\n-\t\t\t\t\t\t\"got %08X expected == %\" PRIx64,\n-\t\t\t\t\t\treg_val, val);\n-\t\t\t\t\tgoto parse_error;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase MLX5_RXP_ROF_ENTRY_GTE:\n-\t\t\tif (skip == 0 && address == 0)\n-\t\t\t\tskip = 1;\n-\t\t\ttmp_addr = rxp_get_reg_address(address);\n-\t\t\tif (tmp_addr == UINT32_MAX)\n-\t\t\t\tgoto parse_error;\n-\t\t\tret = mlx5_devx_regex_register_read(priv->ctx, id,\n-\t\t\t\t\t\t\t    tmp_addr, &reg_val);\n-\t\t\tif (ret)\n-\t\t\t\tgoto parse_error;\n-\t\t\tif (skip == -1 && address == 0) {\n-\t\t\t\tif (reg_val >= val) {\n-\t\t\t\t\tskip = 0;\n-\t\t\t\t\tcontinue;\n-\t\t\t\t}\n-\t\t\t} else if (skip == 0) {\n-\t\t\t\tif (reg_val < val) {\n-\t\t\t\t\tDRV_LOG(ERR,\n-\t\t\t\t\t\t\"got %08X expected >= %\" PRIx64,\n-\t\t\t\t\t\treg_val, val);\n-\t\t\t\t\tgoto parse_error;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase MLX5_RXP_ROF_ENTRY_LTE:\n-\t\t\ttmp_addr = rxp_get_reg_address(address);\n-\t\t\tif (tmp_addr == UINT32_MAX)\n-\t\t\t\tgoto parse_error;\n-\t\t\tret = mlx5_devx_regex_register_read(priv->ctx, id,\n-\t\t\t\t\t\t\t    tmp_addr, &reg_val);\n-\t\t\tif (ret)\n-\t\t\t\tgoto parse_error;\n-\t\t\tif (skip == 0 && address == 0 &&\n-\t\t\t    last != MLX5_RXP_ROF_ENTRY_GTE) {\n-\t\t\t\tskip = 1;\n-\t\t\t} else if (skip == 0 && address == 0 &&\n-\t\t\t\t   last == MLX5_RXP_ROF_ENTRY_GTE) {\n-\t\t\t\tif (reg_val > val)\n-\t\t\t\t\tskip = -1;\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\t\t\tif (skip == -1 && address == 0) {\n-\t\t\t\tif (reg_val <= val) {\n-\t\t\t\t\tskip = 0;\n-\t\t\t\t\tcontinue;\n-\t\t\t\t}\n-\t\t\t} else if (skip == 0) {\n-\t\t\t\tif (reg_val > val) {\n-\t\t\t\t\tDRV_LOG(ERR,\n-\t\t\t\t\t\t\"got %08X expected <= %\" PRIx64,\n-\t\t\t\t\t\treg_val, val);\n-\t\t\t\t\tgoto parse_error;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase MLX5_RXP_ROF_ENTRY_CHECKSUM:\n-\t\t\tbreak;\n-\t\tcase MLX5_RXP_ROF_ENTRY_CHECKSUM_EX_EM:\n-\t\t\tif (skip)\n-\t\t\t\tcontinue;\n-\t\t\ttmp_addr = rxp_get_reg_address(address);\n-\t\t\tif (tmp_addr == UINT32_MAX)\n-\t\t\t\tgoto parse_error;\n-\n-\t\t\tret = mlx5_devx_regex_register_read(priv->ctx, id,\n-\t\t\t\t\t\t\t    tmp_addr, &reg_val);\n-\t\t\tif (ret) {\n-\t\t\t\tDRV_LOG(ERR, \"RXP CSR read failed!\");\n-\t\t\t\treturn ret;\n-\t\t\t}\n-\t\t\tif (reg_val != val) {\n-\t\t\t\tDRV_LOG(ERR, \"got %08X expected <= %\" PRIx64,\n-\t\t\t\t\treg_val, val);\n-\t\t\t\tgoto parse_error;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase MLX5_RXP_ROF_ENTRY_IM:\n-\t\t\tif (skip)\n-\t\t\t\tcontinue;\n-\t\t\t/*\n-\t\t\t * NOTE: All rules written to RXP must be carried out in\n-\t\t\t * triplets of: 2xData + 1xAddr.\n-\t\t\t * No optimisation is currently allowed in this\n-\t\t\t * sequence to perform less writes.\n-\t\t\t */\n-\t\t\ttemp = val;\n-\t\t\tret |= mlx5_devx_regex_register_write\n-\t\t\t\t\t(priv->ctx, id,\n-\t\t\t\t\t MLX5_RXP_RTRU_CSR_DATA_0, temp);\n-\t\t\ttemp = (uint32_t)(val >> 32);\n-\t\t\tret |= mlx5_devx_regex_register_write\n-\t\t\t\t\t(priv->ctx, id,\n-\t\t\t\t\t MLX5_RXP_RTRU_CSR_DATA_0 +\n-\t\t\t\t\t MLX5_RXP_CSR_WIDTH, temp);\n-\t\t\ttemp = address;\n-\t\t\tret |= mlx5_devx_regex_register_write\n-\t\t\t\t\t(priv->ctx, id, MLX5_RXP_RTRU_CSR_ADDR,\n-\t\t\t\t\t temp);\n-\t\t\tif (ret) {\n-\t\t\t\tDRV_LOG(ERR,\n-\t\t\t\t\t\"Failed to copy instructions to RXP.\");\n-\t\t\t\tgoto parse_error;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase MLX5_RXP_ROF_ENTRY_EM:\n-\t\t\tif (skip)\n-\t\t\t\tcontinue;\n-\t\t\tfor (i = 0; i < MLX5_RXP_NUM_LINES_PER_BLOCK; i++) {\n-\t\t\t\tret = rxp_parse_line(line, &type,\n-\t\t\t\t\t\t     &rules[i].addr,\n-\t\t\t\t\t\t     &rules[i].value);\n-\t\t\t\tif (ret != 0)\n-\t\t\t\t\tgoto parse_error;\n-\t\t\t\tif (i < (MLX5_RXP_NUM_LINES_PER_BLOCK - 1)) {\n-\t\t\t\t\tline = strtok(NULL, del);\n-\t\t\t\t\tif (!line)\n-\t\t\t\t\t\tgoto parse_error;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t\tif ((uint8_t *)((uint8_t *)\n-\t\t\t\t\tpriv->db[id].ptr +\n-\t\t\t\t\t((rules[7].addr <<\n-\t\t\t\t\t MLX5_RXP_INST_OFFSET))) >=\n-\t\t\t\t\t((uint8_t *)((uint8_t *)\n-\t\t\t\t\tpriv->db[id].ptr + MLX5_MAX_DB_SIZE))) {\n-\t\t\t\tDRV_LOG(ERR, \"DB exceeded memory!\");\n-\t\t\t\tgoto parse_error;\n-\t\t\t}\n-\t\t\t/*\n-\t\t\t * Rule address Offset to align with RXP\n-\t\t\t * external instruction offset.\n-\t\t\t */\n-\t\t\trof_rule_addr = (rules[0].addr << MLX5_RXP_INST_OFFSET);\n-\t\t\t/* 32 byte instruction swap (sw work around)! */\n-\t\t\ttmp_write_swap[0] = le64toh(rules[4].value);\n-\t\t\ttmp_write_swap[1] = le64toh(rules[5].value);\n-\t\t\ttmp_write_swap[2] = le64toh(rules[6].value);\n-\t\t\ttmp_write_swap[3] = le64toh(rules[7].value);\n-\t\t\t/* Write only 4 of the 8 instructions. */\n-\t\t\tmemcpy((uint8_t *)((uint8_t *)\n-\t\t\t\tpriv->db[id].ptr + rof_rule_addr),\n-\t\t\t\t&tmp_write_swap, (sizeof(uint64_t) * 4));\n-\t\t\t/* Write 1st 4 rules of block after last 4. */\n-\t\t\trof_rule_addr = (rules[4].addr << MLX5_RXP_INST_OFFSET);\n-\t\t\ttmp_write_swap[0] = le64toh(rules[0].value);\n-\t\t\ttmp_write_swap[1] = le64toh(rules[1].value);\n-\t\t\ttmp_write_swap[2] = le64toh(rules[2].value);\n-\t\t\ttmp_write_swap[3] = le64toh(rules[3].value);\n-\t\t\tmemcpy((uint8_t *)((uint8_t *)\n-\t\t\t\tpriv->db[id].ptr + rof_rule_addr),\n-\t\t\t\t&tmp_write_swap, (sizeof(uint64_t) * 4));\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\n-\t}\n-\trte_free(tmp);\n-\treturn 0;\n-parse_error:\n-\trte_free(tmp);\n-\treturn ret;\n-}\n-\n-static int\n-mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id)\n-{\n-\tmlx5_devx_regex_database_resume(priv->ctx, id);\n-\treturn 0;\n-}\n-\n-/*\n- * Assign db memory for RXP programming.\n- */\n-static int\n-mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id)\n-{\n-\tunsigned int i;\n-\tuint8_t db_free = MLX5_RXP_DB_NOT_ASSIGNED;\n-\tuint8_t eng_assigned = MLX5_RXP_DB_NOT_ASSIGNED;\n-\n-\t/* Check which database rxp_eng is currently located if any? */\n-\tfor (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT);\n-\t     i++) {\n-\t\tif (priv->db[i].db_assigned_to_eng_num == id) {\n-\t\t\teng_assigned = i;\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\t/*\n-\t * If private mode then, we can keep the same db ptr as RXP will be\n-\t * programming EM itself if necessary, however need to see if\n-\t * programmed yet.\n-\t */\n-\tif ((priv->prog_mode == MLX5_RXP_PRIVATE_PROG_MODE) &&\n-\t    (eng_assigned != MLX5_RXP_DB_NOT_ASSIGNED))\n-\t\treturn eng_assigned;\n-\t/* Check for inactive db memory to use. */\n-\tfor (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT);\n-\t     i++) {\n-\t\tif (priv->db[i].active == true)\n-\t\t\tcontinue; /* Already in use, so skip db. */\n-\t\t/* Set this db to active now as free to use. */\n-\t\tpriv->db[i].active = true;\n-\t\t/* Now unassign last db index in use by RXP Eng. */\n-\t\tif (eng_assigned != MLX5_RXP_DB_NOT_ASSIGNED) {\n-\t\t\tpriv->db[eng_assigned].active = false;\n-\t\t\tpriv->db[eng_assigned].db_assigned_to_eng_num =\n-\t\t\t\tMLX5_RXP_DB_NOT_ASSIGNED;\n-\n-\t\t\t/* Set all DB memory to 0's before setting up DB. */\n-\t\t\tmemset(priv->db[i].ptr, 0x00, MLX5_MAX_DB_SIZE);\n-\t\t}\n-\t\t/* Now reassign new db index with RXP Engine. */\n-\t\tpriv->db[i].db_assigned_to_eng_num = id;\n-\t\tdb_free = i;\n-\t\tbreak;\n-\t}\n-\tif (db_free == MLX5_RXP_DB_NOT_ASSIGNED)\n-\t\treturn -1;\n-\treturn db_free;\n-}\n-\n-/*\n- * Program RXP instruction db to RXP engine/s.\n- */\n-static int\n-program_rxp_rules(struct mlx5_regex_priv *priv, const char *buf, uint32_t len,\n-\t\t  uint8_t id)\n-{\n-\tint ret;\n-\tuint32_t val;\n-\n-\tret = rxp_init_eng(priv, id);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\t/* Confirm the RXP is initialised. */\n-\tif (mlx5_devx_regex_register_read(priv->ctx, id,\n-\t\t\t\t\t    MLX5_RXP_CSR_STATUS, &val)) {\n-\t\tDRV_LOG(ERR, \"Failed to read from RXP!\");\n-\t\treturn -ENODEV;\n-\t}\n-\tif (!(val & MLX5_RXP_CSR_STATUS_INIT_DONE)) {\n-\t\tDRV_LOG(ERR, \"RXP not initialised...\");\n-\t\treturn -EBUSY;\n-\t}\n-\tret = mlx5_devx_regex_register_read(priv->ctx, id,\n-\t\t\t\t\t    MLX5_RXP_RTRU_CSR_CTRL, &val);\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"CSR read failed!\");\n-\t\treturn -1;\n-\t}\n-\tval |= MLX5_RXP_RTRU_CSR_CTRL_GO;\n-\tret = mlx5_devx_regex_register_write(priv->ctx, id,\n-\t\t\t\t\t     MLX5_RXP_RTRU_CSR_CTRL, val);\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"Can't program rof file!\");\n-\t\treturn -1;\n-\t}\n-\tret = rxp_program_rof(priv, buf, len, id);\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"Can't program rof file!\");\n-\t\treturn -1;\n-\t}\n-\tif (priv->is_bf2) {\n-\t\tret = rxp_poll_csr_for_value\n-\t\t\t(priv->ctx, &val, MLX5_RXP_RTRU_CSR_STATUS,\n-\t\t\t MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,\n-\t\t\t MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,\n-\t\t\t MLX5_RXP_POLL_CSR_FOR_VALUE_TIMEOUT, id);\n-\t\tif (ret < 0) {\n-\t\t\tDRV_LOG(ERR, \"Rules update timeout: 0x%08X\", val);\n-\t\t\treturn ret;\n-\t\t}\n-\t\tDRV_LOG(DEBUG, \"Rules update took %d cycles\", ret);\n-\t}\n-\tif (mlx5_devx_regex_register_read(priv->ctx, id, MLX5_RXP_RTRU_CSR_CTRL,\n-\t\t\t\t\t  &val)) {\n-\t\tDRV_LOG(ERR, \"CSR read failed!\");\n-\t\treturn -1;\n-\t}\n-\tval &= ~(MLX5_RXP_RTRU_CSR_CTRL_GO);\n-\tif (mlx5_devx_regex_register_write(priv->ctx, id,\n-\t\t\t\t\t   MLX5_RXP_RTRU_CSR_CTRL, val)) {\n-\t\tDRV_LOG(ERR, \"CSR write failed!\");\n-\t\treturn -1;\n-\t}\n-\tret = mlx5_devx_regex_register_read(priv->ctx, id, MLX5_RXP_CSR_CTRL,\n-\t\t\t\t\t    &val);\n-\tif (ret)\n-\t\treturn ret;\n-\tval &= ~MLX5_RXP_CSR_CTRL_INIT;\n-\tret = mlx5_devx_regex_register_write(priv->ctx, id, MLX5_RXP_CSR_CTRL,\n-\t\t\t\t\t     val);\n-\tif (ret)\n-\t\treturn ret;\n-\trxp_init_rtru(priv, id, MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2);\n-\tif (priv->is_bf2) {\n-\t\tret = rxp_poll_csr_for_value(priv->ctx, &val,\n-\t\t\t\t\t     MLX5_RXP_CSR_STATUS,\n-\t\t\t\t\t     MLX5_RXP_CSR_STATUS_INIT_DONE,\n-\t\t\t\t\t     MLX5_RXP_CSR_STATUS_INIT_DONE,\n-\t\t\t\t\t     MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT,\n-\t\t\t\t\t     id);\n-\t\tif (ret) {\n-\t\t\tDRV_LOG(ERR, \"Device init failed!\");\n-\t\t\treturn ret;\n-\t\t}\n-\t}\n-\tret = mlnx_resume_database(priv, id);\n-\tif (ret < 0) {\n-\t\tDRV_LOG(ERR, \"Failed to resume engine!\");\n-\t\treturn ret;\n-\t}\n-\n-\treturn ret;\n-\n-}\n-\n-static int\n-rxp_init_eng(struct mlx5_regex_priv *priv, uint8_t id)\n-{\n-\tuint32_t ctrl;\n-\tuint32_t reg;\n-\tstruct ibv_context *ctx = priv->ctx;\n-\tint ret;\n-\n-\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);\n-\tif (ret)\n-\t\treturn ret;\n-\tif (ctrl & MLX5_RXP_CSR_CTRL_INIT) {\n-\t\tctrl &= ~MLX5_RXP_CSR_CTRL_INIT;\n-\t\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,\n-\t\t\t\t\t\t     ctrl);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t}\n-\tctrl |= MLX5_RXP_CSR_CTRL_INIT;\n-\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);\n-\tif (ret)\n-\t\treturn ret;\n-\tctrl &= ~MLX5_RXP_CSR_CTRL_INIT;\n-\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL, ctrl);\n-\tif (ret)\n-\t\treturn ret;\n-\trte_delay_us(20000);\n-\tret = rxp_poll_csr_for_value(ctx, &ctrl, MLX5_RXP_CSR_STATUS,\n-\t\t\t\t     MLX5_RXP_CSR_STATUS_INIT_DONE,\n-\t\t\t\t     MLX5_RXP_CSR_STATUS_INIT_DONE,\n-\t\t\t\t     MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT, id);\n-\tif (ret)\n-\t\treturn ret;\n-\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CTRL, &ctrl);\n-\tif (ret)\n-\t\treturn ret;\n-\tctrl &= ~MLX5_RXP_CSR_CTRL_INIT;\n-\tret = mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_CTRL,\n-\t\t\t\t\t     ctrl);\n-\tif (ret)\n-\t\treturn ret;\n-\tret = rxp_init_rtru(priv, id,\n-\t\t\t    MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2);\n-\tif (ret)\n-\t\treturn ret;\n-\tret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_CSR_CAPABILITY_5,\n-\t\t\t\t\t    &reg);\n-\tif (ret)\n-\t\treturn ret;\n-\tDRV_LOG(DEBUG, \"max matches: %d, DDOS threshold: %d\", reg >> 16,\n-\t\treg & 0xffff);\n-\tif ((reg >> 16) >= priv->nb_max_matches)\n-\t\tret = mlx5_devx_regex_register_write(ctx, id,\n-\t\t\t\t\t\t     MLX5_RXP_CSR_MAX_MATCH,\n-\t\t\t\t\t\t     priv->nb_max_matches);\n-\telse\n-\t\tret = mlx5_devx_regex_register_write(ctx, id,\n-\t\t\t\t\t\t     MLX5_RXP_CSR_MAX_MATCH,\n-\t\t\t\t\t\t     (reg >> 16));\n-\tret |= mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_CSR_MAX_PREFIX,\n-\t\t\t\t\t (reg & 0xFFFF));\n-\tret |= mlx5_devx_regex_register_write(ctx, id,\n-\t\t\t\t\t      MLX5_RXP_CSR_MAX_LATENCY, 0);\n-\tret |= mlx5_devx_regex_register_write(ctx, id,\n-\t\t\t\t\t      MLX5_RXP_CSR_MAX_PRI_THREAD, 0);\n-\treturn ret;\n-}\n-\n static int\n rxp_db_setup(struct mlx5_regex_priv *priv)\n {\n@@ -762,10 +89,6 @@ mlx5_regex_rules_db_import(struct rte_regexdev *dev,\n \t\t     const char *rule_db, uint32_t rule_db_len)\n {\n \tstruct mlx5_regex_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxp_ctl_rules_pgm *rules = NULL;\n-\tuint32_t id;\n-\tint ret;\n-\tuint32_t ver;\n \n \tif (priv->prog_mode == MLX5_RXP_MODE_NOT_DEFINED) {\n \t\tDRV_LOG(ERR, \"RXP programming mode not set!\");\n@@ -777,37 +100,8 @@ mlx5_regex_rules_db_import(struct rte_regexdev *dev,\n \t}\n \tif (rule_db_len == 0)\n \t\treturn -EINVAL;\n-\tif (mlx5_devx_regex_register_read(priv->ctx, 0,\n-\t\t\t\t\t  MLX5_RXP_CSR_BASE_ADDRESS, &ver)) {\n-\t\tDRV_LOG(ERR, \"Failed to read Main CSRs Engine 0!\");\n-\t\treturn -1;\n-\t}\n-\t/* Need to ensure RXP not busy before stop! */\n-\tfor (id = 0; id < priv->nb_engines; id++) {\n-\t\tret = rxp_stop_engine(priv->ctx, id);\n-\t\tif (ret) {\n-\t\t\tDRV_LOG(ERR, \"Can't stop engine.\");\n-\t\t\tret = -ENODEV;\n-\t\t\tgoto tidyup_error;\n-\t\t}\n-\t\tret = program_rxp_rules(priv, rule_db, rule_db_len, id);\n-\t\tif (ret < 0) {\n-\t\t\tDRV_LOG(ERR, \"Failed to program rxp rules.\");\n-\t\t\tret = -ENODEV;\n-\t\t\tgoto tidyup_error;\n-\t\t}\n-\t\tret = rxp_start_engine(priv->ctx, id);\n-\t\tif (ret) {\n-\t\t\tDRV_LOG(ERR, \"Can't start engine.\");\n-\t\t\tret = -ENODEV;\n-\t\t\tgoto tidyup_error;\n-\t\t}\n-\t}\n-\trte_free(rules);\n+\n \treturn 0;\n-tidyup_error:\n-\trte_free(rules);\n-\treturn ret;\n }\n \n int\n",
    "prefixes": [
        "04/10"
    ]
}