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GET /api/patches/104625/?format=api
{ "id": 104625, "url": "http://patchwork.dpdk.org/api/patches/104625/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211123183805.2905792-4-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211123183805.2905792-4-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211123183805.2905792-4-michaelba@nvidia.com", "date": "2021-11-23T18:38:05", "name": "[3/3] net/mlx5: fix missing adjustment MPRQ stride devargs", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "107da906263ee3560aa21292a993509f0e1e46f4", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211123183805.2905792-4-michaelba@nvidia.com/mbox/", "series": [ { "id": 20719, "url": "http://patchwork.dpdk.org/api/series/20719/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20719", "date": "2021-11-23T18:38:02", "name": "fix MPRQ prepare", "version": 1, "mbox": "http://patchwork.dpdk.org/series/20719/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/104625/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/104625/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E8424A0C4C;\n\tTue, 23 Nov 2021 19:38:56 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0FF8141160;\n\tTue, 23 Nov 2021 19:38:39 +0100 (CET)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2050.outbound.protection.outlook.com [40.107.244.50])\n by mails.dpdk.org (Postfix) with ESMTP id 79D534114E;\n Tue, 23 Nov 2021 19:38:36 +0100 (CET)", "from DM5PR1401CA0013.namprd14.prod.outlook.com (2603:10b6:4:4a::23)\n by CY4PR12MB1383.namprd12.prod.outlook.com (2603:10b6:903:41::16)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4713.19; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "<michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Michael Baum\n <michaelba@nvidia.com>, <stable@dpdk.org>", "Subject": "[PATCH 3/3] net/mlx5: fix missing adjustment MPRQ stride devargs", "Date": "Tue, 23 Nov 2021 20:38:05 +0200", "Message-ID": "<20211123183805.2905792-4-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211123183805.2905792-1-michaelba@nvidia.com>", "References": "<20211123183805.2905792-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "30df050c-3f06-4424-ceea-08d9aeb07429", "X-MS-TrafficTypeDiagnostic": "CY4PR12MB1383:", "X-Microsoft-Antispam-PRVS": "\n <CY4PR12MB13835AA8A976E0E118C523BCCC609@CY4PR12MB1383.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:8273;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n uKE1XtTSM+QUn0G2KtkxZo+QHjdCO2k000nwHWYbHrhGCpMwnnK7eV17PTcEARbzapWRXJGMflYlkZsFfvx2ZYYyCpv33Q7A/gxi7kJYkQdKChvTVpi2GyU286m45WLaepsSnphY+fru7zqCIZi3uchYO82au8BT0nLMJgcbgni4dE8Rn8fdprtmXGf/+tWAJfJMOr8dU4MCgYmHL3zjR2oxgWNZqSLLTjx1pwpvwWnCXUU33nFOJ8wMXzn5er5mMcL0yQFYr6WpiOUqCRNX43PmpixR4XuDyL8JLy/eF5EKH2x34Z8YZLrPvmO8FEz9qkpWCUiM0iZMmbnK+HwoHlH5sp69JPuXwkrojYisnNYGOH44616ChsoYzG2Gt7VdA3S2Rxx0r6PLEOFQ5ePDm9FpqeNO+5pjsYBXLhtKjqoU1sh3riqrir0tDvDss23FNyXbMy+so5MjKZT6hj7oezUdDE8vz/tXk1bQvFtQivWWIRspKaKwhPUvG1hybUzLNdN2S0r3pH3eZqct7aGXU0czWaJ22BofO8W+nVhGQOZvkEDvNulPoTG2PtoaRZDDg291JT03CUlVUf/lZ5dmRh+oQjLbWJ7vGssGi9HUxOJpViZtWb/YBU6rS8hhKn7Zpb61BIzqGzq27K4rT6PuNzKhPmNYx+Sd+ccGi/PzINSWUNZK3afC5LV0CrCptqfvCqMcl7yoDwWZ2g61aLtDL2RsY5dB9fX6V+qV6y/J4NA=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(8936002)(8676002)(83380400001)(356005)(47076005)(30864003)(6286002)(36860700001)(7636003)(186003)(26005)(70206006)(54906003)(508600001)(6916009)(6666004)(16526019)(1076003)(2876002)(82310400004)(86362001)(316002)(2906002)(55016003)(7696005)(5660300002)(450100002)(70586007)(426003)(4326008)(336012)(36756003)(2616005)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Nov 2021 18:38:33.4740 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 30df050c-3f06-4424-ceea-08d9aeb07429", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT013.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR12MB1383", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Michael Baum <michaelba@nvidia.com>\n\nIn Multy-Packet RQ creation, the user can choose the number of strides\nand their size in bytes. The user updates it using specific devargs for\nboth of these parameters.\nThe above two parameters determine the size of the WQE which is actually\ntheir product of multiplication.\n\nIf the user selects values that are not in the supported range, the PMD\nchanges them to default values. However, apart from the range\nlimitations for each parameter individually there is also a minimum\nvalue on their multiplication. When the user selects values that their\nmultiplication are lower than minimum value, no adjustment is made and\nthe creation of the WQE fails.\n\nThis patch adds an adjustment in these cases as well. When the user\nselects values whose multiplication is lower than the minimum, they are\nreplaced with the default values.\n\nFixes: ecb160456aed (\"net/mlx5: add device parameter for MPRQ stride size\")\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 56 +++------\n drivers/net/mlx5/mlx5.h | 4 +\n drivers/net/mlx5/mlx5_rxq.c | 209 +++++++++++++++++++++----------\n 3 files changed, 159 insertions(+), 110 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 70472efc29..3e496d68ea 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -881,10 +881,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tunsigned int mpls_en = 0;\n \tunsigned int swp = 0;\n \tunsigned int mprq = 0;\n-\tunsigned int mprq_min_stride_size_n = 0;\n-\tunsigned int mprq_max_stride_size_n = 0;\n-\tunsigned int mprq_min_stride_num_n = 0;\n-\tunsigned int mprq_max_stride_num_n = 0;\n \tstruct rte_ether_addr mac;\n \tchar name[RTE_ETH_NAME_MAX_LEN];\n \tint own_domain_id = 0;\n@@ -1039,15 +1035,17 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\tmprq_caps.max_single_wqe_log_num_of_strides);\n \t\tDRV_LOG(DEBUG, \"\\tsupported_qpts: %d\",\n \t\t\tmprq_caps.supported_qpts);\n+\t\tDRV_LOG(DEBUG, \"\\tmin_stride_wqe_log_size: %d\",\n+\t\t\tconfig->mprq.log_min_stride_wqe_size);\n \t\tDRV_LOG(DEBUG, \"device supports Multi-Packet RQ\");\n \t\tmprq = 1;\n-\t\tmprq_min_stride_size_n =\n+\t\tconfig->mprq.log_min_stride_size =\n \t\t\tmprq_caps.min_single_stride_log_num_of_bytes;\n-\t\tmprq_max_stride_size_n =\n+\t\tconfig->mprq.log_max_stride_size =\n \t\t\tmprq_caps.max_single_stride_log_num_of_bytes;\n-\t\tmprq_min_stride_num_n =\n+\t\tconfig->mprq.log_min_stride_num =\n \t\t\tmprq_caps.min_single_wqe_log_num_of_strides;\n-\t\tmprq_max_stride_num_n =\n+\t\tconfig->mprq.log_max_stride_num =\n \t\t\tmprq_caps.max_single_wqe_log_num_of_strides;\n \t}\n #endif\n@@ -1548,36 +1546,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tconfig->hw_fcs_strip = 0;\n \tDRV_LOG(DEBUG, \"FCS stripping configuration is %ssupported\",\n \t\t(config->hw_fcs_strip ? \"\" : \"not \"));\n-\tif (config->mprq.enabled && mprq) {\n-\t\tif (config->mprq.log_stride_num &&\n-\t\t (config->mprq.log_stride_num > mprq_max_stride_num_n ||\n-\t\t config->mprq.log_stride_num < mprq_min_stride_num_n)) {\n-\t\t\tconfig->mprq.log_stride_num =\n-\t\t\t RTE_MIN(RTE_MAX(MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM,\n-\t\t\t\t\t mprq_min_stride_num_n),\n-\t\t\t\t mprq_max_stride_num_n);\n-\t\t\tDRV_LOG(WARNING,\n-\t\t\t\t\"the number of strides\"\n-\t\t\t\t\" for Multi-Packet RQ is out of range,\"\n-\t\t\t\t\" setting default value (%u)\",\n-\t\t\t\t1 << config->mprq.log_stride_num);\n-\t\t}\n-\t\tif (config->mprq.log_stride_size &&\n-\t\t (config->mprq.log_stride_size > mprq_max_stride_size_n ||\n-\t\t config->mprq.log_stride_size < mprq_min_stride_size_n)) {\n-\t\t\tconfig->mprq.log_stride_size =\n-\t\t\t RTE_MIN(RTE_MAX(MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE,\n-\t\t\t\t\t mprq_min_stride_size_n),\n-\t\t\t\t mprq_max_stride_size_n);\n-\t\t\tDRV_LOG(WARNING,\n-\t\t\t\t\"the size of a stride\"\n-\t\t\t\t\" for Multi-Packet RQ is out of range,\"\n-\t\t\t\t\" setting default value (%u)\",\n-\t\t\t\t1 << config->mprq.log_stride_size);\n-\t\t}\n-\t\tconfig->mprq.log_min_stride_size = mprq_min_stride_size_n;\n-\t\tconfig->mprq.log_max_stride_size = mprq_max_stride_size_n;\n-\t} else if (config->mprq.enabled && !mprq) {\n+\tif (config->mprq.enabled && !mprq) {\n \t\tDRV_LOG(WARNING, \"Multi-Packet RQ isn't supported\");\n \t\tconfig->mprq.enabled = 0;\n \t}\n@@ -2068,7 +2037,8 @@ mlx5_device_bond_pci_match(const char *ibdev_name,\n }\n \n static void\n-mlx5_os_config_default(struct mlx5_dev_config *config)\n+mlx5_os_config_default(struct mlx5_dev_config *config,\n+\t\t struct mlx5_common_dev_config *cconf)\n {\n \tmemset(config, 0, sizeof(*config));\n \tconfig->mps = MLX5_ARG_UNSET;\n@@ -2080,6 +2050,10 @@ mlx5_os_config_default(struct mlx5_dev_config *config)\n \tconfig->vf_nl_en = 1;\n \tconfig->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;\n \tconfig->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;\n+\tconfig->mprq.log_min_stride_wqe_size = cconf->devx ?\n+\t\t\t\t\tcconf->hca_attr.log_min_stride_wqe_sz :\n+\t\t\t\t\tMLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;\n+\tconfig->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM;\n \tconfig->dv_esw_en = 1;\n \tconfig->dv_flow_en = 1;\n \tconfig->decap_en = 1;\n@@ -2496,7 +2470,7 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev,\n \t\tuint32_t restore;\n \n \t\t/* Default configuration. */\n-\t\tmlx5_os_config_default(&dev_config);\n+\t\tmlx5_os_config_default(&dev_config, &cdev->config);\n \t\tdev_config.vf = dev_config_vf;\n \t\tlist[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i],\n \t\t\t\t\t\t &dev_config, ð_da);\n@@ -2666,7 +2640,7 @@ mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev)\n \tif (ret != 0)\n \t\treturn ret;\n \t/* Set default config data. */\n-\tmlx5_os_config_default(&config);\n+\tmlx5_os_config_default(&config, &cdev->config);\n \tconfig.sf = 1;\n \t/* Init spawn data. */\n \tspawn.max_port = 1;\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 4ba90db816..c01fb9566e 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -279,6 +279,10 @@ struct mlx5_dev_config {\n \t\tunsigned int log_stride_size; /* Log size of a stride. */\n \t\tunsigned int log_min_stride_size; /* Log min size of a stride.*/\n \t\tunsigned int log_max_stride_size; /* Log max size of a stride.*/\n+\t\tunsigned int log_min_stride_num; /* Log min num of strides. */\n+\t\tunsigned int log_max_stride_num; /* Log max num of strides. */\n+\t\tunsigned int log_min_stride_wqe_size;\n+\t\t/* Log min WQE size, (size of single stride)*(num of strides).*/\n \t\tunsigned int max_memcpy_len;\n \t\t/* Maximum packet size to memcpy Rx packets. */\n \t\tunsigned int min_rxqs_num;\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex e76bfaa000..891ac3d874 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -1528,6 +1528,126 @@ mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,\n \t\tpriv->max_lro_msg_size * MLX5_LRO_SEG_CHUNK_SIZE);\n }\n \n+/**\n+ * Prepare both size and number of stride for Multi-Packet RQ.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @param idx\n+ * RX queue index.\n+ * @param desc\n+ * Number of descriptors to configure in queue.\n+ * @param rx_seg_en\n+ * Indicator if Rx segment enables, if so Multi-Packet RQ doesn't enable.\n+ * @param min_mbuf_size\n+ * Non scatter min mbuf size, max_rx_pktlen plus overhead.\n+ * @param actual_log_stride_num\n+ * Log number of strides to configure for this queue.\n+ * @param actual_log_stride_size\n+ * Log stride size to configure for this queue.\n+ *\n+ * @return\n+ * 0 if Multi-Packet RQ is supported, otherwise -1.\n+ */\n+static int\n+mlx5_mprq_prepare(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,\n+\t\t bool rx_seg_en, uint32_t min_mbuf_size,\n+\t\t uint32_t *actual_log_stride_num,\n+\t\t uint32_t *actual_log_stride_size)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_config *config = &priv->config;\n+\tuint32_t log_min_stride_num = config->mprq.log_min_stride_num;\n+\tuint32_t log_max_stride_num = config->mprq.log_max_stride_num;\n+\tuint32_t log_def_stride_num =\n+\t\t\tRTE_MIN(RTE_MAX(MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM,\n+\t\t\t\t\tlog_min_stride_num),\n+\t\t\t\tlog_max_stride_num);\n+\tuint32_t log_min_stride_size = config->mprq.log_min_stride_size;\n+\tuint32_t log_max_stride_size = config->mprq.log_max_stride_size;\n+\tuint32_t log_def_stride_size =\n+\t\t\tRTE_MIN(RTE_MAX(MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE,\n+\t\t\t\t\tlog_min_stride_size),\n+\t\t\t\tlog_max_stride_size);\n+\tuint32_t log_stride_wqe_size;\n+\n+\tif (mlx5_check_mprq_support(dev) != 1 || rx_seg_en)\n+\t\tgoto unsupport;\n+\t/* Checks if chosen number of strides is in supported range. */\n+\tif (config->mprq.log_stride_num > log_max_stride_num ||\n+\t config->mprq.log_stride_num < log_min_stride_num) {\n+\t\t*actual_log_stride_num = log_def_stride_num;\n+\t\tDRV_LOG(WARNING,\n+\t\t\t\"Port %u Rx queue %u number of strides for Multi-Packet RQ is out of range, setting default value (%u)\",\n+\t\t\tdev->data->port_id, idx, RTE_BIT32(log_def_stride_num));\n+\t} else {\n+\t\t*actual_log_stride_num = config->mprq.log_stride_num;\n+\t}\n+\tif (config->mprq.log_stride_size) {\n+\t\t/* Checks if chosen size of stride is in supported range. */\n+\t\tif (config->mprq.log_stride_size > log_max_stride_size ||\n+\t\t config->mprq.log_stride_size < log_min_stride_size) {\n+\t\t\t*actual_log_stride_size = log_def_stride_size;\n+\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\"Port %u Rx queue %u size of a stride for Multi-Packet RQ is out of range, setting default value (%u)\",\n+\t\t\t\tdev->data->port_id, idx,\n+\t\t\t\tRTE_BIT32(log_def_stride_size));\n+\t\t} else {\n+\t\t\t*actual_log_stride_size = config->mprq.log_stride_size;\n+\t\t}\n+\t} else {\n+\t\tif (min_mbuf_size <= RTE_BIT32(log_max_stride_size))\n+\t\t\t*actual_log_stride_size = log2above(min_mbuf_size);\n+\t\telse\n+\t\t\tgoto unsupport;\n+\t}\n+\tlog_stride_wqe_size = *actual_log_stride_num + *actual_log_stride_size;\n+\t/* Check if WQE buffer size is supported by hardware. */\n+\tif (log_stride_wqe_size < config->mprq.log_min_stride_wqe_size) {\n+\t\t*actual_log_stride_num = log_def_stride_num;\n+\t\t*actual_log_stride_size = log_def_stride_size;\n+\t\tDRV_LOG(WARNING,\n+\t\t\t\"Port %u Rx queue %u size of WQE buffer for Multi-Packet RQ is too small, setting default values (stride_num_n=%u, stride_size_n=%u)\",\n+\t\t\tdev->data->port_id, idx, RTE_BIT32(log_def_stride_num),\n+\t\t\tRTE_BIT32(log_def_stride_size));\n+\t\tlog_stride_wqe_size = log_def_stride_num + log_def_stride_size;\n+\t}\n+\tMLX5_ASSERT(log_stride_wqe_size < config->mprq.log_min_stride_wqe_size);\n+\tif (desc <= RTE_BIT32(*actual_log_stride_num))\n+\t\tgoto unsupport;\n+\tif (min_mbuf_size > RTE_BIT32(log_stride_wqe_size)) {\n+\t\tDRV_LOG(WARNING, \"Port %u Rx queue %u \"\n+\t\t\t\"Multi-Packet RQ is unsupported, WQE buffer size (%u) \"\n+\t\t\t\"is smaller than min mbuf size (%u)\",\n+\t\t\tdev->data->port_id, idx, RTE_BIT32(log_stride_wqe_size),\n+\t\t\tmin_mbuf_size);\n+\t\tgoto unsupport;\n+\t}\n+\tDRV_LOG(DEBUG, \"Port %u Rx queue %u \"\n+\t\t\"Multi-Packet RQ is enabled strd_num_n = %u, strd_sz_n = %u\",\n+\t\tdev->data->port_id, idx, RTE_BIT32(*actual_log_stride_num),\n+\t\tRTE_BIT32(*actual_log_stride_size));\n+\treturn 0;\n+unsupport:\n+\tif (config->mprq.enabled)\n+\t\tDRV_LOG(WARNING,\n+\t\t\t\"Port %u MPRQ is requested but cannot be enabled\\n\"\n+\t\t\t\" (requested: pkt_sz = %u, desc_num = %u,\"\n+\t\t\t\" rxq_num = %u, stride_sz = %u, stride_num = %u\\n\"\n+\t\t\t\" supported: min_rxqs_num = %u, min_buf_wqe_sz = %u\"\n+\t\t\t\" min_stride_sz = %u, max_stride_sz = %u).\\n\"\n+\t\t\t\"Rx segment is %senable.\",\n+\t\t\tdev->data->port_id, min_mbuf_size, desc, priv->rxqs_n,\n+\t\t\tRTE_BIT32(config->mprq.log_stride_size),\n+\t\t\tRTE_BIT32(config->mprq.log_stride_num),\n+\t\t\tconfig->mprq.min_rxqs_num,\n+\t\t\tRTE_BIT32(config->mprq.log_min_stride_wqe_size),\n+\t\t\tRTE_BIT32(config->mprq.log_min_stride_size),\n+\t\t\tRTE_BIT32(config->mprq.log_max_stride_size),\n+\t\t\trx_seg_en ? \"\" : \"not \");\n+\treturn -1;\n+}\n+\n /**\n * Create a DPDK Rx queue.\n *\n@@ -1565,33 +1685,28 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \t\t\t\t\t\t\tRTE_PKTMBUF_HEADROOM;\n \tunsigned int max_lro_size = 0;\n \tunsigned int first_mb_free_size = mb_len - RTE_PKTMBUF_HEADROOM;\n-\tconst int mprq_en = mlx5_check_mprq_support(dev) > 0 && n_seg == 1 &&\n-\t\t\t !rx_seg[0].offset && !rx_seg[0].length;\n-\tunsigned int log_mprq_stride_nums = config->mprq.log_stride_num ?\n-\t\tconfig->mprq.log_stride_num : MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM;\n-\tunsigned int log_mprq_stride_size = non_scatter_min_mbuf_size <=\n-\t\tRTE_BIT32(config->mprq.log_max_stride_size) ?\n-\t\tlog2above(non_scatter_min_mbuf_size) :\n-\t\tMLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE;\n-\tunsigned int mprq_stride_cap = (config->mprq.log_stride_num ?\n-\t\t\t\t\tRTE_BIT32(config->mprq.log_stride_num) :\n-\t\t\t\t\tRTE_BIT32(log_mprq_stride_nums)) *\n-\t\t\t\t (config->mprq.log_stride_size ?\n-\t\t\t\t RTE_BIT32(config->mprq.log_stride_size) :\n-\t\t\t\t\tRTE_BIT32(log_mprq_stride_size));\n+\tuint32_t mprq_log_actual_stride_num = 0;\n+\tuint32_t mprq_log_actual_stride_size = 0;\n+\tbool rx_seg_en = n_seg != 1 || rx_seg[0].offset || rx_seg[0].length;\n+\tconst int mprq_en = !mlx5_mprq_prepare(dev, idx, desc, rx_seg_en,\n+\t\t\t\t\t non_scatter_min_mbuf_size,\n+\t\t\t\t\t &mprq_log_actual_stride_num,\n+\t\t\t\t\t &mprq_log_actual_stride_size);\n \t/*\n \t * Always allocate extra slots, even if eventually\n \t * the vector Rx will not be used.\n \t */\n \tuint16_t desc_n = desc + config->rx_vec_en * MLX5_VPMD_DESCS_PER_LOOP;\n+\tsize_t alloc_size = sizeof(*tmpl) + desc_n * sizeof(struct rte_mbuf *);\n \tconst struct rte_eth_rxseg_split *qs_seg = rx_seg;\n \tunsigned int tail_len;\n \n-\ttmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,\n-\t\tsizeof(*tmpl) + desc_n * sizeof(struct rte_mbuf *) +\n-\t\t(!!mprq_en) *\n-\t\t(desc >> log_mprq_stride_nums) * sizeof(struct mlx5_mprq_buf *),\n-\t\t0, socket);\n+\tif (mprq_en) {\n+\t\t/* Trim the number of descs needed. */\n+\t\tdesc >>= mprq_log_actual_stride_num;\n+\t\talloc_size += desc * sizeof(struct mlx5_mprq_buf *);\n+\t}\n+\ttmpl = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, alloc_size, 0, socket);\n \tif (!tmpl) {\n \t\trte_errno = ENOMEM;\n \t\treturn NULL;\n@@ -1689,30 +1804,11 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \ttmpl->socket = socket;\n \tif (dev->data->dev_conf.intr_conf.rxq)\n \t\ttmpl->irq = 1;\n-\t/*\n-\t * This Rx queue can be configured as a Multi-Packet RQ if all of the\n-\t * following conditions are met:\n-\t * - MPRQ is enabled.\n-\t * - The number of descs is more than the number of strides.\n-\t * - max_rx_pktlen plus overhead is less than the max size\n-\t * of a stride or log_mprq_stride_size is specified by a user.\n-\t * Need to make sure that there are enough strides to encap\n-\t * the maximum packet size in case log_mprq_stride_size is set.\n-\t * Otherwise, enable Rx scatter if necessary.\n-\t */\n-\tif (mprq_en && desc > RTE_BIT32(log_mprq_stride_nums) &&\n-\t (non_scatter_min_mbuf_size <=\n-\t RTE_BIT32(config->mprq.log_max_stride_size) ||\n-\t (config->mprq.log_stride_size &&\n-\t non_scatter_min_mbuf_size <= mprq_stride_cap))) {\n+\tif (mprq_en) {\n \t\t/* TODO: Rx scatter isn't supported yet. */\n \t\ttmpl->rxq.sges_n = 0;\n-\t\t/* Trim the number of descs needed. */\n-\t\tdesc >>= log_mprq_stride_nums;\n-\t\ttmpl->rxq.log_strd_num = config->mprq.log_stride_num ?\n-\t\t\tconfig->mprq.log_stride_num : log_mprq_stride_nums;\n-\t\ttmpl->rxq.log_strd_sz = config->mprq.log_stride_size ?\n-\t\t\tconfig->mprq.log_stride_size : log_mprq_stride_size;\n+\t\ttmpl->rxq.log_strd_num = mprq_log_actual_stride_num;\n+\t\ttmpl->rxq.log_strd_sz = mprq_log_actual_stride_size;\n \t\ttmpl->rxq.strd_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT;\n \t\ttmpl->rxq.strd_scatter_en =\n \t\t\t\t!!(offloads & RTE_ETH_RX_OFFLOAD_SCATTER);\n@@ -1721,11 +1817,6 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \t\tmax_lro_size = RTE_MIN(max_rx_pktlen,\n \t\t\t\t RTE_BIT32(tmpl->rxq.log_strd_num) *\n \t\t\t\t RTE_BIT32(tmpl->rxq.log_strd_sz));\n-\t\tDRV_LOG(DEBUG,\n-\t\t\t\"port %u Rx queue %u: Multi-Packet RQ is enabled\"\n-\t\t\t\" strd_num_n = %u, strd_sz_n = %u\",\n-\t\t\tdev->data->port_id, idx,\n-\t\t\ttmpl->rxq.log_strd_num, tmpl->rxq.log_strd_sz);\n \t} else if (tmpl->rxq.rxseg_n == 1) {\n \t\tMLX5_ASSERT(max_rx_pktlen <= first_mb_free_size);\n \t\ttmpl->rxq.sges_n = 0;\n@@ -1759,24 +1850,6 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \t\ttmpl->rxq.sges_n = sges_n;\n \t\tmax_lro_size = max_rx_pktlen;\n \t}\n-\tif (config->mprq.enabled && !mlx5_rxq_mprq_enabled(&tmpl->rxq))\n-\t\tDRV_LOG(WARNING,\n-\t\t\t\"port %u MPRQ is requested but cannot be enabled\\n\"\n-\t\t\t\" (requested: pkt_sz = %u, desc_num = %u,\"\n-\t\t\t\" rxq_num = %u, stride_sz = %u, stride_num = %u\\n\"\n-\t\t\t\" supported: min_rxqs_num = %u,\"\n-\t\t\t\" min_stride_sz = %u, max_stride_sz = %u).\",\n-\t\t\tdev->data->port_id, non_scatter_min_mbuf_size,\n-\t\t\tdesc, priv->rxqs_n,\n-\t\t\tconfig->mprq.log_stride_size ?\n-\t\t\t\tRTE_BIT32(config->mprq.log_stride_size) :\n-\t\t\t\tRTE_BIT32(log_mprq_stride_size),\n-\t\t\tconfig->mprq.log_stride_num ?\n-\t\t\t\tRTE_BIT32(config->mprq.log_stride_num) :\n-\t\t\t\tRTE_BIT32(log_mprq_stride_nums),\n-\t\t\tconfig->mprq.min_rxqs_num,\n-\t\t\tRTE_BIT32(config->mprq.log_min_stride_size),\n-\t\t\tRTE_BIT32(config->mprq.log_max_stride_size));\n \tDRV_LOG(DEBUG, \"port %u maximum number of segments per packet: %u\",\n \t\tdev->data->port_id, 1 << tmpl->rxq.sges_n);\n \tif (desc % (1 << tmpl->rxq.sges_n)) {\n@@ -1834,17 +1907,15 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \t\tdev->data->port_id,\n \t\ttmpl->rxq.crc_present ? \"disabled\" : \"enabled\",\n \t\ttmpl->rxq.crc_present << 2);\n-\t/* Save port ID. */\n \ttmpl->rxq.rss_hash = !!priv->rss_conf.rss_hf &&\n \t\t(!!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS));\n+\t/* Save port ID. */\n \ttmpl->rxq.port_id = dev->data->port_id;\n \ttmpl->sh = priv->sh;\n \ttmpl->rxq.mp = rx_seg[0].mp;\n \ttmpl->rxq.elts_n = log2above(desc);\n-\ttmpl->rxq.rq_repl_thresh =\n-\t\tMLX5_VPMD_RXQ_RPLNSH_THRESH(desc_n);\n-\ttmpl->rxq.elts =\n-\t\t(struct rte_mbuf *(*)[desc_n])(tmpl + 1);\n+\ttmpl->rxq.rq_repl_thresh = MLX5_VPMD_RXQ_RPLNSH_THRESH(desc_n);\n+\ttmpl->rxq.elts = (struct rte_mbuf *(*)[desc_n])(tmpl + 1);\n \ttmpl->rxq.mprq_bufs =\n \t\t(struct mlx5_mprq_buf *(*)[desc])(*tmpl->rxq.elts + desc_n);\n \ttmpl->rxq.idx = idx;\n", "prefixes": [ "3/3" ] }