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GET /api/patches/104657/?format=api
{ "id": 104657, "url": "http://patchwork.dpdk.org/api/patches/104657/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211124093556.3358394-5-dkozlyuk@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211124093556.3358394-5-dkozlyuk@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211124093556.3358394-5-dkozlyuk@nvidia.com", "date": "2021-11-24T09:35:55", "name": "[v2,1/2] net/mlx5: fix indirect RSS creation when port is stopped", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6f2952ab36a96b4620be63bda310e3c5c14b565f", "submitter": { "id": 2248, "url": "http://patchwork.dpdk.org/api/people/2248/?format=api", "name": "Dmitry Kozlyuk", "email": "dkozlyuk@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211124093556.3358394-5-dkozlyuk@nvidia.com/mbox/", "series": [ { "id": 20740, "url": "http://patchwork.dpdk.org/api/series/20740/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20740", "date": "2021-11-24T09:35:55", "name": "[v2,1/2] net/mlx5: fix indirect RSS creation when port is stopped", "version": 2, "mbox": "http://patchwork.dpdk.org/series/20740/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/104657/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/104657/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C250CA0C52;\n\tWed, 24 Nov 2021 10:36:42 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5818141163;\n\tWed, 24 Nov 2021 10:36:24 +0100 (CET)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2052.outbound.protection.outlook.com [40.107.237.52])\n by mails.dpdk.org (Postfix) with ESMTP id 5250D4114B\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Dmitry Kozlyuk <dkozlyuk@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Raslan Darawsheh <rasland@nvidia.com>, Matan Azrad <matan@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Subject": "[PATCH v2 1/2] net/mlx5: fix indirect RSS creation when port is\n stopped", "Date": "Wed, 24 Nov 2021 11:35:55 +0200", "Message-ID": "<20211124093556.3358394-5-dkozlyuk@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20211124093556.3358394-1-dkozlyuk@nvidia.com>", "References": "<20211123223159.3324247-1-dkozlyuk@nvidia.com>\n <20211124093556.3358394-1-dkozlyuk@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "ff02739e-4bdc-4923-c278-08d9af2dde3c", "X-MS-TrafficTypeDiagnostic": "BYAPR12MB2838:", "X-Microsoft-Antispam-PRVS": "\n <BYAPR12MB2838B7C40C8EDD62057AD533B9619@BYAPR12MB2838.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:3513;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n NjpFA4ydwylEJWCo+r3hx+QDYbpmUVDAsGclpjCR5BPi+KurYfmsGoRidfqEX2fP3QtJSwxC5k5W4inMM1+WieZZSQImaWrxx7T7dOPokeD4K0IhEzjrSKvYh4v3G8dpE4VAj18DDZagVYrm/JEGwZ31pySx7OXGQt+s5pnTCPzLnRqsdbo4fV8N9/Vu0mPmbfS4y1HHnyTetEQ/gd3yIIVSJSm5oKF8OHh+FkB8hzYjCNBSmbx+57RzWXP5vHof1rnKpDmVO14qQwtOsTkxNdISHJwns1CVw8FRbppCRWpCfPp/tqP7T3J+Ldp50qzhviKIKeCa0rkYGMzjqxodTUVsvk2bK1maL9AtUneZbeBrbyhV7v+er77XpAg2kUeJvXfy3YMfMUZHFMIx+d0V54Aa8katAtl7N9q/M1yuRY2GvK7qx0iOYOw42YBEmr6x1/PhJHu0EHp2keoTD4pJA9kU1MRRgN9OpLC4orba7i3oYhVr4bWUs/PTEdCmVpsWGK2XMLl8dvlVaVB055dNctLYXSu+hIhcDYipYQu0V551TFZ7fEck3zEkodKnNO+QVGC/cuzWbZSD7CuTT1l71oZr2HW3Sl7CE8Lm8ZfEt6PHEyTMcSEUPkETQ6ZX0O/2oebWnHlbubfo3B/KBJXLUonVIc+8iiYz+T3j9Rb4TUeOnKN18n4mmBPwMX8W+XnA9lq7eZCne/ARl2eWjddnKSQJhFQwODT+W3m5SywzIBw=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(26005)(8936002)(8676002)(426003)(186003)(508600001)(356005)(7636003)(316002)(1076003)(36860700001)(86362001)(6916009)(83380400001)(16526019)(4326008)(6666004)(54906003)(47076005)(5660300002)(2616005)(107886003)(6286002)(70206006)(55016003)(82310400004)(2906002)(336012)(7696005)(36756003)(70586007)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Nov 2021 09:36:18.5349 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ff02739e-4bdc-4923-c278-08d9af2dde3c", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT026.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR12MB2838", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "mlx5_ind_table_obj_setup() was incrementing RxQ reference counters\neven when the port was stopped, which prevented RxQ release\nand triggered an internal assertion.\nOnly increment reference counter when the port is started.\n\nFixes: ec4e11d41d12 (\"net/mlx5: preserve indirect actions on restart\")\n\nSigned-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>\nReviewed-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_dv.c | 3 ++-\n drivers/net/mlx5/mlx5_rx.h | 3 ++-\n drivers/net/mlx5/mlx5_rxq.c | 41 +++++++++++++++++++++------------\n 3 files changed, 30 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 9d4bd0560c..a8f63e22c4 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -14700,7 +14700,8 @@ __flow_dv_action_rss_setup(struct rte_eth_dev *dev,\n \tsize_t i;\n \tint err;\n \n-\tif (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {\n+\tif (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl,\n+\t\t\t\t !!dev->data->dev_started)) {\n \t\treturn rte_flow_error_set(error, rte_errno,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n \t\t\t\t\t \"cannot setup indirection table\");\ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex b19464bb37..283242f530 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -228,7 +228,8 @@ int mlx5_ind_table_obj_release(struct rte_eth_dev *dev,\n \t\t\t bool standalone,\n \t\t\t bool deref_rxqs);\n int mlx5_ind_table_obj_setup(struct rte_eth_dev *dev,\n-\t\t\t struct mlx5_ind_table_obj *ind_tbl);\n+\t\t\t struct mlx5_ind_table_obj *ind_tbl,\n+\t\t\t bool ref_qs);\n int mlx5_ind_table_obj_modify(struct rte_eth_dev *dev,\n \t\t\t struct mlx5_ind_table_obj *ind_tbl,\n \t\t\t uint16_t *queues, const uint32_t queues_n,\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 191f1e483f..2dd9490c36 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -2263,39 +2263,45 @@ mlx5_ind_table_obj_verify(struct rte_eth_dev *dev)\n * Pointer to Ethernet device.\n * @param ind_table\n * Indirection table to modify.\n+ * @param ref_qs\n+ * Whether to increment RxQ reference counters.\n *\n * @return\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n int\n mlx5_ind_table_obj_setup(struct rte_eth_dev *dev,\n-\t\t\t struct mlx5_ind_table_obj *ind_tbl)\n+\t\t\t struct mlx5_ind_table_obj *ind_tbl,\n+\t\t\t bool ref_qs)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tuint32_t queues_n = ind_tbl->queues_n;\n \tuint16_t *queues = ind_tbl->queues;\n-\tunsigned int i, j;\n+\tunsigned int i = 0, j;\n \tint ret = 0, err;\n \tconst unsigned int n = rte_is_power_of_2(queues_n) ?\n \t\t\t log2above(queues_n) :\n \t\t\t log2above(priv->config.ind_table_max_size);\n \n-\tfor (i = 0; i != queues_n; ++i) {\n-\t\tif (mlx5_rxq_ref(dev, queues[i]) == NULL) {\n-\t\t\tret = -rte_errno;\n-\t\t\tgoto error;\n+\tif (ref_qs)\n+\t\tfor (i = 0; i != queues_n; ++i) {\n+\t\t\tif (mlx5_rxq_ref(dev, queues[i]) == NULL) {\n+\t\t\t\tret = -rte_errno;\n+\t\t\t\tgoto error;\n+\t\t\t}\n \t\t}\n-\t}\n \tret = priv->obj_ops.ind_table_new(dev, n, ind_tbl);\n \tif (ret)\n \t\tgoto error;\n \t__atomic_fetch_add(&ind_tbl->refcnt, 1, __ATOMIC_RELAXED);\n \treturn 0;\n error:\n-\terr = rte_errno;\n-\tfor (j = 0; j < i; j++)\n-\t\tmlx5_rxq_deref(dev, ind_tbl->queues[j]);\n-\trte_errno = err;\n+\tif (ref_qs) {\n+\t\terr = rte_errno;\n+\t\tfor (j = 0; j < i; j++)\n+\t\t\tmlx5_rxq_deref(dev, queues[j]);\n+\t\trte_errno = err;\n+\t}\n \tDRV_LOG(DEBUG, \"Port %u cannot setup indirection table.\",\n \t\tdev->data->port_id);\n \treturn ret;\n@@ -2312,13 +2318,15 @@ mlx5_ind_table_obj_setup(struct rte_eth_dev *dev,\n * Number of queues in the array.\n * @param standalone\n * Indirection table for Standalone queue.\n+ * @param ref_qs\n+ * Whether to increment RxQ reference counters.\n *\n * @return\n * The Verbs/DevX object initialized, NULL otherwise and rte_errno is set.\n */\n static struct mlx5_ind_table_obj *\n mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,\n-\t\t uint32_t queues_n, bool standalone)\n+\t\t uint32_t queues_n, bool standalone, bool ref_qs)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_ind_table_obj *ind_tbl;\n@@ -2333,7 +2341,7 @@ mlx5_ind_table_obj_new(struct rte_eth_dev *dev, const uint16_t *queues,\n \tind_tbl->queues_n = queues_n;\n \tind_tbl->queues = (uint16_t *)(ind_tbl + 1);\n \tmemcpy(ind_tbl->queues, queues, queues_n * sizeof(*queues));\n-\tret = mlx5_ind_table_obj_setup(dev, ind_tbl);\n+\tret = mlx5_ind_table_obj_setup(dev, ind_tbl, ref_qs);\n \tif (ret < 0) {\n \t\tmlx5_free(ind_tbl);\n \t\treturn NULL;\n@@ -2537,6 +2545,7 @@ mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hrxq_idx,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_hrxq *hrxq =\n \t\tmlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], hrxq_idx);\n+\tbool dev_started = !!dev->data->dev_started;\n \tint ret;\n \n \tif (!hrxq) {\n@@ -2565,7 +2574,8 @@ mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hrxq_idx,\n \t\tind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);\n \t\tif (!ind_tbl)\n \t\t\tind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n,\n-\t\t\t\t\t\t\t hrxq->standalone);\n+\t\t\t\t\t\t\t hrxq->standalone,\n+\t\t\t\t\t\t\t dev_started);\n \t}\n \tif (!ind_tbl) {\n \t\trte_errno = ENOMEM;\n@@ -2657,7 +2667,8 @@ __mlx5_hrxq_create(struct rte_eth_dev *dev,\n \t\tind_tbl = mlx5_ind_table_obj_get(dev, queues, queues_n);\n \tif (!ind_tbl)\n \t\tind_tbl = mlx5_ind_table_obj_new(dev, queues, queues_n,\n-\t\t\t\t\t\t standalone);\n+\t\t\t\t\t\t standalone,\n+\t\t\t\t\t\t !!dev->data->dev_started);\n \tif (!ind_tbl)\n \t\treturn NULL;\n \thrxq = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_HRXQ], &hrxq_idx);\n", "prefixes": [ "v2", "1/2" ] }