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GET /api/patches/104675/?format=api
{ "id": 104675, "url": "http://patchwork.dpdk.org/api/patches/104675/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211124143316.30449-1-viacheslavo@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211124143316.30449-1-viacheslavo@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211124143316.30449-1-viacheslavo@nvidia.com", "date": "2021-11-24T14:33:16", "name": "net/mlx5: fix shared Rx queue segment configuration match", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "89cb6136917df262fa6d209479f044d6b7737973", "submitter": { "id": 1926, "url": "http://patchwork.dpdk.org/api/people/1926/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211124143316.30449-1-viacheslavo@nvidia.com/mbox/", "series": [ { "id": 20756, "url": "http://patchwork.dpdk.org/api/series/20756/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20756", "date": "2021-11-24T14:33:16", "name": "net/mlx5: fix shared Rx queue segment configuration match", "version": 1, "mbox": "http://patchwork.dpdk.org/series/20756/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/104675/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/104675/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F40A0A0C52;\n\tWed, 24 Nov 2021 15:33:37 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8E2A740E78;\n\tWed, 24 Nov 2021 15:33:37 +0100 (CET)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2043.outbound.protection.outlook.com [40.107.220.43])\n by mails.dpdk.org (Postfix) with ESMTP id EDE664003C\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>, <xuemingl@nvidia.com>, <rasland@nvidia.com>,\n <matan@nvidia.com>", "Subject": "[PATCH] net/mlx5: fix shared Rx queue segment configuration match", "Date": "Wed, 24 Nov 2021 16:33:16 +0200", "Message-ID": "<20211124143316.30449-1-viacheslavo@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "521f69bb-9eef-44e2-e4a2-08d9af576483", "X-MS-TrafficTypeDiagnostic": "SN6PR12MB4687:", "X-Microsoft-Antispam-PRVS": "\n <SN6PR12MB4687ECBA50C89116BF2772DDDF619@SN6PR12MB4687.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:6790;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n W16m3JmK951EocKO/+rIIXX7r3HujnR8y5On5viPd8G9zwgOw7Be+hflYn96aArx/UhyyNIfVInJd8VdJ1h8kN31Z+EOyWE2vDl7yYF88deQkDV4LlYFg2evzo8ymYlx+yhKRzH2tdNeNadPCPac68/jKTbWa/cdqWGCJTDgFOiPJ4qYU0XfGHlwuMH+Bzk3iqwSdNTezX/X+3ydXhmsUoXVz1R3/n7axHhX0+yrQNGbGPxF1LkJWRvg0skT82Vq/aS06Z9YWHSqDjdTIpLUyxvS9TcjVUdtDeAQ5z/02Vqx32otv1zWQRAe/sh+xSitkza1bH6cF0kf9s/AGb6ENVjy8O2FpyB6iGgaP3YmvWLfUNOAdY3CEq1nY0SZ2+GgUfmQ+Mr+ZOEGS5JyhWoysLJ7vBh8SfsNmwhYMTjPGamiRpw14FE0dCo6WnYbP1finaybeypIqFoj7KLBI3dzypwopgoqp3dgy19kN0hyI/iodHqtMdh4lzbzpwzffCOjBZUYCA3xYW6/Ze64q3rmhbTZkaBjGPspYjw4CxgnMz2Kpoe6hqyjqanqRIHsdou3sMGJmHzNdIkM4FWKwe1hV/43DT2d6+wnopmFARDohaL77jmIpj35hhhTt4PKxQG0zlz1Z10gV1+dRZPfI+RK+0s03QMQcxasJFlhzzzucfcoqPJYLGaJ2F6ZdOlr5MPk7YJdTSD5pbtGtYmZBk9ccA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(36840700001)(46966006)(316002)(5660300002)(70206006)(55016003)(82310400004)(70586007)(6666004)(8936002)(356005)(4326008)(16526019)(6286002)(36756003)(107886003)(426003)(47076005)(2616005)(83380400001)(7696005)(86362001)(7636003)(2906002)(8676002)(336012)(6916009)(26005)(1076003)(36860700001)(54906003)(508600001)(186003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Nov 2021 14:33:33.1937 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 521f69bb-9eef-44e2-e4a2-08d9af576483", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT063.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN6PR12MB4687", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "While joining the shared Rx queue to the existing queue group\nthe queue configurations is checked to be the same as it was\nspecified in the first group queue creation - all shared\nqueues should be created with identical configurations.\n\nDuring the Rx queue creation the buffer split segment\nconfiguration can be altered - the zero segment sizes are\nsubstituted with the actual ones, inherited from the pools,\nnumber of segments can be extended to cover the maximal\npacket length, etc. It means the actual queue segment\nconfiguration can not be used directly to match the\nconfiguration provided in the queue setup call.\n\nTo resolve an issue we should store original parameters\nin the shared queue structure and perform the check against\none these stored ones.\n\nFixes: 09c2555303be (\"net/mlx5: support shared Rx queue\")\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rx.h | 3 +++\n drivers/net/mlx5/mlx5_rxq.c | 18 ++++++++++++++----\n 2 files changed, 17 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex b19464bb37..a2dda91fc7 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -164,6 +164,9 @@ struct mlx5_rxq_ctrl {\n \tuint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */\n \tuint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */\n \tuint32_t wqn; /* WQ number. */\n+\tuint32_t rxseg_n; /* Number of split segment descriptions. */\n+\tstruct rte_eth_rxseg_split rxseg[MLX5_MAX_RXQ_NSEG];\n+\t/* Saved original buffer split segment configuration. */\n \tuint16_t dump_file_n; /* Number of dump files. */\n };\n \ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 191f1e483f..c3ede0108f 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -775,11 +775,14 @@ mlx5_shared_rxq_match(struct mlx5_rxq_ctrl *rxq_ctrl, struct rte_eth_dev *dev,\n \t\t\tdev->data->port_id, idx);\n \t\treturn false;\n \t} else if (mp == NULL) {\n+\t\tif (conf->rx_nseg != rxq_ctrl->rxseg_n) {\n+\t\t\tDRV_LOG(ERR, \"port %u queue index %u failed to join shared group: segment number mismatch\",\n+\t\t\t\tdev->data->port_id, idx);\n+\t\t\treturn false;\n+\t\t}\n \t\tfor (i = 0; i < conf->rx_nseg; i++) {\n-\t\t\tif (conf->rx_seg[i].split.mp !=\n-\t\t\t rxq_ctrl->rxq.rxseg[i].mp ||\n-\t\t\t conf->rx_seg[i].split.length !=\n-\t\t\t rxq_ctrl->rxq.rxseg[i].length) {\n+\t\t\tif (memcmp(&conf->rx_seg[i].split, &rxq_ctrl->rxseg[i],\n+\t\t\t\t sizeof(struct rte_eth_rxseg_split))) {\n \t\t\t\tDRV_LOG(ERR, \"port %u queue index %u failed to join shared group: segment %u configuration mismatch\",\n \t\t\t\t\tdev->data->port_id, idx, i);\n \t\t\t\treturn false;\n@@ -1602,6 +1605,13 @@ mlx5_rxq_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \trxq->ctrl = tmpl;\n \tLIST_INSERT_HEAD(&tmpl->owners, rxq, owner_entry);\n \tMLX5_ASSERT(n_seg && n_seg <= MLX5_MAX_RXQ_NSEG);\n+\t/*\n+\t * Save the original segment confgiuration in the shared queue\n+\t * descriptor for the later check on the sibling queue creation.\n+\t */\n+\ttmpl->rxseg_n = n_seg;\n+\trte_memcpy(tmpl->rxseg, qs_seg,\n+\t\t sizeof(struct rte_eth_rxseg_split) * n_seg);\n \t/*\n \t * Build the array of actual buffer offsets and lengths.\n \t * Pad with the buffers from the last memory pool if\n", "prefixes": [] }