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{
    "id": 104767,
    "url": "http://patchwork.dpdk.org/api/patches/104767/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211130053822.2696736-1-asekhar@marvell.com/",
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    "msgid": "<20211130053822.2696736-1-asekhar@marvell.com>",
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    "date": "2021-11-30T05:38:22",
    "name": "common/cnxk: ensure ROC cache alignment of NPA stack size",
    "commit_ref": null,
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    "hash": "7e2d31b9a40240b7be887a7a05a33dc4d674e627",
    "submitter": {
        "id": 2125,
        "url": "http://patchwork.dpdk.org/api/people/2125/?format=api",
        "name": "Ashwin Sekhar T K",
        "email": "asekhar@marvell.com"
    },
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        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
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    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211130053822.2696736-1-asekhar@marvell.com/mbox/",
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        {
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            "url": "http://patchwork.dpdk.org/api/series/20809/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20809",
            "date": "2021-11-30T05:38:22",
            "name": "common/cnxk: ensure ROC cache alignment of NPA stack size",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/20809/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/104767/comments/",
    "check": "fail",
    "checks": "http://patchwork.dpdk.org/api/patches/104767/checks/",
    "tags": {},
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        "From": "Ashwin Sekhar T K <asekhar@marvell.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<ndabilpuram@marvell.com>, <jerinj@marvell.com>, <skori@marvell.com>,\n <skoteshwar@marvell.com>, <pbhagavatula@marvell.com>,\n <kirankumark@marvell.com>, <psatheesh@marvell.com>,\n <asekhar@marvell.com>, <anoobj@marvell.com>, <gakhil@marvell.com>",
        "Subject": "[PATCH] common/cnxk: ensure ROC cache alignment of NPA stack size",
        "Date": "Tue, 30 Nov 2021 11:08:22 +0530",
        "Message-ID": "<20211130053822.2696736-1-asekhar@marvell.com>",
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    },
    "content": "When PLT_CACHE_LINE_SIZE is set to 64B, the memzone size reserved for\nNPA stack could be a multiple of 64B. In such a case, when NDC SYNC\nis initiated for the NPA LF, it could go and corrupt an additional\n64B bytes as NDC flushes in multiples of ROC cache line size (128B).\n\nSo ensure that NPA stack size requested is a multiple of 128B.\n\nSigned-off-by: Ashwin Sekhar T K <asekhar@marvell.com>\n---\n drivers/common/cnxk/roc_npa.c | 1 +\n 1 file changed, 1 insertion(+)",
    "diff": "diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c\nindex efcb7582eb..75fc22442f 100644\n--- a/drivers/common/cnxk/roc_npa.c\n+++ b/drivers/common/cnxk/roc_npa.c\n@@ -205,6 +205,7 @@ static inline const struct plt_memzone *\n npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)\n {\n \tconst char *mz_name = npa_stack_memzone_name(lf, pool_id, name);\n+\tsize = PLT_ALIGN_CEIL(size, ROC_ALIGN);\n \n \treturn plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);\n }\n",
    "prefixes": []
}