Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/104902/?format=api
{ "id": 104902, "url": "http://patchwork.dpdk.org/api/patches/104902/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211206083542.3115019-1-jerinj@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211206083542.3115019-1-jerinj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211206083542.3115019-1-jerinj@marvell.com", "date": "2021-12-06T08:35:41", "name": "[v1] drivers: remove octeontx2 drivers", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "44953adc739bba133c384f2264cb52e9ded430b3", "submitter": { "id": 1188, "url": "http://patchwork.dpdk.org/api/people/1188/?format=api", "name": "Jerin Jacob Kollanukkaran", "email": "jerinj@marvell.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211206083542.3115019-1-jerinj@marvell.com/mbox/", "series": [ { "id": 20865, "url": "http://patchwork.dpdk.org/api/series/20865/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20865", "date": "2021-12-06T08:35:41", "name": "[v1] drivers: remove octeontx2 drivers", "version": 1, "mbox": "http://patchwork.dpdk.org/series/20865/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/104902/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/104902/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0DB33A034F;\n\tMon, 6 Dec 2021 10:50:45 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 803704013F;\n\tMon, 6 Dec 2021 10:50:44 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 407C340040\n for <dev@dpdk.org>; Mon, 6 Dec 2021 09:40:10 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1B5MOkSZ031530;\n Mon, 6 Dec 2021 00:39:58 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cs0qn2bhc-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 06 Dec 2021 00:39:57 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 6 Dec 2021 00:39:53 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 6 Dec 2021 00:39:53 -0800", "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n by maili.marvell.com (Postfix) with ESMTP id 757C03F704A;\n Mon, 6 Dec 2021 00:39:45 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : mime-version : content-type :\n content-transfer-encoding; s=pfpt0220;\n bh=eiW8KlerVETm0vMN2C9ms1ZpO3EnhdYA1wOih+Of92U=;\n b=OiJNf8tbebh/3pKdCJicOo6yydDwXski8CyPvza5GOULj4dLcv/3431htllln9hJ0M4f\n 7NYirNOw2Y4Og4cX5Y8n5KOS4XpC+yGSTLDygL1IVjGCTELWXnBHNCt6DVCnXSOajfN7\n VGIcMVdUxXU508pROwj7DSrS6a7Q6txVBX6dnLlTxP33NDxUvZn1CG4ZTF3OsoCRLr4g\n FxGdhdkodYGVVMUK7ntE63uwCnxlj9WpMZyizHHKdhh1OtuVmHUzHqM+sNVbGNHbr3Rq\n 3hymggA8FD/rqp3h94Q3+TZoDHXs93Y70YI5U0dyiYPNWGmEjtCfdSburJ1L5awSR1zm 4g==", "From": "<jerinj@marvell.com>", "To": "<dev@dpdk.org>, Thomas Monjalon <thomas@monjalon.net>, Akhil Goyal\n <gakhil@marvell.com>, Declan Doherty <declan.doherty@intel.com>,\n Jerin Jacob <jerinj@marvell.com>, Ruifeng Wang <ruifeng.wang@arm.com>,\n Jan Viktorin <viktorin@rehivetech.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n \"Ray Kinsella\" <mdr@ashroe.eu>, Radha Mohan Chintakuntla\n <radhac@marvell.com>, Veerasenareddy Burru <vburru@marvell.com>, Nithin\n Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, \"Sunil Kumar Kori\" <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, \"Nalla Pradeep\" <pnalla@marvell.com>,\n Ciara Power <ciara.power@intel.com>,\n \"Pavan Nikhilesh\" <pbhagavatula@marvell.com>,\n Shijith Thotton <sthotton@marvell.com>, Ashwin Sekhar T K\n <asekhar@marvell.com>, Anatoly Burakov <anatoly.burakov@intel.com>", "CC": "<ferruh.yigit@intel.com>, <sburla@marvell.com>, <lironh@marvell.com>", "Subject": "[dpdk-dev] [PATCH v1] drivers: remove octeontx2 drivers", "Date": "Mon, 6 Dec 2021 14:05:41 +0530", "Message-ID": "<20211206083542.3115019-1-jerinj@marvell.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-GUID": "pQ9iJZx9ng-WIUVnxXu1fqVErlVe9jzX", "X-Proofpoint-ORIG-GUID": "pQ9iJZx9ng-WIUVnxXu1fqVErlVe9jzX", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-06_03,2021-12-06_01,2021-12-02_01", "X-Mailman-Approved-At": "Mon, 06 Dec 2021 10:50:43 +0100", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nAs per the deprecation notice, In the view of enabling unified driver\nfor octeontx2(cn9k)/octeontx3(cn10k), removing drivers/octeontx2\ndrivers and replace with drivers/cnxk/ which\nsupports both octeontx2(cn9k) and octeontx3(cn10k) SoCs.\n\nThis patch does the following\n\n- Replace drivers/common/octeontx2/ with drivers/common/cnxk/\n- Replace drivers/mempool/octeontx2/ with drivers/mempool/cnxk/\n- Replace drivers/net/octeontx2/ with drivers/net/cnxk/\n- Replace drivers/event/octeontx2/ with drivers/event/cnxk/\n- Replace drivers/crypto/octeontx2/ with drivers/crypto/cnxk/\n- Rename config/arm/arm64_octeontx2_linux_gcc as\n config/arm/arm64_cn9k_linux_gcc\n- Update the documentation and MAINTAINERS to reflect the same.\n- Change the reference to OCTEONTX2 as OCTEON 9. The kernel related\ndocumentation is not accounted for this change as kernel documentation\nstill uses OCTEONTX2.\n\nDepends-on: series-20804 (\"common/cnxk: add REE HW definitions\")\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\n---\n MAINTAINERS | 37 -\n app/test/meson.build | 1 -\n app/test/test_cryptodev.c | 7 -\n app/test/test_cryptodev.h | 1 -\n app/test/test_cryptodev_asym.c | 17 -\n app/test/test_eventdev.c | 8 -\n config/arm/arm64_cn10k_linux_gcc | 1 -\n ...teontx2_linux_gcc => arm64_cn9k_linux_gcc} | 3 +-\n config/arm/meson.build | 10 +-\n devtools/check-abi.sh | 4 +\n doc/guides/cryptodevs/features/octeontx2.ini | 87 -\n doc/guides/cryptodevs/index.rst | 1 -\n doc/guides/cryptodevs/octeontx2.rst | 188 -\n doc/guides/dmadevs/cnxk.rst | 2 +-\n doc/guides/eventdevs/features/octeontx2.ini | 30 -\n doc/guides/eventdevs/index.rst | 1 -\n doc/guides/eventdevs/octeontx2.rst | 178 -\n doc/guides/mempool/index.rst | 1 -\n doc/guides/mempool/octeontx2.rst | 92 -\n doc/guides/nics/cnxk.rst | 4 +-\n doc/guides/nics/features/octeontx2.ini | 97 -\n doc/guides/nics/features/octeontx2_vec.ini | 48 -\n doc/guides/nics/features/octeontx2_vf.ini | 45 -\n doc/guides/nics/index.rst | 1 -\n doc/guides/nics/octeontx2.rst | 465 ---\n doc/guides/nics/octeontx_ep.rst | 4 +-\n doc/guides/platform/cnxk.rst | 12 +\n .../octeontx2_packet_flow_hw_accelerators.svg | 2804 --------------\n .../img/octeontx2_resource_virtualization.svg | 2418 ------------\n doc/guides/platform/index.rst | 1 -\n doc/guides/platform/octeontx2.rst | 520 ---\n doc/guides/rel_notes/deprecation.rst | 17 -\n doc/guides/rel_notes/release_19_08.rst | 12 +-\n doc/guides/rel_notes/release_19_11.rst | 6 +-\n doc/guides/rel_notes/release_20_02.rst | 8 +-\n doc/guides/rel_notes/release_20_05.rst | 4 +-\n doc/guides/rel_notes/release_20_08.rst | 6 +-\n doc/guides/rel_notes/release_20_11.rst | 8 +-\n doc/guides/rel_notes/release_21_02.rst | 10 +-\n doc/guides/rel_notes/release_21_05.rst | 6 +-\n doc/guides/rel_notes/release_21_11.rst | 2 +-\n doc/guides/tools/cryptoperf.rst | 1 -\n drivers/common/meson.build | 1 -\n drivers/common/octeontx2/hw/otx2_nix.h | 1391 -------\n drivers/common/octeontx2/hw/otx2_npa.h | 305 --\n drivers/common/octeontx2/hw/otx2_npc.h | 503 ---\n drivers/common/octeontx2/hw/otx2_ree.h | 27 -\n drivers/common/octeontx2/hw/otx2_rvu.h | 219 --\n drivers/common/octeontx2/hw/otx2_sdp.h | 184 -\n drivers/common/octeontx2/hw/otx2_sso.h | 209 --\n drivers/common/octeontx2/hw/otx2_ssow.h | 56 -\n drivers/common/octeontx2/hw/otx2_tim.h | 34 -\n drivers/common/octeontx2/meson.build | 24 -\n drivers/common/octeontx2/otx2_common.c | 216 --\n drivers/common/octeontx2/otx2_common.h | 179 -\n drivers/common/octeontx2/otx2_dev.c | 1074 ------\n drivers/common/octeontx2/otx2_dev.h | 161 -\n drivers/common/octeontx2/otx2_io_arm64.h | 114 -\n drivers/common/octeontx2/otx2_io_generic.h | 75 -\n drivers/common/octeontx2/otx2_irq.c | 288 --\n drivers/common/octeontx2/otx2_irq.h | 28 -\n drivers/common/octeontx2/otx2_mbox.c | 465 ---\n drivers/common/octeontx2/otx2_mbox.h | 1958 ----------\n drivers/common/octeontx2/otx2_sec_idev.c | 183 -\n drivers/common/octeontx2/otx2_sec_idev.h | 43 -\n drivers/common/octeontx2/version.map | 44 -\n drivers/crypto/meson.build | 1 -\n drivers/crypto/octeontx2/meson.build | 30 -\n drivers/crypto/octeontx2/otx2_cryptodev.c | 188 -\n drivers/crypto/octeontx2/otx2_cryptodev.h | 63 -\n .../octeontx2/otx2_cryptodev_capabilities.c | 924 -----\n .../octeontx2/otx2_cryptodev_capabilities.h | 45 -\n .../octeontx2/otx2_cryptodev_hw_access.c | 225 --\n .../octeontx2/otx2_cryptodev_hw_access.h | 161 -\n .../crypto/octeontx2/otx2_cryptodev_mbox.c | 285 --\n .../crypto/octeontx2/otx2_cryptodev_mbox.h | 37 -\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 1438 -------\n drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 15 -\n .../octeontx2/otx2_cryptodev_ops_helper.h | 82 -\n drivers/crypto/octeontx2/otx2_cryptodev_qp.h | 46 -\n drivers/crypto/octeontx2/otx2_cryptodev_sec.c | 655 ----\n drivers/crypto/octeontx2/otx2_cryptodev_sec.h | 64 -\n .../crypto/octeontx2/otx2_ipsec_anti_replay.h | 227 --\n drivers/crypto/octeontx2/otx2_ipsec_fp.h | 371 --\n drivers/crypto/octeontx2/otx2_ipsec_po.h | 447 ---\n drivers/crypto/octeontx2/otx2_ipsec_po_ops.h | 167 -\n drivers/crypto/octeontx2/otx2_security.h | 37 -\n drivers/crypto/octeontx2/version.map | 13 -\n drivers/event/cnxk/cn9k_eventdev.c | 10 +\n drivers/event/meson.build | 1 -\n drivers/event/octeontx2/meson.build | 26 -\n drivers/event/octeontx2/otx2_evdev.c | 1900 ----------\n drivers/event/octeontx2/otx2_evdev.h | 430 ---\n drivers/event/octeontx2/otx2_evdev_adptr.c | 656 ----\n .../event/octeontx2/otx2_evdev_crypto_adptr.c | 132 -\n .../octeontx2/otx2_evdev_crypto_adptr_rx.h | 77 -\n .../octeontx2/otx2_evdev_crypto_adptr_tx.h | 83 -\n drivers/event/octeontx2/otx2_evdev_irq.c | 272 --\n drivers/event/octeontx2/otx2_evdev_selftest.c | 1517 --------\n drivers/event/octeontx2/otx2_evdev_stats.h | 286 --\n drivers/event/octeontx2/otx2_tim_evdev.c | 735 ----\n drivers/event/octeontx2/otx2_tim_evdev.h | 256 --\n drivers/event/octeontx2/otx2_tim_worker.c | 192 -\n drivers/event/octeontx2/otx2_tim_worker.h | 598 ---\n drivers/event/octeontx2/otx2_worker.c | 372 --\n drivers/event/octeontx2/otx2_worker.h | 339 --\n drivers/event/octeontx2/otx2_worker_dual.c | 345 --\n drivers/event/octeontx2/otx2_worker_dual.h | 110 -\n drivers/event/octeontx2/version.map | 3 -\n drivers/mempool/cnxk/cnxk_mempool.c | 56 +-\n drivers/mempool/meson.build | 1 -\n drivers/mempool/octeontx2/meson.build | 18 -\n drivers/mempool/octeontx2/otx2_mempool.c | 457 ---\n drivers/mempool/octeontx2/otx2_mempool.h | 221 --\n .../mempool/octeontx2/otx2_mempool_debug.c | 135 -\n drivers/mempool/octeontx2/otx2_mempool_irq.c | 303 --\n drivers/mempool/octeontx2/otx2_mempool_ops.c | 901 -----\n drivers/mempool/octeontx2/version.map | 8 -\n drivers/net/cnxk/cn9k_ethdev.c | 15 +\n drivers/net/meson.build | 1 -\n drivers/net/octeontx2/meson.build | 47 -\n drivers/net/octeontx2/otx2_ethdev.c | 2814 --------------\n drivers/net/octeontx2/otx2_ethdev.h | 619 ---\n drivers/net/octeontx2/otx2_ethdev_debug.c | 811 ----\n drivers/net/octeontx2/otx2_ethdev_devargs.c | 215 --\n drivers/net/octeontx2/otx2_ethdev_irq.c | 493 ---\n drivers/net/octeontx2/otx2_ethdev_ops.c | 589 ---\n drivers/net/octeontx2/otx2_ethdev_sec.c | 923 -----\n drivers/net/octeontx2/otx2_ethdev_sec.h | 130 -\n drivers/net/octeontx2/otx2_ethdev_sec_tx.h | 182 -\n drivers/net/octeontx2/otx2_flow.c | 1189 ------\n drivers/net/octeontx2/otx2_flow.h | 414 --\n drivers/net/octeontx2/otx2_flow_ctrl.c | 252 --\n drivers/net/octeontx2/otx2_flow_dump.c | 595 ---\n drivers/net/octeontx2/otx2_flow_parse.c | 1239 ------\n drivers/net/octeontx2/otx2_flow_utils.c | 969 -----\n drivers/net/octeontx2/otx2_link.c | 287 --\n drivers/net/octeontx2/otx2_lookup.c | 352 --\n drivers/net/octeontx2/otx2_mac.c | 151 -\n drivers/net/octeontx2/otx2_mcast.c | 339 --\n drivers/net/octeontx2/otx2_ptp.c | 450 ---\n drivers/net/octeontx2/otx2_rss.c | 427 ---\n drivers/net/octeontx2/otx2_rx.c | 430 ---\n drivers/net/octeontx2/otx2_rx.h | 583 ---\n drivers/net/octeontx2/otx2_stats.c | 397 --\n drivers/net/octeontx2/otx2_tm.c | 3317 -----------------\n drivers/net/octeontx2/otx2_tm.h | 176 -\n drivers/net/octeontx2/otx2_tx.c | 1077 ------\n drivers/net/octeontx2/otx2_tx.h | 791 ----\n drivers/net/octeontx2/otx2_vlan.c | 1035 -----\n drivers/net/octeontx2/version.map | 3 -\n drivers/net/octeontx_ep/otx2_ep_vf.h | 2 +-\n drivers/net/octeontx_ep/otx_ep_common.h | 16 +-\n drivers/net/octeontx_ep/otx_ep_ethdev.c | 8 +-\n drivers/net/octeontx_ep/otx_ep_rxtx.c | 10 +-\n usertools/dpdk-devbind.py | 12 +-\n 156 files changed, 121 insertions(+), 52149 deletions(-)\n rename config/arm/{arm64_octeontx2_linux_gcc => arm64_cn9k_linux_gcc} (84%)\n delete mode 100644 doc/guides/cryptodevs/features/octeontx2.ini\n delete mode 100644 doc/guides/cryptodevs/octeontx2.rst\n delete mode 100644 doc/guides/eventdevs/features/octeontx2.ini\n delete mode 100644 doc/guides/eventdevs/octeontx2.rst\n delete mode 100644 doc/guides/mempool/octeontx2.rst\n delete mode 100644 doc/guides/nics/features/octeontx2.ini\n delete mode 100644 doc/guides/nics/features/octeontx2_vec.ini\n delete mode 100644 doc/guides/nics/features/octeontx2_vf.ini\n delete mode 100644 doc/guides/nics/octeontx2.rst\n delete mode 100644 doc/guides/platform/img/octeontx2_packet_flow_hw_accelerators.svg\n delete mode 100644 doc/guides/platform/img/octeontx2_resource_virtualization.svg\n delete mode 100644 doc/guides/platform/octeontx2.rst\n delete mode 100644 drivers/common/octeontx2/hw/otx2_nix.h\n delete mode 100644 drivers/common/octeontx2/hw/otx2_npa.h\n delete mode 100644 drivers/common/octeontx2/hw/otx2_npc.h\n delete mode 100644 drivers/common/octeontx2/hw/otx2_ree.h\n delete mode 100644 drivers/common/octeontx2/hw/otx2_rvu.h\n delete mode 100644 drivers/common/octeontx2/hw/otx2_sdp.h\n delete mode 100644 drivers/common/octeontx2/hw/otx2_sso.h\n delete mode 100644 drivers/common/octeontx2/hw/otx2_ssow.h\n delete mode 100644 drivers/common/octeontx2/hw/otx2_tim.h\n delete mode 100644 drivers/common/octeontx2/meson.build\n delete mode 100644 drivers/common/octeontx2/otx2_common.c\n delete mode 100644 drivers/common/octeontx2/otx2_common.h\n delete mode 100644 drivers/common/octeontx2/otx2_dev.c\n delete mode 100644 drivers/common/octeontx2/otx2_dev.h\n delete mode 100644 drivers/common/octeontx2/otx2_io_arm64.h\n delete mode 100644 drivers/common/octeontx2/otx2_io_generic.h\n delete mode 100644 drivers/common/octeontx2/otx2_irq.c\n delete mode 100644 drivers/common/octeontx2/otx2_irq.h\n delete mode 100644 drivers/common/octeontx2/otx2_mbox.c\n delete mode 100644 drivers/common/octeontx2/otx2_mbox.h\n delete mode 100644 drivers/common/octeontx2/otx2_sec_idev.c\n delete mode 100644 drivers/common/octeontx2/otx2_sec_idev.h\n delete mode 100644 drivers/common/octeontx2/version.map\n delete mode 100644 drivers/crypto/octeontx2/meson.build\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.c\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.h\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.h\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops_helper.h\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_qp.h\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_sec.c\n delete mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_sec.h\n delete mode 100644 drivers/crypto/octeontx2/otx2_ipsec_anti_replay.h\n delete mode 100644 drivers/crypto/octeontx2/otx2_ipsec_fp.h\n delete mode 100644 drivers/crypto/octeontx2/otx2_ipsec_po.h\n delete mode 100644 drivers/crypto/octeontx2/otx2_ipsec_po_ops.h\n delete mode 100644 drivers/crypto/octeontx2/otx2_security.h\n delete mode 100644 drivers/crypto/octeontx2/version.map\n delete mode 100644 drivers/event/octeontx2/meson.build\n delete mode 100644 drivers/event/octeontx2/otx2_evdev.c\n delete mode 100644 drivers/event/octeontx2/otx2_evdev.h\n delete mode 100644 drivers/event/octeontx2/otx2_evdev_adptr.c\n delete mode 100644 drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\n delete mode 100644 drivers/event/octeontx2/otx2_evdev_crypto_adptr_rx.h\n delete mode 100644 drivers/event/octeontx2/otx2_evdev_crypto_adptr_tx.h\n delete mode 100644 drivers/event/octeontx2/otx2_evdev_irq.c\n delete mode 100644 drivers/event/octeontx2/otx2_evdev_selftest.c\n delete mode 100644 drivers/event/octeontx2/otx2_evdev_stats.h\n delete mode 100644 drivers/event/octeontx2/otx2_tim_evdev.c\n delete mode 100644 drivers/event/octeontx2/otx2_tim_evdev.h\n delete mode 100644 drivers/event/octeontx2/otx2_tim_worker.c\n delete mode 100644 drivers/event/octeontx2/otx2_tim_worker.h\n delete mode 100644 drivers/event/octeontx2/otx2_worker.c\n delete mode 100644 drivers/event/octeontx2/otx2_worker.h\n delete mode 100644 drivers/event/octeontx2/otx2_worker_dual.c\n delete mode 100644 drivers/event/octeontx2/otx2_worker_dual.h\n delete mode 100644 drivers/event/octeontx2/version.map\n delete mode 100644 drivers/mempool/octeontx2/meson.build\n delete mode 100644 drivers/mempool/octeontx2/otx2_mempool.c\n delete mode 100644 drivers/mempool/octeontx2/otx2_mempool.h\n delete mode 100644 drivers/mempool/octeontx2/otx2_mempool_debug.c\n delete mode 100644 drivers/mempool/octeontx2/otx2_mempool_irq.c\n delete mode 100644 drivers/mempool/octeontx2/otx2_mempool_ops.c\n delete mode 100644 drivers/mempool/octeontx2/version.map\n delete mode 100644 drivers/net/octeontx2/meson.build\n delete mode 100644 drivers/net/octeontx2/otx2_ethdev.c\n delete mode 100644 drivers/net/octeontx2/otx2_ethdev.h\n delete mode 100644 drivers/net/octeontx2/otx2_ethdev_debug.c\n delete mode 100644 drivers/net/octeontx2/otx2_ethdev_devargs.c\n delete mode 100644 drivers/net/octeontx2/otx2_ethdev_irq.c\n delete mode 100644 drivers/net/octeontx2/otx2_ethdev_ops.c\n delete mode 100644 drivers/net/octeontx2/otx2_ethdev_sec.c\n delete mode 100644 drivers/net/octeontx2/otx2_ethdev_sec.h\n delete mode 100644 drivers/net/octeontx2/otx2_ethdev_sec_tx.h\n delete mode 100644 drivers/net/octeontx2/otx2_flow.c\n delete mode 100644 drivers/net/octeontx2/otx2_flow.h\n delete mode 100644 drivers/net/octeontx2/otx2_flow_ctrl.c\n delete mode 100644 drivers/net/octeontx2/otx2_flow_dump.c\n delete mode 100644 drivers/net/octeontx2/otx2_flow_parse.c\n delete mode 100644 drivers/net/octeontx2/otx2_flow_utils.c\n delete mode 100644 drivers/net/octeontx2/otx2_link.c\n delete mode 100644 drivers/net/octeontx2/otx2_lookup.c\n delete mode 100644 drivers/net/octeontx2/otx2_mac.c\n delete mode 100644 drivers/net/octeontx2/otx2_mcast.c\n delete mode 100644 drivers/net/octeontx2/otx2_ptp.c\n delete mode 100644 drivers/net/octeontx2/otx2_rss.c\n delete mode 100644 drivers/net/octeontx2/otx2_rx.c\n delete mode 100644 drivers/net/octeontx2/otx2_rx.h\n delete mode 100644 drivers/net/octeontx2/otx2_stats.c\n delete mode 100644 drivers/net/octeontx2/otx2_tm.c\n delete mode 100644 drivers/net/octeontx2/otx2_tm.h\n delete mode 100644 drivers/net/octeontx2/otx2_tx.c\n delete mode 100644 drivers/net/octeontx2/otx2_tx.h\n delete mode 100644 drivers/net/octeontx2/otx2_vlan.c\n delete mode 100644 drivers/net/octeontx2/version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 854b81f2a3..336bbb3547 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -534,15 +534,6 @@ T: git://dpdk.org/next/dpdk-next-net-mrvl\n F: drivers/mempool/cnxk/\n F: doc/guides/mempool/cnxk.rst\n \n-Marvell OCTEON TX2\n-M: Jerin Jacob <jerinj@marvell.com>\n-M: Nithin Dabilpuram <ndabilpuram@marvell.com>\n-F: drivers/common/octeontx2/\n-F: drivers/mempool/octeontx2/\n-F: doc/guides/platform/img/octeontx2_*\n-F: doc/guides/platform/octeontx2.rst\n-F: doc/guides/mempool/octeontx2.rst\n-\n \n Bus Drivers\n -----------\n@@ -795,21 +786,6 @@ F: drivers/net/mvneta/\n F: doc/guides/nics/mvneta.rst\n F: doc/guides/nics/features/mvneta.ini\n \n-Marvell OCTEON TX2\n-M: Jerin Jacob <jerinj@marvell.com>\n-M: Nithin Dabilpuram <ndabilpuram@marvell.com>\n-M: Kiran Kumar K <kirankumark@marvell.com>\n-T: git://dpdk.org/next/dpdk-next-net-mrvl\n-F: drivers/net/octeontx2/\n-F: doc/guides/nics/features/octeontx2*.ini\n-F: doc/guides/nics/octeontx2.rst\n-\n-Marvell OCTEON TX2 - security\n-M: Anoob Joseph <anoobj@marvell.com>\n-T: git://dpdk.org/next/dpdk-next-crypto\n-F: drivers/common/octeontx2/otx2_sec*\n-F: drivers/net/octeontx2/otx2_ethdev_sec*\n-\n Marvell OCTEON TX EP - endpoint\n M: Nalla Pradeep <pnalla@marvell.com>\n M: Radha Mohan Chintakuntla <radhac@marvell.com>\n@@ -1115,13 +1091,6 @@ F: drivers/crypto/nitrox/\n F: doc/guides/cryptodevs/nitrox.rst\n F: doc/guides/cryptodevs/features/nitrox.ini\n \n-Marvell OCTEON TX2 crypto\n-M: Ankur Dwivedi <adwivedi@marvell.com>\n-M: Anoob Joseph <anoobj@marvell.com>\n-F: drivers/crypto/octeontx2/\n-F: doc/guides/cryptodevs/octeontx2.rst\n-F: doc/guides/cryptodevs/features/octeontx2.ini\n-\n Mellanox mlx5\n M: Matan Azrad <matan@nvidia.com>\n F: drivers/crypto/mlx5/\n@@ -1298,12 +1267,6 @@ M: Shijith Thotton <sthotton@marvell.com>\n F: drivers/event/cnxk/\n F: doc/guides/eventdevs/cnxk.rst\n \n-Marvell OCTEON TX2\n-M: Pavan Nikhilesh <pbhagavatula@marvell.com>\n-M: Jerin Jacob <jerinj@marvell.com>\n-F: drivers/event/octeontx2/\n-F: doc/guides/eventdevs/octeontx2.rst\n-\n NXP DPAA eventdev\n M: Hemant Agrawal <hemant.agrawal@nxp.com>\n M: Nipun Gupta <nipun.gupta@nxp.com>\ndiff --git a/app/test/meson.build b/app/test/meson.build\nindex 2b480adfba..344a609a4d 100644\n--- a/app/test/meson.build\n+++ b/app/test/meson.build\n@@ -341,7 +341,6 @@ driver_test_names = [\n 'cryptodev_dpaa_sec_autotest',\n 'cryptodev_dpaa2_sec_autotest',\n 'cryptodev_null_autotest',\n- 'cryptodev_octeontx2_autotest',\n 'cryptodev_openssl_autotest',\n 'cryptodev_openssl_asym_autotest',\n 'cryptodev_qat_autotest',\ndiff --git a/app/test/test_cryptodev.c b/app/test/test_cryptodev.c\nindex 10b48cdadb..293f59b48c 100644\n--- a/app/test/test_cryptodev.c\n+++ b/app/test/test_cryptodev.c\n@@ -15615,12 +15615,6 @@ test_cryptodev_octeontx(void)\n \treturn run_cryptodev_testsuite(RTE_STR(CRYPTODEV_NAME_OCTEONTX_SYM_PMD));\n }\n \n-static int\n-test_cryptodev_octeontx2(void)\n-{\n-\treturn run_cryptodev_testsuite(RTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD));\n-}\n-\n static int\n test_cryptodev_caam_jr(void)\n {\n@@ -15733,7 +15727,6 @@ REGISTER_TEST_COMMAND(cryptodev_dpaa_sec_autotest, test_cryptodev_dpaa_sec);\n REGISTER_TEST_COMMAND(cryptodev_ccp_autotest, test_cryptodev_ccp);\n REGISTER_TEST_COMMAND(cryptodev_virtio_autotest, test_cryptodev_virtio);\n REGISTER_TEST_COMMAND(cryptodev_octeontx_autotest, test_cryptodev_octeontx);\n-REGISTER_TEST_COMMAND(cryptodev_octeontx2_autotest, test_cryptodev_octeontx2);\n REGISTER_TEST_COMMAND(cryptodev_caam_jr_autotest, test_cryptodev_caam_jr);\n REGISTER_TEST_COMMAND(cryptodev_nitrox_autotest, test_cryptodev_nitrox);\n REGISTER_TEST_COMMAND(cryptodev_bcmfs_autotest, test_cryptodev_bcmfs);\ndiff --git a/app/test/test_cryptodev.h b/app/test/test_cryptodev.h\nindex 90c8287365..70f23a3f67 100644\n--- a/app/test/test_cryptodev.h\n+++ b/app/test/test_cryptodev.h\n@@ -68,7 +68,6 @@\n #define CRYPTODEV_NAME_CCP_PMD\t\tcrypto_ccp\n #define CRYPTODEV_NAME_VIRTIO_PMD\tcrypto_virtio\n #define CRYPTODEV_NAME_OCTEONTX_SYM_PMD\tcrypto_octeontx\n-#define CRYPTODEV_NAME_OCTEONTX2_PMD\tcrypto_octeontx2\n #define CRYPTODEV_NAME_CAAM_JR_PMD\tcrypto_caam_jr\n #define CRYPTODEV_NAME_NITROX_PMD\tcrypto_nitrox_sym\n #define CRYPTODEV_NAME_BCMFS_PMD\tcrypto_bcmfs\ndiff --git a/app/test/test_cryptodev_asym.c b/app/test/test_cryptodev_asym.c\nindex 9d19a6d6d9..68f4d8e7a6 100644\n--- a/app/test/test_cryptodev_asym.c\n+++ b/app/test/test_cryptodev_asym.c\n@@ -2375,20 +2375,6 @@ test_cryptodev_octeontx_asym(void)\n \treturn unit_test_suite_runner(&cryptodev_octeontx_asym_testsuite);\n }\n \n-static int\n-test_cryptodev_octeontx2_asym(void)\n-{\n-\tgbl_driver_id = rte_cryptodev_driver_id_get(\n-\t\t\tRTE_STR(CRYPTODEV_NAME_OCTEONTX2_PMD));\n-\tif (gbl_driver_id == -1) {\n-\t\tRTE_LOG(ERR, USER1, \"OCTEONTX2 PMD must be loaded.\\n\");\n-\t\treturn TEST_FAILED;\n-\t}\n-\n-\t/* Use test suite registered for crypto_octeontx PMD */\n-\treturn unit_test_suite_runner(&cryptodev_octeontx_asym_testsuite);\n-}\n-\n static int\n test_cryptodev_cn9k_asym(void)\n {\n@@ -2424,8 +2410,5 @@ REGISTER_TEST_COMMAND(cryptodev_qat_asym_autotest, test_cryptodev_qat_asym);\n \n REGISTER_TEST_COMMAND(cryptodev_octeontx_asym_autotest,\n \t\t\t\t\t test_cryptodev_octeontx_asym);\n-\n-REGISTER_TEST_COMMAND(cryptodev_octeontx2_asym_autotest,\n-\t\t\t\t\t test_cryptodev_octeontx2_asym);\n REGISTER_TEST_COMMAND(cryptodev_cn9k_asym_autotest, test_cryptodev_cn9k_asym);\n REGISTER_TEST_COMMAND(cryptodev_cn10k_asym_autotest, test_cryptodev_cn10k_asym);\ndiff --git a/app/test/test_eventdev.c b/app/test/test_eventdev.c\nindex 843d9766b0..10028fe11d 100644\n--- a/app/test/test_eventdev.c\n+++ b/app/test/test_eventdev.c\n@@ -1018,12 +1018,6 @@ test_eventdev_selftest_octeontx(void)\n \treturn test_eventdev_selftest_impl(\"event_octeontx\", \"\");\n }\n \n-static int\n-test_eventdev_selftest_octeontx2(void)\n-{\n-\treturn test_eventdev_selftest_impl(\"event_octeontx2\", \"\");\n-}\n-\n static int\n test_eventdev_selftest_dpaa2(void)\n {\n@@ -1052,8 +1046,6 @@ REGISTER_TEST_COMMAND(eventdev_common_autotest, test_eventdev_common);\n REGISTER_TEST_COMMAND(eventdev_selftest_sw, test_eventdev_selftest_sw);\n REGISTER_TEST_COMMAND(eventdev_selftest_octeontx,\n \t\ttest_eventdev_selftest_octeontx);\n-REGISTER_TEST_COMMAND(eventdev_selftest_octeontx2,\n-\t\ttest_eventdev_selftest_octeontx2);\n REGISTER_TEST_COMMAND(eventdev_selftest_dpaa2, test_eventdev_selftest_dpaa2);\n REGISTER_TEST_COMMAND(eventdev_selftest_dlb2, test_eventdev_selftest_dlb2);\n REGISTER_TEST_COMMAND(eventdev_selftest_cn9k, test_eventdev_selftest_cn9k);\ndiff --git a/config/arm/arm64_cn10k_linux_gcc b/config/arm/arm64_cn10k_linux_gcc\nindex 88e5f10945..a3578c03a1 100644\n--- a/config/arm/arm64_cn10k_linux_gcc\n+++ b/config/arm/arm64_cn10k_linux_gcc\n@@ -14,4 +14,3 @@ endian = 'little'\n \n [properties]\n platform = 'cn10k'\n-disable_drivers = 'common/octeontx2'\ndiff --git a/config/arm/arm64_octeontx2_linux_gcc b/config/arm/arm64_cn9k_linux_gcc\nsimilarity index 84%\nrename from config/arm/arm64_octeontx2_linux_gcc\nrename to config/arm/arm64_cn9k_linux_gcc\nindex 8fbdd3868d..a94b44a551 100644\n--- a/config/arm/arm64_octeontx2_linux_gcc\n+++ b/config/arm/arm64_cn9k_linux_gcc\n@@ -13,5 +13,4 @@ cpu = 'armv8-a'\n endian = 'little'\n \n [properties]\n-platform = 'octeontx2'\n-disable_drivers = 'common/cnxk'\n+platform = 'cn9k'\ndiff --git a/config/arm/meson.build b/config/arm/meson.build\nindex 213324d262..16e808cdd5 100644\n--- a/config/arm/meson.build\n+++ b/config/arm/meson.build\n@@ -139,7 +139,7 @@ implementer_cavium = {\n 'march_features': ['crc', 'crypto', 'lse'],\n 'compiler_options': ['-mcpu=octeontx2'],\n 'flags': [\n- ['RTE_MACHINE', '\"octeontx2\"'],\n+ ['RTE_MACHINE', '\"cn9k\"'],\n ['RTE_ARM_FEATURE_ATOMICS', true],\n ['RTE_USE_C11_MEM_MODEL', true],\n ['RTE_MAX_LCORE', 36],\n@@ -340,8 +340,8 @@ soc_n2 = {\n 'numa': false\n }\n \n-soc_octeontx2 = {\n- 'description': 'Marvell OCTEON TX2',\n+soc_cn9k = {\n+ 'description': 'Marvell OCTEON 9',\n 'implementer': '0x43',\n 'part_number': '0xb2',\n 'numa': false\n@@ -377,6 +377,7 @@ generic_aarch32: Generic un-optimized build for armv8 aarch32 execution mode.\n armada: Marvell ARMADA\n bluefield: NVIDIA BlueField\n centriq2400: Qualcomm Centriq 2400\n+cn9k: Marvell OCTEON 9\n cn10k: Marvell OCTEON 10\n dpaa: NXP DPAA\n emag: Ampere eMAG\n@@ -385,7 +386,6 @@ kunpeng920: HiSilicon Kunpeng 920\n kunpeng930: HiSilicon Kunpeng 930\n n1sdp: Arm Neoverse N1SDP\n n2: Arm Neoverse N2\n-octeontx2: Marvell OCTEON TX2\n stingray: Broadcom Stingray\n thunderx2: Marvell ThunderX2 T99\n thunderxt88: Marvell ThunderX T88\n@@ -399,6 +399,7 @@ socs = {\n 'armada': soc_armada,\n 'bluefield': soc_bluefield,\n 'centriq2400': soc_centriq2400,\n+ 'cn9k': soc_cn9k,\n 'cn10k' : soc_cn10k,\n 'dpaa': soc_dpaa,\n 'emag': soc_emag,\n@@ -407,7 +408,6 @@ socs = {\n 'kunpeng930': soc_kunpeng930,\n 'n1sdp': soc_n1sdp,\n 'n2': soc_n2,\n- 'octeontx2': soc_octeontx2,\n 'stingray': soc_stingray,\n 'thunderx2': soc_thunderx2,\n 'thunderxt88': soc_thunderxt88\ndiff --git a/devtools/check-abi.sh b/devtools/check-abi.sh\nindex ca523eb94c..675f10142e 100755\n--- a/devtools/check-abi.sh\n+++ b/devtools/check-abi.sh\n@@ -48,6 +48,10 @@ for dump in $(find $refdir -name \"*.dump\"); do\n \t\techo \"Skipped removed driver $name.\"\n \t\tcontinue\n \tfi\n+\tif grep -qE \"\\<librte_*.*_octeontx2\" $dump; then\n+\t\techo \"Skipped removed driver $name.\"\n+\t\tcontinue\n+\tfi\n \tdump2=$(find $newdir -name $name)\n \tif [ -z \"$dump2\" ] || [ ! -e \"$dump2\" ]; then\n \t\techo \"Error: cannot find $name in $newdir\" >&2\ndiff --git a/doc/guides/cryptodevs/features/octeontx2.ini b/doc/guides/cryptodevs/features/octeontx2.ini\ndeleted file mode 100644\nindex c54dc9409c..0000000000\n--- a/doc/guides/cryptodevs/features/octeontx2.ini\n+++ /dev/null\n@@ -1,87 +0,0 @@\n-;\n-; Supported features of the 'octeontx2' crypto driver.\n-;\n-; Refer to default.ini for the full list of available PMD features.\n-;\n-[Features]\n-Symmetric crypto = Y\n-Asymmetric crypto = Y\n-Sym operation chaining = Y\n-HW Accelerated = Y\n-Protocol offload = Y\n-In Place SGL = Y\n-OOP SGL In LB Out = Y\n-OOP SGL In SGL Out = Y\n-OOP LB In LB Out = Y\n-RSA PRIV OP KEY QT = Y\n-Digest encrypted = Y\n-Symmetric sessionless = Y\n-\n-;\n-; Supported crypto algorithms of 'octeontx2' crypto driver.\n-;\n-[Cipher]\n-NULL = Y\n-3DES CBC = Y\n-3DES ECB = Y\n-AES CBC (128) = Y\n-AES CBC (192) = Y\n-AES CBC (256) = Y\n-AES CTR (128) = Y\n-AES CTR (192) = Y\n-AES CTR (256) = Y\n-AES XTS (128) = Y\n-AES XTS (256) = Y\n-DES CBC = Y\n-KASUMI F8 = Y\n-SNOW3G UEA2 = Y\n-ZUC EEA3 = Y\n-\n-;\n-; Supported authentication algorithms of 'octeontx2' crypto driver.\n-;\n-[Auth]\n-NULL = Y\n-AES GMAC = Y\n-KASUMI F9 = Y\n-MD5 = Y\n-MD5 HMAC = Y\n-SHA1 = Y\n-SHA1 HMAC = Y\n-SHA224 = Y\n-SHA224 HMAC = Y\n-SHA256 = Y\n-SHA256 HMAC = Y\n-SHA384 = Y\n-SHA384 HMAC = Y\n-SHA512 = Y\n-SHA512 HMAC = Y\n-SNOW3G UIA2 = Y\n-ZUC EIA3 = Y\n-\n-;\n-; Supported AEAD algorithms of 'octeontx2' crypto driver.\n-;\n-[AEAD]\n-AES GCM (128) = Y\n-AES GCM (192) = Y\n-AES GCM (256) = Y\n-CHACHA20-POLY1305 = Y\n-\n-;\n-; Supported Asymmetric algorithms of the 'octeontx2' crypto driver.\n-;\n-[Asymmetric]\n-RSA = Y\n-DSA =\n-Modular Exponentiation = Y\n-Modular Inversion =\n-Diffie-hellman =\n-ECDSA = Y\n-ECPM = Y\n-\n-;\n-; Supported Operating systems of the 'octeontx2' crypto driver.\n-;\n-[OS]\n-Linux = Y\ndiff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.rst\nindex 3dcc2ecd2e..39cca6dbde 100644\n--- a/doc/guides/cryptodevs/index.rst\n+++ b/doc/guides/cryptodevs/index.rst\n@@ -22,7 +22,6 @@ Crypto Device Drivers\n dpaa_sec\n kasumi\n octeontx\n- octeontx2\n openssl\n mlx5\n mvsam\ndiff --git a/doc/guides/cryptodevs/octeontx2.rst b/doc/guides/cryptodevs/octeontx2.rst\ndeleted file mode 100644\nindex 811e61a1f6..0000000000\n--- a/doc/guides/cryptodevs/octeontx2.rst\n+++ /dev/null\n@@ -1,188 +0,0 @@\n-.. SPDX-License-Identifier: BSD-3-Clause\n- Copyright(c) 2019 Marvell International Ltd.\n-\n-\n-Marvell OCTEON TX2 Crypto Poll Mode Driver\n-==========================================\n-\n-The OCTEON TX2 crypto poll mode driver provides support for offloading\n-cryptographic operations to cryptographic accelerator units on the\n-**OCTEON TX2** :sup:`®` family of processors (CN9XXX).\n-\n-More information about OCTEON TX2 SoCs may be obtained from `<https://www.marvell.com>`_\n-\n-Features\n---------\n-\n-The OCTEON TX2 crypto PMD has support for:\n-\n-Symmetric Crypto Algorithms\n-~~~~~~~~~~~~~~~~~~~~~~~~~~~\n-\n-Cipher algorithms:\n-\n-* ``RTE_CRYPTO_CIPHER_NULL``\n-* ``RTE_CRYPTO_CIPHER_3DES_CBC``\n-* ``RTE_CRYPTO_CIPHER_3DES_ECB``\n-* ``RTE_CRYPTO_CIPHER_AES_CBC``\n-* ``RTE_CRYPTO_CIPHER_AES_CTR``\n-* ``RTE_CRYPTO_CIPHER_AES_XTS``\n-* ``RTE_CRYPTO_CIPHER_DES_CBC``\n-* ``RTE_CRYPTO_CIPHER_KASUMI_F8``\n-* ``RTE_CRYPTO_CIPHER_SNOW3G_UEA2``\n-* ``RTE_CRYPTO_CIPHER_ZUC_EEA3``\n-\n-Hash algorithms:\n-\n-* ``RTE_CRYPTO_AUTH_NULL``\n-* ``RTE_CRYPTO_AUTH_AES_GMAC``\n-* ``RTE_CRYPTO_AUTH_KASUMI_F9``\n-* ``RTE_CRYPTO_AUTH_MD5``\n-* ``RTE_CRYPTO_AUTH_MD5_HMAC``\n-* ``RTE_CRYPTO_AUTH_SHA1``\n-* ``RTE_CRYPTO_AUTH_SHA1_HMAC``\n-* ``RTE_CRYPTO_AUTH_SHA224``\n-* ``RTE_CRYPTO_AUTH_SHA224_HMAC``\n-* ``RTE_CRYPTO_AUTH_SHA256``\n-* ``RTE_CRYPTO_AUTH_SHA256_HMAC``\n-* ``RTE_CRYPTO_AUTH_SHA384``\n-* ``RTE_CRYPTO_AUTH_SHA384_HMAC``\n-* ``RTE_CRYPTO_AUTH_SHA512``\n-* ``RTE_CRYPTO_AUTH_SHA512_HMAC``\n-* ``RTE_CRYPTO_AUTH_SNOW3G_UIA2``\n-* ``RTE_CRYPTO_AUTH_ZUC_EIA3``\n-\n-AEAD algorithms:\n-\n-* ``RTE_CRYPTO_AEAD_AES_GCM``\n-* ``RTE_CRYPTO_AEAD_CHACHA20_POLY1305``\n-\n-Asymmetric Crypto Algorithms\n-~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n-\n-* ``RTE_CRYPTO_ASYM_XFORM_RSA``\n-* ``RTE_CRYPTO_ASYM_XFORM_MODEX``\n-\n-\n-Installation\n-------------\n-\n-The OCTEON TX2 crypto PMD may be compiled natively on an OCTEON TX2 platform or\n-cross-compiled on an x86 platform.\n-\n-Refer to :doc:`../platform/octeontx2` for instructions to build your DPDK\n-application.\n-\n-.. note::\n-\n- The OCTEON TX2 crypto PMD uses services from the kernel mode OCTEON TX2\n- crypto PF driver in linux. This driver is included in the OCTEON TX SDK.\n-\n-Initialization\n---------------\n-\n-List the CPT PF devices available on your OCTEON TX2 platform:\n-\n-.. code-block:: console\n-\n- lspci -d:a0fd\n-\n-``a0fd`` is the CPT PF device id. You should see output similar to:\n-\n-.. code-block:: console\n-\n- 0002:10:00.0 Class 1080: Device 177d:a0fd\n-\n-Set ``sriov_numvfs`` on the CPT PF device, to create a VF:\n-\n-.. code-block:: console\n-\n- echo 1 > /sys/bus/pci/drivers/octeontx2-cpt/0002:10:00.0/sriov_numvfs\n-\n-Bind the CPT VF device to the vfio_pci driver:\n-\n-.. code-block:: console\n-\n- echo '177d a0fe' > /sys/bus/pci/drivers/vfio-pci/new_id\n- echo 0002:10:00.1 > /sys/bus/pci/devices/0002:10:00.1/driver/unbind\n- echo 0002:10:00.1 > /sys/bus/pci/drivers/vfio-pci/bind\n-\n-Another way to bind the VF would be to use the ``dpdk-devbind.py`` script:\n-\n-.. code-block:: console\n-\n- cd <dpdk directory>\n- ./usertools/dpdk-devbind.py -u 0002:10:00.1\n- ./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1\n-\n-.. note::\n-\n- * For CN98xx SoC, it is recommended to use even and odd DBDF VFs to achieve\n- higher performance as even VF uses one crypto engine and odd one uses\n- another crypto engine.\n-\n- * Ensure that sufficient huge pages are available for your application::\n-\n- dpdk-hugepages.py --setup 4G --pagesize 512M\n-\n- Refer to :ref:`linux_gsg_hugepages` for more details.\n-\n-Debugging Options\n------------------\n-\n-.. _table_octeontx2_crypto_debug_options:\n-\n-.. table:: OCTEON TX2 crypto PMD debug options\n-\n- +---+------------+-------------------------------------------------------+\n- | # | Component | EAL log command |\n- +===+============+=======================================================+\n- | 1 | CPT | --log-level='pmd\\.crypto\\.octeontx2,8' |\n- +---+------------+-------------------------------------------------------+\n-\n-Testing\n--------\n-\n-The symmetric crypto operations on OCTEON TX2 crypto PMD may be verified by running the test\n-application:\n-\n-.. code-block:: console\n-\n- ./dpdk-test\n- RTE>>cryptodev_octeontx2_autotest\n-\n-The asymmetric crypto operations on OCTEON TX2 crypto PMD may be verified by running the test\n-application:\n-\n-.. code-block:: console\n-\n- ./dpdk-test\n- RTE>>cryptodev_octeontx2_asym_autotest\n-\n-\n-Lookaside IPsec Support\n------------------------\n-\n-The OCTEON TX2 SoC can accelerate IPsec traffic in lookaside protocol mode,\n-with its **cryptographic accelerator (CPT)**. ``OCTEON TX2 crypto PMD`` implements\n-this as an ``RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL`` offload.\n-\n-Refer to :doc:`../prog_guide/rte_security` for more details on protocol offloads.\n-\n-This feature can be tested with ipsec-secgw sample application.\n-\n-\n-Features supported\n-~~~~~~~~~~~~~~~~~~\n-\n-* IPv4\n-* IPv6\n-* ESP\n-* Tunnel mode\n-* Transport mode(IPv4)\n-* ESN\n-* Anti-replay\n-* UDP Encapsulation\n-* AES-128/192/256-GCM\n-* AES-128/192/256-CBC-SHA1-HMAC\n-* AES-128/192/256-CBC-SHA256-128-HMAC\ndiff --git a/doc/guides/dmadevs/cnxk.rst b/doc/guides/dmadevs/cnxk.rst\nindex da2dd59071..418b9a9d63 100644\n--- a/doc/guides/dmadevs/cnxk.rst\n+++ b/doc/guides/dmadevs/cnxk.rst\n@@ -7,7 +7,7 @@ CNXK DMA Device Driver\n ======================\n \n The ``cnxk`` dmadev driver provides a poll-mode driver (PMD) for Marvell DPI DMA\n-Hardware Accelerator block found in OCTEONTX2 and OCTEONTX3 family of SoCs.\n+Hardware Accelerator block found in OCTEON 9 and OCTEON 10 family of SoCs.\n Each DMA queue is exposed as a VF function when SRIOV is enabled.\n \n The block supports following modes of DMA transfers:\ndiff --git a/doc/guides/eventdevs/features/octeontx2.ini b/doc/guides/eventdevs/features/octeontx2.ini\ndeleted file mode 100644\nindex 05b84beb6e..0000000000\n--- a/doc/guides/eventdevs/features/octeontx2.ini\n+++ /dev/null\n@@ -1,30 +0,0 @@\n-;\n-; Supported features of the 'octeontx2' eventdev driver.\n-;\n-; Refer to default.ini for the full list of available PMD features.\n-;\n-[Scheduling Features]\n-queue_qos = Y\n-distributed_sched = Y\n-queue_all_types = Y\n-nonseq_mode = Y\n-runtime_port_link = Y\n-multiple_queue_port = Y\n-carry_flow_id = Y\n-maintenance_free = Y\n-\n-[Eth Rx adapter Features]\n-internal_port = Y\n-multi_eventq = Y\n-\n-[Eth Tx adapter Features]\n-internal_port = Y\n-\n-[Crypto adapter Features]\n-internal_port_op_new = Y\n-internal_port_op_fwd = Y\n-internal_port_qp_ev_bind = Y\n-\n-[Timer adapter Features]\n-internal_port = Y\n-periodic = Y\ndiff --git a/doc/guides/eventdevs/index.rst b/doc/guides/eventdevs/index.rst\nindex b11657f7ae..eed19ad28c 100644\n--- a/doc/guides/eventdevs/index.rst\n+++ b/doc/guides/eventdevs/index.rst\n@@ -19,5 +19,4 @@ application through the eventdev API.\n dsw\n sw\n octeontx\n- octeontx2\n opdl\ndiff --git a/doc/guides/eventdevs/octeontx2.rst b/doc/guides/eventdevs/octeontx2.rst\ndeleted file mode 100644\nindex 0fa57abfa3..0000000000\n--- a/doc/guides/eventdevs/octeontx2.rst\n+++ /dev/null\n@@ -1,178 +0,0 @@\n-.. SPDX-License-Identifier: BSD-3-Clause\n- Copyright(c) 2019 Marvell International Ltd.\n-\n-OCTEON TX2 SSO Eventdev Driver\n-===============================\n-\n-The OCTEON TX2 SSO PMD (**librte_event_octeontx2**) provides poll mode\n-eventdev driver support for the inbuilt event device found in the **Marvell OCTEON TX2**\n-SoC family.\n-\n-More information about OCTEON TX2 SoC can be found at `Marvell Official Website\n-<https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.\n-\n-Features\n---------\n-\n-Features of the OCTEON TX2 SSO PMD are:\n-\n-- 256 Event queues\n-- 26 (dual) and 52 (single) Event ports\n-- HW event scheduler\n-- Supports 1M flows per event queue\n-- Flow based event pipelining\n-- Flow pinning support in flow based event pipelining\n-- Queue based event pipelining\n-- Supports ATOMIC, ORDERED, PARALLEL schedule types per flow\n-- Event scheduling QoS based on event queue priority\n-- Open system with configurable amount of outstanding events limited only by\n- DRAM\n-- HW accelerated dequeue timeout support to enable power management\n-- HW managed event timers support through TIM, with high precision and\n- time granularity of 2.5us.\n-- Up to 256 TIM rings aka event timer adapters.\n-- Up to 8 rings traversed in parallel.\n-- HW managed packets enqueued from ethdev to eventdev exposed through event eth\n- RX adapter.\n-- N:1 ethernet device Rx queue to Event queue mapping.\n-- Lockfree Tx from event eth Tx adapter using ``RTE_ETH_TX_OFFLOAD_MT_LOCKFREE``\n- capability while maintaining receive packet order.\n-- Full Rx/Tx offload support defined through ethdev queue config.\n-\n-Prerequisites and Compilation procedure\n----------------------------------------\n-\n- See :doc:`../platform/octeontx2` for setup information.\n-\n-\n-Runtime Config Options\n-----------------------\n-\n-- ``Maximum number of in-flight events`` (default ``8192``)\n-\n- In **Marvell OCTEON TX2** the max number of in-flight events are only limited\n- by DRAM size, the ``xae_cnt`` devargs parameter is introduced to provide\n- upper limit for in-flight events.\n- For example::\n-\n- -a 0002:0e:00.0,xae_cnt=16384\n-\n-- ``Force legacy mode``\n-\n- The ``single_ws`` devargs parameter is introduced to force legacy mode i.e\n- single workslot mode in SSO and disable the default dual workslot mode.\n- For example::\n-\n- -a 0002:0e:00.0,single_ws=1\n-\n-- ``Event Group QoS support``\n-\n- SSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight\n- events. By default the buffers are assigned to the SSO GGRPs to\n- satisfy minimum HW requirements. SSO is free to assign the remaining\n- buffers to GGRPs based on a preconfigured threshold.\n- We can control the QoS of SSO GGRP by modifying the above mentioned\n- thresholds. GGRPs that have higher importance can be assigned higher\n- thresholds than the rest. The dictionary format is as follows\n- [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] expressed in percentages, 0 represents\n- default.\n- For example::\n-\n- -a 0002:0e:00.0,qos=[1-50-50-50]\n-\n-- ``TIM disable NPA``\n-\n- By default chunks are allocated from NPA then TIM can automatically free\n- them when traversing the list of chunks. The ``tim_disable_npa`` devargs\n- parameter disables NPA and uses software mempool to manage chunks\n- For example::\n-\n- -a 0002:0e:00.0,tim_disable_npa=1\n-\n-- ``TIM modify chunk slots``\n-\n- The ``tim_chnk_slots`` devargs can be used to modify number of chunk slots.\n- Chunks are used to store event timers, a chunk can be visualised as an array\n- where the last element points to the next chunk and rest of them are used to\n- store events. TIM traverses the list of chunks and enqueues the event timers\n- to SSO. The default value is 255 and the max value is 4095.\n- For example::\n-\n- -a 0002:0e:00.0,tim_chnk_slots=1023\n-\n-- ``TIM enable arm/cancel statistics``\n-\n- The ``tim_stats_ena`` devargs can be used to enable arm and cancel stats of\n- event timer adapter.\n- For example::\n-\n- -a 0002:0e:00.0,tim_stats_ena=1\n-\n-- ``TIM limit max rings reserved``\n-\n- The ``tim_rings_lmt`` devargs can be used to limit the max number of TIM\n- rings i.e. event timer adapter reserved on probe. Since, TIM rings are HW\n- resources we can avoid starving other applications by not grabbing all the\n- rings.\n- For example::\n-\n- -a 0002:0e:00.0,tim_rings_lmt=5\n-\n-- ``TIM ring control internal parameters``\n-\n- When using multiple TIM rings the ``tim_ring_ctl`` devargs can be used to\n- control each TIM rings internal parameters uniquely. The following dict\n- format is expected [ring-chnk_slots-disable_npa-stats_ena]. 0 represents\n- default values.\n- For Example::\n-\n- -a 0002:0e:00.0,tim_ring_ctl=[2-1023-1-0]\n-\n-- ``Lock NPA contexts in NDC``\n-\n- Lock NPA aura and pool contexts in NDC cache.\n- The device args take hexadecimal bitmask where each bit represent the\n- corresponding aura/pool id.\n-\n- For example::\n-\n- -a 0002:0e:00.0,npa_lock_mask=0xf\n-\n-- ``Force Rx Back pressure``\n-\n- Force Rx back pressure when same mempool is used across ethernet device\n- connected to event device.\n-\n- For example::\n-\n- -a 0002:0e:00.0,force_rx_bp=1\n-\n-Debugging Options\n------------------\n-\n-.. _table_octeontx2_event_debug_options:\n-\n-.. table:: OCTEON TX2 event device debug options\n-\n- +---+------------+-------------------------------------------------------+\n- | # | Component | EAL log command |\n- +===+============+=======================================================+\n- | 1 | SSO | --log-level='pmd\\.event\\.octeontx2,8' |\n- +---+------------+-------------------------------------------------------+\n- | 2 | TIM | --log-level='pmd\\.event\\.octeontx2\\.timer,8' |\n- +---+------------+-------------------------------------------------------+\n-\n-Limitations\n------------\n-\n-Rx adapter support\n-~~~~~~~~~~~~~~~~~~\n-\n-Using the same mempool for all the ethernet device ports connected to\n-event device would cause back pressure to be asserted only on the first\n-ethernet device.\n-Back pressure is automatically disabled when using same mempool for all the\n-ethernet devices connected to event device to override this applications can\n-use `force_rx_bp=1` device arguments.\n-Using unique mempool per each ethernet device is recommended when they are\n-connected to event device.\ndiff --git a/doc/guides/mempool/index.rst b/doc/guides/mempool/index.rst\nindex ce53bc1ac7..e4b6ee7d31 100644\n--- a/doc/guides/mempool/index.rst\n+++ b/doc/guides/mempool/index.rst\n@@ -13,6 +13,5 @@ application through the mempool API.\n \n cnxk\n octeontx\n- octeontx2\n ring\n stack\ndiff --git a/doc/guides/mempool/octeontx2.rst b/doc/guides/mempool/octeontx2.rst\ndeleted file mode 100644\nindex 1272c1e72b..0000000000\n--- a/doc/guides/mempool/octeontx2.rst\n+++ /dev/null\n@@ -1,92 +0,0 @@\n-.. SPDX-License-Identifier: BSD-3-Clause\n- Copyright(c) 2019 Marvell International Ltd.\n-\n-OCTEON TX2 NPA Mempool Driver\n-=============================\n-\n-The OCTEON TX2 NPA PMD (**librte_mempool_octeontx2**) provides mempool\n-driver support for the integrated mempool device found in **Marvell OCTEON TX2** SoC family.\n-\n-More information about OCTEON TX2 SoC can be found at `Marvell Official Website\n-<https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.\n-\n-Features\n---------\n-\n-OCTEON TX2 NPA PMD supports:\n-\n-- Up to 128 NPA LFs\n-- 1M Pools per LF\n-- HW mempool manager\n-- Ethdev Rx buffer allocation in HW to save CPU cycles in the Rx path.\n-- Ethdev Tx buffer recycling in HW to save CPU cycles in the Tx path.\n-\n-Prerequisites and Compilation procedure\n----------------------------------------\n-\n- See :doc:`../platform/octeontx2` for setup information.\n-\n-Pre-Installation Configuration\n-------------------------------\n-\n-\n-Runtime Config Options\n-~~~~~~~~~~~~~~~~~~~~~~\n-\n-- ``Maximum number of mempools per application`` (default ``128``)\n-\n- The maximum number of mempools per application needs to be configured on\n- HW during mempool driver initialization. HW can support up to 1M mempools,\n- Since each mempool costs set of HW resources, the ``max_pools`` ``devargs``\n- parameter is being introduced to configure the number of mempools required\n- for the application.\n- For example::\n-\n- -a 0002:02:00.0,max_pools=512\n-\n- With the above configuration, the driver will set up only 512 mempools for\n- the given application to save HW resources.\n-\n-.. note::\n-\n- Since this configuration is per application, the end user needs to\n- provide ``max_pools`` parameter to the first PCIe device probed by the given\n- application.\n-\n-- ``Lock NPA contexts in NDC``\n-\n- Lock NPA aura and pool contexts in NDC cache.\n- The device args take hexadecimal bitmask where each bit represent the\n- corresponding aura/pool id.\n-\n- For example::\n-\n- -a 0002:02:00.0,npa_lock_mask=0xf\n-\n-Debugging Options\n-~~~~~~~~~~~~~~~~~\n-\n-.. _table_octeontx2_mempool_debug_options:\n-\n-.. table:: OCTEON TX2 mempool debug options\n-\n- +---+------------+-------------------------------------------------------+\n- | # | Component | EAL log command |\n- +===+============+=======================================================+\n- | 1 | NPA | --log-level='pmd\\.mempool.octeontx2,8' |\n- +---+------------+-------------------------------------------------------+\n-\n-Standalone mempool device\n-~~~~~~~~~~~~~~~~~~~~~~~~~\n-\n- The ``usertools/dpdk-devbind.py`` script shall enumerate all the mempool devices\n- available in the system. In order to avoid, the end user to bind the mempool\n- device prior to use ethdev and/or eventdev device, the respective driver\n- configures an NPA LF and attach to the first probed ethdev or eventdev device.\n- In case, if end user need to run mempool as a standalone device\n- (without ethdev or eventdev), end user needs to bind a mempool device using\n- ``usertools/dpdk-devbind.py``\n-\n- Example command to run ``mempool_autotest`` test with standalone OCTEONTX2 NPA device::\n-\n- echo \"mempool_autotest\" | <build_dir>/app/test/dpdk-test -c 0xf0 --mbuf-pool-ops-name=\"octeontx2_npa\"\ndiff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex 84f9865654..2119ba51c8 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -178,7 +178,7 @@ Runtime Config Options\n * ``rss_adder<7:0> = flow_tag<7:0>``\n \n Latter one aligns with standard NIC behavior vs former one is a legacy\n- RSS adder scheme used in OCTEON TX2 products.\n+ RSS adder scheme used in OCTEON 9 products.\n \n By default, the driver runs in the latter mode.\n Setting this flag to 1 to select the legacy mode.\n@@ -291,7 +291,7 @@ Limitations\n The OCTEON CN9K/CN10K SoC family NIC has inbuilt HW assisted external mempool manager.\n ``net_cnxk`` PMD only works with ``mempool_cnxk`` mempool handler\n as it is performance wise most effective way for packet allocation and Tx buffer\n-recycling on OCTEON TX2 SoC platform.\n+recycling on OCTEON 9 SoC platform.\n \n CRC stripping\n ~~~~~~~~~~~~~\ndiff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini\ndeleted file mode 100644\nindex bf0c2890f2..0000000000\n--- a/doc/guides/nics/features/octeontx2.ini\n+++ /dev/null\n@@ -1,97 +0,0 @@\n-;\n-; Supported features of the 'octeontx2' network poll mode driver.\n-;\n-; Refer to default.ini for the full list of available PMD features.\n-;\n-[Features]\n-Speed capabilities = Y\n-Rx interrupt = Y\n-Lock-free Tx queue = Y\n-SR-IOV = Y\n-Multiprocess aware = Y\n-Link status = Y\n-Link status event = Y\n-Runtime Rx queue setup = Y\n-Runtime Tx queue setup = Y\n-Burst mode info = Y\n-Fast mbuf free = Y\n-Free Tx mbuf on demand = Y\n-Queue start/stop = Y\n-MTU update = Y\n-TSO = Y\n-Promiscuous mode = Y\n-Allmulticast mode = Y\n-Unicast MAC filter = Y\n-Multicast MAC filter = Y\n-RSS hash = Y\n-RSS key update = Y\n-RSS reta update = Y\n-Inner RSS = Y\n-Inline protocol = Y\n-VLAN filter = Y\n-Flow control = Y\n-Rate limitation = Y\n-Scattered Rx = Y\n-VLAN offload = Y\n-QinQ offload = Y\n-L3 checksum offload = Y\n-L4 checksum offload = Y\n-Inner L3 checksum = Y\n-Inner L4 checksum = Y\n-Packet type parsing = Y\n-Timesync = Y\n-Timestamp offload = Y\n-Rx descriptor status = Y\n-Tx descriptor status = Y\n-Basic stats = Y\n-Stats per queue = Y\n-Extended stats = Y\n-FW version = Y\n-Module EEPROM dump = Y\n-Registers dump = Y\n-Linux = Y\n-ARMv8 = Y\n-Usage doc = Y\n-\n-[rte_flow items]\n-any = Y\n-arp_eth_ipv4 = Y\n-esp = Y\n-eth = Y\n-e_tag = Y\n-geneve = Y\n-gre = Y\n-gre_key = Y\n-gtpc = Y\n-gtpu = Y\n-higig2 = Y\n-icmp = Y\n-ipv4 = Y\n-ipv6 = Y\n-ipv6_ext = Y\n-mpls = Y\n-nvgre = Y\n-raw = Y\n-sctp = Y\n-tcp = Y\n-udp = Y\n-vlan = Y\n-vxlan = Y\n-vxlan_gpe = Y\n-\n-[rte_flow actions]\n-count = Y\n-drop = Y\n-flag = Y\n-mark = Y\n-of_pop_vlan = Y\n-of_push_vlan = Y\n-of_set_vlan_pcp = Y\n-of_set_vlan_vid = Y\n-pf = Y\n-port_id = Y\n-port_representor = Y\n-queue = Y\n-rss = Y\n-security = Y\n-vf = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vec.ini b/doc/guides/nics/features/octeontx2_vec.ini\ndeleted file mode 100644\nindex c405db7cf9..0000000000\n--- a/doc/guides/nics/features/octeontx2_vec.ini\n+++ /dev/null\n@@ -1,48 +0,0 @@\n-;\n-; Supported features of the 'octeontx2_vec' network poll mode driver.\n-;\n-; Refer to default.ini for the full list of available PMD features.\n-;\n-[Features]\n-Speed capabilities = Y\n-Lock-free Tx queue = Y\n-SR-IOV = Y\n-Multiprocess aware = Y\n-Link status = Y\n-Link status event = Y\n-Runtime Rx queue setup = Y\n-Runtime Tx queue setup = Y\n-Burst mode info = Y\n-Fast mbuf free = Y\n-Free Tx mbuf on demand = Y\n-Queue start/stop = Y\n-MTU update = Y\n-Promiscuous mode = Y\n-Allmulticast mode = Y\n-Unicast MAC filter = Y\n-Multicast MAC filter = Y\n-RSS hash = Y\n-RSS key update = Y\n-RSS reta update = Y\n-Inner RSS = Y\n-VLAN filter = Y\n-Flow control = Y\n-Rate limitation = Y\n-VLAN offload = Y\n-QinQ offload = Y\n-L3 checksum offload = Y\n-L4 checksum offload = Y\n-Inner L3 checksum = Y\n-Inner L4 checksum = Y\n-Packet type parsing = Y\n-Rx descriptor status = Y\n-Tx descriptor status = Y\n-Basic stats = Y\n-Extended stats = Y\n-Stats per queue = Y\n-FW version = Y\n-Module EEPROM dump = Y\n-Registers dump = Y\n-Linux = Y\n-ARMv8 = Y\n-Usage doc = Y\ndiff --git a/doc/guides/nics/features/octeontx2_vf.ini b/doc/guides/nics/features/octeontx2_vf.ini\ndeleted file mode 100644\nindex 5ac7a49a5c..0000000000\n--- a/doc/guides/nics/features/octeontx2_vf.ini\n+++ /dev/null\n@@ -1,45 +0,0 @@\n-;\n-; Supported features of the 'octeontx2_vf' network poll mode driver.\n-;\n-; Refer to default.ini for the full list of available PMD features.\n-;\n-[Features]\n-Speed capabilities = Y\n-Lock-free Tx queue = Y\n-Multiprocess aware = Y\n-Rx interrupt = Y\n-Link status = Y\n-Link status event = Y\n-Runtime Rx queue setup = Y\n-Runtime Tx queue setup = Y\n-Burst mode info = Y\n-Fast mbuf free = Y\n-Free Tx mbuf on demand = Y\n-Queue start/stop = Y\n-TSO = Y\n-RSS hash = Y\n-RSS key update = Y\n-RSS reta update = Y\n-Inner RSS = Y\n-Inline protocol = Y\n-VLAN filter = Y\n-Rate limitation = Y\n-Scattered Rx = Y\n-VLAN offload = Y\n-QinQ offload = Y\n-L3 checksum offload = Y\n-L4 checksum offload = Y\n-Inner L3 checksum = Y\n-Inner L4 checksum = Y\n-Packet type parsing = Y\n-Rx descriptor status = Y\n-Tx descriptor status = Y\n-Basic stats = Y\n-Extended stats = Y\n-Stats per queue = Y\n-FW version = Y\n-Module EEPROM dump = Y\n-Registers dump = Y\n-Linux = Y\n-ARMv8 = Y\n-Usage doc = Y\ndiff --git a/doc/guides/nics/index.rst b/doc/guides/nics/index.rst\nindex 1c94caccea..f48e9f815c 100644\n--- a/doc/guides/nics/index.rst\n+++ b/doc/guides/nics/index.rst\n@@ -52,7 +52,6 @@ Network Interface Controller Drivers\n ngbe\n null\n octeontx\n- octeontx2\n octeontx_ep\n pfe\n qede\ndiff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst\ndeleted file mode 100644\nindex 4ce067f2c5..0000000000\n--- a/doc/guides/nics/octeontx2.rst\n+++ /dev/null\n@@ -1,465 +0,0 @@\n-.. SPDX-License-Identifier: BSD-3-Clause\n- Copyright(C) 2019 Marvell International Ltd.\n-\n-OCTEON TX2 Poll Mode driver\n-===========================\n-\n-The OCTEON TX2 ETHDEV PMD (**librte_net_octeontx2**) provides poll mode ethdev\n-driver support for the inbuilt network device found in **Marvell OCTEON TX2**\n-SoC family as well as for their virtual functions (VF) in SR-IOV context.\n-\n-More information can be found at `Marvell Official Website\n-<https://www.marvell.com/embedded-processors/infrastructure-processors>`_.\n-\n-Features\n---------\n-\n-Features of the OCTEON TX2 Ethdev PMD are:\n-\n-- Packet type information\n-- Promiscuous mode\n-- Jumbo frames\n-- SR-IOV VF\n-- Lock-free Tx queue\n-- Multiple queues for TX and RX\n-- Receiver Side Scaling (RSS)\n-- MAC/VLAN filtering\n-- Multicast MAC filtering\n-- Generic flow API\n-- Inner and Outer Checksum offload\n-- VLAN/QinQ stripping and insertion\n-- Port hardware statistics\n-- Link state information\n-- Link flow control\n-- MTU update\n-- Scatter-Gather IO support\n-- Vector Poll mode driver\n-- Debug utilities - Context dump and error interrupt support\n-- IEEE1588 timestamping\n-- HW offloaded `ethdev Rx queue` to `eventdev event queue` packet injection\n-- Support Rx interrupt\n-- Inline IPsec processing support\n-- :ref:`Traffic Management API <otx2_tmapi>`\n-\n-Prerequisites\n--------------\n-\n-See :doc:`../platform/octeontx2` for setup information.\n-\n-\n-Driver compilation and testing\n-------------------------------\n-\n-Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`\n-for details.\n-\n-#. Running testpmd:\n-\n- Follow instructions available in the document\n- :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`\n- to run testpmd.\n-\n- Example output:\n-\n- .. code-block:: console\n-\n- ./<build_dir>/app/dpdk-testpmd -c 0x300 -a 0002:02:00.0 -- --portmask=0x1 --nb-cores=1 --port-topology=loop --rxq=1 --txq=1\n- EAL: Detected 24 lcore(s)\n- EAL: Detected 1 NUMA nodes\n- EAL: Multi-process socket /var/run/dpdk/rte/mp_socket\n- EAL: No available hugepages reported in hugepages-2048kB\n- EAL: Probing VFIO support...\n- EAL: VFIO support initialized\n- EAL: PCI device 0002:02:00.0 on NUMA socket 0\n- EAL: probe driver: 177d:a063 net_octeontx2\n- EAL: using IOMMU type 1 (Type 1)\n- testpmd: create a new mbuf pool <mbuf_pool_socket_0>: n=267456, size=2176, socket=0\n- testpmd: preferred mempool ops selected: octeontx2_npa\n- Configuring Port 0 (socket 0)\n- PMD: Port 0: Link Up - speed 40000 Mbps - full-duplex\n-\n- Port 0: link state change event\n- Port 0: 36:10:66:88:7A:57\n- Checking link statuses...\n- Done\n- No commandline core given, start packet forwarding\n- io packet forwarding - ports=1 - cores=1 - streams=1 - NUMA support enabled, MP allocation mode: native\n- Logical Core 9 (socket 0) forwards packets on 1 streams:\n- RX P=0/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00\n-\n- io packet forwarding packets/burst=32\n- nb forwarding cores=1 - nb forwarding ports=1\n- port 0: RX queue number: 1 Tx queue number: 1\n- Rx offloads=0x0 Tx offloads=0x10000\n- RX queue: 0\n- RX desc=512 - RX free threshold=0\n- RX threshold registers: pthresh=0 hthresh=0 wthresh=0\n- RX Offloads=0x0\n- TX queue: 0\n- TX desc=512 - TX free threshold=0\n- TX threshold registers: pthresh=0 hthresh=0 wthresh=0\n- TX offloads=0x10000 - TX RS bit threshold=0\n- Press enter to exit\n-\n-Runtime Config Options\n-----------------------\n-\n-- ``Rx&Tx scalar mode enable`` (default ``0``)\n-\n- Ethdev supports both scalar and vector mode, it may be selected at runtime\n- using ``scalar_enable`` ``devargs`` parameter.\n-\n-- ``RSS reta size`` (default ``64``)\n-\n- RSS redirection table size may be configured during runtime using ``reta_size``\n- ``devargs`` parameter.\n-\n- For example::\n-\n- -a 0002:02:00.0,reta_size=256\n-\n- With the above configuration, reta table of size 256 is populated.\n-\n-- ``Flow priority levels`` (default ``3``)\n-\n- RTE Flow priority levels can be configured during runtime using\n- ``flow_max_priority`` ``devargs`` parameter.\n-\n- For example::\n-\n- -a 0002:02:00.0,flow_max_priority=10\n-\n- With the above configuration, priority level was set to 10 (0-9). Max\n- priority level supported is 32.\n-\n-- ``Reserve Flow entries`` (default ``8``)\n-\n- RTE flow entries can be pre allocated and the size of pre allocation can be\n- selected runtime using ``flow_prealloc_size`` ``devargs`` parameter.\n-\n- For example::\n-\n- -a 0002:02:00.0,flow_prealloc_size=4\n-\n- With the above configuration, pre alloc size was set to 4. Max pre alloc\n- size supported is 32.\n-\n-- ``Max SQB buffer count`` (default ``512``)\n-\n- Send queue descriptor buffer count may be limited during runtime using\n- ``max_sqb_count`` ``devargs`` parameter.\n-\n- For example::\n-\n- -a 0002:02:00.0,max_sqb_count=64\n-\n- With the above configuration, each send queue's descriptor buffer count is\n- limited to a maximum of 64 buffers.\n-\n-- ``Switch header enable`` (default ``none``)\n-\n- A port can be configured to a specific switch header type by using\n- ``switch_header`` ``devargs`` parameter.\n-\n- For example::\n-\n- -a 0002:02:00.0,switch_header=\"higig2\"\n-\n- With the above configuration, higig2 will be enabled on that port and the\n- traffic on this port should be higig2 traffic only. Supported switch header\n- types are \"chlen24b\", \"chlen90b\", \"dsa\", \"exdsa\", \"higig2\" and \"vlan_exdsa\".\n-\n-- ``RSS tag as XOR`` (default ``0``)\n-\n- C0 HW revision onward, The HW gives an option to configure the RSS adder as\n-\n- * ``rss_adder<7:0> = flow_tag<7:0> ^ flow_tag<15:8> ^ flow_tag<23:16> ^ flow_tag<31:24>``\n-\n- * ``rss_adder<7:0> = flow_tag<7:0>``\n-\n- Latter one aligns with standard NIC behavior vs former one is a legacy\n- RSS adder scheme used in OCTEON TX2 products.\n-\n- By default, the driver runs in the latter mode from C0 HW revision onward.\n- Setting this flag to 1 to select the legacy mode.\n-\n- For example to select the legacy mode(RSS tag adder as XOR)::\n-\n- -a 0002:02:00.0,tag_as_xor=1\n-\n-- ``Max SPI for inbound inline IPsec`` (default ``1``)\n-\n- Max SPI supported for inbound inline IPsec processing can be specified by\n- ``ipsec_in_max_spi`` ``devargs`` parameter.\n-\n- For example::\n-\n- -a 0002:02:00.0,ipsec_in_max_spi=128\n-\n- With the above configuration, application can enable inline IPsec processing\n- on 128 SAs (SPI 0-127).\n-\n-- ``Lock Rx contexts in NDC cache``\n-\n- Lock Rx contexts in NDC cache by using ``lock_rx_ctx`` parameter.\n-\n- For example::\n-\n- -a 0002:02:00.0,lock_rx_ctx=1\n-\n-- ``Lock Tx contexts in NDC cache``\n-\n- Lock Tx contexts in NDC cache by using ``lock_tx_ctx`` parameter.\n-\n- For example::\n-\n- -a 0002:02:00.0,lock_tx_ctx=1\n-\n-.. note::\n-\n- Above devarg parameters are configurable per device, user needs to pass the\n- parameters to all the PCIe devices if application requires to configure on\n- all the ethdev ports.\n-\n-- ``Lock NPA contexts in NDC``\n-\n- Lock NPA aura and pool contexts in NDC cache.\n- The device args take hexadecimal bitmask where each bit represent the\n- corresponding aura/pool id.\n-\n- For example::\n-\n- -a 0002:02:00.0,npa_lock_mask=0xf\n-\n-.. _otx2_tmapi:\n-\n-Traffic Management API\n-----------------------\n-\n-OCTEON TX2 PMD supports generic DPDK Traffic Management API which allows to\n-configure the following features:\n-\n-#. Hierarchical scheduling\n-#. Single rate - Two color, Two rate - Three color shaping\n-\n-Both DWRR and Static Priority(SP) hierarchical scheduling is supported.\n-\n-Every parent can have atmost 10 SP Children and unlimited DWRR children.\n-\n-Both PF & VF supports traffic management API with PF supporting 6 levels\n-and VF supporting 5 levels of topology.\n-\n-Limitations\n------------\n-\n-``mempool_octeontx2`` external mempool handler dependency\n-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n-\n-The OCTEON TX2 SoC family NIC has inbuilt HW assisted external mempool manager.\n-``net_octeontx2`` PMD only works with ``mempool_octeontx2`` mempool handler\n-as it is performance wise most effective way for packet allocation and Tx buffer\n-recycling on OCTEON TX2 SoC platform.\n-\n-CRC stripping\n-~~~~~~~~~~~~~\n-\n-The OCTEON TX2 SoC family NICs strip the CRC for every packet being received by\n-the host interface irrespective of the offload configuration.\n-\n-Multicast MAC filtering\n-~~~~~~~~~~~~~~~~~~~~~~~\n-\n-``net_octeontx2`` PMD supports multicast mac filtering feature only on physical\n-function devices.\n-\n-SDP interface support\n-~~~~~~~~~~~~~~~~~~~~~\n-OCTEON TX2 SDP interface support is limited to PF device, No VF support.\n-\n-Inline Protocol Processing\n-~~~~~~~~~~~~~~~~~~~~~~~~~~\n-``net_octeontx2`` PMD doesn't support the following features for packets to be\n-inline protocol processed.\n-- TSO offload\n-- VLAN/QinQ offload\n-- Fragmentation\n-\n-Debugging Options\n------------------\n-\n-.. _table_octeontx2_ethdev_debug_options:\n-\n-.. table:: OCTEON TX2 ethdev debug options\n-\n- +---+------------+-------------------------------------------------------+\n- | # | Component | EAL log command |\n- +===+============+=======================================================+\n- | 1 | NIX | --log-level='pmd\\.net.octeontx2,8' |\n- +---+------------+-------------------------------------------------------+\n- | 2 | NPC | --log-level='pmd\\.net.octeontx2\\.flow,8' |\n- +---+------------+-------------------------------------------------------+\n-\n-RTE Flow Support\n-----------------\n-\n-The OCTEON TX2 SoC family NIC has support for the following patterns and\n-actions.\n-\n-Patterns:\n-\n-.. _table_octeontx2_supported_flow_item_types:\n-\n-.. table:: Item types\n-\n- +----+--------------------------------+\n- | # | Pattern Type |\n- +====+================================+\n- | 1 | RTE_FLOW_ITEM_TYPE_ETH |\n- +----+--------------------------------+\n- | 2 | RTE_FLOW_ITEM_TYPE_VLAN |\n- +----+--------------------------------+\n- | 3 | RTE_FLOW_ITEM_TYPE_E_TAG |\n- +----+--------------------------------+\n- | 4 | RTE_FLOW_ITEM_TYPE_IPV4 |\n- +----+--------------------------------+\n- | 5 | RTE_FLOW_ITEM_TYPE_IPV6 |\n- +----+--------------------------------+\n- | 6 | RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4|\n- +----+--------------------------------+\n- | 7 | RTE_FLOW_ITEM_TYPE_MPLS |\n- +----+--------------------------------+\n- | 8 | RTE_FLOW_ITEM_TYPE_ICMP |\n- +----+--------------------------------+\n- | 9 | RTE_FLOW_ITEM_TYPE_UDP |\n- +----+--------------------------------+\n- | 10 | RTE_FLOW_ITEM_TYPE_TCP |\n- +----+--------------------------------+\n- | 11 | RTE_FLOW_ITEM_TYPE_SCTP |\n- +----+--------------------------------+\n- | 12 | RTE_FLOW_ITEM_TYPE_ESP |\n- +----+--------------------------------+\n- | 13 | RTE_FLOW_ITEM_TYPE_GRE |\n- +----+--------------------------------+\n- | 14 | RTE_FLOW_ITEM_TYPE_NVGRE |\n- +----+--------------------------------+\n- | 15 | RTE_FLOW_ITEM_TYPE_VXLAN |\n- +----+--------------------------------+\n- | 16 | RTE_FLOW_ITEM_TYPE_GTPC |\n- +----+--------------------------------+\n- | 17 | RTE_FLOW_ITEM_TYPE_GTPU |\n- +----+--------------------------------+\n- | 18 | RTE_FLOW_ITEM_TYPE_GENEVE |\n- +----+--------------------------------+\n- | 19 | RTE_FLOW_ITEM_TYPE_VXLAN_GPE |\n- +----+--------------------------------+\n- | 20 | RTE_FLOW_ITEM_TYPE_IPV6_EXT |\n- +----+--------------------------------+\n- | 21 | RTE_FLOW_ITEM_TYPE_VOID |\n- +----+--------------------------------+\n- | 22 | RTE_FLOW_ITEM_TYPE_ANY |\n- +----+--------------------------------+\n- | 23 | RTE_FLOW_ITEM_TYPE_GRE_KEY |\n- +----+--------------------------------+\n- | 24 | RTE_FLOW_ITEM_TYPE_HIGIG2 |\n- +----+--------------------------------+\n- | 25 | RTE_FLOW_ITEM_TYPE_RAW |\n- +----+--------------------------------+\n-\n-.. note::\n-\n- ``RTE_FLOW_ITEM_TYPE_GRE_KEY`` works only when checksum and routing\n- bits in the GRE header are equal to 0.\n-\n-Actions:\n-\n-.. _table_octeontx2_supported_ingress_action_types:\n-\n-.. table:: Ingress action types\n-\n- +----+-----------------------------------------+\n- | # | Action Type |\n- +====+=========================================+\n- | 1 | RTE_FLOW_ACTION_TYPE_VOID |\n- +----+-----------------------------------------+\n- | 2 | RTE_FLOW_ACTION_TYPE_MARK |\n- +----+-----------------------------------------+\n- | 3 | RTE_FLOW_ACTION_TYPE_FLAG |\n- +----+-----------------------------------------+\n- | 4 | RTE_FLOW_ACTION_TYPE_COUNT |\n- +----+-----------------------------------------+\n- | 5 | RTE_FLOW_ACTION_TYPE_DROP |\n- +----+-----------------------------------------+\n- | 6 | RTE_FLOW_ACTION_TYPE_QUEUE |\n- +----+-----------------------------------------+\n- | 7 | RTE_FLOW_ACTION_TYPE_RSS |\n- +----+-----------------------------------------+\n- | 8 | RTE_FLOW_ACTION_TYPE_SECURITY |\n- +----+-----------------------------------------+\n- | 9 | RTE_FLOW_ACTION_TYPE_PF |\n- +----+-----------------------------------------+\n- | 10 | RTE_FLOW_ACTION_TYPE_VF |\n- +----+-----------------------------------------+\n- | 11 | RTE_FLOW_ACTION_TYPE_OF_POP_VLAN |\n- +----+-----------------------------------------+\n- | 12 | RTE_FLOW_ACTION_TYPE_PORT_ID |\n- +----+-----------------------------------------+\n- | 13 | RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR |\n- +----+-----------------------------------------+\n-\n-.. note::\n-\n- ``RTE_FLOW_ACTION_TYPE_PORT_ID``, ``RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR``\n- are only supported between PF and its VFs.\n-\n-.. _table_octeontx2_supported_egress_action_types:\n-\n-.. table:: Egress action types\n-\n- +----+-----------------------------------------+\n- | # | Action Type |\n- +====+=========================================+\n- | 1 | RTE_FLOW_ACTION_TYPE_COUNT |\n- +----+-----------------------------------------+\n- | 2 | RTE_FLOW_ACTION_TYPE_DROP |\n- +----+-----------------------------------------+\n- | 3 | RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN |\n- +----+-----------------------------------------+\n- | 4 | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID |\n- +----+-----------------------------------------+\n- | 5 | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP |\n- +----+-----------------------------------------+\n-\n-Custom protocols supported in RTE Flow\n-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n-\n-The ``RTE_FLOW_ITEM_TYPE_RAW`` can be used to parse the below custom protocols.\n-\n-* ``vlan_exdsa`` and ``exdsa`` can be parsed at L2 level.\n-* ``NGIO`` can be parsed at L3 level.\n-\n-For ``vlan_exdsa`` and ``exdsa``, the port has to be configured with the\n-respective switch header.\n-\n-For example::\n-\n- -a 0002:02:00.0,switch_header=\"vlan_exdsa\"\n-\n-The below fields of ``struct rte_flow_item_raw`` shall be used to specify the\n-pattern.\n-\n-- ``relative`` Selects the layer at which parsing is done.\n-\n- - 0 for ``exdsa`` and ``vlan_exdsa``.\n-\n- - 1 for ``NGIO``.\n-\n-- ``offset`` The offset in the header where the pattern should be matched.\n-- ``length`` Length of the pattern.\n-- ``pattern`` Pattern as a byte string.\n-\n-Example usage in testpmd::\n-\n- ./dpdk-testpmd -c 3 -w 0002:02:00.0,switch_header=exdsa -- -i \\\n- --rx-offloads=0x00080000 --rxq 8 --txq 8\n- testpmd> flow create 0 ingress pattern eth / raw relative is 0 pattern \\\n- spec ab pattern mask ab offset is 4 / end actions queue index 1 / end\ndiff --git a/doc/guides/nics/octeontx_ep.rst b/doc/guides/nics/octeontx_ep.rst\nindex b512ccfdab..2ec8a034b5 100644\n--- a/doc/guides/nics/octeontx_ep.rst\n+++ b/doc/guides/nics/octeontx_ep.rst\n@@ -5,7 +5,7 @@ OCTEON TX EP Poll Mode driver\n =============================\n \n The OCTEON TX EP ETHDEV PMD (**librte_pmd_octeontx_ep**) provides poll mode\n-ethdev driver support for the virtual functions (VF) of **Marvell OCTEON TX2**\n+ethdev driver support for the virtual functions (VF) of **Marvell OCTEON 9**\n and **Cavium OCTEON TX** families of adapters in SR-IOV context.\n \n More information can be found at `Marvell Official Website\n@@ -24,4 +24,4 @@ must be installed separately:\n allocates resources such as number of VFs, input/output queues for itself and\n the number of i/o queues each VF can use.\n \n-See :doc:`../platform/octeontx2` for SDP interface information which provides PCIe endpoint support for a remote host.\n+See :doc:`../platform/cnxk` for SDP interface information which provides PCIe endpoint support for a remote host.\ndiff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst\nindex 5213df3ccd..97e38c868c 100644\n--- a/doc/guides/platform/cnxk.rst\n+++ b/doc/guides/platform/cnxk.rst\n@@ -13,6 +13,9 @@ More information about CN9K and CN10K SoC can be found at `Marvell Official Webs\n Supported OCTEON cnxk SoCs\n --------------------------\n \n+- CN93xx\n+- CN96xx\n+- CN98xx\n - CN106xx\n - CNF105xx\n \n@@ -583,6 +586,15 @@ Cross Compilation\n \n Refer to :doc:`../linux_gsg/cross_build_dpdk_for_arm64` for generic arm64 details.\n \n+CN9K:\n+\n+.. code-block:: console\n+\n+ meson build --cross-file config/arm/arm64_cn9k_linux_gcc\n+ ninja -C build\n+\n+CN10K:\n+\n .. code-block:: console\n \n meson build --cross-file config/arm/arm64_cn10k_linux_gcc\ndiff --git a/doc/guides/platform/img/octeontx2_packet_flow_hw_accelerators.svg b/doc/guides/platform/img/octeontx2_packet_flow_hw_accelerators.svg\ndeleted file mode 100644\nindex ecd575947a..0000000000\n--- a/doc/guides/platform/img/octeontx2_packet_flow_hw_accelerators.svg\n+++ /dev/null\n@@ -1,2804 +0,0 @@\n-<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\"?>\n-<!-- Created with Inkscape (http://www.inkscape.org/) -->\n-\n-<!--\n-# SPDX-License-Identifier: BSD-3-Clause\n-# Copyright(c) 2019 Marvell International Ltd.\n-#\n--->\n-\n-<svg\n- xmlns:osb=\"http://www.openswatchbook.org/uri/2009/osb\"\n- xmlns:dc=\"http://purl.org/dc/elements/1.1/\"\n- xmlns:cc=\"http://creativecommons.org/ns#\"\n- xmlns:rdf=\"http://www.w3.org/1999/02/22-rdf-syntax-ns#\"\n- xmlns:svg=\"http://www.w3.org/2000/svg\"\n- xmlns=\"http://www.w3.org/2000/svg\"\n- xmlns:xlink=\"http://www.w3.org/1999/xlink\"\n- xmlns:sodipodi=\"http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd\"\n- xmlns:inkscape=\"http://www.inkscape.org/namespaces/inkscape\"\n- width=\"631.91431\"\n- height=\"288.34286\"\n- id=\"svg3868\"\n- version=\"1.1\"\n- inkscape:version=\"0.92.4 (5da689c313, 2019-01-14)\"\n- sodipodi:docname=\"octeontx2_packet_flow_hw_accelerators.svg\"\n- sodipodi:version=\"0.32\"\n- inkscape:output_extension=\"org.inkscape.output.svg.inkscape\">\n- <defs\n- id=\"defs3870\">\n- <marker\n- inkscape:isstock=\"true\"\n- style=\"overflow:visible;\"\n- id=\"marker18508\"\n- refX=\"0.0\"\n- refY=\"0.0\"\n- orient=\"auto\"\n- inkscape:stockid=\"Arrow1Send\">\n- <path\n- transform=\"scale(0.2) rotate(180) translate(6,0)\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1;fill:#000000;fill-opacity:1\"\n- d=\"M 0.0,0.0 L 5.0,-5.0 L -12.5,0.0 L 5.0,5.0 L 0.0,0.0 z \"\n- id=\"path18506\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Sstart\"\n- orient=\"auto\"\n- refY=\"0.0\"\n- refX=\"0.0\"\n- id=\"marker18096\"\n- style=\"overflow:visible\"\n- inkscape:isstock=\"true\">\n- <path\n- id=\"path18094\"\n- d=\"M 0.0,0.0 L 5.0,-5.0 L -12.5,0.0 L 5.0,5.0 L 0.0,0.0 z \"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1;fill:#000000;fill-opacity:1\"\n- transform=\"scale(0.2) translate(6,0)\" />\n- </marker>\n- <marker\n- inkscape:isstock=\"true\"\n- style=\"overflow:visible\"\n- id=\"marker17550\"\n- refX=\"0.0\"\n- refY=\"0.0\"\n- orient=\"auto\"\n- inkscape:stockid=\"Arrow1Sstart\"\n- inkscape:collect=\"always\">\n- <path\n- transform=\"scale(0.2) translate(6,0)\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1;fill:#000000;fill-opacity:1\"\n- d=\"M 0.0,0.0 L 5.0,-5.0 L -12.5,0.0 L 5.0,5.0 L 0.0,0.0 z \"\n- id=\"path17548\" />\n- </marker>\n- <marker\n- inkscape:isstock=\"true\"\n- style=\"overflow:visible;\"\n- id=\"marker17156\"\n- refX=\"0.0\"\n- refY=\"0.0\"\n- orient=\"auto\"\n- inkscape:stockid=\"Arrow1Send\">\n- <path\n- transform=\"scale(0.2) rotate(180) translate(6,0)\"\n- style=\"fill-rule:evenodd;stroke:#00db00;stroke-width:1pt;stroke-opacity:1;fill:#00db00;fill-opacity:1\"\n- d=\"M 0.0,0.0 L 5.0,-5.0 L -12.5,0.0 L 5.0,5.0 L 0.0,0.0 z \"\n- id=\"path17154\" />\n- </marker>\n- <linearGradient\n- inkscape:collect=\"always\"\n- id=\"linearGradient13962\">\n- <stop\n- style=\"stop-color:#fc0000;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop13958\" />\n- <stop\n- style=\"stop-color:#fc0000;stop-opacity:0;\"\n- offset=\"1\"\n- id=\"stop13960\" />\n- </linearGradient>\n- <marker\n- inkscape:stockid=\"Arrow1Send\"\n- orient=\"auto\"\n- refY=\"0.0\"\n- refX=\"0.0\"\n- id=\"Arrow1Send\"\n- style=\"overflow:visible;\"\n- inkscape:isstock=\"true\"\n- inkscape:collect=\"always\">\n- <path\n- id=\"path6218\"\n- d=\"M 0.0,0.0 L 5.0,-5.0 L -12.5,0.0 L 5.0,5.0 L 0.0,0.0 z \"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1;fill:#000000;fill-opacity:1\"\n- transform=\"scale(0.2) rotate(180) translate(6,0)\" />\n- </marker>\n- <linearGradient\n- id=\"linearGradient13170\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#ff0000;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop13168\" />\n- </linearGradient>\n- <marker\n- inkscape:stockid=\"Arrow2Mend\"\n- orient=\"auto\"\n- refY=\"0.0\"\n- refX=\"0.0\"\n- id=\"marker12747\"\n- style=\"overflow:visible;\"\n- inkscape:isstock=\"true\">\n- <path\n- id=\"path12745\"\n- style=\"fill-rule:evenodd;stroke-width:0.625;stroke-linejoin:round;stroke:#ff0000;stroke-opacity:1;fill:#ff0000;fill-opacity:1\"\n- d=\"M 8.7185878,4.0337352 L -2.2072895,0.016013256 L 8.7185884,-4.0017078 C 6.9730900,-1.6296469 6.9831476,1.6157441 8.7185878,4.0337352 z \"\n- transform=\"scale(0.6) rotate(180) translate(0,0)\" />\n- </marker>\n- <marker\n- inkscape:isstock=\"true\"\n- style=\"overflow:visible;\"\n- id=\"marker10821\"\n- refX=\"0.0\"\n- refY=\"0.0\"\n- orient=\"auto\"\n- inkscape:stockid=\"Arrow2Mend\"\n- inkscape:collect=\"always\">\n- <path\n- transform=\"scale(0.6) rotate(180) translate(0,0)\"\n- d=\"M 8.7185878,4.0337352 L -2.2072895,0.016013256 L 8.7185884,-4.0017078 C 6.9730900,-1.6296469 6.9831476,1.6157441 8.7185878,4.0337352 z \"\n- style=\"fill-rule:evenodd;stroke-width:0.625;stroke-linejoin:round;stroke:#fe0000;stroke-opacity:1;fill:#fe0000;fill-opacity:1\"\n- id=\"path10819\" />\n- </marker>\n- <marker\n- inkscape:isstock=\"true\"\n- style=\"overflow:visible;\"\n- id=\"marker10463\"\n- refX=\"0.0\"\n- refY=\"0.0\"\n- orient=\"auto\"\n- inkscape:stockid=\"Arrow2Mend\">\n- <path\n- transform=\"scale(0.6) rotate(180) translate(0,0)\"\n- d=\"M 8.7185878,4.0337352 L -2.2072895,0.016013256 L 8.7185884,-4.0017078 C 6.9730900,-1.6296469 6.9831476,1.6157441 8.7185878,4.0337352 z \"\n- style=\"fill-rule:evenodd;stroke-width:0.625;stroke-linejoin:round;stroke:#fe0000;stroke-opacity:1;fill:#fe0000;fill-opacity:1\"\n- id=\"path10461\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow2Mend\"\n- orient=\"auto\"\n- refY=\"0.0\"\n- refX=\"0.0\"\n- id=\"Arrow2Mend\"\n- style=\"overflow:visible;\"\n- inkscape:isstock=\"true\"\n- inkscape:collect=\"always\">\n- <path\n- id=\"path6230\"\n- style=\"fill-rule:evenodd;stroke-width:0.625;stroke-linejoin:round;stroke:#fe0000;stroke-opacity:1;fill:#fe0000;fill-opacity:1\"\n- d=\"M 8.7185878,4.0337352 L -2.2072895,0.016013256 L 8.7185884,-4.0017078 C 6.9730900,-1.6296469 6.9831476,1.6157441 8.7185878,4.0337352 z \"\n- transform=\"scale(0.6) rotate(180) translate(0,0)\" />\n- </marker>\n- <marker\n- inkscape:isstock=\"true\"\n- style=\"overflow:visible\"\n- id=\"marker9807\"\n- refX=\"0.0\"\n- refY=\"0.0\"\n- orient=\"auto\"\n- inkscape:stockid=\"TriangleOutS\">\n- <path\n- transform=\"scale(0.2)\"\n- style=\"fill-rule:evenodd;stroke:#fe0000;stroke-width:1pt;stroke-opacity:1;fill:#fe0000;fill-opacity:1\"\n- d=\"M 5.77,0.0 L -2.88,5.0 L -2.88,-5.0 L 5.77,0.0 z \"\n- id=\"path9805\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"TriangleOutS\"\n- orient=\"auto\"\n- refY=\"0.0\"\n- refX=\"0.0\"\n- id=\"TriangleOutS\"\n- style=\"overflow:visible\"\n- inkscape:isstock=\"true\"\n- inkscape:collect=\"always\">\n- <path\n- id=\"path6351\"\n- d=\"M 5.77,0.0 L -2.88,5.0 L -2.88,-5.0 L 5.77,0.0 z \"\n- style=\"fill-rule:evenodd;stroke:#fe0000;stroke-width:1pt;stroke-opacity:1;fill:#fe0000;fill-opacity:1\"\n- transform=\"scale(0.2)\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Sstart\"\n- orient=\"auto\"\n- refY=\"0.0\"\n- refX=\"0.0\"\n- id=\"Arrow1Sstart\"\n- style=\"overflow:visible\"\n- inkscape:isstock=\"true\"\n- inkscape:collect=\"always\">\n- <path\n- id=\"path6215\"\n- d=\"M 0.0,0.0 L 5.0,-5.0 L -12.5,0.0 L 5.0,5.0 L 0.0,0.0 z \"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1;fill:#000000;fill-opacity:1\"\n- transform=\"scale(0.2) translate(6,0)\" />\n- </marker>\n- <linearGradient\n- inkscape:collect=\"always\"\n- id=\"linearGradient4340\">\n- <stop\n- style=\"stop-color:#d7eef4;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop4336\" />\n- <stop\n- style=\"stop-color:#d7eef4;stop-opacity:0;\"\n- offset=\"1\"\n- id=\"stop4338\" />\n- </linearGradient>\n- <linearGradient\n- inkscape:collect=\"always\"\n- id=\"linearGradient4330\">\n- <stop\n- style=\"stop-color:#d7eef4;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop4326\" />\n- <stop\n- style=\"stop-color:#d7eef4;stop-opacity:0;\"\n- offset=\"1\"\n- id=\"stop4328\" />\n- </linearGradient>\n- <linearGradient\n- inkscape:collect=\"always\"\n- id=\"linearGradient3596\">\n- <stop\n- style=\"stop-color:#6ba6fd;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3592\" />\n- <stop\n- style=\"stop-color:#6ba6fd;stop-opacity:0;\"\n- offset=\"1\"\n- id=\"stop3594\" />\n- </linearGradient>\n- <marker\n- inkscape:stockid=\"Arrow1Lstart\"\n- orient=\"auto\"\n- refY=\"0.0\"\n- refX=\"0.0\"\n- id=\"marker9460\"\n- style=\"overflow:visible\"\n- inkscape:isstock=\"true\">\n- <path\n- id=\"path9458\"\n- d=\"M 0.0,0.0 L 5.0,-5.0 L -12.5,0.0 L 5.0,5.0 L 0.0,0.0 z \"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1;fill:#000000;fill-opacity:1\"\n- transform=\"scale(0.8) translate(12.5,0)\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lstart\"\n- orient=\"auto\"\n- refY=\"0.0\"\n- refX=\"0.0\"\n- id=\"marker7396\"\n- style=\"overflow:visible\"\n- inkscape:isstock=\"true\">\n- <path\n- id=\"path7133\"\n- d=\"M 0.0,0.0 L 5.0,-5.0 L -12.5,0.0 L 5.0,5.0 L 0.0,0.0 z \"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1;fill:#000000;fill-opacity:1\"\n- transform=\"scale(0.8) translate(12.5,0)\" />\n- </marker>\n- <linearGradient\n- inkscape:collect=\"always\"\n- id=\"linearGradient5474\">\n- <stop\n- style=\"stop-color:#ffffff;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop5470\" />\n- <stop\n- style=\"stop-color:#ffffff;stop-opacity:0;\"\n- offset=\"1\"\n- id=\"stop5472\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient6545\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#ffa600;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop6543\" />\n- </linearGradient>\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3302\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3294\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3290\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3286\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3228\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3188\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3184\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3180\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3176\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3172\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3168\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3164\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3160\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3120\"\n- is_visible=\"true\" />\n- <linearGradient\n- id=\"linearGradient3114\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#00f900;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3112\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient3088\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#00f900;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3086\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient3058\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#00f900;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3056\" />\n- </linearGradient>\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3054\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3050\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3046\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3042\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3038\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3034\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3030\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3008\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3004\"\n- is_visible=\"true\" />\n- <linearGradient\n- id=\"linearGradient2975\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#ff2200;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop2973\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient2969\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#69ff72;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop2967\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient2963\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#000000;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop2961\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient2929\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#ff2d00;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop2927\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient4610\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#00ffff;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop4608\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient3993\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#6ba6fd;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3991\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient3808\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#6ba6fd;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3806\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient3776\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#fc0000;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3774\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient3438\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#b8e132;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3436\" />\n- </linearGradient>\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3408\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3404\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3400\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3392\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3376\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3044\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3040\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3036\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3032\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3028\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3024\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3020\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect2858\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect2854\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect2844\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <linearGradient\n- id=\"linearGradient2828\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#ff0000;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop2826\" />\n- </linearGradient>\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect329\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <linearGradient\n- id=\"linearGradient4513\">\n- <stop\n- style=\"stop-color:#fdffdb;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop4515\" />\n- <stop\n- style=\"stop-color:#dfe2d8;stop-opacity:0;\"\n- offset=\"1\"\n- id=\"stop4517\" />\n- </linearGradient>\n- <inkscape:perspective\n- sodipodi:type=\"inkscape:persp3d\"\n- inkscape:vp_x=\"0 : 526.18109 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_z=\"744.09448 : 526.18109 : 1\"\n- inkscape:persp3d-origin=\"372.04724 : 350.78739 : 1\"\n- id=\"perspective3876\" />\n- <inkscape:perspective\n- id=\"perspective3886\"\n- inkscape:persp3d-origin=\"0.5 : 0.33333333 : 1\"\n- inkscape:vp_z=\"1 : 0.5 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_x=\"0 : 0.5 : 1\"\n- sodipodi:type=\"inkscape:persp3d\" />\n- <marker\n- inkscape:stockid=\"Arrow1Lend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Lend\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3211\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.8,0,0,-0.8,-10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker3892\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3894\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.8,0,0,-0.8,-10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker3896\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3898\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.8,0,0,-0.8,-10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Lstart\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3208\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(0.8,0,0,0.8,10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker3902\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3904\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.8,0,0,-0.8,-10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker3906\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3908\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(0.8,0,0,0.8,10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker3910\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3912\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.8,0,0,-0.8,-10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:perspective\n- id=\"perspective4086\"\n- inkscape:persp3d-origin=\"0.5 : 0.33333333 : 1\"\n- inkscape:vp_z=\"1 : 0.5 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_x=\"0 : 0.5 : 1\"\n- sodipodi:type=\"inkscape:persp3d\" />\n- <inkscape:perspective\n- id=\"perspective4113\"\n- inkscape:persp3d-origin=\"0.5 : 0.33333333 : 1\"\n- inkscape:vp_z=\"1 : 0.5 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_x=\"0 : 0.5 : 1\"\n- sodipodi:type=\"inkscape:persp3d\" />\n- <inkscape:perspective\n- id=\"perspective5195\"\n- inkscape:persp3d-origin=\"0.5 : 0.33333333 : 1\"\n- inkscape:vp_z=\"1 : 0.5 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_x=\"0 : 0.5 : 1\"\n- sodipodi:type=\"inkscape:persp3d\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-4\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-7\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:perspective\n- id=\"perspective5272\"\n- inkscape:persp3d-origin=\"0.5 : 0.33333333 : 1\"\n- inkscape:vp_z=\"1 : 0.5 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_x=\"0 : 0.5 : 1\"\n- sodipodi:type=\"inkscape:persp3d\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-4\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-5\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-0\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-3\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:perspective\n- id=\"perspective5317\"\n- inkscape:persp3d-origin=\"0.5 : 0.33333333 : 1\"\n- inkscape:vp_z=\"1 : 0.5 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_x=\"0 : 0.5 : 1\"\n- sodipodi:type=\"inkscape:persp3d\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-3\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-2\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-06\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-1\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-8\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-7\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-9\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-2\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect2858-0\"\n- is_visible=\"true\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-3\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-75\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3044-9\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-3-2\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-75-8\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3044-9-9\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3008-3\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3120-7\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3120-7-3\"\n- is_visible=\"true\" />\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient5474\"\n- id=\"linearGradient5695\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"matrix(0.62723639,0,0,1.0109144,206.76869,3.9208776)\"\n- x1=\"-89.501146\"\n- y1=\"363.57419\"\n- x2=\"-30.959395\"\n- y2=\"363.57419\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-34\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-3\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-45\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-16\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-7\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-58\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-1\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-6\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-7-6\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-58-4\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-1-9\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-6-3\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-7-2\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-58-46\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-1-1\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-6-4\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-7-2-6\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-58-46-8\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-1-1-9\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-6-4-9\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#grad0-40\"\n- id=\"linearGradient5917\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"matrix(8.8786147,-0.0235964,-0.00460261,1.50035,-400.25558,-2006.3745)\"\n- x1=\"-0.12893644\"\n- y1=\"1717.1688\"\n- x2=\"28.140806\"\n- y2=\"1717.1688\" />\n- <linearGradient\n- id=\"grad0-40\"\n- x1=\"0\"\n- y1=\"0\"\n- x2=\"1\"\n- y2=\"0\"\n- gradientTransform=\"rotate(60,0.5,0.5)\">\n- <stop\n- offset=\"0\"\n- stop-color=\"#f3f6fa\"\n- stop-opacity=\"1\"\n- id=\"stop3419\" />\n- <stop\n- offset=\"0.24\"\n- stop-color=\"#f9fafc\"\n- stop-opacity=\"1\"\n- id=\"stop3421\" />\n- <stop\n- offset=\"0.54\"\n- stop-color=\"#feffff\"\n- stop-opacity=\"1\"\n- id=\"stop3423\" />\n- </linearGradient>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-30\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-0\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-6\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-19\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-30-0\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-0-6\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-6-8\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-19-6\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-30-0-9\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-0-6-4\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-6-8-3\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-19-6-1\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient5474\"\n- id=\"linearGradient6997-7\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"matrix(0.62723639,0,0,1.0109144,321.82147,-1.8659026)\"\n- x1=\"-89.501144\"\n- y1=\"363.57419\"\n- x2=\"-30.959394\"\n- y2=\"363.57419\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-81\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-9\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-5\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-72\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-1\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-6\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker9714\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path9712\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-48\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-4\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker10117\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path10115\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-48-6\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-4-0\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker11186\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path11184\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-30-0-9-0\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-0-6-4-1\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-6-8-3-7\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-19-6-1-5\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3602\"\n- x1=\"113.62777\"\n- y1=\"238.35289\"\n- x2=\"178.07406\"\n- y2=\"238.35289\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"translate(4,-22)\" />\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3604\"\n- x1=\"106.04746\"\n- y1=\"231.17514\"\n- x2=\"170.49375\"\n- y2=\"231.17514\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"translate(4,-22)\" />\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3606\"\n- x1=\"97.456466\"\n- y1=\"223.48468\"\n- x2=\"161.90276\"\n- y2=\"223.48468\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"translate(4,-22)\" />\n- <linearGradient\n- gradientTransform=\"matrix(1.2309135,0,0,0.9993652,112.21043,-29.394096)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608-4\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <linearGradient\n- gradientTransform=\"matrix(1.2419105,0,0,0.99933655,110.714,51.863352)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608-4-8\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <linearGradient\n- gradientTransform=\"matrix(1.3078944,0,0,0.99916717,224.87462,63.380078)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608-4-8-7\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <linearGradient\n- gradientTransform=\"matrix(1.2309135,0,0,0.9993652,359.82239,-48.56566)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608-4-9\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <linearGradient\n- gradientTransform=\"translate(-35.122992,139.17627)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <linearGradient\n- gradientTransform=\"translate(32.977515,139.08289)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608-9\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <linearGradient\n- gradientTransform=\"translate(100.97751,139.08289)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608-9-1\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <linearGradient\n- gradientTransform=\"translate(168.97751,139.08289)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608-9-1-5\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <linearGradient\n- gradientTransform=\"translate(236.97751,139.08289)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608-9-1-5-7\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <linearGradient\n- gradientTransform=\"translate(516.30192,138.74331)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608-9-1-5-73\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <linearGradient\n- gradientTransform=\"translate(448.30192,138.74331)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608-9-1-59\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <linearGradient\n- gradientTransform=\"translate(380.30193,138.74331)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608-9-8\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <linearGradient\n- gradientTransform=\"translate(312.20142,138.83669)\"\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient3596\"\n- id=\"linearGradient3608-8\"\n- x1=\"88.739166\"\n- y1=\"215.40981\"\n- x2=\"153.18546\"\n- y2=\"215.40981\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <radialGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient4330\"\n- id=\"radialGradient4334\"\n- cx=\"222.02666\"\n- cy=\"354.61401\"\n- fx=\"222.02666\"\n- fy=\"354.61401\"\n- r=\"171.25233\"\n- gradientTransform=\"matrix(1,0,0,0.15767701,0,298.69953)\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <radialGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient4340\"\n- id=\"radialGradient4342\"\n- cx=\"535.05641\"\n- cy=\"353.56737\"\n- fx=\"535.05641\"\n- fy=\"353.56737\"\n- r=\"136.95767\"\n- gradientTransform=\"matrix(1.0000096,0,0,0.19866251,-0.00515595,284.82679)\"\n- gradientUnits=\"userSpaceOnUse\" />\n- <marker\n- inkscape:isstock=\"true\"\n- style=\"overflow:visible\"\n- id=\"marker28236\"\n- refX=\"0\"\n- refY=\"0\"\n- orient=\"auto\"\n- inkscape:stockid=\"Arrow2Mstart\">\n- <path\n- inkscape:connector-curvature=\"0\"\n- transform=\"scale(0.6)\"\n- d=\"M 8.7185878,4.0337352 -2.2072895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z\"\n- style=\"fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:0.625;stroke-linejoin:round;stroke-opacity:1\"\n- id=\"path28234\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker3706\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3704\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect14461\"\n- is_visible=\"true\" />\n- <marker\n- inkscape:stockid=\"Arrow2Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow2Mend-3\"\n- style=\"overflow:visible\"\n- inkscape:isstock=\"true\"\n- inkscape:collect=\"always\">\n- <path\n- inkscape:connector-curvature=\"0\"\n- id=\"path6230-9\"\n- style=\"fill:#fe0000;fill-opacity:1;fill-rule:evenodd;stroke:#fe0000;stroke-width:0.625;stroke-linejoin:round;stroke-opacity:1\"\n- d=\"M 8.7185878,4.0337352 -2.2072895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z\"\n- transform=\"scale(-0.6)\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow2Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow2Mend-3-1\"\n- style=\"overflow:visible\"\n- inkscape:isstock=\"true\"\n- inkscape:collect=\"always\">\n- <path\n- inkscape:connector-curvature=\"0\"\n- id=\"path6230-9-8\"\n- style=\"fill:#fe0000;fill-opacity:1;fill-rule:evenodd;stroke:#fe0000;stroke-width:0.625;stroke-linejoin:round;stroke-opacity:1\"\n- d=\"M 8.7185878,4.0337352 -2.2072895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z\"\n- transform=\"scale(-0.6)\" />\n- </marker>\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient13962\"\n- id=\"linearGradient14808\"\n- x1=\"447.95767\"\n- y1=\"176.3018\"\n- x2=\"576.27008\"\n- y2=\"176.3018\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"translate(0,-8)\" />\n- <marker\n- inkscape:stockid=\"Arrow2Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow2Mend-3-1-6\"\n- style=\"overflow:visible\"\n- inkscape:isstock=\"true\"\n- inkscape:collect=\"always\">\n- <path\n- inkscape:connector-curvature=\"0\"\n- id=\"path6230-9-8-5\"\n- style=\"fill:#808080;fill-opacity:1;fill-rule:evenodd;stroke:#808080;stroke-width:0.625;stroke-linejoin:round;stroke-opacity:1\"\n- d=\"M 8.7185878,4.0337352 -2.2072895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354408,5.6174519 -6e-7,8.035443 z\"\n- transform=\"scale(-0.6)\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-53\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-35\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-99\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-8\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- </defs>\n- <sodipodi:namedview\n- id=\"base\"\n- pagecolor=\"#ffffff\"\n- bordercolor=\"#666666\"\n- borderopacity=\"1.0\"\n- inkscape:pageopacity=\"0.0\"\n- inkscape:pageshadow=\"2\"\n- inkscape:zoom=\"1.8101934\"\n- inkscape:cx=\"434.42776\"\n- inkscape:cy=\"99.90063\"\n- inkscape:document-units=\"px\"\n- inkscape:current-layer=\"layer1\"\n- showgrid=\"false\"\n- inkscape:window-width=\"1920\"\n- inkscape:window-height=\"1057\"\n- inkscape:window-x=\"-8\"\n- inkscape:window-y=\"-8\"\n- inkscape:window-maximized=\"1\"\n- fit-margin-top=\"0.1\"\n- fit-margin-left=\"0.1\"\n- fit-margin-right=\"0.1\"\n- fit-margin-bottom=\"0.1\"\n- inkscape:measure-start=\"-29.078,219.858\"\n- inkscape:measure-end=\"346.809,219.858\"\n- showguides=\"true\"\n- inkscape:snap-page=\"true\"\n- inkscape:snap-others=\"false\"\n- inkscape:snap-nodes=\"false\"\n- inkscape:snap-bbox=\"true\"\n- inkscape:lockguides=\"false\"\n- inkscape:guide-bbox=\"true\">\n- <sodipodi:guide\n- position=\"-120.20815,574.17069\"\n- orientation=\"0,1\"\n- id=\"guide7077\"\n- inkscape:locked=\"false\" />\n- </sodipodi:namedview>\n- <metadata\n- id=\"metadata3873\">\n- <rdf:RDF>\n- <cc:Work\n- rdf:about=\"\">\n- <dc:format>image/svg+xml</dc:format>\n- <dc:type\n- rdf:resource=\"http://purl.org/dc/dcmitype/StillImage\" />\n- <dc:title />\n- </cc:Work>\n- </rdf:RDF>\n- </metadata>\n- <g\n- inkscape:label=\"Layer 1\"\n- inkscape:groupmode=\"layer\"\n- id=\"layer1\"\n- transform=\"translate(-46.542857,-100.33361)\">\n- <rect\n- style=\"fill:#aaffcc;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.26491222;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-7\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"575.72662\"\n- y=\"144.79553\" />\n- <rect\n- style=\"fill:#aaffcc;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.26491222;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-8-5\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"584.44391\"\n- y=\"152.87041\" />\n- <rect\n- style=\"fill:#aaffcc;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.26491222;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-42-0\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"593.03491\"\n- y=\"160.56087\" />\n- <rect\n- style=\"fill:#aaffcc;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.26491222;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-0-3\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"600.61523\"\n- y=\"167.73862\" />\n- <rect\n- style=\"fill:#aaffcc;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.26491222;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-46-4\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"608.70087\"\n- y=\"175.42906\" />\n- <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot1853-7\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#aaffcc;fill-opacity:1;stroke:none\"\n- transform=\"matrix(0.71467688,0,0,0.72506311,529.61388,101.41825)\"><flowRegion\n- id=\"flowRegion1855-0\"\n- style=\"fill:#aaffcc\"><rect\n- id=\"rect1857-5\"\n- width=\"67.17514\"\n- height=\"33.941124\"\n- x=\"120.20815\"\n- y=\"120.75856\"\n- style=\"fill:#aaffcc\" /></flowRegion><flowPara\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#aaffcc\"\n- id=\"flowPara1976\" /></flowRoot> <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot5313\"\n- style=\"fill:black;fill-opacity:1;stroke:none;font-family:sans-serif;font-style:normal;font-weight:normal;font-size:40px;line-height:1.25;letter-spacing:0px;word-spacing:0px\"><flowRegion\n- id=\"flowRegion5315\"><rect\n- id=\"rect5317\"\n- width=\"120.91525\"\n- height=\"96.873627\"\n- x=\"-192.33304\"\n- y=\"-87.130829\" /></flowRegion><flowPara\n- id=\"flowPara5319\" /></flowRoot> <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot8331\"\n- style=\"fill:black;fill-opacity:1;stroke:none;font-family:sans-serif;font-style:normal;font-weight:normal;font-size:13.33333333px;line-height:1.25;letter-spacing:0px;word-spacing:0px;-inkscape-font-specification:'sans-serif, Normal';font-stretch:normal;font-variant:normal;text-anchor:start;text-align:start;writing-mode:lr;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal\"><flowRegion\n- id=\"flowRegion8333\"><rect\n- id=\"rect8335\"\n- width=\"48.5\"\n- height=\"28\"\n- x=\"252.5\"\n- y=\"208.34286\" /></flowRegion><flowPara\n- id=\"flowPara8337\" /></flowRoot> <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot11473\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- transform=\"translate(46.542857,100.33361)\"><flowRegion\n- id=\"flowRegion11475\"><rect\n- id=\"rect11477\"\n- width=\"90\"\n- height=\"14.5\"\n- x=\"426\"\n- y=\"26.342873\" /></flowRegion><flowPara\n- id=\"flowPara11479\">DDDpk</flowPara></flowRoot> <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"533.54285\"\n- y=\"158.17648\"\n- id=\"text11489\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan11487\"\n- x=\"533.54285\"\n- y=\"170.34088\" /></text>\n- <rect\n- style=\"fill:#f4d7d7;fill-opacity:1;stroke:url(#linearGradient3606);stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-8\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"101.58897\"\n- y=\"178.70938\" />\n- <rect\n- style=\"fill:#f4d7d7;fill-opacity:1;stroke:url(#linearGradient3604);stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-42\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"110.17996\"\n- y=\"186.39984\" />\n- <rect\n- style=\"fill:#f4d7d7;fill-opacity:1;stroke:url(#linearGradient3602);stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-0\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"117.76027\"\n- y=\"193.57759\" />\n- <rect\n- style=\"fill:#f4d7d7;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-46\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"125.84592\"\n- y=\"201.26804\" />\n- <rect\n- style=\"fill:#d7f4e3;fill-opacity:1;stroke:url(#linearGradient3608-4);stroke-width:0.293915;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-86\"\n- width=\"79.001617\"\n- height=\"45.521675\"\n- x=\"221.60374\"\n- y=\"163.11812\" />\n- <rect\n- style=\"fill:#d7f4e3;fill-opacity:1;stroke:url(#linearGradient3608-4-8);stroke-width:0.29522076;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-86-5\"\n- width=\"79.70742\"\n- height=\"45.52037\"\n- x=\"221.08463\"\n- y=\"244.37004\" />\n- <rect\n- style=\"opacity:1;fill:#d7eef4;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.31139579;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718\"\n- width=\"125.8186\"\n- height=\"100.36277\"\n- x=\"321.87323\"\n- y=\"112.72702\" />\n- <rect\n- style=\"fill:#ffd5d5;fill-opacity:1;stroke:url(#linearGradient3608-4-8-7);stroke-width:0.30293623;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-86-5-3\"\n- width=\"83.942352\"\n- height=\"45.512653\"\n- x=\"341.10928\"\n- y=\"255.85414\" />\n- <rect\n- style=\"fill:#ffb380;fill-opacity:1;stroke:url(#linearGradient3608-4-9);stroke-width:0.293915;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-86-2\"\n- width=\"79.001617\"\n- height=\"45.521675\"\n- x=\"469.21576\"\n- y=\"143.94656\" />\n- <rect\n- style=\"opacity:1;fill:url(#radialGradient4334);fill-opacity:1;stroke:#6ba6fd;stroke-width:0.32037571;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3783\"\n- width=\"342.1843\"\n- height=\"53.684738\"\n- x=\"50.934502\"\n- y=\"327.77164\" />\n- <rect\n- style=\"fill:#e9ddaf;fill-opacity:1;stroke:url(#linearGradient3608);stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"53.748672\"\n- y=\"331.81079\" />\n- <rect\n- style=\"fill:#e9ddaf;fill-opacity:1;stroke:url(#linearGradient3608-9);stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-3\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"121.84918\"\n- y=\"331.71741\" />\n- <rect\n- style=\"fill:#e9ddaf;fill-opacity:1;stroke:url(#linearGradient3608-9-1);stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-3-6\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"189.84918\"\n- y=\"331.71741\" />\n- <rect\n- style=\"fill:#e9ddaf;fill-opacity:1;stroke:url(#linearGradient3608-9-1-5);stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-3-6-4\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"257.84918\"\n- y=\"331.71741\" />\n- <rect\n- style=\"fill:#e9ddaf;fill-opacity:1;stroke:url(#linearGradient3608-9-1-5-7);stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-3-6-4-9\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"325.84918\"\n- y=\"331.71741\" />\n- <rect\n- style=\"opacity:1;fill:url(#radialGradient4342);fill-opacity:1;stroke:#6ba6fd;stroke-width:0.28768006;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3783-8\"\n- width=\"273.62766\"\n- height=\"54.131645\"\n- x=\"398.24258\"\n- y=\"328.00156\" />\n- <rect\n- style=\"fill:#dde9af;fill-opacity:1;stroke:url(#linearGradient3608-8);stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-5\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"401.07309\"\n- y=\"331.47122\" />\n- <rect\n- style=\"fill:#dde9af;fill-opacity:1;stroke:url(#linearGradient3608-9-8);stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-3-0\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"469.17358\"\n- y=\"331.37781\" />\n- <rect\n- style=\"fill:#dde9af;fill-opacity:1;stroke:url(#linearGradient3608-9-1-59);stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-3-6-3\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"537.17358\"\n- y=\"331.37781\" />\n- <rect\n- style=\"fill:#dde9af;fill-opacity:1;stroke:url(#linearGradient3608-9-1-5-73);stroke-width:0.26499999;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-3-6-4-6\"\n- width=\"64.18129\"\n- height=\"45.550591\"\n- x=\"605.17358\"\n- y=\"331.37781\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"325.80197\"\n- y=\"117.21037\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"325.2959\"\n- y=\"140.20857\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"325.2959\"\n- y=\"164.20857\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-5\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"356.37054\"\n- y=\"117.39072\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-1\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"355.86447\"\n- y=\"140.38893\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-2\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"355.86447\"\n- y=\"164.38893\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-5-5\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"386.37054\"\n- y=\"117.39072\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-1-9\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"385.86447\"\n- y=\"140.38895\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-2-6\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"385.86447\"\n- y=\"164.38895\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-5-5-9\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"416.37054\"\n- y=\"117.39072\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-1-9-3\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"415.86447\"\n- y=\"140.38895\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-2-6-8\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"415.86447\"\n- y=\"164.38896\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-5\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"324.61139\"\n- y=\"187.85849\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-2-0\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"355.17996\"\n- y=\"188.03886\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-2-6-0\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"385.17996\"\n- y=\"188.03888\" />\n- <rect\n- style=\"opacity:1;fill:#ffeeaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-2-6-8-4\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"415.17996\"\n- y=\"188.03889\" />\n- <rect\n- style=\"opacity:1;fill:#d7eef4;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.31139579;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-5\"\n- width=\"125.8186\"\n- height=\"100.36277\"\n- x=\"452.24075\"\n- y=\"208.56764\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-9\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"456.16949\"\n- y=\"213.05098\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-8\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"455.66342\"\n- y=\"236.04919\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-55\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"455.66342\"\n- y=\"260.04919\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-5-7\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"486.73807\"\n- y=\"213.23134\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-1-5\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"486.23199\"\n- y=\"236.22954\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-2-3\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"486.23199\"\n- y=\"260.22955\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-5-5-2\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"516.73804\"\n- y=\"213.23134\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-1-9-5\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"516.23199\"\n- y=\"236.22955\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-2-6-1\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"516.23199\"\n- y=\"260.22955\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-5-5-9-6\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"546.73804\"\n- y=\"213.23134\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-1-9-3-1\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"546.23199\"\n- y=\"236.22955\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-2-6-8-7\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"546.23199\"\n- y=\"260.22955\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-5-1\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"454.97891\"\n- y=\"283.6991\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-2-0-6\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"485.54749\"\n- y=\"283.87946\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-2-6-0-7\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"515.54749\"\n- y=\"283.87949\" />\n- <rect\n- style=\"opacity:1;fill:#ffccaa;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.837071;stroke-linecap:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect3718-3-8-9-2-6-8-4-2\"\n- width=\"27.798103\"\n- height=\"21.434149\"\n- x=\"545.54749\"\n- y=\"283.87952\" />\n- <g\n- id=\"g5089\"\n- transform=\"matrix(0.7206312,0,0,1.0073979,12.37404,-312.02679)\"\n- style=\"fill:#ff8080\">\n- <path\n- inkscape:connector-curvature=\"0\"\n- d=\"m 64.439519,501.23542 v 5.43455 h 45.917801 v -5.43455 z\"\n- style=\"opacity:1;fill:#ff8080;fill-opacity:1;stroke:#6ba6fd;stroke-width:1.09656608;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;paint-order:fill markers stroke\"\n- id=\"rect4455\" />\n- <path\n- inkscape:connector-curvature=\"0\"\n- id=\"path5083\"\n- d=\"m 108.30535,494.82846 c 13.96414,8.6951 13.96414,8.40526 13.96414,8.40526 l -12.46798,9.85445 z\"\n- style=\"fill:#ff8080;stroke:#000000;stroke-width:0.53767502px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1\" />\n- </g>\n- <g\n- id=\"g5089-4\"\n- transform=\"matrix(-0.6745281,0,0,0.97266112,143.12774,-266.3349)\"\n- style=\"fill:#000080;fill-opacity:1\">\n- <path\n- inkscape:connector-curvature=\"0\"\n- d=\"m 64.439519,501.23542 v 5.43455 h 45.917801 v -5.43455 z\"\n- style=\"opacity:1;fill:#000080;fill-opacity:1;stroke:#6ba6fd;stroke-width:1.09656608;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;paint-order:fill markers stroke\"\n- id=\"rect4455-9\" />\n- <path\n- inkscape:connector-curvature=\"0\"\n- id=\"path5083-2\"\n- d=\"m 108.30535,494.82846 c 13.96414,8.6951 13.96414,8.40526 13.96414,8.40526 l -12.46798,9.85445 z\"\n- style=\"fill:#000080;stroke:#000000;stroke-width:0.53767502px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;fill-opacity:1\" />\n- </g>\n- <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot5112\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- transform=\"translate(52.199711,162.55901)\"><flowRegion\n- id=\"flowRegion5114\"><rect\n- id=\"rect5116\"\n- width=\"28.991377\"\n- height=\"19.79899\"\n- x=\"22.627417\"\n- y=\"64.897125\" /></flowRegion><flowPara\n- id=\"flowPara5118\">Tx</flowPara></flowRoot> <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot5112-8\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- transform=\"translate(49.878465,112.26812)\"><flowRegion\n- id=\"flowRegion5114-7\"><rect\n- id=\"rect5116-7\"\n- width=\"28.991377\"\n- height=\"19.79899\"\n- x=\"22.627417\"\n- y=\"64.897125\" /></flowRegion><flowPara\n- id=\"flowPara5118-5\">Rx</flowPara></flowRoot> <path\n- style=\"fill:none;stroke:#f60300;stroke-width:0.783;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:0.783, 0.78300000000000003;stroke-dashoffset:0;marker-start:url(#Arrow1Sstart);marker-end:url(#TriangleOutS)\"\n- d=\"m 116.81066,179.28348 v -11.31903 l -0.37893,-12.93605 0.37893,-5.25526 3.03134,-5.25526 4.16811,-2.82976 8.3362,-1.61701 h 7.19945 l 7.19946,2.02126 3.03135,2.02126 0.37892,2.02125 -0.37892,3.23401 -0.37892,7.27652 -0.37892,8.48927 -0.37892,14.55304\"\n- id=\"path8433\"\n- inkscape:connector-curvature=\"0\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"104.04285\"\n- y=\"144.86398\"\n- id=\"text9071\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan9069\"\n- x=\"104.04285\"\n- y=\"144.86398\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333333px;font-family:monospace;-inkscape-font-specification:monospace;fill:#0000ff\">HW loop back device</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"59.542858\"\n- y=\"53.676483\"\n- id=\"text9621\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan9619\"\n- x=\"59.542858\"\n- y=\"65.840889\" /></text>\n- <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot1853-7-2-7-8-7-2-4-3-9-0-2-9-5-6-7-7\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- transform=\"matrix(0.57822568,0,0,0.72506311,454.1297,247.6848)\"><flowRegion\n- id=\"flowRegion1855-0-1-3-66-99-9-2-5-4-1-1-1-4-0-5-4\"><rect\n- id=\"rect1857-5-1-5-2-6-1-4-9-3-8-1-8-5-7-9-1\"\n- width=\"162.09244\"\n- height=\"78.764809\"\n- x=\"120.20815\"\n- y=\"120.75856\" /></flowRegion><flowPara\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#5500d4\"\n- id=\"flowPara9723\" /></flowRoot> <path\n- style=\"fill:none;stroke:#fe0000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:1, 1;stroke-dashoffset:0;marker-end:url(#Arrow2Mend)\"\n- d=\"m 181.60025,194.22211 12.72792,-7.07106 14.14214,-2.82843 12.02081,0.70711 h 1.41422 v 0\"\n- id=\"path9797\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#fe0000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:1, 1;stroke-dashoffset:0;marker-end:url(#marker10821)\"\n- d=\"m 179.47893,193.51501 3.53554,-14.14214 5.65685,-12.72792 16.97056,-9.19239 8.48528,-9.19238 14.84924,-7.77818 24.04163,-8.48528 18.38478,-6.36396 38.89087,-2.82843 h 12.02082 l -2.12132,-0.7071\"\n- id=\"path10453\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#fe0000;stroke-width:0.70021206;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:0.70021208, 0.70021208;stroke-dashoffset:0;stroke-opacity:1;marker-end:url(#Arrow2Mend-3)\"\n- d=\"m 299.68795,188.0612 7.97521,-5.53298 8.86135,-2.2132 7.53214,0.5533 h 0.88614 v 0\"\n- id=\"path9797-9\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#fe0000;stroke-width:0.96708673;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:0.96708673, 0.96708673;stroke-dashoffset:0;stroke-opacity:1;marker-end:url(#Arrow2Mend-3-1)\"\n- d=\"m 300.49277,174.25976 7.49033,-11.23756 8.32259,-4.49504 7.07419,1.12376 h 0.83227 v 0\"\n- id=\"path9797-9-7\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#ff0000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:1, 1;stroke-dashoffset:0;marker-end:url(#marker12747)\"\n- d=\"m 299.68708,196.34344 9.19239,7.77817 7.07107,1.41421 h 4.94974 v 0\"\n- id=\"path12737\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:url(#linearGradient14808);stroke-width:4.66056013;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:4.66056002, 4.66056002;stroke-dashoffset:0;stroke-opacity:1;marker-end:url(#Arrow1Send)\"\n- d=\"m 447.95767,168.30181 c 119.99171,0 119.99171,0 119.99171,0\"\n- id=\"path13236\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#808080;stroke-width:0.96708673;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:0.96708673, 0.96708673000000001;stroke-dashoffset:0;stroke-opacity:1;marker-end:url(#Arrow2Mend-3-1-6)\"\n- d=\"m 529.56098,142.71226 7.49033,-11.23756 8.32259,-4.49504 7.07419,1.12376 h 0.83227 v 0\"\n- id=\"path9797-9-7-3\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#00ffff;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:1, 1;stroke-dashoffset:0;marker-end:url(#Arrow1Mend)\"\n- d=\"m 612.93538,222.50639 -5.65686,12.72792 -14.84924,3.53553 -14.14213,0.70711\"\n- id=\"path16128\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#00ffff;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#Arrow1Mend);stroke-miterlimit:4;stroke-dasharray:1, 1;stroke-dashoffset:0\"\n- d=\"m 624.95619,220.38507 -3.53553,13.43502 -12.72792,14.84925 -9.19239,5.65685 -19.09188,2.82843 -1.41422,-0.70711 h -1.41421\"\n- id=\"path16130\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#00ffff;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-end:url(#Arrow1Mend);stroke-miterlimit:4;stroke-dasharray:1, 1;stroke-dashoffset:0\"\n- d=\"m 635.56279,221.09217 -7.77817,33.94113 -4.24264,6.36396 -8.48528,3.53553 -10.6066,4.94975 -19.09189,5.65685 -6.36396,3.53554\"\n- id=\"path16132\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#00ffff;stroke-width:1.01083219;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:1.01083222, 1.01083221999999995;stroke-dashoffset:0;stroke-opacity:1;marker-end:url(#Arrow1Mend-53)\"\n- d=\"m 456.03282,270.85761 -4.96024,14.83162 -13.02062,4.11988 -12.40058,0.82399\"\n- id=\"path16128-3\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#00ffff;stroke-width:0.80101544;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:0.80101541, 0.80101540999999998;stroke-dashoffset:0;stroke-opacity:1;marker-end:url(#Arrow1Mend-99)\"\n- d=\"m 341.29831,266.70565 -6.88826,6.70663 -18.08168,1.86296 -17.22065,0.37258\"\n- id=\"path16128-6\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#00faf5;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:1, 1;stroke-dashoffset:0;marker-end:url(#Arrow1Mend)\"\n- d=\"m 219.78402,264.93279 -6.36396,-9.89949 -3.53554,-16.26346 -7.77817,-8.48528 -8.48528,-4.94975 -4.94975,-2.82842\"\n- id=\"path17144\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#00db00;stroke-width:1.4;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:1.4, 1.39999999999999991;stroke-dashoffset:0;marker-end:url(#marker17156);marker-start:url(#marker17550)\"\n- d=\"m 651.11914,221.09217 -7.07107,31.81981 -17.67766,34.64823 -21.21321,26.87005 -80.61017,1.41422 -86.97413,1.41421 -79.90306,-3.53553 -52.3259,1.41421 -24.04163,10.6066 -2.82843,1.41422\"\n- id=\"path17146\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#000000;stroke-width:1.3;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:1.3, 1.30000000000000004;stroke-dashoffset:0;marker-start:url(#marker18096);marker-end:url(#marker18508)\"\n- d=\"M 659.60442,221.09217 C 656.776,327.86529 656.776,328.5724 656.776,328.5724\"\n- id=\"path18086\"\n- inkscape:connector-curvature=\"0\" />\n- <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot1853-7-2-7-8-7-2\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- transform=\"matrix(0.57822568,0,0,0.72506311,137.7802,161.1139)\"><flowRegion\n- id=\"flowRegion1855-0-1-3-66-99-9\"><rect\n- id=\"rect1857-5-1-5-2-6-1\"\n- width=\"174.19844\"\n- height=\"91.867104\"\n- x=\"120.20815\"\n- y=\"120.75856\" /></flowRegion><flowPara\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#5500d4\"\n- id=\"flowPara9188-8-4\" /></flowRoot> <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"155.96185\"\n- y=\"220.07472\"\n- id=\"text9071-6\"><tspan\n- sodipodi:role=\"line\"\n- x=\"158.29518\"\n- y=\"220.07472\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\"\n- id=\"tspan2100\"> <tspan\n- style=\"fill:#0000ff\"\n- id=\"tspan2327\">Ethdev Ports </tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"155.96185\"\n- y=\"236.74139\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2104\">(NIX)</tspan></text>\n- <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot2106\"\n- style=\"fill:black;fill-opacity:1;stroke:none;font-family:sans-serif;font-style:normal;font-weight:normal;font-size:13.33333333px;line-height:1.25;letter-spacing:0px;word-spacing:0px;-inkscape-font-specification:'sans-serif, Normal';font-stretch:normal;font-variant:normal;text-anchor:start;text-align:start;writing-mode:lr;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal\"><flowRegion\n- id=\"flowRegion2108\"><rect\n- id=\"rect2110\"\n- width=\"42.1875\"\n- height=\"28.125\"\n- x=\"178.125\"\n- y=\"71.155365\" /></flowRegion><flowPara\n- id=\"flowPara2112\" /></flowRoot> <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot2114\"\n- style=\"fill:black;fill-opacity:1;stroke:none;font-family:sans-serif;font-style:normal;font-weight:normal;font-size:13.33333333px;line-height:1.25;letter-spacing:0px;word-spacing:0px;-inkscape-font-specification:'sans-serif, Normal';font-stretch:normal;font-variant:normal;text-anchor:start;text-align:start;writing-mode:lr;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal\"><flowRegion\n- id=\"flowRegion2116\"><rect\n- id=\"rect2118\"\n- width=\"38.28125\"\n- height=\"28.90625\"\n- x=\"196.09375\"\n- y=\"74.280365\" /></flowRegion><flowPara\n- id=\"flowPara2120\" /></flowRoot> <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot2122\"\n- style=\"fill:black;fill-opacity:1;stroke:none;font-family:sans-serif;font-style:normal;font-weight:normal;font-size:13.33333333px;line-height:1.25;letter-spacing:0px;word-spacing:0px;-inkscape-font-specification:'sans-serif, Normal';font-stretch:normal;font-variant:normal;text-anchor:start;text-align:start;writing-mode:lr;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal\"><flowRegion\n- id=\"flowRegion2124\"><rect\n- id=\"rect2126\"\n- width=\"39.0625\"\n- height=\"23.4375\"\n- x=\"186.71875\"\n- y=\"153.96786\" /></flowRegion><flowPara\n- id=\"flowPara2128\" /></flowRoot> <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"262.1366\"\n- y=\"172.08614\"\n- id=\"text9071-6-4\"><tspan\n- sodipodi:role=\"line\"\n- x=\"264.46994\"\n- y=\"172.08614\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2104-0\">Ingress </tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"262.1366\"\n- y=\"188.75281\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2176\">Classification</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"262.1366\"\n- y=\"205.41946\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2180\">(NPC)</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"262.1366\"\n- y=\"222.08614\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2178\" /><tspan\n- sodipodi:role=\"line\"\n- x=\"262.1366\"\n- y=\"238.75281\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2174\" /></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"261.26727\"\n- y=\"254.46307\"\n- id=\"text9071-6-4-9\"><tspan\n- sodipodi:role=\"line\"\n- x=\"263.60062\"\n- y=\"254.46307\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2104-0-0\">Egress </tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"261.26727\"\n- y=\"271.12973\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2176-8\">Classification</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"261.26727\"\n- y=\"287.79642\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2180-9\">(NPC)</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"261.26727\"\n- y=\"304.46307\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2178-3\" /><tspan\n- sodipodi:role=\"line\"\n- x=\"261.26727\"\n- y=\"321.12973\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\"\n- id=\"tspan2174-7\" /></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"362.7016\"\n- y=\"111.81297\"\n- id=\"text9071-4\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan9069-8\"\n- x=\"362.7016\"\n- y=\"111.81297\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;fill:#0000ff\">Rx Queues</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"488.21777\"\n- y=\"207.21898\"\n- id=\"text9071-4-3\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan9069-8-8\"\n- x=\"488.21777\"\n- y=\"207.21898\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;fill:#0000ff\">Tx Queues</tspan></text>\n- <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot2311\"\n- style=\"fill:black;fill-opacity:1;stroke:none;font-family:sans-serif;font-style:normal;font-weight:normal;font-size:13.33333333px;line-height:1.25;letter-spacing:0px;word-spacing:0px;-inkscape-font-specification:'sans-serif, Normal';font-stretch:normal;font-variant:normal;text-anchor:start;text-align:start;writing-mode:lr;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal\"><flowRegion\n- id=\"flowRegion2313\"><rect\n- id=\"rect2315\"\n- width=\"49.21875\"\n- height=\"41.40625\"\n- x=\"195.3125\"\n- y=\"68.811615\" /></flowRegion><flowPara\n- id=\"flowPara2317\" /></flowRoot> <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot2319\"\n- style=\"fill:black;fill-opacity:1;stroke:none;font-family:sans-serif;font-style:normal;font-weight:normal;font-size:13.33333333px;line-height:1.25;letter-spacing:0px;word-spacing:0px;-inkscape-font-specification:'sans-serif, Normal';font-stretch:normal;font-variant:normal;text-anchor:start;text-align:start;writing-mode:lr;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal\"><flowRegion\n- id=\"flowRegion2321\"><rect\n- id=\"rect2323\"\n- width=\"40.625\"\n- height=\"39.0625\"\n- x=\"196.09375\"\n- y=\"69.592865\" /></flowRegion><flowPara\n- id=\"flowPara2325\" /></flowRoot> <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"382.20477\"\n- y=\"263.74432\"\n- id=\"text9071-6-4-6\"><tspan\n- sodipodi:role=\"line\"\n- x=\"382.20477\"\n- y=\"263.74432\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2104-0-9\">Egress</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"382.20477\"\n- y=\"280.41098\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2176-3\">Traffic Manager</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"382.20477\"\n- y=\"297.07767\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2180-1\">(NIX)</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"382.20477\"\n- y=\"313.74432\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2178-6\" /><tspan\n- sodipodi:role=\"line\"\n- x=\"382.20477\"\n- y=\"330.41098\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2174-8\" /></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"500.98602\"\n- y=\"154.02556\"\n- id=\"text9071-6-4-0\"><tspan\n- sodipodi:role=\"line\"\n- x=\"503.31937\"\n- y=\"154.02556\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2104-0-97\">Scheduler </tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"500.98602\"\n- y=\"170.69223\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2389\" /><tspan\n- sodipodi:role=\"line\"\n- x=\"500.98602\"\n- y=\"187.35889\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2391\">SSO</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"500.98602\"\n- y=\"204.02556\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2178-60\" /><tspan\n- sodipodi:role=\"line\"\n- x=\"500.98602\"\n- y=\"220.69223\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2174-3\" /></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"571.61627\"\n- y=\"119.24016\"\n- id=\"text9071-4-2\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan9069-8-82\"\n- x=\"571.61627\"\n- y=\"119.24016\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:8px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\">Supports both poll mode and/or event mode</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"571.61627\"\n- y=\"135.90683\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:8px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2416\">by configuring scheduler</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"571.61627\"\n- y=\"152.57349\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2418\" /></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:center;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"638.14227\"\n- y=\"192.46773\"\n- id=\"text9071-6-4-9-2\"><tspan\n- sodipodi:role=\"line\"\n- x=\"638.14227\"\n- y=\"192.46773\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2178-3-2\">ARMv8</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"638.14227\"\n- y=\"209.1344\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2499\">Cores</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"638.14227\"\n- y=\"225.80106\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\"\n- id=\"tspan2174-7-8\" /></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"180.24902\"\n- y=\"325.09399\"\n- id=\"text9071-4-1\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan9069-8-7\"\n- x=\"180.24902\"\n- y=\"325.09399\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;fill:#0000ff\">Hardware Libraries</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"487.8916\"\n- y=\"325.91599\"\n- id=\"text9071-4-1-1\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan9069-8-7-1\"\n- x=\"487.8916\"\n- y=\"325.91599\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;fill:#0000ff\">Software Libraries</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"81.178604\"\n- y=\"350.03149\"\n- id=\"text9071-4-18\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan9069-8-83\"\n- x=\"81.178604\"\n- y=\"350.03149\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\">Mempool</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"81.178604\"\n- y=\"366.69815\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2555\">(NPA)</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"151.09518\"\n- y=\"348.77365\"\n- id=\"text9071-4-18-9\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan9069-8-83-3\"\n- x=\"151.09518\"\n- y=\"348.77365\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\">Timer</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"151.09518\"\n- y=\"365.44031\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2555-9\">(TIM)</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"222.56393\"\n- y=\"347.1174\"\n- id=\"text9071-4-18-0\"><tspan\n- sodipodi:role=\"line\"\n- x=\"222.56393\"\n- y=\"347.1174\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2555-90\">Crypto</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"222.56393\"\n- y=\"363.78406\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2601\">(CPT)</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"289.00229\"\n- y=\"347.69473\"\n- id=\"text9071-4-18-0-5\"><tspan\n- sodipodi:role=\"line\"\n- x=\"289.00229\"\n- y=\"347.69473\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2555-90-9\">Compress</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"289.00229\"\n- y=\"364.36139\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2601-6\">(ZIP)</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"355.50653\"\n- y=\"348.60098\"\n- id=\"text9071-4-18-0-5-6\"><tspan\n- sodipodi:role=\"line\"\n- x=\"355.50653\"\n- y=\"348.60098\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2555-90-9-5\">Shared</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"355.50653\"\n- y=\"365.26764\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2645\">Memory</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"355.50653\"\n- y=\"381.93433\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2601-6-1\" /></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"430.31393\"\n- y=\"356.4924\"\n- id=\"text9071-4-18-1\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan9069-8-83-35\"\n- x=\"430.31393\"\n- y=\"356.4924\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\">SW Ring</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"430.31393\"\n- y=\"373.15906\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2555-6\" /></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"569.37646\"\n- y=\"341.1799\"\n- id=\"text9071-4-18-2\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan9069-8-83-4\"\n- x=\"569.37646\"\n- y=\"341.1799\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\">HASH</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"569.37646\"\n- y=\"357.84656\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2742\">LPM</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"569.37646\"\n- y=\"374.51324\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2555-2\">ACL</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"503.75143\"\n- y=\"355.02365\"\n- id=\"text9071-4-18-2-3\"><tspan\n- sodipodi:role=\"line\"\n- x=\"503.75143\"\n- y=\"355.02365\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2733\">Mbuf</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"639.34521\"\n- y=\"355.6174\"\n- id=\"text9071-4-18-19\"><tspan\n- sodipodi:role=\"line\"\n- x=\"639.34521\"\n- y=\"355.6174\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#0000ff\"\n- id=\"tspan2771\">De(Frag)</tspan></text>\n- </g>\n-</svg>\ndiff --git a/doc/guides/platform/img/octeontx2_resource_virtualization.svg b/doc/guides/platform/img/octeontx2_resource_virtualization.svg\ndeleted file mode 100644\nindex bf976b52af..0000000000\n--- a/doc/guides/platform/img/octeontx2_resource_virtualization.svg\n+++ /dev/null\n@@ -1,2418 +0,0 @@\n-<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\"?>\n-<!-- Created with Inkscape (http://www.inkscape.org/) -->\n-\n-<!--\n-# SPDX-License-Identifier: BSD-3-Clause\n-# Copyright(c) 2019 Marvell International Ltd.\n-#\n--->\n-\n-<svg\n- xmlns:osb=\"http://www.openswatchbook.org/uri/2009/osb\"\n- xmlns:dc=\"http://purl.org/dc/elements/1.1/\"\n- xmlns:cc=\"http://creativecommons.org/ns#\"\n- xmlns:rdf=\"http://www.w3.org/1999/02/22-rdf-syntax-ns#\"\n- xmlns:svg=\"http://www.w3.org/2000/svg\"\n- xmlns=\"http://www.w3.org/2000/svg\"\n- xmlns:xlink=\"http://www.w3.org/1999/xlink\"\n- xmlns:sodipodi=\"http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd\"\n- xmlns:inkscape=\"http://www.inkscape.org/namespaces/inkscape\"\n- width=\"631.91431\"\n- height=\"288.34286\"\n- id=\"svg3868\"\n- version=\"1.1\"\n- inkscape:version=\"0.92.4 (5da689c313, 2019-01-14)\"\n- sodipodi:docname=\"octeontx2_resource_virtualization.svg\"\n- sodipodi:version=\"0.32\"\n- inkscape:output_extension=\"org.inkscape.output.svg.inkscape\">\n- <defs\n- id=\"defs3870\">\n- <marker\n- inkscape:stockid=\"Arrow1Lstart\"\n- orient=\"auto\"\n- refY=\"0.0\"\n- refX=\"0.0\"\n- id=\"marker9460\"\n- style=\"overflow:visible\"\n- inkscape:isstock=\"true\">\n- <path\n- id=\"path9458\"\n- d=\"M 0.0,0.0 L 5.0,-5.0 L -12.5,0.0 L 5.0,5.0 L 0.0,0.0 z \"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1;fill:#000000;fill-opacity:1\"\n- transform=\"scale(0.8) translate(12.5,0)\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lstart\"\n- orient=\"auto\"\n- refY=\"0.0\"\n- refX=\"0.0\"\n- id=\"marker7396\"\n- style=\"overflow:visible\"\n- inkscape:isstock=\"true\">\n- <path\n- id=\"path7133\"\n- d=\"M 0.0,0.0 L 5.0,-5.0 L -12.5,0.0 L 5.0,5.0 L 0.0,0.0 z \"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1;fill:#000000;fill-opacity:1\"\n- transform=\"scale(0.8) translate(12.5,0)\" />\n- </marker>\n- <linearGradient\n- inkscape:collect=\"always\"\n- id=\"linearGradient5474\">\n- <stop\n- style=\"stop-color:#ffffff;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop5470\" />\n- <stop\n- style=\"stop-color:#ffffff;stop-opacity:0;\"\n- offset=\"1\"\n- id=\"stop5472\" />\n- </linearGradient>\n- <linearGradient\n- inkscape:collect=\"always\"\n- id=\"linearGradient5464\">\n- <stop\n- style=\"stop-color:#daeef5;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop5460\" />\n- <stop\n- style=\"stop-color:#daeef5;stop-opacity:0;\"\n- offset=\"1\"\n- id=\"stop5462\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient6545\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#ffa600;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop6543\" />\n- </linearGradient>\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3302\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3294\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3290\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3286\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3228\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3188\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3184\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3180\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3176\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3172\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3168\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3164\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3160\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3120\"\n- is_visible=\"true\" />\n- <linearGradient\n- id=\"linearGradient3114\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#00f900;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3112\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient3088\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#00f900;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3086\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient3058\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#00f900;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3056\" />\n- </linearGradient>\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3054\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3050\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3046\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3042\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3038\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3034\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3030\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3008\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3004\"\n- is_visible=\"true\" />\n- <linearGradient\n- id=\"linearGradient2975\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#ff2200;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop2973\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient2969\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#69ff72;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop2967\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient2963\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#000000;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop2961\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient2929\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#ff2d00;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop2927\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient4610\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#00ffff;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop4608\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient3993\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#6ba6fd;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3991\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient3808\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#6ba6fd;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3806\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient3776\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#fc0000;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3774\" />\n- </linearGradient>\n- <linearGradient\n- id=\"linearGradient3438\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#b8e132;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop3436\" />\n- </linearGradient>\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3408\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3404\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3400\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3392\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3376\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3044\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3040\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3036\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3032\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3028\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3024\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3020\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect2858\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect2854\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect2844\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <linearGradient\n- id=\"linearGradient2828\"\n- osb:paint=\"solid\">\n- <stop\n- style=\"stop-color:#ff0000;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop2826\" />\n- </linearGradient>\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect329\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <linearGradient\n- id=\"linearGradient4513\">\n- <stop\n- style=\"stop-color:#fdffdb;stop-opacity:1;\"\n- offset=\"0\"\n- id=\"stop4515\" />\n- <stop\n- style=\"stop-color:#dfe2d8;stop-opacity:0;\"\n- offset=\"1\"\n- id=\"stop4517\" />\n- </linearGradient>\n- <inkscape:perspective\n- sodipodi:type=\"inkscape:persp3d\"\n- inkscape:vp_x=\"0 : 526.18109 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_z=\"744.09448 : 526.18109 : 1\"\n- inkscape:persp3d-origin=\"372.04724 : 350.78739 : 1\"\n- id=\"perspective3876\" />\n- <inkscape:perspective\n- id=\"perspective3886\"\n- inkscape:persp3d-origin=\"0.5 : 0.33333333 : 1\"\n- inkscape:vp_z=\"1 : 0.5 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_x=\"0 : 0.5 : 1\"\n- sodipodi:type=\"inkscape:persp3d\" />\n- <marker\n- inkscape:stockid=\"Arrow1Lend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Lend\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3211\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.8,0,0,-0.8,-10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker3892\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3894\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.8,0,0,-0.8,-10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker3896\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3898\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.8,0,0,-0.8,-10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Lstart\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3208\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(0.8,0,0,0.8,10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker3902\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3904\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.8,0,0,-0.8,-10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker3906\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3908\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(0.8,0,0,0.8,10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Lend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker3910\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path3912\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.8,0,0,-0.8,-10,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:perspective\n- id=\"perspective4086\"\n- inkscape:persp3d-origin=\"0.5 : 0.33333333 : 1\"\n- inkscape:vp_z=\"1 : 0.5 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_x=\"0 : 0.5 : 1\"\n- sodipodi:type=\"inkscape:persp3d\" />\n- <inkscape:perspective\n- id=\"perspective4113\"\n- inkscape:persp3d-origin=\"0.5 : 0.33333333 : 1\"\n- inkscape:vp_z=\"1 : 0.5 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_x=\"0 : 0.5 : 1\"\n- sodipodi:type=\"inkscape:persp3d\" />\n- <inkscape:perspective\n- id=\"perspective5195\"\n- inkscape:persp3d-origin=\"0.5 : 0.33333333 : 1\"\n- inkscape:vp_z=\"1 : 0.5 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_x=\"0 : 0.5 : 1\"\n- sodipodi:type=\"inkscape:persp3d\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-4\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-7\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:perspective\n- id=\"perspective5272\"\n- inkscape:persp3d-origin=\"0.5 : 0.33333333 : 1\"\n- inkscape:vp_z=\"1 : 0.5 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_x=\"0 : 0.5 : 1\"\n- sodipodi:type=\"inkscape:persp3d\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-4\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-5\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-0\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-3\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:perspective\n- id=\"perspective5317\"\n- inkscape:persp3d-origin=\"0.5 : 0.33333333 : 1\"\n- inkscape:vp_z=\"1 : 0.5 : 1\"\n- inkscape:vp_y=\"0 : 1000 : 0\"\n- inkscape:vp_x=\"0 : 0.5 : 1\"\n- sodipodi:type=\"inkscape:persp3d\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-3\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-2\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-06\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-1\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 0,0 z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-8\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-7\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-9\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-2\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect2858-0\"\n- is_visible=\"true\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-3\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-75\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3044-9\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-3-2\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-75-8\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <inkscape:path-effect\n- effect=\"bspline\"\n- id=\"path-effect3044-9-9\"\n- is_visible=\"true\"\n- weight=\"33.333333\"\n- steps=\"2\"\n- helper_size=\"0\"\n- apply_no_weight=\"true\"\n- apply_with_weight=\"true\"\n- only_selected=\"false\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3008-3\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3120-7\"\n- is_visible=\"true\" />\n- <inkscape:path-effect\n- effect=\"spiro\"\n- id=\"path-effect3120-7-3\"\n- is_visible=\"true\" />\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient5464\"\n- id=\"linearGradient5466\"\n- x1=\"65.724048\"\n- y1=\"169.38839\"\n- x2=\"183.38978\"\n- y2=\"169.38839\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"translate(-14,-4)\" />\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient5474\"\n- id=\"linearGradient5476\"\n- x1=\"-89.501146\"\n- y1=\"363.57419\"\n- x2=\"-30.959395\"\n- y2=\"363.57419\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"matrix(0.62723639,0,0,1.0109144,105.65926,-0.6580533)\" />\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient5474\"\n- id=\"linearGradient5658\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"matrix(0.62723639,0,0,1.0109144,148.76869,-0.0791224)\"\n- x1=\"-89.501146\"\n- y1=\"363.57419\"\n- x2=\"-30.959395\"\n- y2=\"363.57419\" />\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient5474\"\n- id=\"linearGradient5695\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"matrix(0.62723639,0,0,1.0109144,206.76869,3.9208776)\"\n- x1=\"-89.501146\"\n- y1=\"363.57419\"\n- x2=\"-30.959395\"\n- y2=\"363.57419\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-34\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-3\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-45\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-16\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-7\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-58\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-1\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-6\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-7-6\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-58-4\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-1-9\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-6-3\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-7-2\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-58-46\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-1-1\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-6-4\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-7-2-6\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-58-46-8\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-1-1-9\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-6-4-9\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient5474\"\n- id=\"linearGradient6997\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"matrix(0.62723639,0,0,1.0109144,192.76869,-0.0791224)\"\n- x1=\"-89.501146\"\n- y1=\"363.57419\"\n- x2=\"-30.959395\"\n- y2=\"363.57419\" />\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#grad0-40\"\n- id=\"linearGradient5917\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"matrix(8.8786147,-0.0235964,-0.00460261,1.50035,-400.25558,-2006.3745)\"\n- x1=\"-0.12893644\"\n- y1=\"1717.1688\"\n- x2=\"28.140806\"\n- y2=\"1717.1688\" />\n- <linearGradient\n- id=\"grad0-40\"\n- x1=\"0\"\n- y1=\"0\"\n- x2=\"1\"\n- y2=\"0\"\n- gradientTransform=\"rotate(60,0.5,0.5)\">\n- <stop\n- offset=\"0\"\n- stop-color=\"#f3f6fa\"\n- stop-opacity=\"1\"\n- id=\"stop3419\" />\n- <stop\n- offset=\"0.24\"\n- stop-color=\"#f9fafc\"\n- stop-opacity=\"1\"\n- id=\"stop3421\" />\n- <stop\n- offset=\"0.54\"\n- stop-color=\"#feffff\"\n- stop-opacity=\"1\"\n- id=\"stop3423\" />\n- </linearGradient>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-30\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-0\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-6\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-19\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-30-0\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-0-6\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-6-8\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-19-6\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-30-0-9\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-0-6-4\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-6-8-3\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-19-6-1\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient5474\"\n- id=\"linearGradient6997-7\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"matrix(0.62723639,0,0,1.0109144,321.82147,-1.8659026)\"\n- x1=\"-89.501144\"\n- y1=\"363.57419\"\n- x2=\"-30.959394\"\n- y2=\"363.57419\" />\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient5474\"\n- id=\"linearGradient6997-8\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"matrix(1.3985479,0,0,0.98036646,376.02779,12.240541)\"\n- x1=\"-89.501144\"\n- y1=\"363.57419\"\n- x2=\"-30.959394\"\n- y2=\"363.57419\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-81\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-9\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-5\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-72\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-1\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-6\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker9714\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path9712\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-48\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-4\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker10117\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path10115\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-48-6\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-4-0\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"marker11186\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path11184\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <linearGradient\n- inkscape:collect=\"always\"\n- xlink:href=\"#linearGradient5474\"\n- id=\"linearGradient6997-8-0\"\n- gradientUnits=\"userSpaceOnUse\"\n- gradientTransform=\"matrix(1.3985479,0,0,0.98036646,497.77779,12.751681)\"\n- x1=\"-89.501144\"\n- y1=\"363.57419\"\n- x2=\"-30.959394\"\n- y2=\"363.57419\" />\n- <marker\n- inkscape:stockid=\"Arrow1Mstart\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mstart-30-0-9-0\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4530-0-6-4-1\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(0.4,0,0,0.4,4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- <marker\n- inkscape:stockid=\"Arrow1Mend\"\n- orient=\"auto\"\n- refY=\"0\"\n- refX=\"0\"\n- id=\"Arrow1Mend-6-8-3-7\"\n- style=\"overflow:visible\">\n- <path\n- id=\"path4533-19-6-1-5\"\n- d=\"M 0,0 5,-5 -12.5,0 5,5 Z\"\n- style=\"fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;marker-start:none\"\n- transform=\"matrix(-0.4,0,0,-0.4,-4,0)\"\n- inkscape:connector-curvature=\"0\" />\n- </marker>\n- </defs>\n- <sodipodi:namedview\n- id=\"base\"\n- pagecolor=\"#ffffff\"\n- bordercolor=\"#666666\"\n- borderopacity=\"1.0\"\n- inkscape:pageopacity=\"0.0\"\n- inkscape:pageshadow=\"2\"\n- inkscape:zoom=\"1.4142136\"\n- inkscape:cx=\"371.09569\"\n- inkscape:cy=\"130.22425\"\n- inkscape:document-units=\"px\"\n- inkscape:current-layer=\"layer1\"\n- showgrid=\"false\"\n- inkscape:window-width=\"1920\"\n- inkscape:window-height=\"1057\"\n- inkscape:window-x=\"-8\"\n- inkscape:window-y=\"-8\"\n- inkscape:window-maximized=\"1\"\n- fit-margin-top=\"0.1\"\n- fit-margin-left=\"0.1\"\n- fit-margin-right=\"0.1\"\n- fit-margin-bottom=\"0.1\"\n- inkscape:measure-start=\"-29.078,219.858\"\n- inkscape:measure-end=\"346.809,219.858\"\n- showguides=\"true\"\n- inkscape:snap-page=\"true\"\n- inkscape:snap-others=\"false\"\n- inkscape:snap-nodes=\"false\"\n- inkscape:snap-bbox=\"true\"\n- inkscape:lockguides=\"false\"\n- inkscape:guide-bbox=\"true\">\n- <sodipodi:guide\n- position=\"-120.20815,574.17069\"\n- orientation=\"0,1\"\n- id=\"guide7077\"\n- inkscape:locked=\"false\" />\n- </sodipodi:namedview>\n- <metadata\n- id=\"metadata3873\">\n- <rdf:RDF>\n- <cc:Work\n- rdf:about=\"\">\n- <dc:format>image/svg+xml</dc:format>\n- <dc:type\n- rdf:resource=\"http://purl.org/dc/dcmitype/StillImage\" />\n- <dc:title />\n- </cc:Work>\n- </rdf:RDF>\n- </metadata>\n- <g\n- inkscape:label=\"Layer 1\"\n- inkscape:groupmode=\"layer\"\n- id=\"layer1\"\n- transform=\"translate(-46.542857,-100.33361)\">\n- <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot5313\"\n- style=\"fill:black;fill-opacity:1;stroke:none;font-family:sans-serif;font-style:normal;font-weight:normal;font-size:40px;line-height:1.25;letter-spacing:0px;word-spacing:0px\"><flowRegion\n- id=\"flowRegion5315\"><rect\n- id=\"rect5317\"\n- width=\"120.91525\"\n- height=\"96.873627\"\n- x=\"-192.33304\"\n- y=\"-87.130829\" /></flowRegion><flowPara\n- id=\"flowPara5319\" /></flowRoot> <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"90.320152\"\n- y=\"299.67871\"\n- id=\"text2978\"\n- inkscape:export-filename=\"/home/matz/barracuda/rapports/mbuf-api-v2-images/octeon_multi.png\"\n- inkscape:export-xdpi=\"112\"\n- inkscape:export-ydpi=\"112\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"90.320152\"\n- y=\"299.67871\"\n- id=\"tspan3006\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:15.74255753px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\"> </tspan></text>\n- <rect\n- style=\"fill:#d6eaf8;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.82973665;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066\"\n- width=\"127.44949\"\n- height=\"225.03024\"\n- x=\"47.185646\"\n- y=\"111.20448\" />\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.55883217;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5096\"\n- width=\"117.1069\"\n- height=\"20.907221\"\n- x=\"52.003464\"\n- y=\"154.93478\" />\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b78fd;stroke-width:0.55900002;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5096-6\"\n- width=\"117.1069\"\n- height=\"20.907221\"\n- x=\"51.955002\"\n- y=\"181.51834\" />\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b7dfd;stroke-width:0.55883217;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5096-6-2\"\n- width=\"117.1069\"\n- height=\"20.907221\"\n- x=\"51.691605\"\n- y=\"205.82234\" />\n- <rect\n- y=\"154.93478\"\n- x=\"52.003464\"\n- height=\"20.907221\"\n- width=\"117.1069\"\n- id=\"rect5160\"\n- style=\"fill:url(#linearGradient5466);fill-opacity:1;stroke:#6b8afd;stroke-width:0.55883217;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\" />\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b78fd;stroke-width:0.55883217;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5162\"\n- width=\"117.1069\"\n- height=\"20.907221\"\n- x=\"52.003464\"\n- y=\"231.92767\" />\n- <rect\n- y=\"255.45328\"\n- x=\"52.003464\"\n- height=\"20.907221\"\n- width=\"117.1069\"\n- id=\"rect5164\"\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b6ffd;stroke-width:0.55883217;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\" />\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.55883217;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166\"\n- width=\"117.1069\"\n- height=\"20.907221\"\n- x=\"52.003464\"\n- y=\"281.11758\" />\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b78fd;stroke-width:0.59729731;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-6\"\n- width=\"117.0697\"\n- height=\"23.892008\"\n- x=\"52.659744\"\n- y=\"306.01089\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:'Bitstream Vera Sans';-inkscape-font-specification:'Bitstream Vera Sans';fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"96.955597\"\n- y=\"163.55217\"\n- id=\"text5219-26-1\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"96.955597\"\n- y=\"163.55217\"\n- id=\"tspan5223-10-9\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.33980179px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\">NIX AF</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"96.098343\"\n- y=\"187.18845\"\n- id=\"text5219-26-1-1\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"96.098343\"\n- y=\"187.18845\"\n- id=\"tspan5223-10-9-4\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.33980179px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\">NPA AF</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"96.829468\"\n- y=\"211.79611\"\n- id=\"text5219-26-1-5\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"96.829468\"\n- y=\"211.79611\"\n- id=\"tspan5223-10-9-1\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.33980179px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\">SSO AF</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"94.770523\"\n- y=\"235.66898\"\n- id=\"text5219-26-1-5-7-6\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"94.770523\"\n- y=\"235.66898\"\n- id=\"tspan5223-10-9-1-6-8\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.33980179px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\">NPC AF</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"94.895973\"\n- y=\"259.25156\"\n- id=\"text5219-26-1-5-7-6-3\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"94.895973\"\n- y=\"259.25156\"\n- id=\"tspan5223-10-9-1-6-8-3\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.33980179px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\">CPT AF</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"94.645073\"\n- y=\"282.35391\"\n- id=\"text5219-26-1-5-7-6-3-0\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"94.645073\"\n- y=\"282.35391\"\n- id=\"tspan5223-10-9-1-6-8-3-1\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.33980179px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\">RVU AF</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.93084431px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.07757032\"\n- x=\"110.2803\"\n- y=\"126.02858\"\n- id=\"text5219-26\"\n- transform=\"scale(1.0076913,0.9923674)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"110.2803\"\n- y=\"126.02858\"\n- id=\"tspan5223-10\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.77570343px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;stroke-width:1.07757032\">Linux AF driver</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"110.2803\"\n- y=\"139.49821\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.77570343px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;stroke-width:1.07757032\"\n- id=\"tspan5325\">(octeontx2_af)</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"110.2803\"\n- y=\"152.96783\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.77570343px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#ff0000;stroke-width:1.07757032\"\n- id=\"tspan5327\">PF0</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"110.2803\"\n- y=\"160.38988\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.77570343px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;stroke-width:1.07757032\"\n- id=\"tspan5329\" /></text>\n- <rect\n- style=\"fill:url(#linearGradient5476);fill-opacity:1;stroke:#695400;stroke-width:1.16700006;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5468\"\n- width=\"36.554455\"\n- height=\"18.169683\"\n- x=\"49.603416\"\n- y=\"357.7995\" />\n- <g\n- id=\"g5594\"\n- transform=\"translate(-18,-40)\">\n- <text\n- id=\"text5480\"\n- y=\"409.46326\"\n- x=\"73.41291\"\n- style=\"font-style:normal;font-weight:normal;font-size:40px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#6a5400;fill-opacity:1;stroke:none\"\n- xml:space=\"preserve\"><tspan\n- style=\"font-size:8px;fill:#6a5400;fill-opacity:1\"\n- y=\"409.46326\"\n- x=\"73.41291\"\n- id=\"tspan5478\"\n- sodipodi:role=\"line\">CGX-0</tspan></text>\n- </g>\n- <rect\n- style=\"fill:url(#linearGradient5658);fill-opacity:1;stroke:#695400;stroke-width:1.16700006;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5468-2\"\n- width=\"36.554455\"\n- height=\"18.169683\"\n- x=\"92.712852\"\n- y=\"358.37842\" />\n- <g\n- id=\"g5594-7\"\n- transform=\"translate(25.109434,2.578931)\">\n- <text\n- id=\"text5480-9\"\n- y=\"367.46326\"\n- x=\"73.41291\"\n- style=\"font-style:normal;font-weight:normal;font-size:40px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#695400;fill-opacity:1;stroke:none\"\n- xml:space=\"preserve\"><tspan\n- style=\"font-size:8px;fill:#695400;fill-opacity:1\"\n- y=\"367.46326\"\n- x=\"73.41291\"\n- id=\"tspan5478-0\"\n- sodipodi:role=\"line\">CGX-1</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-weight:normal;font-size:40px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"104.15788\"\n- y=\"355.79947\"\n- id=\"text5711\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan5709\"\n- x=\"104.15788\"\n- y=\"392.29269\" /></text>\n- </g>\n- <rect\n- style=\"opacity:1;fill:url(#linearGradient6997);fill-opacity:1;stroke:#695400;stroke-width:1.16700006;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect5468-2-1\"\n- width=\"36.554455\"\n- height=\"18.169683\"\n- x=\"136.71284\"\n- y=\"358.37842\" />\n- <g\n- id=\"g5594-7-0\"\n- transform=\"translate(69.109434,2.578931)\">\n- <text\n- id=\"text5480-9-7\"\n- y=\"367.46326\"\n- x=\"73.41291\"\n- style=\"font-style:normal;font-weight:normal;font-size:40px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none\"\n- xml:space=\"preserve\"><tspan\n- style=\"font-size:8px;fill:#695400;fill-opacity:1\"\n- y=\"367.46326\"\n- x=\"73.41291\"\n- id=\"tspan5478-0-4\"\n- sodipodi:role=\"line\">CGX-2</tspan></text>\n- </g>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"116.4436\"\n- y=\"309.90784\"\n- id=\"text5219-26-1-5-7-6-3-0-4\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"116.4436\"\n- y=\"309.90784\"\n- id=\"tspan5223-10-9-1-6-8-3-1-1\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.33980179px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;stroke-width:1.03398025\">CGX-FW Interface</tspan></text>\n- <path\n- style=\"fill:none;stroke:#ff0000;stroke-width:0.45899999;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:2.29999995;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#Arrow1Mstart);marker-end:url(#Arrow1Mend)\"\n- d=\"m 65.54286,336.17648 v 23\"\n- id=\"path7614\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#ff0000;stroke-width:0.45899999;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:2.29999995;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#Arrow1Mstart-30);marker-end:url(#Arrow1Mend-6)\"\n- d=\"m 108.54285,336.67647 v 23\"\n- id=\"path7614-2\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#ff0000;stroke-width:0.45899999;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:2.29999995;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#Arrow1Mstart-30-0);marker-end:url(#Arrow1Mend-6-8)\"\n- d=\"m 152.54285,336.67647 v 23\"\n- id=\"path7614-2-2\"\n- inkscape:connector-curvature=\"0\" />\n- <rect\n- style=\"fill:#d6eaf8;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.50469553;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1\"\n- width=\"100.27454\"\n- height=\"105.81976\"\n- x=\"242.65558\"\n- y=\"233.7666\" />\n- <rect\n- style=\"fill:#d6eaf8;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.50588065;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-6\"\n- width=\"100.27335\"\n- height=\"106.31857\"\n- x=\"361.40619\"\n- y=\"233.7672\" />\n- <rect\n- style=\"fill:#d6eaf8;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.50588065;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-6-7\"\n- width=\"100.27335\"\n- height=\"106.31857\"\n- x=\"467.40619\"\n- y=\"233.7672\" />\n- <rect\n- style=\"fill:#d6eaf8;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.49445513;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-6-7-0\"\n- width=\"95.784782\"\n- height=\"106.33\"\n- x=\"573.40039\"\n- y=\"233.76149\" />\n- <path\n- style=\"fill:none;stroke:#00ff00;stroke-width:0.984;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:0.984, 0.98400000000000021;stroke-dashoffset:0;stroke-opacity:1;marker-start:url(#Arrow1Mstart);marker-end:url(#Arrow1Mend)\"\n- d=\"M 176.02438,304.15296 C 237.06133,305.2 237.06133,305.2 237.06133,305.2\"\n- id=\"path8315\"\n- inkscape:connector-curvature=\"0\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"177.04286\"\n- y=\"299.17648\"\n- id=\"text8319\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8317\"\n- x=\"177.04286\"\n- y=\"299.17648\"\n- style=\"font-size:10.66666698px;line-height:1\">AF-PF MBOX</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"291.53308\"\n- y=\"264.67648\"\n- id=\"text8323\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8321\"\n- x=\"291.53308\"\n- y=\"264.67648\"\n- style=\"font-size:10px;text-align:center;text-anchor:middle\"><tspan\n- style=\"font-size:10px;fill:#0000ff\"\n- id=\"tspan8339\"><tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace\"\n- id=\"tspan11972\">Linux</tspan></tspan><tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace\"\n- id=\"tspan11970\"> Netdev </tspan><tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;fill:#00d4aa\"\n- id=\"tspan8343\">PF</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"291.53308\"\n- y=\"281.34314\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\"\n- id=\"tspan8345\">driver</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"291.53308\"\n- y=\"298.00983\"\n- id=\"tspan8325\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\">(octeontx2_pf)</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"291.53308\"\n- y=\"314.67648\"\n- id=\"tspan8327\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\">PF<tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace;fill:#ff0000\"\n- id=\"tspan10511\">x</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"291.53308\"\n- y=\"331.34314\"\n- id=\"tspan8329\" /></text>\n- <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot8331\"\n- style=\"fill:black;fill-opacity:1;stroke:none;font-family:sans-serif;font-style:normal;font-weight:normal;font-size:13.33333333px;line-height:1.25;letter-spacing:0px;word-spacing:0px;-inkscape-font-specification:'sans-serif, Normal';font-stretch:normal;font-variant:normal;text-anchor:start;text-align:start;writing-mode:lr;font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal\"><flowRegion\n- id=\"flowRegion8333\"><rect\n- id=\"rect8335\"\n- width=\"48.5\"\n- height=\"28\"\n- x=\"252.5\"\n- y=\"208.34286\" /></flowRegion><flowPara\n- id=\"flowPara8337\" /></flowRoot> <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.37650499;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9\"\n- width=\"71.28923\"\n- height=\"15.589548\"\n- x=\"253.89825\"\n- y=\"320.63168\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"283.97266\"\n- y=\"319.09348\"\n- id=\"text5219-26-1-5-7-6-3-0-1\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"283.97266\"\n- y=\"319.09348\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\">NIX LF</tspan></text>\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.37650499;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9-7\"\n- width=\"71.28923\"\n- height=\"15.589548\"\n- x=\"255.89822\"\n- y=\"237.88171\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"285.03787\"\n- y=\"239.81017\"\n- id=\"text5219-26-1-5-7-6-3-0-1-4\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"285.03787\"\n- y=\"239.81017\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0-8\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333333px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\">NPA LF</tspan></text>\n- <path\n- style=\"fill:none;stroke:#ff0000;stroke-width:0.41014698;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:2.29999995;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#Arrow1Mstart-30-0-9);marker-end:url(#Arrow1Mend-6-8-3)\"\n- d=\"m 287.54285,340.99417 v 18.3646\"\n- id=\"path7614-2-2-8\"\n- inkscape:connector-curvature=\"0\" />\n- <rect\n- style=\"opacity:1;fill:url(#linearGradient6997-8);fill-opacity:1;stroke:#695400;stroke-width:1.316;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect5468-2-1-4\"\n- width=\"81.505402\"\n- height=\"17.62063\"\n- x=\"251.04015\"\n- y=\"359.86615\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"263.46152\"\n- y=\"224.99915\"\n- id=\"text8319-7\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8317-7\"\n- x=\"263.46152\"\n- y=\"224.99915\"\n- style=\"font-size:10.66666698px;line-height:1\">PF-VF MBOX</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"259.23218\"\n- y=\"371.46179\"\n- id=\"text8319-7-7\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8317-7-3\"\n- x=\"259.23218\"\n- y=\"371.46179\"\n- style=\"font-size:9.33333302px;line-height:1\">CGX-x LMAC-y</tspan></text>\n- <rect\n- style=\"fill:#d6eaf8;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.42349124;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-6-3\"\n- width=\"80.855743\"\n- height=\"92.400963\"\n- x=\"197.86496\"\n- y=\"112.97599\" />\n- <rect\n- style=\"fill:#d6eaf8;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.42349124;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-6-3-4\"\n- width=\"80.855743\"\n- height=\"92.400963\"\n- x=\"286.61499\"\n- y=\"112.476\" />\n- <path\n- style=\"fill:none;stroke:#580000;stroke-width:0.60000002;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:0.3, 0.3;stroke-dashoffset:0;stroke-opacity:1\"\n- d=\"m 188.04286,109.67648 c 2.5,238.5 2,238 2,238 163.49999,0.5 163.49999,0.5 163.49999,0.5 v -124 l -70,0.5 -1.5,-116 v 1.5 z\"\n- id=\"path9240\"\n- inkscape:connector-curvature=\"0\" />\n- <rect\n- style=\"fill:#d6eaf8;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.42349124;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-6-3-4-0\"\n- width=\"80.855743\"\n- height=\"92.400963\"\n- x=\"375.11499\"\n- y=\"111.976\" />\n- <rect\n- style=\"fill:#d6eaf8;fill-opacity:1;stroke:#6ba6fd;stroke-width:0.42349124;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5066-1-6-3-4-0-0\"\n- width=\"80.855743\"\n- height=\"92.400963\"\n- x=\"586.61499\"\n- y=\"111.476\" />\n- <path\n- style=\"fill:none;stroke:#ff00cc;stroke-width:0.3;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:7.2, 0.29999999999999999;stroke-dashoffset:0\"\n- d=\"m 675.54284,107.17648 1,239.5 -317.99999,0.5 -1,-125 14.5,0.5 -0.5,-113.5 z\"\n- id=\"path9272\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#00ffff;stroke-width:0.3;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:7.2,0.3;stroke-dashoffset:0\"\n- d=\"m 284.54285,109.17648 0.5,100 84,-0.5 v -99.5 z\"\n- id=\"path9274\"\n- inkscape:connector-curvature=\"0\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.82769489px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.81207716\"\n- x=\"231.87221\"\n- y=\"146.02637\"\n- id=\"text8323-1\"\n- transform=\"scale(1.0315378,0.96942639)\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8321-2\"\n- x=\"231.87221\"\n- y=\"146.02637\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"><tspan\n- style=\"font-size:8.12077141px;fill:#0000ff;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan8339-6\">Linux</tspan> Netdev <tspan\n- style=\"fill:#0066ff;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan9396\">VF</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"231.87221\"\n- y=\"159.56099\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan8345-6\">driver</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"231.87221\"\n- y=\"173.09561\"\n- id=\"tspan8325-2\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\">(octeontx2_vf)</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"231.87221\"\n- y=\"186.63022\"\n- id=\"tspan8327-7\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\">PF<tspan\n- style=\"fill:#782121;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan10513\">x</tspan><tspan\n- style=\"font-size:8.12077141px;fill:#782121;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan8347-1\">-VF0</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"231.87221\"\n- y=\"200.16484\"\n- id=\"tspan8329-3\"\n- style=\"stroke-width:0.81207716;fill:#782121\" /></text>\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.30575109;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9-9\"\n- width=\"59.718147\"\n- height=\"12.272857\"\n- x=\"207.65872\"\n- y=\"185.61246\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.0760603px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.83967167\"\n- x=\"225.56583\"\n- y=\"192.49615\"\n- id=\"text5219-26-1-5-7-6-3-0-1-6\"\n- transform=\"scale(0.99742277,1.0025839)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"225.56583\"\n- y=\"192.49615\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0-5\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:7.57938623px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:0.83967167\">NIX LF</tspan></text>\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.30575109;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9-7-5\"\n- width=\"59.718147\"\n- height=\"12.272857\"\n- x=\"209.33406\"\n- y=\"116.46765\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.0760603px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.83967167\"\n- x=\"226.43088\"\n- y=\"124.1223\"\n- id=\"text5219-26-1-5-7-6-3-0-1-4-7\"\n- transform=\"scale(0.99742276,1.0025839)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"226.43088\"\n- y=\"124.1223\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0-8-0\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:7.57938623px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:0.83967167\">NPA LF</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.82769489px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.81207716\"\n- x=\"317.66635\"\n- y=\"121.26925\"\n- id=\"text8323-1-9\"\n- transform=\"scale(1.0315378,0.96942642)\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8321-2-3\"\n- x=\"317.66635\"\n- y=\"131.14769\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716\" /><tspan\n- sodipodi:role=\"line\"\n- x=\"317.66635\"\n- y=\"144.6823\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan9400\"><tspan\n- style=\"fill:#ff2a2a;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan9402\">DPDK</tspan> Ethdev <tspan\n- style=\"fill:#0066ff;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan9398\">VF</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"317.66635\"\n- y=\"158.21692\"\n- id=\"tspan8325-2-7\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\">driver</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"317.66635\"\n- y=\"171.75154\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan9392\" /><tspan\n- sodipodi:role=\"line\"\n- x=\"317.66635\"\n- y=\"185.28616\"\n- id=\"tspan8327-7-8\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\">PF<tspan\n- style=\"fill:#782121;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan10515\">x</tspan><tspan\n- style=\"font-size:8.12077141px;fill:#782121;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan8347-1-0\">-VF1</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"317.66635\"\n- y=\"198.82077\"\n- id=\"tspan8329-3-3\"\n- style=\"stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\" /></text>\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.30575109;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9-9-3\"\n- width=\"59.718147\"\n- height=\"12.272857\"\n- x=\"295.65872\"\n- y=\"185.11246\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.0760603px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.83967167\"\n- x=\"313.79312\"\n- y=\"191.99756\"\n- id=\"text5219-26-1-5-7-6-3-0-1-6-1\"\n- transform=\"scale(0.99742276,1.0025839)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"313.79312\"\n- y=\"191.99756\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0-5-5\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:7.57938623px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:0.83967167\">NIX LF</tspan></text>\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.30575109;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9-7-5-8\"\n- width=\"59.718147\"\n- height=\"12.272857\"\n- x=\"297.33408\"\n- y=\"115.96765\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.0760603px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.83967167\"\n- x=\"314.65817\"\n- y=\"123.62372\"\n- id=\"text5219-26-1-5-7-6-3-0-1-4-7-9\"\n- transform=\"scale(0.99742276,1.0025839)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"314.65817\"\n- y=\"123.62372\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0-8-0-9\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:7.57938623px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:0.83967167\">NPA LF</tspan></text>\n- <path\n- style=\"fill:none;stroke:#00ff00;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;stroke-miterlimit:4;stroke-dasharray:1, 1;stroke-dashoffset:0;marker-end:url(#Arrow1Mstart);marker-start:url(#Arrow1Mstart)\"\n- d=\"m 254.54285,205.17648 c 1,29 1,28.5 1,28.5\"\n- id=\"path9405\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#00ff00;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:1, 1;stroke-dashoffset:0;stroke-opacity:1;marker-start:url(#Arrow1Mstart-1);marker-end:url(#Arrow1Mstart-1)\"\n- d=\"m 324.42292,203.92589 c 1,29 1,28.5 1,28.5\"\n- id=\"path9405-3\"\n- inkscape:connector-curvature=\"0\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"408.28308\"\n- y=\"265.83011\"\n- id=\"text8323-7\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8321-3\"\n- x=\"408.28308\"\n- y=\"265.83011\"\n- style=\"font-size:10px;text-align:center;text-anchor:middle;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"><tspan\n- style=\"fill:#ff2a2a;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan10440\">DPDK</tspan> Ethdev <tspan\n- style=\"font-size:10px;fill:#00d4aa;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan8343-5\">PF</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"408.28308\"\n- y=\"282.49677\"\n- style=\"font-size:10px;text-align:center;text-anchor:middle;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan8345-8\">driver</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"408.28308\"\n- y=\"299.16345\"\n- id=\"tspan8325-5\"\n- style=\"font-size:10px;text-align:center;text-anchor:middle;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\" /><tspan\n- sodipodi:role=\"line\"\n- x=\"408.28308\"\n- y=\"315.83011\"\n- id=\"tspan8327-1\"\n- style=\"font-size:10px;text-align:center;text-anchor:middle;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\">PF<tspan\n- style=\"fill:#ff0000;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan10517\">y</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"408.28308\"\n- y=\"332.49677\"\n- id=\"tspan8329-2\" /></text>\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.37650499;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9-3\"\n- width=\"71.28923\"\n- height=\"15.589548\"\n- x=\"376.64825\"\n- y=\"319.78531\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"410.92075\"\n- y=\"318.27411\"\n- id=\"text5219-26-1-5-7-6-3-0-1-62\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"410.92075\"\n- y=\"318.27411\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0-4\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\">NIX LF</tspan></text>\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.37650499;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9-7-2\"\n- width=\"71.28923\"\n- height=\"15.589548\"\n- x=\"378.64822\"\n- y=\"237.03534\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"411.98596\"\n- y=\"238.99095\"\n- id=\"text5219-26-1-5-7-6-3-0-1-4-4\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"411.98596\"\n- y=\"238.99095\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0-8-7\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\">NPA LF</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"386.21152\"\n- y=\"224.15277\"\n- id=\"text8319-7-5\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8317-7-8\"\n- x=\"386.21152\"\n- y=\"224.15277\"\n- style=\"font-size:10.66666698px;line-height:1\">PF-VF MBOX</tspan></text>\n- <path\n- style=\"fill:none;stroke:#00ff00;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:1, 1;stroke-dashoffset:0;stroke-opacity:1;marker-start:url(#Arrow1Mstart-48);marker-end:url(#Arrow1Mstart-48)\"\n- d=\"m 411.29285,204.33011 c 1,29 1,28.5 1,28.5\"\n- id=\"path9405-0\"\n- inkscape:connector-curvature=\"0\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"520.61176\"\n- y=\"265.49265\"\n- id=\"text8323-7-8\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8321-3-3\"\n- x=\"520.61176\"\n- y=\"265.49265\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\"><tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace;fill:#ff2a2a\"\n- id=\"tspan10440-2\">DPDK</tspan> Eventdev <tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;fill:#00d4aa\"\n- id=\"tspan8343-5-3\">PF</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"520.61176\"\n- y=\"282.1593\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\"\n- id=\"tspan8345-8-6\">driver</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"520.61176\"\n- y=\"298.82599\"\n- id=\"tspan8325-5-4\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\" /><tspan\n- sodipodi:role=\"line\"\n- x=\"520.61176\"\n- y=\"315.49265\"\n- id=\"tspan8327-1-0\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\">PF<tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace;fill:#ff0000\"\n- id=\"tspan10519\">z</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"520.61176\"\n- y=\"332.1593\"\n- id=\"tspan8329-2-1\" /></text>\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.37650499;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9-3-6\"\n- width=\"71.28923\"\n- height=\"15.589548\"\n- x=\"484.97693\"\n- y=\"319.44785\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"522.95496\"\n- y=\"317.94733\"\n- id=\"text5219-26-1-5-7-6-3-0-1-62-1\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"522.95496\"\n- y=\"317.94733\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0-4-7\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\">TIM LF</tspan></text>\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.37650499;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9-7-2-8\"\n- width=\"71.28923\"\n- height=\"15.589548\"\n- x=\"486.9769\"\n- y=\"236.69788\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12.40776253px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.03398025\"\n- x=\"524.0202\"\n- y=\"238.66432\"\n- id=\"text5219-26-1-5-7-6-3-0-1-4-4-3\"\n- transform=\"scale(0.96692797,1.0342032)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"524.0202\"\n- y=\"238.66432\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0-8-7-6\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:9.33333302px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:1.03398025\">SSO LF</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"619.6156\"\n- y=\"265.47531\"\n- id=\"text8323-7-8-3\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8321-3-3-1\"\n- x=\"619.6156\"\n- y=\"265.47531\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\"> <tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace;fill:#0000ff\"\n- id=\"tspan10562\">Linux </tspan>Crypto <tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;fill:#00d4aa\"\n- id=\"tspan8343-5-3-7\">PF</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"619.6156\"\n- y=\"282.14197\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\"\n- id=\"tspan8345-8-6-8\">driver</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"619.6156\"\n- y=\"298.80865\"\n- id=\"tspan8325-5-4-3\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\" /><tspan\n- sodipodi:role=\"line\"\n- x=\"619.6156\"\n- y=\"315.47531\"\n- id=\"tspan8327-1-0-5\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle\">PF<tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace;fill:#ff0000\"\n- id=\"tspan10560\">m</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"619.6156\"\n- y=\"332.14197\"\n- id=\"tspan8329-2-1-9\" /></text>\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.30575109;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9-9-3-0\"\n- width=\"59.718147\"\n- height=\"12.272857\"\n- x=\"385.10458\"\n- y=\"183.92126\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.0760603px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.83967167\"\n- x=\"403.46997\"\n- y=\"190.80957\"\n- id=\"text5219-26-1-5-7-6-3-0-1-6-1-5\"\n- transform=\"scale(0.99742276,1.0025839)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"403.46997\"\n- y=\"190.80957\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0-5-5-5\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:7.57938623px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:0.83967167\">NIX LF</tspan></text>\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.30575109;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9-7-5-8-5\"\n- width=\"59.718147\"\n- height=\"12.272857\"\n- x=\"386.77994\"\n- y=\"116.77647\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.0760603px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.83967167\"\n- x=\"404.33502\"\n- y=\"124.43062\"\n- id=\"text5219-26-1-5-7-6-3-0-1-4-7-9-8\"\n- transform=\"scale(0.99742276,1.0025839)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"404.33502\"\n- y=\"124.43062\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0-8-0-9-8\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:7.57938623px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:0.83967167\">NPA LF</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.82769489px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.81207716\"\n- x=\"402.97598\"\n- y=\"143.8235\"\n- id=\"text8323-1-7\"\n- transform=\"scale(1.0315378,0.96942642)\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8321-2-1\"\n- x=\"402.97598\"\n- y=\"143.8235\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"><tspan\n- style=\"fill:#ff2a2a;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan11102\">DPDK</tspan> Ethdev <tspan\n- style=\"fill:#0066ff;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan9396-1\">VF</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"402.97598\"\n- y=\"157.35812\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan8345-6-5\">driver</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"402.97598\"\n- y=\"170.89275\"\n- id=\"tspan8327-7-2\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\" /><tspan\n- sodipodi:role=\"line\"\n- x=\"402.97598\"\n- y=\"184.42735\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan11106\">PF<tspan\n- style=\"fill:#a02c2c;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan11110\">y</tspan><tspan\n- style=\"font-size:8.12077141px;fill:#a02c2c;stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan8347-1-2\">-VF0</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"402.97598\"\n- y=\"197.96198\"\n- id=\"tspan8329-3-4\"\n- style=\"stroke-width:0.81207716;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\" /></text>\n- <rect\n- style=\"fill:#daeef5;fill-opacity:1;stroke:#6b86fd;stroke-width:0.30575109;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1\"\n- id=\"rect5166-9-9-3-0-0\"\n- width=\"59.718147\"\n- height=\"12.272857\"\n- x=\"596.60461\"\n- y=\"185.11246\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.0760603px;line-height:0%;font-family:monospace;-inkscape-font-specification:monospace;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.83967167\"\n- x=\"615.51703\"\n- y=\"191.99774\"\n- id=\"text5219-26-1-5-7-6-3-0-1-6-1-5-1\"\n- transform=\"scale(0.99742276,1.0025839)\"><tspan\n- sodipodi:role=\"line\"\n- x=\"615.51703\"\n- y=\"191.99774\"\n- id=\"tspan5223-10-9-1-6-8-3-1-0-5-5-5-2\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:7.57938623px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;stroke-width:0.83967167\">CPT LF</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:10.82769489px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.81207716\"\n- x=\"608.00879\"\n- y=\"145.05219\"\n- id=\"text8323-1-7-3\"\n- transform=\"scale(1.0315378,0.96942642)\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8321-2-1-5\"\n- x=\"608.00879\"\n- y=\"145.05219\"\n- style=\"font-size:8.12077141px;text-align:center;text-anchor:middle;stroke-width:0.81207716\"><tspan\n- id=\"tspan1793\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace;fill:#ff2a2a\">DPDK</tspan><tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace\"\n- id=\"tspan11966\"> Crypto </tspan><tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace;fill:#0066ff\"\n- id=\"tspan9396-1-1\">VF</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"608.00879\"\n- y=\"158.58681\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:8.12077141px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;stroke-width:0.81207716\"\n- id=\"tspan8345-6-5-4\">driver</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"608.00879\"\n- y=\"172.12143\"\n- id=\"tspan8327-7-2-1\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:8.12077141px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;stroke-width:0.81207716\" /><tspan\n- sodipodi:role=\"line\"\n- x=\"608.00879\"\n- y=\"185.65604\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:8.12077141px;font-family:monospace;-inkscape-font-specification:monospace;text-align:center;text-anchor:middle;stroke-width:0.81207716\"\n- id=\"tspan11106-8\">PF<tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:monospace;-inkscape-font-specification:monospace;fill:#c83737\"\n- id=\"tspan11172\">m</tspan><tspan\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:8.12077141px;font-family:monospace;-inkscape-font-specification:monospace;fill:#c83737;stroke-width:0.81207716\"\n- id=\"tspan8347-1-2-0\">-VF0</tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"608.00879\"\n- y=\"199.19066\"\n- id=\"tspan8329-3-4-0\"\n- style=\"stroke-width:0.81207716\" /></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"603.23218\"\n- y=\"224.74855\"\n- id=\"text8319-7-5-1\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8317-7-8-4\"\n- x=\"603.23218\"\n- y=\"224.74855\"\n- style=\"font-size:10.66666698px;line-height:1\">PF-VF MBOX</tspan></text>\n- <path\n- style=\"fill:none;stroke:#00ff00;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:1, 1;stroke-dashoffset:0;stroke-opacity:1;marker-start:url(#Arrow1Mstart-48-6);marker-end:url(#Arrow1Mstart-48-6)\"\n- d=\"m 628.31351,204.92589 c 1,29 1,28.5 1,28.5\"\n- id=\"path9405-0-2\"\n- inkscape:connector-curvature=\"0\" />\n- <flowRoot\n- xml:space=\"preserve\"\n- id=\"flowRoot11473\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- transform=\"translate(46.542857,100.33361)\"><flowRegion\n- id=\"flowRegion11475\"><rect\n- id=\"rect11477\"\n- width=\"90\"\n- height=\"14.5\"\n- x=\"426\"\n- y=\"26.342873\" /></flowRegion><flowPara\n- id=\"flowPara11479\">DDDpk</flowPara></flowRoot> <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"509.60013\"\n- y=\"128.17648\"\n- id=\"text11483\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan11481\"\n- x=\"511.47513\"\n- y=\"128.17648\"\n- style=\"font-size:8px;text-align:center;text-anchor:middle;fill:#005544\">D<tspan\n- style=\"-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal;fill:#005544\"\n- id=\"tspan11962\">PDK-APP1 with </tspan></tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"511.47513\"\n- y=\"144.84315\"\n- style=\"font-size:8px;text-align:center;text-anchor:middle;fill:#005544;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan11485\">one ethdev </tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"509.60013\"\n- y=\"161.50981\"\n- style=\"font-size:8px;text-align:center;text-anchor:middle;fill:#005544;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan11491\">over Linux PF</tspan></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"533.54285\"\n- y=\"158.17648\"\n- id=\"text11489\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan11487\"\n- x=\"533.54285\"\n- y=\"170.34088\" /></text>\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-feature-settings:normal;text-align:start;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"518.02197\"\n- y=\"179.98117\"\n- id=\"text11483-6\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan11481-4\"\n- x=\"519.42822\"\n- y=\"179.98117\"\n- style=\"font-size:8px;text-align:center;text-anchor:middle;fill:#ff2a2a;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\">DPDK-APP2 with </tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"518.02197\"\n- y=\"196.64784\"\n- style=\"font-size:8px;text-align:center;text-anchor:middle;fill:#ff2a2a;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan11485-5\">Two ethdevs(PF,VF) ,</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"518.02197\"\n- y=\"213.3145\"\n- style=\"font-size:8px;text-align:center;text-anchor:middle;fill:#ff2a2a;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan11517\">eventdev, timer adapter and</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"518.02197\"\n- y=\"229.98117\"\n- style=\"font-size:8px;text-align:center;text-anchor:middle;fill:#ff2a2a;-inkscape-font-specification:monospace;font-family:monospace;font-weight:normal;font-style:normal;font-stretch:normal;font-variant:normal\"\n- id=\"tspan11519\"> cryptodev</tspan><tspan\n- sodipodi:role=\"line\"\n- x=\"518.02197\"\n- y=\"246.64784\"\n- style=\"font-size:10.66666698px;text-align:center;text-anchor:middle;fill:#00ffff\"\n- id=\"tspan11491-6\" /></text>\n- <path\n- style=\"fill:#005544;stroke:#00ffff;stroke-width:1.02430511;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:1.02430516, 4.09722065999999963;stroke-dashoffset:0;stroke-opacity:1;marker-end:url(#Arrow1Mstart-8)\"\n- d=\"m 483.99846,150.16496 -112.95349,13.41069 v 0 l -0.48897,-0.53643 h 0.48897\"\n- id=\"path11521\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:#ff0000;stroke:#ff5555;stroke-width:1.16440296;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:1.16440301, 2.32880602999999997;stroke-dashoffset:0;stroke-opacity:1;marker-end:url(#Arrow1Mend-0)\"\n- d=\"m 545.54814,186.52569 c 26.3521,-76.73875 26.3521,-76.73875 26.3521,-76.73875\"\n- id=\"path11523\"\n- inkscape:connector-curvature=\"0\" />\n- <path\n- style=\"fill:none;stroke:#ff0000;stroke-width:0.41014698;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:2.29999995;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#Arrow1Mstart-30-0-9-0);marker-end:url(#Arrow1Mend-6-8-3-7)\"\n- d=\"m 409.29286,341.50531 v 18.3646\"\n- id=\"path7614-2-2-8-2\"\n- inkscape:connector-curvature=\"0\" />\n- <rect\n- style=\"opacity:1;fill:url(#linearGradient6997-8-0);fill-opacity:1;stroke:#695400;stroke-width:1.31599998;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1\"\n- id=\"rect5468-2-1-4-9\"\n- width=\"81.505402\"\n- height=\"17.62063\"\n- x=\"372.79016\"\n- y=\"360.37729\" />\n- <text\n- xml:space=\"preserve\"\n- style=\"font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.33333302px;line-height:1.25;font-family:monospace;-inkscape-font-specification:monospace;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none\"\n- x=\"380.98218\"\n- y=\"371.97293\"\n- id=\"text8319-7-7-1\"><tspan\n- sodipodi:role=\"line\"\n- id=\"tspan8317-7-3-1\"\n- x=\"380.98218\"\n- y=\"371.97293\"\n- style=\"font-size:9.33333302px;line-height:1\">CGX-x LMAC-y</tspan></text>\n- </g>\n-</svg>\ndiff --git a/doc/guides/platform/index.rst b/doc/guides/platform/index.rst\nindex 7614e1a368..2ff91a6018 100644\n--- a/doc/guides/platform/index.rst\n+++ b/doc/guides/platform/index.rst\n@@ -15,4 +15,3 @@ The following are platform specific guides and setup information.\n dpaa\n dpaa2\n octeontx\n- octeontx2\ndiff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst\ndeleted file mode 100644\nindex 5ab43abbdd..0000000000\n--- a/doc/guides/platform/octeontx2.rst\n+++ /dev/null\n@@ -1,520 +0,0 @@\n-.. SPDX-License-Identifier: BSD-3-Clause\n- Copyright(c) 2019 Marvell International Ltd.\n-\n-Marvell OCTEON TX2 Platform Guide\n-=================================\n-\n-This document gives an overview of **Marvell OCTEON TX2** RVU H/W block,\n-packet flow and procedure to build DPDK on OCTEON TX2 platform.\n-\n-More information about OCTEON TX2 SoC can be found at `Marvell Official Website\n-<https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.\n-\n-Supported OCTEON TX2 SoCs\n--------------------------\n-\n-- CN98xx\n-- CN96xx\n-- CN93xx\n-\n-OCTEON TX2 Resource Virtualization Unit architecture\n-----------------------------------------------------\n-\n-The :numref:`figure_octeontx2_resource_virtualization` diagram depicts the\n-RVU architecture and a resource provisioning example.\n-\n-.. _figure_octeontx2_resource_virtualization:\n-\n-.. figure:: img/octeontx2_resource_virtualization.*\n-\n- OCTEON TX2 Resource virtualization architecture and provisioning example\n-\n-\n-Resource Virtualization Unit (RVU) on Marvell's OCTEON TX2 SoC maps HW\n-resources belonging to the network, crypto and other functional blocks onto\n-PCI-compatible physical and virtual functions.\n-\n-Each functional block has multiple local functions (LFs) for\n-provisioning to different PCIe devices. RVU supports multiple PCIe SRIOV\n-physical functions (PFs) and virtual functions (VFs).\n-\n-The :numref:`table_octeontx2_rvu_dpdk_mapping` shows the various local\n-functions (LFs) provided by the RVU and its functional mapping to\n-DPDK subsystem.\n-\n-.. _table_octeontx2_rvu_dpdk_mapping:\n-\n-.. table:: RVU managed functional blocks and its mapping to DPDK subsystem\n-\n- +---+-----+--------------------------------------------------------------+\n- | # | LF | DPDK subsystem mapping |\n- +===+=====+==============================================================+\n- | 1 | NIX | rte_ethdev, rte_tm, rte_event_eth_[rt]x_adapter, rte_security|\n- +---+-----+--------------------------------------------------------------+\n- | 2 | NPA | rte_mempool |\n- +---+-----+--------------------------------------------------------------+\n- | 3 | NPC | rte_flow |\n- +---+-----+--------------------------------------------------------------+\n- | 4 | CPT | rte_cryptodev, rte_event_crypto_adapter |\n- +---+-----+--------------------------------------------------------------+\n- | 5 | SSO | rte_eventdev |\n- +---+-----+--------------------------------------------------------------+\n- | 6 | TIM | rte_event_timer_adapter |\n- +---+-----+--------------------------------------------------------------+\n- | 7 | LBK | rte_ethdev |\n- +---+-----+--------------------------------------------------------------+\n- | 8 | DPI | rte_rawdev |\n- +---+-----+--------------------------------------------------------------+\n- | 9 | SDP | rte_ethdev |\n- +---+-----+--------------------------------------------------------------+\n- | 10| REE | rte_regexdev |\n- +---+-----+--------------------------------------------------------------+\n-\n-PF0 is called the administrative / admin function (AF) and has exclusive\n-privileges to provision RVU functional block's LFs to each of the PF/VF.\n-\n-PF/VFs communicates with AF via a shared memory region (mailbox).Upon receiving\n-requests from PF/VF, AF does resource provisioning and other HW configuration.\n-\n-AF is always attached to host, but PF/VFs may be used by host kernel itself,\n-or attached to VMs or to userspace applications like DPDK, etc. So, AF has to\n-handle provisioning/configuration requests sent by any device from any domain.\n-\n-The AF driver does not receive or process any data.\n-It is only a configuration driver used in control path.\n-\n-The :numref:`figure_octeontx2_resource_virtualization` diagram also shows a\n-resource provisioning example where,\n-\n-1. PFx and PFx-VF0 bound to Linux netdev driver.\n-2. PFx-VF1 ethdev driver bound to the first DPDK application.\n-3. PFy ethdev driver, PFy-VF0 ethdev driver, PFz eventdev driver, PFm-VF0 cryptodev driver bound to the second DPDK application.\n-\n-LBK HW Access\n--------------\n-\n-Loopback HW Unit (LBK) receives packets from NIX-RX and sends packets back to NIX-TX.\n-The loopback block has N channels and contains data buffering that is shared across\n-all channels. The LBK HW Unit is abstracted using ethdev subsystem, Where PF0's\n-VFs are exposed as ethdev device and odd-even pairs of VFs are tied together,\n-that is, packets sent on odd VF end up received on even VF and vice versa.\n-This would enable HW accelerated means of communication between two domains\n-where even VF bound to the first domain and odd VF bound to the second domain.\n-\n-Typical application usage models are,\n-\n-#. Communication between the Linux kernel and DPDK application.\n-#. Exception path to Linux kernel from DPDK application as SW ``KNI`` replacement.\n-#. Communication between two different DPDK applications.\n-\n-SDP interface\n--------------\n-\n-System DPI Packet Interface unit(SDP) provides PCIe endpoint support for remote host\n-to DMA packets into and out of OCTEON TX2 SoC. SDP interface comes in to live only when\n-OCTEON TX2 SoC is connected in PCIe endpoint mode. It can be used to send/receive\n-packets to/from remote host machine using input/output queue pairs exposed to it.\n-SDP interface receives input packets from remote host from NIX-RX and sends packets\n-to remote host using NIX-TX. Remote host machine need to use corresponding driver\n-(kernel/user mode) to communicate with SDP interface on OCTEON TX2 SoC. SDP supports\n-single PCIe SRIOV physical function(PF) and multiple virtual functions(VF's). Users\n-can bind PF or VF to use SDP interface and it will be enumerated as ethdev ports.\n-\n-The primary use case for SDP is to enable the smart NIC use case. Typical usage models are,\n-\n-#. Communication channel between remote host and OCTEON TX2 SoC over PCIe.\n-#. Transfer packets received from network interface to remote host over PCIe and\n- vice-versa.\n-\n-OCTEON TX2 packet flow\n-----------------------\n-\n-The :numref:`figure_octeontx2_packet_flow_hw_accelerators` diagram depicts\n-the packet flow on OCTEON TX2 SoC in conjunction with use of various HW accelerators.\n-\n-.. _figure_octeontx2_packet_flow_hw_accelerators:\n-\n-.. figure:: img/octeontx2_packet_flow_hw_accelerators.*\n-\n- OCTEON TX2 packet flow in conjunction with use of HW accelerators\n-\n-HW Offload Drivers\n-------------------\n-\n-This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.\n-\n-#. **Ethdev Driver**\n- See :doc:`../nics/octeontx2` for NIX Ethdev driver information.\n-\n-#. **Mempool Driver**\n- See :doc:`../mempool/octeontx2` for NPA mempool driver information.\n-\n-#. **Event Device Driver**\n- See :doc:`../eventdevs/octeontx2` for SSO event device driver information.\n-\n-#. **Crypto Device Driver**\n- See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.\n-\n-Procedure to Setup Platform\n----------------------------\n-\n-There are three main prerequisites for setting up DPDK on OCTEON TX2\n-compatible board:\n-\n-1. **OCTEON TX2 Linux kernel driver**\n-\n- The dependent kernel drivers can be obtained from the\n- `kernel.org <https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/ethernet/marvell/octeontx2>`_.\n-\n- Alternatively, the Marvell SDK also provides the required kernel drivers.\n-\n- Linux kernel should be configured with the following features enabled:\n-\n-.. code-block:: console\n-\n- # 64K pages enabled for better performance\n- CONFIG_ARM64_64K_PAGES=y\n- CONFIG_ARM64_VA_BITS_48=y\n- # huge pages support enabled\n- CONFIG_HUGETLBFS=y\n- CONFIG_HUGETLB_PAGE=y\n- # VFIO enabled with TYPE1 IOMMU at minimum\n- CONFIG_VFIO_IOMMU_TYPE1=y\n- CONFIG_VFIO_VIRQFD=y\n- CONFIG_VFIO=y\n- CONFIG_VFIO_NOIOMMU=y\n- CONFIG_VFIO_PCI=y\n- CONFIG_VFIO_PCI_MMAP=y\n- # SMMUv3 driver\n- CONFIG_ARM_SMMU_V3=y\n- # ARMv8.1 LSE atomics\n- CONFIG_ARM64_LSE_ATOMICS=y\n- # OCTEONTX2 drivers\n- CONFIG_OCTEONTX2_MBOX=y\n- CONFIG_OCTEONTX2_AF=y\n- # Enable if netdev PF driver required\n- CONFIG_OCTEONTX2_PF=y\n- # Enable if netdev VF driver required\n- CONFIG_OCTEONTX2_VF=y\n- CONFIG_CRYPTO_DEV_OCTEONTX2_CPT=y\n- # Enable if OCTEONTX2 DMA PF driver required\n- CONFIG_OCTEONTX2_DPI_PF=n\n-\n-2. **ARM64 Linux Tool Chain**\n-\n- For example, the *aarch64* Linaro Toolchain, which can be obtained from\n- `here <https://releases.linaro.org/components/toolchain/binaries/7.4-2019.02/aarch64-linux-gnu/>`_.\n-\n- Alternatively, the Marvell SDK also provides GNU GCC toolchain, which is\n- optimized for OCTEON TX2 CPU.\n-\n-3. **Rootfile system**\n-\n- Any *aarch64* supporting filesystem may be used. For example,\n- Ubuntu 15.10 (Wily) or 16.04 LTS (Xenial) userland which can be obtained\n- from `<http://cdimage.ubuntu.com/ubuntu-base/releases/16.04/release/ubuntu-base-16.04.1-base-arm64.tar.gz>`_.\n-\n- Alternatively, the Marvell SDK provides the buildroot based root filesystem.\n- The SDK includes all the above prerequisites necessary to bring up the OCTEON TX2 board.\n-\n-- Follow the DPDK :doc:`../linux_gsg/index` to setup the basic DPDK environment.\n-\n-\n-Debugging Options\n------------------\n-\n-.. _table_octeontx2_common_debug_options:\n-\n-.. table:: OCTEON TX2 common debug options\n-\n- +---+------------+-------------------------------------------------------+\n- | # | Component | EAL log command |\n- +===+============+=======================================================+\n- | 1 | Common | --log-level='pmd\\.octeontx2\\.base,8' |\n- +---+------------+-------------------------------------------------------+\n- | 2 | Mailbox | --log-level='pmd\\.octeontx2\\.mbox,8' |\n- +---+------------+-------------------------------------------------------+\n-\n-Debugfs support\n-~~~~~~~~~~~~~~~\n-\n-The **OCTEON TX2 Linux kernel driver** provides support to dump RVU blocks\n-context or stats using debugfs.\n-\n-Enable ``debugfs`` by:\n-\n-1. Compile kernel with debugfs enabled, i.e ``CONFIG_DEBUGFS=y``.\n-2. Boot OCTEON TX2 with debugfs supported kernel.\n-3. Verify ``debugfs`` mounted by default \"mount | grep -i debugfs\" or mount it manually by using.\n-\n-.. code-block:: console\n-\n- # mount -t debugfs none /sys/kernel/debug\n-\n-Currently ``debugfs`` supports the following RVU blocks NIX, NPA, NPC, NDC,\n-SSO & CGX.\n-\n-The file structure under ``/sys/kernel/debug`` is as follows\n-\n-.. code-block:: console\n-\n- octeontx2/\n- |-- cgx\n- | |-- cgx0\n- | | '-- lmac0\n- | | '-- stats\n- | |-- cgx1\n- | | |-- lmac0\n- | | | '-- stats\n- | | '-- lmac1\n- | | '-- stats\n- | '-- cgx2\n- | '-- lmac0\n- | '-- stats\n- |-- cpt\n- | |-- cpt_engines_info\n- | |-- cpt_engines_sts\n- | |-- cpt_err_info\n- | |-- cpt_lfs_info\n- | '-- cpt_pc\n- |---- nix\n- | |-- cq_ctx\n- | |-- ndc_rx_cache\n- | |-- ndc_rx_hits_miss\n- | |-- ndc_tx_cache\n- | |-- ndc_tx_hits_miss\n- | |-- qsize\n- | |-- rq_ctx\n- | |-- sq_ctx\n- | '-- tx_stall_hwissue\n- |-- npa\n- | |-- aura_ctx\n- | |-- ndc_cache\n- | |-- ndc_hits_miss\n- | |-- pool_ctx\n- | '-- qsize\n- |-- npc\n- | |-- mcam_info\n- | '-- rx_miss_act_stats\n- |-- rsrc_alloc\n- '-- sso\n- |-- hws\n- | '-- sso_hws_info\n- '-- hwgrp\n- |-- sso_hwgrp_aq_thresh\n- |-- sso_hwgrp_iaq_walk\n- |-- sso_hwgrp_pc\n- |-- sso_hwgrp_free_list_walk\n- |-- sso_hwgrp_ient_walk\n- '-- sso_hwgrp_taq_walk\n-\n-RVU block LF allocation:\n-\n-.. code-block:: console\n-\n- cat /sys/kernel/debug/octeontx2/rsrc_alloc\n-\n- pcifunc NPA NIX SSO GROUP SSOWS TIM CPT\n- PF1 0 0\n- PF4 1\n- PF13 0, 1 0, 1 0\n-\n-CGX example usage:\n-\n-.. code-block:: console\n-\n- cat /sys/kernel/debug/octeontx2/cgx/cgx2/lmac0/stats\n-\n- =======Link Status======\n- Link is UP 40000 Mbps\n- =======RX_STATS======\n- Received packets: 0\n- Octets of received packets: 0\n- Received PAUSE packets: 0\n- Received PAUSE and control packets: 0\n- Filtered DMAC0 (NIX-bound) packets: 0\n- Filtered DMAC0 (NIX-bound) octets: 0\n- Packets dropped due to RX FIFO full: 0\n- Octets dropped due to RX FIFO full: 0\n- Error packets: 0\n- Filtered DMAC1 (NCSI-bound) packets: 0\n- Filtered DMAC1 (NCSI-bound) octets: 0\n- NCSI-bound packets dropped: 0\n- NCSI-bound octets dropped: 0\n- =======TX_STATS======\n- Packets dropped due to excessive collisions: 0\n- Packets dropped due to excessive deferral: 0\n- Multiple collisions before successful transmission: 0\n- Single collisions before successful transmission: 0\n- Total octets sent on the interface: 0\n- Total frames sent on the interface: 0\n- Packets sent with an octet count < 64: 0\n- Packets sent with an octet count == 64: 0\n- Packets sent with an octet count of 65127: 0\n- Packets sent with an octet count of 128-255: 0\n- Packets sent with an octet count of 256-511: 0\n- Packets sent with an octet count of 512-1023: 0\n- Packets sent with an octet count of 1024-1518: 0\n- Packets sent with an octet count of > 1518: 0\n- Packets sent to a broadcast DMAC: 0\n- Packets sent to the multicast DMAC: 0\n- Transmit underflow and were truncated: 0\n- Control/PAUSE packets sent: 0\n-\n-CPT example usage:\n-\n-.. code-block:: console\n-\n- cat /sys/kernel/debug/octeontx2/cpt/cpt_pc\n-\n- CPT instruction requests 0\n- CPT instruction latency 0\n- CPT NCB read requests 0\n- CPT NCB read latency 0\n- CPT read requests caused by UC fills 0\n- CPT active cycles pc 1395642\n- CPT clock count pc 5579867595493\n-\n-NIX example usage:\n-\n-.. code-block:: console\n-\n- Usage: echo <nixlf> [cq number/all] > /sys/kernel/debug/octeontx2/nix/cq_ctx\n- cat /sys/kernel/debug/octeontx2/nix/cq_ctx\n- echo 0 0 > /sys/kernel/debug/octeontx2/nix/cq_ctx\n- cat /sys/kernel/debug/octeontx2/nix/cq_ctx\n-\n- =====cq_ctx for nixlf:0 and qidx:0 is=====\n- W0: base 158ef1a00\n-\n- W1: wrptr 0\n- W1: avg_con 0\n- W1: cint_idx 0\n- W1: cq_err 0\n- W1: qint_idx 0\n- W1: bpid 0\n- W1: bp_ena 0\n-\n- W2: update_time 31043\n- W2:avg_level 255\n- W2: head 0\n- W2:tail 0\n-\n- W3: cq_err_int_ena 5\n- W3:cq_err_int 0\n- W3: qsize 4\n- W3:caching 1\n- W3: substream 0x000\n- W3: ena 1\n- W3: drop_ena 1\n- W3: drop 64\n- W3: bp 0\n-\n-NPA example usage:\n-\n-.. code-block:: console\n-\n- Usage: echo <npalf> [pool number/all] > /sys/kernel/debug/octeontx2/npa/pool_ctx\n- cat /sys/kernel/debug/octeontx2/npa/pool_ctx\n- echo 0 0 > /sys/kernel/debug/octeontx2/npa/pool_ctx\n- cat /sys/kernel/debug/octeontx2/npa/pool_ctx\n-\n- ======POOL : 0=======\n- W0: Stack base 1375bff00\n- W1: ena 1\n- W1: nat_align 1\n- W1: stack_caching 1\n- W1: stack_way_mask 0\n- W1: buf_offset 1\n- W1: buf_size 19\n- W2: stack_max_pages 24315\n- W2: stack_pages 24314\n- W3: op_pc 267456\n- W4: stack_offset 2\n- W4: shift 5\n- W4: avg_level 255\n- W4: avg_con 0\n- W4: fc_ena 0\n- W4: fc_stype 0\n- W4: fc_hyst_bits 0\n- W4: fc_up_crossing 0\n- W4: update_time 62993\n- W5: fc_addr 0\n- W6: ptr_start 1593adf00\n- W7: ptr_end 180000000\n- W8: err_int 0\n- W8: err_int_ena 7\n- W8: thresh_int 0\n- W8: thresh_int_ena 0\n- W8: thresh_up 0\n- W8: thresh_qint_idx 0\n- W8: err_qint_idx 0\n-\n-NPC example usage:\n-\n-.. code-block:: console\n-\n- cat /sys/kernel/debug/octeontx2/npc/mcam_info\n-\n- NPC MCAM info:\n- RX keywidth : 224bits\n- TX keywidth : 224bits\n-\n- MCAM entries : 2048\n- Reserved : 158\n- Available : 1890\n-\n- MCAM counters : 512\n- Reserved : 1\n- Available : 511\n-\n-SSO example usage:\n-\n-.. code-block:: console\n-\n- Usage: echo [<hws>/all] > /sys/kernel/debug/octeontx2/sso/hws/sso_hws_info\n- echo 0 > /sys/kernel/debug/octeontx2/sso/hws/sso_hws_info\n-\n- ==================================================\n- SSOW HWS[0] Arbitration State 0x0\n- SSOW HWS[0] Guest Machine Control 0x0\n- SSOW HWS[0] SET[0] Group Mask[0] 0xffffffffffffffff\n- SSOW HWS[0] SET[0] Group Mask[1] 0xffffffffffffffff\n- SSOW HWS[0] SET[0] Group Mask[2] 0xffffffffffffffff\n- SSOW HWS[0] SET[0] Group Mask[3] 0xffffffffffffffff\n- SSOW HWS[0] SET[1] Group Mask[0] 0xffffffffffffffff\n- SSOW HWS[0] SET[1] Group Mask[1] 0xffffffffffffffff\n- SSOW HWS[0] SET[1] Group Mask[2] 0xffffffffffffffff\n- SSOW HWS[0] SET[1] Group Mask[3] 0xffffffffffffffff\n- ==================================================\n-\n-Compile DPDK\n-------------\n-\n-DPDK may be compiled either natively on OCTEON TX2 platform or cross-compiled on\n-an x86 based platform.\n-\n-Native Compilation\n-~~~~~~~~~~~~~~~~~~\n-\n-.. code-block:: console\n-\n- meson build\n- ninja -C build\n-\n-Cross Compilation\n-~~~~~~~~~~~~~~~~~\n-\n-Refer to :doc:`../linux_gsg/cross_build_dpdk_for_arm64` for generic arm64 details.\n-\n-.. code-block:: console\n-\n- meson build --cross-file config/arm/arm64_octeontx2_linux_gcc\n- ninja -C build\n-\n-.. note::\n-\n- By default, meson cross compilation uses ``aarch64-linux-gnu-gcc`` toolchain,\n- if Marvell toolchain is available then it can be used by overriding the\n- c, cpp, ar, strip ``binaries`` attributes to respective Marvell\n- toolchain binaries in ``config/arm/arm64_octeontx2_linux_gcc`` file.\ndiff --git a/doc/guides/rel_notes/deprecation.rst b/doc/guides/rel_notes/deprecation.rst\nindex 5581822d10..4e5b23c53d 100644\n--- a/doc/guides/rel_notes/deprecation.rst\n+++ b/doc/guides/rel_notes/deprecation.rst\n@@ -125,20 +125,3 @@ Deprecation Notices\n applications should be updated to use the ``dmadev`` library instead,\n with the underlying HW-functionality being provided by the ``ioat`` or\n ``idxd`` dma drivers\n-\n-* drivers/octeontx2: remove octeontx2 drivers\n-\n- In the view of enabling unified driver for ``octeontx2(cn9k)``/``octeontx3(cn10k)``,\n- removing ``drivers/octeontx2`` drivers and replace with ``drivers/cnxk/`` which\n- supports both ``octeontx2(cn9k)`` and ``octeontx3(cn10k)`` SoCs.\n- This deprecation notice is to do following actions in DPDK v22.02 version.\n-\n- #. Replace ``drivers/common/octeontx2/`` with ``drivers/common/cnxk/``\n- #. Replace ``drivers/mempool/octeontx2/`` with ``drivers/mempool/cnxk/``\n- #. Replace ``drivers/net/octeontx2/`` with ``drivers/net/cnxk/``\n- #. Replace ``drivers/event/octeontx2/`` with ``drivers/event/cnxk/``\n- #. Replace ``drivers/crypto/octeontx2/`` with ``drivers/crypto/cnxk/``\n- #. Rename ``drivers/regex/octeontx2/`` as ``drivers/regex/cn9k/``\n- #. Rename ``config/arm/arm64_octeontx2_linux_gcc`` as ``config/arm/arm64_cn9k_linux_gcc``\n-\n- Last two actions are to align naming convention as cnxk scheme.\ndiff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst\nindex 1a0e6111d7..2f6973cef3 100644\n--- a/doc/guides/rel_notes/release_19_08.rst\n+++ b/doc/guides/rel_notes/release_19_08.rst\n@@ -146,17 +146,17 @@ New Features\n of via software, reducing cycles spent copying large blocks of data in\n applications.\n \n-* **Added Marvell OCTEON TX2 drivers.**\n+* **Added Marvell OCTEON 9 drivers.**\n \n Added the new ``ethdev``, ``eventdev``, ``mempool``, ``eventdev Rx adapter``,\n ``eventdev Tx adapter``, ``eventdev Timer adapter`` and ``rawdev DMA``\n- drivers for various HW co-processors available in ``OCTEON TX2`` SoC.\n+ drivers for various HW co-processors available in ``OCTEON 9`` SoC.\n \n- See :doc:`../platform/octeontx2` and driver information:\n+ See ``platform/octeontx2`` and driver information:\n \n- * :doc:`../nics/octeontx2`\n- * :doc:`../mempool/octeontx2`\n- * :doc:`../eventdevs/octeontx2`\n+ * ``nics/octeontx2``\n+ * ``mempool/octeontx2``\n+ * ``eventdevs/octeontx2``\n * ``rawdevs/octeontx2_dma``\n \n * **Introduced the Intel NTB PMD.**\ndiff --git a/doc/guides/rel_notes/release_19_11.rst b/doc/guides/rel_notes/release_19_11.rst\nindex 302b3e5f37..6c3aa14c0d 100644\n--- a/doc/guides/rel_notes/release_19_11.rst\n+++ b/doc/guides/rel_notes/release_19_11.rst\n@@ -187,12 +187,12 @@ New Features\n Added support for asymmetric operations to Marvell OCTEON TX crypto PMD.\n Supports RSA and modexp operations.\n \n-* **Added Marvell OCTEON TX2 crypto PMD.**\n+* **Added Marvell OCTEON 9 crypto PMD.**\n \n- Added a new PMD for hardware crypto offload block on ``OCTEON TX2``\n+ Added a new PMD for hardware crypto offload block on ``OCTEON 9``\n SoC.\n \n- See :doc:`../cryptodevs/octeontx2` for more details\n+ See ``cryptodevs/octeontx2`` for more details\n \n * **Updated NXP crypto PMDs for PDCP support.**\n \ndiff --git a/doc/guides/rel_notes/release_20_02.rst b/doc/guides/rel_notes/release_20_02.rst\nindex 925985b4f8..daeca868e0 100644\n--- a/doc/guides/rel_notes/release_20_02.rst\n+++ b/doc/guides/rel_notes/release_20_02.rst\n@@ -175,18 +175,18 @@ New Features\n armv8 crypto library is not used anymore. The library name has been changed\n from armv8_crypto to AArch64crypto.\n \n-* **Added inline IPsec support to Marvell OCTEON TX2 PMD.**\n+* **Added inline IPsec support to Marvell OCTEON 9 PMD.**\n \n- Added inline IPsec support to Marvell OCTEON TX2 PMD. With this feature,\n+ Added inline IPsec support to Marvell OCTEON 9 PMD. With this feature,\n applications will be able to offload entire IPsec offload to the hardware.\n For the configured sessions, hardware will do the lookup and perform\n decryption and IPsec transformation. For the outbound path, applications\n can submit a plain packet to the PMD, and it will be sent out on the wire\n after doing encryption and IPsec transformation of the packet.\n \n-* **Added Marvell OCTEON TX2 End Point rawdev PMD.**\n+* **Added Marvell OCTEON 9 End Point rawdev PMD.**\n \n- Added a new OCTEON TX2 rawdev PMD for End Point mode of operation.\n+ Added a new OCTEON 9 rawdev PMD for End Point mode of operation.\n See ``rawdevs/octeontx2_ep`` for more details on this new PMD.\n \n * **Added event mode to l3fwd sample application.**\ndiff --git a/doc/guides/rel_notes/release_20_05.rst b/doc/guides/rel_notes/release_20_05.rst\nindex a38c6c673d..b853f00ae6 100644\n--- a/doc/guides/rel_notes/release_20_05.rst\n+++ b/doc/guides/rel_notes/release_20_05.rst\n@@ -116,9 +116,9 @@ New Features\n * Added support for DCF (Device Config Function) feature.\n * Added switch filter support for Intel DCF.\n \n-* **Updated Marvell OCTEON TX2 ethdev driver.**\n+* **Updated Marvell OCTEON 9 ethdev driver.**\n \n- Updated Marvell OCTEON TX2 ethdev driver with traffic manager support,\n+ Updated Marvell OCTEON 9 ethdev driver with traffic manager support,\n including:\n \n * Hierarchical Scheduling with DWRR and SP.\ndiff --git a/doc/guides/rel_notes/release_20_08.rst b/doc/guides/rel_notes/release_20_08.rst\nindex 445e40fbac..e597cd0130 100644\n--- a/doc/guides/rel_notes/release_20_08.rst\n+++ b/doc/guides/rel_notes/release_20_08.rst\n@@ -183,11 +183,11 @@ New Features\n * Added support for Intel GEN2 QuickAssist device 200xx\n (PF device id 0x18ee, VF device id 0x18ef).\n \n-* **Updated the OCTEON TX2 crypto PMD.**\n+* **Updated the OCTEON 9 crypto PMD.**\n \n- * Added Chacha20-Poly1305 AEAD algorithm support in OCTEON TX2 crypto PMD.\n+ * Added Chacha20-Poly1305 AEAD algorithm support in OCTEON 9 crypto PMD.\n \n- * Updated the OCTEON TX2 crypto PMD to support ``rte_security`` lookaside\n+ * Updated the OCTEON 9 crypto PMD to support ``rte_security`` lookaside\n protocol offload for IPsec.\n \n * **Added support for BPF_ABS/BPF_IND load instructions.**\ndiff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst\nindex 7fd15398e4..4ce9b6aea9 100644\n--- a/doc/guides/rel_notes/release_20_11.rst\n+++ b/doc/guides/rel_notes/release_20_11.rst\n@@ -265,9 +265,9 @@ New Features\n * Added AES-GCM support.\n * Added cipher only offload support.\n \n-* **Updated Marvell OCTEON TX2 crypto PMD.**\n+* **Updated Marvell OCTEON 9 crypto PMD.**\n \n- * Updated the OCTEON TX2 crypto PMD lookaside protocol offload for IPsec with\n+ * Updated the OCTEON 9 crypto PMD lookaside protocol offload for IPsec with\n IPv6 support.\n \n * **Updated Intel QAT PMD.**\n@@ -286,9 +286,9 @@ New Features\n ``rte_security_pdcp_xform`` in ``rte_security`` lib is updated to enable\n 5G NR processing of SDAP headers in PMDs.\n \n-* **Added Marvell OCTEON TX2 regex PMD.**\n+* **Added Marvell OCTEON 9 regex PMD.**\n \n- Added a new PMD for the hardware regex offload block for OCTEON TX2 SoC.\n+ Added a new PMD for the hardware regex offload block for OCTEON 9 SoC.\n \n See ``regexdevs/octeontx2`` for more details.\n \ndiff --git a/doc/guides/rel_notes/release_21_02.rst b/doc/guides/rel_notes/release_21_02.rst\nindex 5fbf5b3d43..ac996dce95 100644\n--- a/doc/guides/rel_notes/release_21_02.rst\n+++ b/doc/guides/rel_notes/release_21_02.rst\n@@ -123,14 +123,14 @@ New Features\n enable applications to add/remove user callbacks which get called\n for every enqueue/dequeue operation.\n \n-* **Updated the OCTEON TX2 crypto PMD.**\n+* **Updated the OCTEON 9 crypto PMD.**\n \n- * Updated the OCTEON TX2 crypto PMD lookaside protocol offload for IPsec with\n+ * Updated the OCTEON 9 crypto PMD lookaside protocol offload for IPsec with\n ESN and anti-replay support.\n- * Updated the OCTEON TX2 crypto PMD with CN98xx support.\n- * Added support for aes-cbc sha1-hmac cipher combination in OCTEON TX2 crypto\n+ * Updated the OCTEON 9 crypto PMD with CN98xx support.\n+ * Added support for aes-cbc sha1-hmac cipher combination in OCTEON 9 crypto\n PMD lookaside protocol offload for IPsec.\n- * Added support for aes-cbc sha256-128-hmac cipher combination in OCTEON TX2\n+ * Added support for aes-cbc sha256-128-hmac cipher combination in OCTEON 9\n crypto PMD lookaside protocol offload for IPsec.\n \n * **Added mlx5 compress PMD.**\ndiff --git a/doc/guides/rel_notes/release_21_05.rst b/doc/guides/rel_notes/release_21_05.rst\nindex 49044ed422..89a261e5f5 100644\n--- a/doc/guides/rel_notes/release_21_05.rst\n+++ b/doc/guides/rel_notes/release_21_05.rst\n@@ -121,7 +121,7 @@ New Features\n * Added GTPU TEID support for DCF switch filter.\n * Added flow priority support for DCF switch filter.\n \n-* **Updated Marvell OCTEON TX2 ethdev driver.**\n+* **Updated Marvell OCTEON 9 ethdev driver.**\n \n * Added support for flow action port id.\n \n@@ -187,9 +187,9 @@ New Features\n \n * Added support for ``DIGEST_ENCRYPTED`` mode in the OCTEON TX crypto PMD.\n \n-* **Updated the OCTEON TX2 crypto PMD.**\n+* **Updated the OCTEON 9 crypto PMD.**\n \n- * Added support for ``DIGEST_ENCRYPTED`` mode in OCTEON TX2 crypto PMD.\n+ * Added support for ``DIGEST_ENCRYPTED`` mode in OCTEON 9 crypto PMD.\n * Added support in lookaside protocol offload mode for IPsec with\n UDP encapsulation support for NAT Traversal.\n * Added support in lookaside protocol offload mode for IPsec with\ndiff --git a/doc/guides/rel_notes/release_21_11.rst b/doc/guides/rel_notes/release_21_11.rst\nindex db09ec01ea..f2497f1447 100644\n--- a/doc/guides/rel_notes/release_21_11.rst\n+++ b/doc/guides/rel_notes/release_21_11.rst\n@@ -54,7 +54,7 @@ New Features\n * **Added Marvell CNXK DMA driver.**\n \n Added dmadev driver for the DPI DMA hardware accelerator\n- of Marvell OCTEONTX2 and OCTEONTX3 family of SoCs.\n+ of Marvell OCTEON 9 and OCTEON 10 family of SoCs.\n \n * **Added NXP DPAA DMA driver.**\n \ndiff --git a/doc/guides/tools/cryptoperf.rst b/doc/guides/tools/cryptoperf.rst\nindex ce93483291..d3d5ebe4dc 100644\n--- a/doc/guides/tools/cryptoperf.rst\n+++ b/doc/guides/tools/cryptoperf.rst\n@@ -157,7 +157,6 @@ The following are the application command-line options:\n crypto_mvsam\n crypto_null\n crypto_octeontx\n- crypto_octeontx2\n crypto_openssl\n crypto_qat\n crypto_scheduler\ndiff --git a/drivers/common/meson.build b/drivers/common/meson.build\nindex 4acbad60b1..ea261dd70a 100644\n--- a/drivers/common/meson.build\n+++ b/drivers/common/meson.build\n@@ -8,5 +8,4 @@ drivers = [\n 'iavf',\n 'mvep',\n 'octeontx',\n- 'octeontx2',\n ]\ndiff --git a/drivers/common/octeontx2/hw/otx2_nix.h b/drivers/common/octeontx2/hw/otx2_nix.h\ndeleted file mode 100644\nindex e3b68505b7..0000000000\n--- a/drivers/common/octeontx2/hw/otx2_nix.h\n+++ /dev/null\n@@ -1,1391 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_NIX_HW_H__\n-#define __OTX2_NIX_HW_H__\n-\n-/* Register offsets */\n-\n-#define NIX_AF_CFG (0x0ull)\n-#define NIX_AF_STATUS (0x10ull)\n-#define NIX_AF_NDC_CFG (0x18ull)\n-#define NIX_AF_CONST (0x20ull)\n-#define NIX_AF_CONST1 (0x28ull)\n-#define NIX_AF_CONST2 (0x30ull)\n-#define NIX_AF_CONST3 (0x38ull)\n-#define NIX_AF_SQ_CONST (0x40ull)\n-#define NIX_AF_CQ_CONST (0x48ull)\n-#define NIX_AF_RQ_CONST (0x50ull)\n-#define NIX_AF_PSE_CONST (0x60ull)\n-#define NIX_AF_TL1_CONST (0x70ull)\n-#define NIX_AF_TL2_CONST (0x78ull)\n-#define NIX_AF_TL3_CONST (0x80ull)\n-#define NIX_AF_TL4_CONST (0x88ull)\n-#define NIX_AF_MDQ_CONST (0x90ull)\n-#define NIX_AF_MC_MIRROR_CONST (0x98ull)\n-#define NIX_AF_LSO_CFG (0xa8ull)\n-#define NIX_AF_BLK_RST (0xb0ull)\n-#define NIX_AF_TX_TSTMP_CFG (0xc0ull)\n-#define NIX_AF_RX_CFG (0xd0ull)\n-#define NIX_AF_AVG_DELAY (0xe0ull)\n-#define NIX_AF_CINT_DELAY (0xf0ull)\n-#define NIX_AF_RX_MCAST_BASE (0x100ull)\n-#define NIX_AF_RX_MCAST_CFG (0x110ull)\n-#define NIX_AF_RX_MCAST_BUF_BASE (0x120ull)\n-#define NIX_AF_RX_MCAST_BUF_CFG (0x130ull)\n-#define NIX_AF_RX_MIRROR_BUF_BASE (0x140ull)\n-#define NIX_AF_RX_MIRROR_BUF_CFG (0x148ull)\n-#define NIX_AF_LF_RST (0x150ull)\n-#define NIX_AF_GEN_INT (0x160ull)\n-#define NIX_AF_GEN_INT_W1S (0x168ull)\n-#define NIX_AF_GEN_INT_ENA_W1S (0x170ull)\n-#define NIX_AF_GEN_INT_ENA_W1C (0x178ull)\n-#define NIX_AF_ERR_INT (0x180ull)\n-#define NIX_AF_ERR_INT_W1S (0x188ull)\n-#define NIX_AF_ERR_INT_ENA_W1S (0x190ull)\n-#define NIX_AF_ERR_INT_ENA_W1C (0x198ull)\n-#define NIX_AF_RAS (0x1a0ull)\n-#define NIX_AF_RAS_W1S (0x1a8ull)\n-#define NIX_AF_RAS_ENA_W1S (0x1b0ull)\n-#define NIX_AF_RAS_ENA_W1C (0x1b8ull)\n-#define NIX_AF_RVU_INT (0x1c0ull)\n-#define NIX_AF_RVU_INT_W1S (0x1c8ull)\n-#define NIX_AF_RVU_INT_ENA_W1S (0x1d0ull)\n-#define NIX_AF_RVU_INT_ENA_W1C (0x1d8ull)\n-#define NIX_AF_TCP_TIMER (0x1e0ull)\n-#define NIX_AF_RX_DEF_OL2 (0x200ull)\n-#define NIX_AF_RX_DEF_OIP4 (0x210ull)\n-#define NIX_AF_RX_DEF_IIP4 (0x220ull)\n-#define NIX_AF_RX_DEF_OIP6 (0x230ull)\n-#define NIX_AF_RX_DEF_IIP6 (0x240ull)\n-#define NIX_AF_RX_DEF_OTCP (0x250ull)\n-#define NIX_AF_RX_DEF_ITCP (0x260ull)\n-#define NIX_AF_RX_DEF_OUDP (0x270ull)\n-#define NIX_AF_RX_DEF_IUDP (0x280ull)\n-#define NIX_AF_RX_DEF_OSCTP (0x290ull)\n-#define NIX_AF_RX_DEF_ISCTP (0x2a0ull)\n-#define NIX_AF_RX_DEF_IPSECX(a) (0x2b0ull | (uint64_t)(a) << 3)\n-#define NIX_AF_RX_IPSEC_GEN_CFG (0x300ull)\n-#define NIX_AF_RX_CPTX_INST_QSEL(a) (0x320ull | (uint64_t)(a) << 3)\n-#define NIX_AF_RX_CPTX_CREDIT(a) (0x360ull | (uint64_t)(a) << 3)\n-#define NIX_AF_NDC_RX_SYNC (0x3e0ull)\n-#define NIX_AF_NDC_TX_SYNC (0x3f0ull)\n-#define NIX_AF_AQ_CFG (0x400ull)\n-#define NIX_AF_AQ_BASE (0x410ull)\n-#define NIX_AF_AQ_STATUS (0x420ull)\n-#define NIX_AF_AQ_DOOR (0x430ull)\n-#define NIX_AF_AQ_DONE_WAIT (0x440ull)\n-#define NIX_AF_AQ_DONE (0x450ull)\n-#define NIX_AF_AQ_DONE_ACK (0x460ull)\n-#define NIX_AF_AQ_DONE_TIMER (0x470ull)\n-#define NIX_AF_AQ_DONE_ENA_W1S (0x490ull)\n-#define NIX_AF_AQ_DONE_ENA_W1C (0x498ull)\n-#define NIX_AF_RX_LINKX_CFG(a) (0x540ull | (uint64_t)(a) << 16)\n-#define NIX_AF_RX_SW_SYNC (0x550ull)\n-#define NIX_AF_RX_LINKX_WRR_CFG(a) (0x560ull | (uint64_t)(a) << 16)\n-#define NIX_AF_EXPR_TX_FIFO_STATUS (0x640ull)\n-#define NIX_AF_NORM_TX_FIFO_STATUS (0x648ull)\n-#define NIX_AF_SDP_TX_FIFO_STATUS (0x650ull)\n-#define NIX_AF_TX_NPC_CAPTURE_CONFIG (0x660ull)\n-#define NIX_AF_TX_NPC_CAPTURE_INFO (0x668ull)\n-#define NIX_AF_TX_NPC_CAPTURE_RESPX(a) (0x680ull | (uint64_t)(a) << 3)\n-#define NIX_AF_SEB_ACTIVE_CYCLES_PCX(a) (0x6c0ull | (uint64_t)(a) << 3)\n-#define NIX_AF_SMQX_CFG(a) (0x700ull | (uint64_t)(a) << 16)\n-#define NIX_AF_SMQX_HEAD(a) (0x710ull | (uint64_t)(a) << 16)\n-#define NIX_AF_SMQX_TAIL(a) (0x720ull | (uint64_t)(a) << 16)\n-#define NIX_AF_SMQX_STATUS(a) (0x730ull | (uint64_t)(a) << 16)\n-#define NIX_AF_SMQX_NXT_HEAD(a) (0x740ull | (uint64_t)(a) << 16)\n-#define NIX_AF_SQM_ACTIVE_CYCLES_PC (0x770ull)\n-#define NIX_AF_PSE_CHANNEL_LEVEL (0x800ull)\n-#define NIX_AF_PSE_SHAPER_CFG (0x810ull)\n-#define NIX_AF_PSE_ACTIVE_CYCLES_PC (0x8c0ull)\n-#define NIX_AF_MARK_FORMATX_CTL(a) (0x900ull | (uint64_t)(a) << 18)\n-#define NIX_AF_TX_LINKX_NORM_CREDIT(a) (0xa00ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TX_LINKX_EXPR_CREDIT(a) (0xa10ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TX_LINKX_SW_XOFF(a) (0xa20ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TX_LINKX_HW_XOFF(a) (0xa30ull | (uint64_t)(a) << 16)\n-#define NIX_AF_SDP_LINK_CREDIT (0xa40ull)\n-#define NIX_AF_SDP_SW_XOFFX(a) (0xa60ull | (uint64_t)(a) << 3)\n-#define NIX_AF_SDP_HW_XOFFX(a) (0xac0ull | (uint64_t)(a) << 3)\n-#define NIX_AF_TL4X_BP_STATUS(a) (0xb00ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_SDP_LINK_CFG(a) (0xb10ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_SCHEDULE(a) (0xc00ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_SHAPE(a) (0xc10ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_CIR(a) (0xc20ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_SHAPE_STATE(a) (0xc50ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_SW_XOFF(a) (0xc70ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_TOPOLOGY(a) (0xc80ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_MD_DEBUG0(a) (0xcc0ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_MD_DEBUG1(a) (0xcc8ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_MD_DEBUG2(a) (0xcd0ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_MD_DEBUG3(a) (0xcd8ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_DROPPED_PACKETS(a) (0xd20ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_DROPPED_BYTES(a) (0xd30ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_RED_PACKETS(a) (0xd40ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_RED_BYTES(a) (0xd50ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_YELLOW_PACKETS(a) (0xd60ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_YELLOW_BYTES(a) (0xd70ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_GREEN_PACKETS(a) (0xd80ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL1X_GREEN_BYTES(a) (0xd90ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_SCHEDULE(a) (0xe00ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_SHAPE(a) (0xe10ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_CIR(a) (0xe20ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_PIR(a) (0xe30ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_SCHED_STATE(a) (0xe40ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_SHAPE_STATE(a) (0xe50ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_SW_XOFF(a) (0xe70ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_TOPOLOGY(a) (0xe80ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_PARENT(a) (0xe88ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_MD_DEBUG0(a) (0xec0ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_MD_DEBUG1(a) (0xec8ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_MD_DEBUG2(a) (0xed0ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL2X_MD_DEBUG3(a) (0xed8ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_SCHEDULE(a) \\\n-\t(0x1000ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_SHAPE(a) \\\n-\t(0x1010ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_CIR(a) \\\n-\t(0x1020ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_PIR(a) \\\n-\t(0x1030ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_SCHED_STATE(a) \\\n-\t(0x1040ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_SHAPE_STATE(a) \\\n-\t(0x1050ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_SW_XOFF(a) \\\n-\t(0x1070ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_TOPOLOGY(a) \\\n-\t(0x1080ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_PARENT(a) \\\n-\t(0x1088ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_MD_DEBUG0(a) \\\n-\t(0x10c0ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_MD_DEBUG1(a) \\\n-\t(0x10c8ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_MD_DEBUG2(a) \\\n-\t(0x10d0ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3X_MD_DEBUG3(a) \\\n-\t(0x10d8ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_SCHEDULE(a) \\\n-\t(0x1200ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_SHAPE(a) \\\n-\t(0x1210ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_CIR(a) \\\n-\t(0x1220ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_PIR(a) \\\n-\t(0x1230ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_SCHED_STATE(a) \\\n-\t(0x1240ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_SHAPE_STATE(a) \\\n-\t(0x1250ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_SW_XOFF(a) \\\n-\t(0x1270ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_TOPOLOGY(a) \\\n-\t(0x1280ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_PARENT(a) \\\n-\t(0x1288ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_MD_DEBUG0(a) \\\n-\t(0x12c0ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_MD_DEBUG1(a) \\\n-\t(0x12c8ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_MD_DEBUG2(a) \\\n-\t(0x12d0ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL4X_MD_DEBUG3(a) \\\n-\t(0x12d8ull | (uint64_t)(a) << 16)\n-#define NIX_AF_MDQX_SCHEDULE(a) \\\n-\t(0x1400ull | (uint64_t)(a) << 16)\n-#define NIX_AF_MDQX_SHAPE(a) \\\n-\t(0x1410ull | (uint64_t)(a) << 16)\n-#define NIX_AF_MDQX_CIR(a) \\\n-\t(0x1420ull | (uint64_t)(a) << 16)\n-#define NIX_AF_MDQX_PIR(a) \\\n-\t(0x1430ull | (uint64_t)(a) << 16)\n-#define NIX_AF_MDQX_SCHED_STATE(a) \\\n-\t(0x1440ull | (uint64_t)(a) << 16)\n-#define NIX_AF_MDQX_SHAPE_STATE(a) \\\n-\t(0x1450ull | (uint64_t)(a) << 16)\n-#define NIX_AF_MDQX_SW_XOFF(a) \\\n-\t(0x1470ull | (uint64_t)(a) << 16)\n-#define NIX_AF_MDQX_PARENT(a) \\\n-\t(0x1480ull | (uint64_t)(a) << 16)\n-#define NIX_AF_MDQX_MD_DEBUG(a) \\\n-\t(0x14c0ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3_TL2X_CFG(a) \\\n-\t(0x1600ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3_TL2X_BP_STATUS(a) \\\n-\t(0x1610ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) \\\n-\t(0x1700ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3)\n-#define NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(a, b) \\\n-\t(0x1800ull | (uint64_t)(a) << 18 | (uint64_t)(b) << 3)\n-#define NIX_AF_TX_MCASTX(a) \\\n-\t(0x1900ull | (uint64_t)(a) << 15)\n-#define NIX_AF_TX_VTAG_DEFX_CTL(a) \\\n-\t(0x1a00ull | (uint64_t)(a) << 16)\n-#define NIX_AF_TX_VTAG_DEFX_DATA(a) \\\n-\t(0x1a10ull | (uint64_t)(a) << 16)\n-#define NIX_AF_RX_BPIDX_STATUS(a) \\\n-\t(0x1a20ull | (uint64_t)(a) << 17)\n-#define NIX_AF_RX_CHANX_CFG(a) \\\n-\t(0x1a30ull | (uint64_t)(a) << 15)\n-#define NIX_AF_CINT_TIMERX(a) \\\n-\t(0x1a40ull | (uint64_t)(a) << 18)\n-#define NIX_AF_LSO_FORMATX_FIELDX(a, b) \\\n-\t(0x1b00ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3)\n-#define NIX_AF_LFX_CFG(a) \\\n-\t(0x4000ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_SQS_CFG(a) \\\n-\t(0x4020ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_TX_CFG2(a) \\\n-\t(0x4028ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_SQS_BASE(a) \\\n-\t(0x4030ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_RQS_CFG(a) \\\n-\t(0x4040ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_RQS_BASE(a) \\\n-\t(0x4050ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_CQS_CFG(a) \\\n-\t(0x4060ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_CQS_BASE(a) \\\n-\t(0x4070ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_TX_CFG(a) \\\n-\t(0x4080ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_TX_PARSE_CFG(a) \\\n-\t(0x4090ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_RX_CFG(a) \\\n-\t(0x40a0ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_RSS_CFG(a) \\\n-\t(0x40c0ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_RSS_BASE(a) \\\n-\t(0x40d0ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_QINTS_CFG(a) \\\n-\t(0x4100ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_QINTS_BASE(a) \\\n-\t(0x4110ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_CINTS_CFG(a) \\\n-\t(0x4120ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_CINTS_BASE(a) \\\n-\t(0x4130ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_RX_IPSEC_CFG0(a) \\\n-\t(0x4140ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_RX_IPSEC_CFG1(a) \\\n-\t(0x4148ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_RX_IPSEC_DYNO_CFG(a) \\\n-\t(0x4150ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_RX_IPSEC_DYNO_BASE(a) \\\n-\t(0x4158ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_RX_IPSEC_SA_BASE(a) \\\n-\t(0x4170ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_TX_STATUS(a) \\\n-\t(0x4180ull | (uint64_t)(a) << 17)\n-#define NIX_AF_LFX_RX_VTAG_TYPEX(a, b) \\\n-\t(0x4200ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)\n-#define NIX_AF_LFX_LOCKX(a, b) \\\n-\t(0x4300ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)\n-#define NIX_AF_LFX_TX_STATX(a, b) \\\n-\t(0x4400ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)\n-#define NIX_AF_LFX_RX_STATX(a, b) \\\n-\t(0x4500ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)\n-#define NIX_AF_LFX_RSS_GRPX(a, b) \\\n-\t(0x4600ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)\n-#define NIX_AF_RX_NPC_MC_RCV (0x4700ull)\n-#define NIX_AF_RX_NPC_MC_DROP (0x4710ull)\n-#define NIX_AF_RX_NPC_MIRROR_RCV (0x4720ull)\n-#define NIX_AF_RX_NPC_MIRROR_DROP (0x4730ull)\n-#define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) \\\n-\t(0x4800ull | (uint64_t)(a) << 16)\n-#define NIX_PRIV_AF_INT_CFG (0x8000000ull)\n-#define NIX_PRIV_LFX_CFG(a) \\\n-\t(0x8000010ull | (uint64_t)(a) << 8)\n-#define NIX_PRIV_LFX_INT_CFG(a) \\\n-\t(0x8000020ull | (uint64_t)(a) << 8)\n-#define NIX_AF_RVU_LF_CFG_DEBUG (0x8000030ull)\n-\n-#define NIX_LF_RX_SECRETX(a) (0x0ull | (uint64_t)(a) << 3)\n-#define NIX_LF_CFG (0x100ull)\n-#define NIX_LF_GINT (0x200ull)\n-#define NIX_LF_GINT_W1S (0x208ull)\n-#define NIX_LF_GINT_ENA_W1C (0x210ull)\n-#define NIX_LF_GINT_ENA_W1S (0x218ull)\n-#define NIX_LF_ERR_INT (0x220ull)\n-#define NIX_LF_ERR_INT_W1S (0x228ull)\n-#define NIX_LF_ERR_INT_ENA_W1C (0x230ull)\n-#define NIX_LF_ERR_INT_ENA_W1S (0x238ull)\n-#define NIX_LF_RAS (0x240ull)\n-#define NIX_LF_RAS_W1S (0x248ull)\n-#define NIX_LF_RAS_ENA_W1C (0x250ull)\n-#define NIX_LF_RAS_ENA_W1S (0x258ull)\n-#define NIX_LF_SQ_OP_ERR_DBG (0x260ull)\n-#define NIX_LF_MNQ_ERR_DBG (0x270ull)\n-#define NIX_LF_SEND_ERR_DBG (0x280ull)\n-#define NIX_LF_TX_STATX(a) (0x300ull | (uint64_t)(a) << 3)\n-#define NIX_LF_RX_STATX(a) (0x400ull | (uint64_t)(a) << 3)\n-#define NIX_LF_OP_SENDX(a) (0x800ull | (uint64_t)(a) << 3)\n-#define NIX_LF_RQ_OP_INT (0x900ull)\n-#define NIX_LF_RQ_OP_OCTS (0x910ull)\n-#define NIX_LF_RQ_OP_PKTS (0x920ull)\n-#define NIX_LF_RQ_OP_DROP_OCTS (0x930ull)\n-#define NIX_LF_RQ_OP_DROP_PKTS (0x940ull)\n-#define NIX_LF_RQ_OP_RE_PKTS (0x950ull)\n-#define NIX_LF_OP_IPSEC_DYNO_CNT (0x980ull)\n-#define NIX_LF_SQ_OP_INT (0xa00ull)\n-#define NIX_LF_SQ_OP_OCTS (0xa10ull)\n-#define NIX_LF_SQ_OP_PKTS (0xa20ull)\n-#define NIX_LF_SQ_OP_STATUS (0xa30ull)\n-#define NIX_LF_SQ_OP_DROP_OCTS (0xa40ull)\n-#define NIX_LF_SQ_OP_DROP_PKTS (0xa50ull)\n-#define NIX_LF_CQ_OP_INT (0xb00ull)\n-#define NIX_LF_CQ_OP_DOOR (0xb30ull)\n-#define NIX_LF_CQ_OP_STATUS (0xb40ull)\n-#define NIX_LF_QINTX_CNT(a) (0xc00ull | (uint64_t)(a) << 12)\n-#define NIX_LF_QINTX_INT(a) (0xc10ull | (uint64_t)(a) << 12)\n-#define NIX_LF_QINTX_ENA_W1S(a) (0xc20ull | (uint64_t)(a) << 12)\n-#define NIX_LF_QINTX_ENA_W1C(a) (0xc30ull | (uint64_t)(a) << 12)\n-#define NIX_LF_CINTX_CNT(a) (0xd00ull | (uint64_t)(a) << 12)\n-#define NIX_LF_CINTX_WAIT(a) (0xd10ull | (uint64_t)(a) << 12)\n-#define NIX_LF_CINTX_INT(a) (0xd20ull | (uint64_t)(a) << 12)\n-#define NIX_LF_CINTX_INT_W1S(a) (0xd30ull | (uint64_t)(a) << 12)\n-#define NIX_LF_CINTX_ENA_W1S(a) (0xd40ull | (uint64_t)(a) << 12)\n-#define NIX_LF_CINTX_ENA_W1C(a) (0xd50ull | (uint64_t)(a) << 12)\n-\n-\n-/* Enum offsets */\n-\n-#define NIX_TX_VTAGOP_NOP (0x0ull)\n-#define NIX_TX_VTAGOP_INSERT (0x1ull)\n-#define NIX_TX_VTAGOP_REPLACE (0x2ull)\n-\n-#define NIX_TX_ACTIONOP_DROP (0x0ull)\n-#define NIX_TX_ACTIONOP_UCAST_DEFAULT (0x1ull)\n-#define NIX_TX_ACTIONOP_UCAST_CHAN (0x2ull)\n-#define NIX_TX_ACTIONOP_MCAST (0x3ull)\n-#define NIX_TX_ACTIONOP_DROP_VIOL (0x5ull)\n-\n-#define NIX_INTF_RX (0x0ull)\n-#define NIX_INTF_TX (0x1ull)\n-\n-#define NIX_TXLAYER_OL3 (0x0ull)\n-#define NIX_TXLAYER_OL4 (0x1ull)\n-#define NIX_TXLAYER_IL3 (0x2ull)\n-#define NIX_TXLAYER_IL4 (0x3ull)\n-\n-#define NIX_SUBDC_NOP (0x0ull)\n-#define NIX_SUBDC_EXT (0x1ull)\n-#define NIX_SUBDC_CRC (0x2ull)\n-#define NIX_SUBDC_IMM (0x3ull)\n-#define NIX_SUBDC_SG (0x4ull)\n-#define NIX_SUBDC_MEM (0x5ull)\n-#define NIX_SUBDC_JUMP (0x6ull)\n-#define NIX_SUBDC_WORK (0x7ull)\n-#define NIX_SUBDC_SOD (0xfull)\n-\n-#define NIX_STYPE_STF (0x0ull)\n-#define NIX_STYPE_STT (0x1ull)\n-#define NIX_STYPE_STP (0x2ull)\n-\n-#define NIX_STAT_LF_TX_TX_UCAST (0x0ull)\n-#define NIX_STAT_LF_TX_TX_BCAST (0x1ull)\n-#define NIX_STAT_LF_TX_TX_MCAST (0x2ull)\n-#define NIX_STAT_LF_TX_TX_DROP (0x3ull)\n-#define NIX_STAT_LF_TX_TX_OCTS (0x4ull)\n-\n-#define NIX_STAT_LF_RX_RX_OCTS (0x0ull)\n-#define NIX_STAT_LF_RX_RX_UCAST (0x1ull)\n-#define NIX_STAT_LF_RX_RX_BCAST (0x2ull)\n-#define NIX_STAT_LF_RX_RX_MCAST (0x3ull)\n-#define NIX_STAT_LF_RX_RX_DROP (0x4ull)\n-#define NIX_STAT_LF_RX_RX_DROP_OCTS (0x5ull)\n-#define NIX_STAT_LF_RX_RX_FCS (0x6ull)\n-#define NIX_STAT_LF_RX_RX_ERR (0x7ull)\n-#define NIX_STAT_LF_RX_RX_DRP_BCAST (0x8ull)\n-#define NIX_STAT_LF_RX_RX_DRP_MCAST (0x9ull)\n-#define NIX_STAT_LF_RX_RX_DRP_L3BCAST (0xaull)\n-#define NIX_STAT_LF_RX_RX_DRP_L3MCAST (0xbull)\n-\n-#define NIX_SQOPERR_SQ_OOR (0x0ull)\n-#define NIX_SQOPERR_SQ_CTX_FAULT (0x1ull)\n-#define NIX_SQOPERR_SQ_CTX_POISON (0x2ull)\n-#define NIX_SQOPERR_SQ_DISABLED (0x3ull)\n-#define NIX_SQOPERR_MAX_SQE_SIZE_ERR (0x4ull)\n-#define NIX_SQOPERR_SQE_OFLOW (0x5ull)\n-#define NIX_SQOPERR_SQB_NULL (0x6ull)\n-#define NIX_SQOPERR_SQB_FAULT (0x7ull)\n-\n-#define NIX_XQESZ_W64 (0x0ull)\n-#define NIX_XQESZ_W16 (0x1ull)\n-\n-#define NIX_VTAGSIZE_T4 (0x0ull)\n-#define NIX_VTAGSIZE_T8 (0x1ull)\n-\n-#define NIX_RX_ACTIONOP_DROP (0x0ull)\n-#define NIX_RX_ACTIONOP_UCAST (0x1ull)\n-#define NIX_RX_ACTIONOP_UCAST_IPSEC (0x2ull)\n-#define NIX_RX_ACTIONOP_MCAST (0x3ull)\n-#define NIX_RX_ACTIONOP_RSS (0x4ull)\n-#define NIX_RX_ACTIONOP_PF_FUNC_DROP (0x5ull)\n-#define NIX_RX_ACTIONOP_MIRROR (0x6ull)\n-\n-#define NIX_RX_VTAGACTION_VTAG0_RELPTR (0x0ull)\n-#define NIX_RX_VTAGACTION_VTAG1_RELPTR (0x4ull)\n-#define NIX_RX_VTAGACTION_VTAG_VALID (0x1ull)\n-#define NIX_TX_VTAGACTION_VTAG0_RELPTR \\\n-\t(sizeof(struct nix_inst_hdr_s) + 2 * 6)\n-#define NIX_TX_VTAGACTION_VTAG1_RELPTR \\\n-\t(sizeof(struct nix_inst_hdr_s) + 2 * 6 + 4)\n-#define NIX_RQINT_DROP (0x0ull)\n-#define NIX_RQINT_RED (0x1ull)\n-#define NIX_RQINT_R2 (0x2ull)\n-#define NIX_RQINT_R3 (0x3ull)\n-#define NIX_RQINT_R4 (0x4ull)\n-#define NIX_RQINT_R5 (0x5ull)\n-#define NIX_RQINT_R6 (0x6ull)\n-#define NIX_RQINT_R7 (0x7ull)\n-\n-#define NIX_MAXSQESZ_W16 (0x0ull)\n-#define NIX_MAXSQESZ_W8 (0x1ull)\n-\n-#define NIX_LSOALG_NOP (0x0ull)\n-#define NIX_LSOALG_ADD_SEGNUM (0x1ull)\n-#define NIX_LSOALG_ADD_PAYLEN (0x2ull)\n-#define NIX_LSOALG_ADD_OFFSET (0x3ull)\n-#define NIX_LSOALG_TCP_FLAGS (0x4ull)\n-\n-#define NIX_MNQERR_SQ_CTX_FAULT (0x0ull)\n-#define NIX_MNQERR_SQ_CTX_POISON (0x1ull)\n-#define NIX_MNQERR_SQB_FAULT (0x2ull)\n-#define NIX_MNQERR_SQB_POISON (0x3ull)\n-#define NIX_MNQERR_TOTAL_ERR (0x4ull)\n-#define NIX_MNQERR_LSO_ERR (0x5ull)\n-#define NIX_MNQERR_CQ_QUERY_ERR (0x6ull)\n-#define NIX_MNQERR_MAX_SQE_SIZE_ERR (0x7ull)\n-#define NIX_MNQERR_MAXLEN_ERR (0x8ull)\n-#define NIX_MNQERR_SQE_SIZEM1_ZERO (0x9ull)\n-\n-#define NIX_MDTYPE_RSVD (0x0ull)\n-#define NIX_MDTYPE_FLUSH (0x1ull)\n-#define NIX_MDTYPE_PMD (0x2ull)\n-\n-#define NIX_NDC_TX_PORT_LMT (0x0ull)\n-#define NIX_NDC_TX_PORT_ENQ (0x1ull)\n-#define NIX_NDC_TX_PORT_MNQ (0x2ull)\n-#define NIX_NDC_TX_PORT_DEQ (0x3ull)\n-#define NIX_NDC_TX_PORT_DMA (0x4ull)\n-#define NIX_NDC_TX_PORT_XQE (0x5ull)\n-\n-#define NIX_NDC_RX_PORT_AQ (0x0ull)\n-#define NIX_NDC_RX_PORT_CQ (0x1ull)\n-#define NIX_NDC_RX_PORT_CINT (0x2ull)\n-#define NIX_NDC_RX_PORT_MC (0x3ull)\n-#define NIX_NDC_RX_PORT_PKT (0x4ull)\n-#define NIX_NDC_RX_PORT_RQ (0x5ull)\n-\n-#define NIX_RE_OPCODE_RE_NONE (0x0ull)\n-#define NIX_RE_OPCODE_RE_PARTIAL (0x1ull)\n-#define NIX_RE_OPCODE_RE_JABBER (0x2ull)\n-#define NIX_RE_OPCODE_RE_FCS (0x7ull)\n-#define NIX_RE_OPCODE_RE_FCS_RCV (0x8ull)\n-#define NIX_RE_OPCODE_RE_TERMINATE (0x9ull)\n-#define NIX_RE_OPCODE_RE_RX_CTL (0xbull)\n-#define NIX_RE_OPCODE_RE_SKIP (0xcull)\n-#define NIX_RE_OPCODE_RE_DMAPKT (0xfull)\n-#define NIX_RE_OPCODE_UNDERSIZE (0x10ull)\n-#define NIX_RE_OPCODE_OVERSIZE (0x11ull)\n-#define NIX_RE_OPCODE_OL2_LENMISM (0x12ull)\n-\n-#define NIX_REDALG_STD (0x0ull)\n-#define NIX_REDALG_SEND (0x1ull)\n-#define NIX_REDALG_STALL (0x2ull)\n-#define NIX_REDALG_DISCARD (0x3ull)\n-\n-#define NIX_RX_MCOP_RQ (0x0ull)\n-#define NIX_RX_MCOP_RSS (0x1ull)\n-\n-#define NIX_RX_PERRCODE_NPC_RESULT_ERR (0x2ull)\n-#define NIX_RX_PERRCODE_MCAST_FAULT (0x4ull)\n-#define NIX_RX_PERRCODE_MIRROR_FAULT (0x5ull)\n-#define NIX_RX_PERRCODE_MCAST_POISON (0x6ull)\n-#define NIX_RX_PERRCODE_MIRROR_POISON (0x7ull)\n-#define NIX_RX_PERRCODE_DATA_FAULT (0x8ull)\n-#define NIX_RX_PERRCODE_MEMOUT (0x9ull)\n-#define NIX_RX_PERRCODE_BUFS_OFLOW (0xaull)\n-#define NIX_RX_PERRCODE_OL3_LEN (0x10ull)\n-#define NIX_RX_PERRCODE_OL4_LEN (0x11ull)\n-#define NIX_RX_PERRCODE_OL4_CHK (0x12ull)\n-#define NIX_RX_PERRCODE_OL4_PORT (0x13ull)\n-#define NIX_RX_PERRCODE_IL3_LEN (0x20ull)\n-#define NIX_RX_PERRCODE_IL4_LEN (0x21ull)\n-#define NIX_RX_PERRCODE_IL4_CHK (0x22ull)\n-#define NIX_RX_PERRCODE_IL4_PORT (0x23ull)\n-\n-#define NIX_SENDCRCALG_CRC32 (0x0ull)\n-#define NIX_SENDCRCALG_CRC32C (0x1ull)\n-#define NIX_SENDCRCALG_ONES16 (0x2ull)\n-\n-#define NIX_SENDL3TYPE_NONE (0x0ull)\n-#define NIX_SENDL3TYPE_IP4 (0x2ull)\n-#define NIX_SENDL3TYPE_IP4_CKSUM (0x3ull)\n-#define NIX_SENDL3TYPE_IP6 (0x4ull)\n-\n-#define NIX_SENDL4TYPE_NONE (0x0ull)\n-#define NIX_SENDL4TYPE_TCP_CKSUM (0x1ull)\n-#define NIX_SENDL4TYPE_SCTP_CKSUM (0x2ull)\n-#define NIX_SENDL4TYPE_UDP_CKSUM (0x3ull)\n-\n-#define NIX_SENDLDTYPE_LDD (0x0ull)\n-#define NIX_SENDLDTYPE_LDT (0x1ull)\n-#define NIX_SENDLDTYPE_LDWB (0x2ull)\n-\n-#define NIX_SENDMEMALG_SET (0x0ull)\n-#define NIX_SENDMEMALG_SETTSTMP (0x1ull)\n-#define NIX_SENDMEMALG_SETRSLT (0x2ull)\n-#define NIX_SENDMEMALG_ADD (0x8ull)\n-#define NIX_SENDMEMALG_SUB (0x9ull)\n-#define NIX_SENDMEMALG_ADDLEN (0xaull)\n-#define NIX_SENDMEMALG_SUBLEN (0xbull)\n-#define NIX_SENDMEMALG_ADDMBUF (0xcull)\n-#define NIX_SENDMEMALG_SUBMBUF (0xdull)\n-\n-#define NIX_SENDMEMDSZ_B64 (0x0ull)\n-#define NIX_SENDMEMDSZ_B32 (0x1ull)\n-#define NIX_SENDMEMDSZ_B16 (0x2ull)\n-#define NIX_SENDMEMDSZ_B8 (0x3ull)\n-\n-#define NIX_SEND_STATUS_GOOD (0x0ull)\n-#define NIX_SEND_STATUS_SQ_CTX_FAULT (0x1ull)\n-#define NIX_SEND_STATUS_SQ_CTX_POISON (0x2ull)\n-#define NIX_SEND_STATUS_SQB_FAULT (0x3ull)\n-#define NIX_SEND_STATUS_SQB_POISON (0x4ull)\n-#define NIX_SEND_STATUS_SEND_HDR_ERR (0x5ull)\n-#define NIX_SEND_STATUS_SEND_EXT_ERR (0x6ull)\n-#define NIX_SEND_STATUS_JUMP_FAULT (0x7ull)\n-#define NIX_SEND_STATUS_JUMP_POISON (0x8ull)\n-#define NIX_SEND_STATUS_SEND_CRC_ERR (0x10ull)\n-#define NIX_SEND_STATUS_SEND_IMM_ERR (0x11ull)\n-#define NIX_SEND_STATUS_SEND_SG_ERR (0x12ull)\n-#define NIX_SEND_STATUS_SEND_MEM_ERR (0x13ull)\n-#define NIX_SEND_STATUS_INVALID_SUBDC (0x14ull)\n-#define NIX_SEND_STATUS_SUBDC_ORDER_ERR (0x15ull)\n-#define NIX_SEND_STATUS_DATA_FAULT (0x16ull)\n-#define NIX_SEND_STATUS_DATA_POISON (0x17ull)\n-#define NIX_SEND_STATUS_NPC_DROP_ACTION (0x20ull)\n-#define NIX_SEND_STATUS_LOCK_VIOL (0x21ull)\n-#define NIX_SEND_STATUS_NPC_UCAST_CHAN_ERR (0x22ull)\n-#define NIX_SEND_STATUS_NPC_MCAST_CHAN_ERR (0x23ull)\n-#define NIX_SEND_STATUS_NPC_MCAST_ABORT (0x24ull)\n-#define NIX_SEND_STATUS_NPC_VTAG_PTR_ERR (0x25ull)\n-#define NIX_SEND_STATUS_NPC_VTAG_SIZE_ERR (0x26ull)\n-#define NIX_SEND_STATUS_SEND_MEM_FAULT (0x27ull)\n-\n-#define NIX_SQINT_LMT_ERR (0x0ull)\n-#define NIX_SQINT_MNQ_ERR (0x1ull)\n-#define NIX_SQINT_SEND_ERR (0x2ull)\n-#define NIX_SQINT_SQB_ALLOC_FAIL (0x3ull)\n-\n-#define NIX_XQE_TYPE_INVALID (0x0ull)\n-#define NIX_XQE_TYPE_RX (0x1ull)\n-#define NIX_XQE_TYPE_RX_IPSECS (0x2ull)\n-#define NIX_XQE_TYPE_RX_IPSECH (0x3ull)\n-#define NIX_XQE_TYPE_RX_IPSECD (0x4ull)\n-#define NIX_XQE_TYPE_SEND (0x8ull)\n-\n-#define NIX_AQ_COMP_NOTDONE (0x0ull)\n-#define NIX_AQ_COMP_GOOD (0x1ull)\n-#define NIX_AQ_COMP_SWERR (0x2ull)\n-#define NIX_AQ_COMP_CTX_POISON (0x3ull)\n-#define NIX_AQ_COMP_CTX_FAULT (0x4ull)\n-#define NIX_AQ_COMP_LOCKERR (0x5ull)\n-#define NIX_AQ_COMP_SQB_ALLOC_FAIL (0x6ull)\n-\n-#define NIX_AF_INT_VEC_RVU (0x0ull)\n-#define NIX_AF_INT_VEC_GEN (0x1ull)\n-#define NIX_AF_INT_VEC_AQ_DONE (0x2ull)\n-#define NIX_AF_INT_VEC_AF_ERR (0x3ull)\n-#define NIX_AF_INT_VEC_POISON (0x4ull)\n-\n-#define NIX_AQINT_GEN_RX_MCAST_DROP (0x0ull)\n-#define NIX_AQINT_GEN_RX_MIRROR_DROP (0x1ull)\n-#define NIX_AQINT_GEN_TL1_DRAIN (0x3ull)\n-#define NIX_AQINT_GEN_SMQ_FLUSH_DONE (0x4ull)\n-\n-#define NIX_AQ_INSTOP_NOP (0x0ull)\n-#define NIX_AQ_INSTOP_INIT (0x1ull)\n-#define NIX_AQ_INSTOP_WRITE (0x2ull)\n-#define NIX_AQ_INSTOP_READ (0x3ull)\n-#define NIX_AQ_INSTOP_LOCK (0x4ull)\n-#define NIX_AQ_INSTOP_UNLOCK (0x5ull)\n-\n-#define NIX_AQ_CTYPE_RQ (0x0ull)\n-#define NIX_AQ_CTYPE_SQ (0x1ull)\n-#define NIX_AQ_CTYPE_CQ (0x2ull)\n-#define NIX_AQ_CTYPE_MCE (0x3ull)\n-#define NIX_AQ_CTYPE_RSS (0x4ull)\n-#define NIX_AQ_CTYPE_DYNO (0x5ull)\n-\n-#define NIX_COLORRESULT_GREEN (0x0ull)\n-#define NIX_COLORRESULT_YELLOW (0x1ull)\n-#define NIX_COLORRESULT_RED_SEND (0x2ull)\n-#define NIX_COLORRESULT_RED_DROP (0x3ull)\n-\n-#define NIX_CHAN_LBKX_CHX(a, b) \\\n-\t(0x000ull | ((uint64_t)(a) << 8) | (uint64_t)(b))\n-#define NIX_CHAN_R4 (0x400ull)\n-#define NIX_CHAN_R5 (0x500ull)\n-#define NIX_CHAN_R6 (0x600ull)\n-#define NIX_CHAN_SDP_CH_END (0x7ffull)\n-#define NIX_CHAN_SDP_CH_START (0x700ull)\n-#define NIX_CHAN_CGXX_LMACX_CHX(a, b, c) \\\n-\t(0x800ull | ((uint64_t)(a) << 8) | ((uint64_t)(b) << 4) | \\\n-\t(uint64_t)(c))\n-\n-#define NIX_INTF_SDP (0x4ull)\n-#define NIX_INTF_CGX0 (0x0ull)\n-#define NIX_INTF_CGX1 (0x1ull)\n-#define NIX_INTF_CGX2 (0x2ull)\n-#define NIX_INTF_LBK0 (0x3ull)\n-\n-#define NIX_CQERRINT_DOOR_ERR (0x0ull)\n-#define NIX_CQERRINT_WR_FULL (0x1ull)\n-#define NIX_CQERRINT_CQE_FAULT (0x2ull)\n-\n-#define NIX_LF_INT_VEC_GINT (0x80ull)\n-#define NIX_LF_INT_VEC_ERR_INT (0x81ull)\n-#define NIX_LF_INT_VEC_POISON (0x82ull)\n-#define NIX_LF_INT_VEC_QINT_END (0x3full)\n-#define NIX_LF_INT_VEC_QINT_START (0x0ull)\n-#define NIX_LF_INT_VEC_CINT_END (0x7full)\n-#define NIX_LF_INT_VEC_CINT_START (0x40ull)\n-\n-/* Enums definitions */\n-\n-/* Structures definitions */\n-\n-/* NIX admin queue instruction structure */\n-struct nix_aq_inst_s {\n-\tuint64_t op : 4;\n-\tuint64_t ctype : 4;\n-\tuint64_t lf : 7;\n-\tuint64_t rsvd_23_15 : 9;\n-\tuint64_t cindex : 20;\n-\tuint64_t rsvd_62_44 : 19;\n-\tuint64_t doneint : 1;\n-\tuint64_t res_addr : 64; /* W1 */\n-};\n-\n-/* NIX admin queue result structure */\n-struct nix_aq_res_s {\n-\tuint64_t op : 4;\n-\tuint64_t ctype : 4;\n-\tuint64_t compcode : 8;\n-\tuint64_t doneint : 1;\n-\tuint64_t rsvd_63_17 : 47;\n-\tuint64_t rsvd_127_64 : 64; /* W1 */\n-};\n-\n-/* NIX completion interrupt context hardware structure */\n-struct nix_cint_hw_s {\n-\tuint64_t ecount : 32;\n-\tuint64_t qcount : 16;\n-\tuint64_t intr : 1;\n-\tuint64_t ena : 1;\n-\tuint64_t timer_idx : 8;\n-\tuint64_t rsvd_63_58 : 6;\n-\tuint64_t ecount_wait : 32;\n-\tuint64_t qcount_wait : 16;\n-\tuint64_t time_wait : 8;\n-\tuint64_t rsvd_127_120 : 8;\n-};\n-\n-/* NIX completion queue entry header structure */\n-struct nix_cqe_hdr_s {\n-\tuint64_t tag : 32;\n-\tuint64_t q : 20;\n-\tuint64_t rsvd_57_52 : 6;\n-\tuint64_t node : 2;\n-\tuint64_t cqe_type : 4;\n-};\n-\n-/* NIX completion queue context structure */\n-struct nix_cq_ctx_s {\n-\tuint64_t base : 64;/* W0 */\n-\tuint64_t rsvd_67_64 : 4;\n-\tuint64_t bp_ena : 1;\n-\tuint64_t rsvd_71_69 : 3;\n-\tuint64_t bpid : 9;\n-\tuint64_t rsvd_83_81 : 3;\n-\tuint64_t qint_idx : 7;\n-\tuint64_t cq_err : 1;\n-\tuint64_t cint_idx : 7;\n-\tuint64_t avg_con : 9;\n-\tuint64_t wrptr : 20;\n-\tuint64_t tail : 20;\n-\tuint64_t head : 20;\n-\tuint64_t avg_level : 8;\n-\tuint64_t update_time : 16;\n-\tuint64_t bp : 8;\n-\tuint64_t drop : 8;\n-\tuint64_t drop_ena : 1;\n-\tuint64_t ena : 1;\n-\tuint64_t rsvd_211_210 : 2;\n-\tuint64_t substream : 20;\n-\tuint64_t caching : 1;\n-\tuint64_t rsvd_235_233 : 3;\n-\tuint64_t qsize : 4;\n-\tuint64_t cq_err_int : 8;\n-\tuint64_t cq_err_int_ena : 8;\n-};\n-\n-/* NIX instruction header structure */\n-struct nix_inst_hdr_s {\n-\tuint64_t pf_func : 16;\n-\tuint64_t sq : 20;\n-\tuint64_t rsvd_63_36 : 28;\n-};\n-\n-/* NIX i/o virtual address structure */\n-struct nix_iova_s {\n-\tuint64_t addr : 64; /* W0 */\n-};\n-\n-/* NIX IPsec dynamic ordering counter structure */\n-struct nix_ipsec_dyno_s {\n-\tuint32_t count : 32; /* W0 */\n-};\n-\n-/* NIX memory value structure */\n-struct nix_mem_result_s {\n-\tuint64_t v : 1;\n-\tuint64_t color : 2;\n-\tuint64_t rsvd_63_3 : 61;\n-};\n-\n-/* NIX statistics operation write data structure */\n-struct nix_op_q_wdata_s {\n-\tuint64_t rsvd_31_0 : 32;\n-\tuint64_t q : 20;\n-\tuint64_t rsvd_63_52 : 12;\n-};\n-\n-/* NIX queue interrupt context hardware structure */\n-struct nix_qint_hw_s {\n-\tuint32_t count : 22;\n-\tuint32_t rsvd_30_22 : 9;\n-\tuint32_t ena : 1;\n-};\n-\n-/* NIX receive queue context structure */\n-struct nix_rq_ctx_hw_s {\n-\tuint64_t ena : 1;\n-\tuint64_t sso_ena : 1;\n-\tuint64_t ipsech_ena : 1;\n-\tuint64_t ena_wqwd : 1;\n-\tuint64_t cq : 20;\n-\tuint64_t substream : 20;\n-\tuint64_t wqe_aura : 20;\n-\tuint64_t spb_aura : 20;\n-\tuint64_t lpb_aura : 20;\n-\tuint64_t sso_grp : 10;\n-\tuint64_t sso_tt : 2;\n-\tuint64_t pb_caching : 2;\n-\tuint64_t wqe_caching : 1;\n-\tuint64_t xqe_drop_ena : 1;\n-\tuint64_t spb_drop_ena : 1;\n-\tuint64_t lpb_drop_ena : 1;\n-\tuint64_t wqe_skip : 2;\n-\tuint64_t rsvd_127_124 : 4;\n-\tuint64_t rsvd_139_128 : 12;\n-\tuint64_t spb_sizem1 : 6;\n-\tuint64_t rsvd_150_146 : 5;\n-\tuint64_t spb_ena : 1;\n-\tuint64_t lpb_sizem1 : 12;\n-\tuint64_t first_skip : 7;\n-\tuint64_t rsvd_171 : 1;\n-\tuint64_t later_skip : 6;\n-\tuint64_t xqe_imm_size : 6;\n-\tuint64_t rsvd_189_184 : 6;\n-\tuint64_t xqe_imm_copy : 1;\n-\tuint64_t xqe_hdr_split : 1;\n-\tuint64_t xqe_drop : 8;\n-\tuint64_t xqe_pass : 8;\n-\tuint64_t wqe_pool_drop : 8;\n-\tuint64_t wqe_pool_pass : 8;\n-\tuint64_t spb_aura_drop : 8;\n-\tuint64_t spb_aura_pass : 8;\n-\tuint64_t spb_pool_drop : 8;\n-\tuint64_t spb_pool_pass : 8;\n-\tuint64_t lpb_aura_drop : 8;\n-\tuint64_t lpb_aura_pass : 8;\n-\tuint64_t lpb_pool_drop : 8;\n-\tuint64_t lpb_pool_pass : 8;\n-\tuint64_t rsvd_319_288 : 32;\n-\tuint64_t ltag : 24;\n-\tuint64_t good_utag : 8;\n-\tuint64_t bad_utag : 8;\n-\tuint64_t flow_tagw : 6;\n-\tuint64_t rsvd_383_366 : 18;\n-\tuint64_t octs : 48;\n-\tuint64_t rsvd_447_432 : 16;\n-\tuint64_t pkts : 48;\n-\tuint64_t rsvd_511_496 : 16;\n-\tuint64_t drop_octs : 48;\n-\tuint64_t rsvd_575_560 : 16;\n-\tuint64_t drop_pkts : 48;\n-\tuint64_t rsvd_639_624 : 16;\n-\tuint64_t re_pkts : 48;\n-\tuint64_t rsvd_702_688 : 15;\n-\tuint64_t ena_copy : 1;\n-\tuint64_t rsvd_739_704 : 36;\n-\tuint64_t rq_int : 8;\n-\tuint64_t rq_int_ena : 8;\n-\tuint64_t qint_idx : 7;\n-\tuint64_t rsvd_767_763 : 5;\n-\tuint64_t rsvd_831_768 : 64;/* W12 */\n-\tuint64_t rsvd_895_832 : 64;/* W13 */\n-\tuint64_t rsvd_959_896 : 64;/* W14 */\n-\tuint64_t rsvd_1023_960 : 64;/* W15 */\n-};\n-\n-/* NIX receive queue context structure */\n-struct nix_rq_ctx_s {\n-\tuint64_t ena : 1;\n-\tuint64_t sso_ena : 1;\n-\tuint64_t ipsech_ena : 1;\n-\tuint64_t ena_wqwd : 1;\n-\tuint64_t cq : 20;\n-\tuint64_t substream : 20;\n-\tuint64_t wqe_aura : 20;\n-\tuint64_t spb_aura : 20;\n-\tuint64_t lpb_aura : 20;\n-\tuint64_t sso_grp : 10;\n-\tuint64_t sso_tt : 2;\n-\tuint64_t pb_caching : 2;\n-\tuint64_t wqe_caching : 1;\n-\tuint64_t xqe_drop_ena : 1;\n-\tuint64_t spb_drop_ena : 1;\n-\tuint64_t lpb_drop_ena : 1;\n-\tuint64_t rsvd_127_122 : 6;\n-\tuint64_t rsvd_139_128 : 12;\n-\tuint64_t spb_sizem1 : 6;\n-\tuint64_t wqe_skip : 2;\n-\tuint64_t rsvd_150_148 : 3;\n-\tuint64_t spb_ena : 1;\n-\tuint64_t lpb_sizem1 : 12;\n-\tuint64_t first_skip : 7;\n-\tuint64_t rsvd_171 : 1;\n-\tuint64_t later_skip : 6;\n-\tuint64_t xqe_imm_size : 6;\n-\tuint64_t rsvd_189_184 : 6;\n-\tuint64_t xqe_imm_copy : 1;\n-\tuint64_t xqe_hdr_split : 1;\n-\tuint64_t xqe_drop : 8;\n-\tuint64_t xqe_pass : 8;\n-\tuint64_t wqe_pool_drop : 8;\n-\tuint64_t wqe_pool_pass : 8;\n-\tuint64_t spb_aura_drop : 8;\n-\tuint64_t spb_aura_pass : 8;\n-\tuint64_t spb_pool_drop : 8;\n-\tuint64_t spb_pool_pass : 8;\n-\tuint64_t lpb_aura_drop : 8;\n-\tuint64_t lpb_aura_pass : 8;\n-\tuint64_t lpb_pool_drop : 8;\n-\tuint64_t lpb_pool_pass : 8;\n-\tuint64_t rsvd_291_288 : 4;\n-\tuint64_t rq_int : 8;\n-\tuint64_t rq_int_ena : 8;\n-\tuint64_t qint_idx : 7;\n-\tuint64_t rsvd_319_315 : 5;\n-\tuint64_t ltag : 24;\n-\tuint64_t good_utag : 8;\n-\tuint64_t bad_utag : 8;\n-\tuint64_t flow_tagw : 6;\n-\tuint64_t rsvd_383_366 : 18;\n-\tuint64_t octs : 48;\n-\tuint64_t rsvd_447_432 : 16;\n-\tuint64_t pkts : 48;\n-\tuint64_t rsvd_511_496 : 16;\n-\tuint64_t drop_octs : 48;\n-\tuint64_t rsvd_575_560 : 16;\n-\tuint64_t drop_pkts : 48;\n-\tuint64_t rsvd_639_624 : 16;\n-\tuint64_t re_pkts : 48;\n-\tuint64_t rsvd_703_688 : 16;\n-\tuint64_t rsvd_767_704 : 64;/* W11 */\n-\tuint64_t rsvd_831_768 : 64;/* W12 */\n-\tuint64_t rsvd_895_832 : 64;/* W13 */\n-\tuint64_t rsvd_959_896 : 64;/* W14 */\n-\tuint64_t rsvd_1023_960 : 64;/* W15 */\n-};\n-\n-/* NIX receive side scaling entry structure */\n-struct nix_rsse_s {\n-\tuint32_t rq : 20;\n-\tuint32_t rsvd_31_20 : 12;\n-};\n-\n-/* NIX receive action structure */\n-struct nix_rx_action_s {\n-\tuint64_t op : 4;\n-\tuint64_t pf_func : 16;\n-\tuint64_t index : 20;\n-\tuint64_t match_id : 16;\n-\tuint64_t flow_key_alg : 5;\n-\tuint64_t rsvd_63_61 : 3;\n-};\n-\n-/* NIX receive immediate sub descriptor structure */\n-struct nix_rx_imm_s {\n-\tuint64_t size : 16;\n-\tuint64_t apad : 3;\n-\tuint64_t rsvd_59_19 : 41;\n-\tuint64_t subdc : 4;\n-};\n-\n-/* NIX receive multicast/mirror entry structure */\n-struct nix_rx_mce_s {\n-\tuint64_t op : 2;\n-\tuint64_t rsvd_2 : 1;\n-\tuint64_t eol : 1;\n-\tuint64_t index : 20;\n-\tuint64_t rsvd_31_24 : 8;\n-\tuint64_t pf_func : 16;\n-\tuint64_t next : 16;\n-};\n-\n-/* NIX receive parse structure */\n-struct nix_rx_parse_s {\n-\tuint64_t chan : 12;\n-\tuint64_t desc_sizem1 : 5;\n-\tuint64_t imm_copy : 1;\n-\tuint64_t express : 1;\n-\tuint64_t wqwd : 1;\n-\tuint64_t errlev : 4;\n-\tuint64_t errcode : 8;\n-\tuint64_t latype : 4;\n-\tuint64_t lbtype : 4;\n-\tuint64_t lctype : 4;\n-\tuint64_t ldtype : 4;\n-\tuint64_t letype : 4;\n-\tuint64_t lftype : 4;\n-\tuint64_t lgtype : 4;\n-\tuint64_t lhtype : 4;\n-\tuint64_t pkt_lenm1 : 16;\n-\tuint64_t l2m : 1;\n-\tuint64_t l2b : 1;\n-\tuint64_t l3m : 1;\n-\tuint64_t l3b : 1;\n-\tuint64_t vtag0_valid : 1;\n-\tuint64_t vtag0_gone : 1;\n-\tuint64_t vtag1_valid : 1;\n-\tuint64_t vtag1_gone : 1;\n-\tuint64_t pkind : 6;\n-\tuint64_t rsvd_95_94 : 2;\n-\tuint64_t vtag0_tci : 16;\n-\tuint64_t vtag1_tci : 16;\n-\tuint64_t laflags : 8;\n-\tuint64_t lbflags : 8;\n-\tuint64_t lcflags : 8;\n-\tuint64_t ldflags : 8;\n-\tuint64_t leflags : 8;\n-\tuint64_t lfflags : 8;\n-\tuint64_t lgflags : 8;\n-\tuint64_t lhflags : 8;\n-\tuint64_t eoh_ptr : 8;\n-\tuint64_t wqe_aura : 20;\n-\tuint64_t pb_aura : 20;\n-\tuint64_t match_id : 16;\n-\tuint64_t laptr : 8;\n-\tuint64_t lbptr : 8;\n-\tuint64_t lcptr : 8;\n-\tuint64_t ldptr : 8;\n-\tuint64_t leptr : 8;\n-\tuint64_t lfptr : 8;\n-\tuint64_t lgptr : 8;\n-\tuint64_t lhptr : 8;\n-\tuint64_t vtag0_ptr : 8;\n-\tuint64_t vtag1_ptr : 8;\n-\tuint64_t flow_key_alg : 5;\n-\tuint64_t rsvd_383_341 : 43;\n-\tuint64_t rsvd_447_384 : 64; /* W6 */\n-};\n-\n-/* NIX receive scatter/gather sub descriptor structure */\n-struct nix_rx_sg_s {\n-\tuint64_t seg1_size : 16;\n-\tuint64_t seg2_size : 16;\n-\tuint64_t seg3_size : 16;\n-\tuint64_t segs : 2;\n-\tuint64_t rsvd_59_50 : 10;\n-\tuint64_t subdc : 4;\n-};\n-\n-/* NIX receive vtag action structure */\n-struct nix_rx_vtag_action_s {\n-\tuint64_t vtag0_relptr : 8;\n-\tuint64_t vtag0_lid : 3;\n-\tuint64_t rsvd_11 : 1;\n-\tuint64_t vtag0_type : 3;\n-\tuint64_t vtag0_valid : 1;\n-\tuint64_t rsvd_31_16 : 16;\n-\tuint64_t vtag1_relptr : 8;\n-\tuint64_t vtag1_lid : 3;\n-\tuint64_t rsvd_43 : 1;\n-\tuint64_t vtag1_type : 3;\n-\tuint64_t vtag1_valid : 1;\n-\tuint64_t rsvd_63_48 : 16;\n-};\n-\n-/* NIX send completion structure */\n-struct nix_send_comp_s {\n-\tuint64_t status : 8;\n-\tuint64_t sqe_id : 16;\n-\tuint64_t rsvd_63_24 : 40;\n-};\n-\n-/* NIX send CRC sub descriptor structure */\n-struct nix_send_crc_s {\n-\tuint64_t size : 16;\n-\tuint64_t start : 16;\n-\tuint64_t insert : 16;\n-\tuint64_t rsvd_57_48 : 10;\n-\tuint64_t alg : 2;\n-\tuint64_t subdc : 4;\n-\tuint64_t iv : 32;\n-\tuint64_t rsvd_127_96 : 32;\n-};\n-\n-/* NIX send extended header sub descriptor structure */\n-RTE_STD_C11\n-union nix_send_ext_w0_u {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t lso_mps : 14;\n-\t\tuint64_t lso : 1;\n-\t\tuint64_t tstmp : 1;\n-\t\tuint64_t lso_sb : 8;\n-\t\tuint64_t lso_format : 5;\n-\t\tuint64_t rsvd_31_29 : 3;\n-\t\tuint64_t shp_chg : 9;\n-\t\tuint64_t shp_dis : 1;\n-\t\tuint64_t shp_ra : 2;\n-\t\tuint64_t markptr : 8;\n-\t\tuint64_t markform : 7;\n-\t\tuint64_t mark_en : 1;\n-\t\tuint64_t subdc : 4;\n-\t};\n-};\n-\n-RTE_STD_C11\n-union nix_send_ext_w1_u {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t vlan0_ins_ptr : 8;\n-\t\tuint64_t vlan0_ins_tci : 16;\n-\t\tuint64_t vlan1_ins_ptr : 8;\n-\t\tuint64_t vlan1_ins_tci : 16;\n-\t\tuint64_t vlan0_ins_ena : 1;\n-\t\tuint64_t vlan1_ins_ena : 1;\n-\t\tuint64_t rsvd_127_114 : 14;\n-\t};\n-};\n-\n-struct nix_send_ext_s {\n-\tunion nix_send_ext_w0_u w0;\n-\tunion nix_send_ext_w1_u w1;\n-};\n-\n-/* NIX send header sub descriptor structure */\n-RTE_STD_C11\n-union nix_send_hdr_w0_u {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t total : 18;\n-\t\tuint64_t rsvd_18 : 1;\n-\t\tuint64_t df : 1;\n-\t\tuint64_t aura : 20;\n-\t\tuint64_t sizem1 : 3;\n-\t\tuint64_t pnc : 1;\n-\t\tuint64_t sq : 20;\n-\t};\n-};\n-\n-RTE_STD_C11\n-union nix_send_hdr_w1_u {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t ol3ptr : 8;\n-\t\tuint64_t ol4ptr : 8;\n-\t\tuint64_t il3ptr : 8;\n-\t\tuint64_t il4ptr : 8;\n-\t\tuint64_t ol3type : 4;\n-\t\tuint64_t ol4type : 4;\n-\t\tuint64_t il3type : 4;\n-\t\tuint64_t il4type : 4;\n-\t\tuint64_t sqe_id : 16;\n-\t};\n-};\n-\n-struct nix_send_hdr_s {\n-\tunion nix_send_hdr_w0_u w0;\n-\tunion nix_send_hdr_w1_u w1;\n-};\n-\n-/* NIX send immediate sub descriptor structure */\n-struct nix_send_imm_s {\n-\tuint64_t size : 16;\n-\tuint64_t apad : 3;\n-\tuint64_t rsvd_59_19 : 41;\n-\tuint64_t subdc : 4;\n-};\n-\n-/* NIX send jump sub descriptor structure */\n-struct nix_send_jump_s {\n-\tuint64_t sizem1 : 7;\n-\tuint64_t rsvd_13_7 : 7;\n-\tuint64_t ld_type : 2;\n-\tuint64_t aura : 20;\n-\tuint64_t rsvd_58_36 : 23;\n-\tuint64_t f : 1;\n-\tuint64_t subdc : 4;\n-\tuint64_t addr : 64; /* W1 */\n-};\n-\n-/* NIX send memory sub descriptor structure */\n-struct nix_send_mem_s {\n-\tuint64_t offset : 16;\n-\tuint64_t rsvd_52_16 : 37;\n-\tuint64_t wmem : 1;\n-\tuint64_t dsz : 2;\n-\tuint64_t alg : 4;\n-\tuint64_t subdc : 4;\n-\tuint64_t addr : 64; /* W1 */\n-};\n-\n-/* NIX send scatter/gather sub descriptor structure */\n-RTE_STD_C11\n-union nix_send_sg_s {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t seg1_size : 16;\n-\t\tuint64_t seg2_size : 16;\n-\t\tuint64_t seg3_size : 16;\n-\t\tuint64_t segs : 2;\n-\t\tuint64_t rsvd_54_50 : 5;\n-\t\tuint64_t i1 : 1;\n-\t\tuint64_t i2 : 1;\n-\t\tuint64_t i3 : 1;\n-\t\tuint64_t ld_type : 2;\n-\t\tuint64_t subdc : 4;\n-\t};\n-};\n-\n-/* NIX send work sub descriptor structure */\n-struct nix_send_work_s {\n-\tuint64_t tag : 32;\n-\tuint64_t tt : 2;\n-\tuint64_t grp : 10;\n-\tuint64_t rsvd_59_44 : 16;\n-\tuint64_t subdc : 4;\n-\tuint64_t addr : 64; /* W1 */\n-};\n-\n-/* NIX sq context hardware structure */\n-struct nix_sq_ctx_hw_s {\n-\tuint64_t ena : 1;\n-\tuint64_t substream : 20;\n-\tuint64_t max_sqe_size : 2;\n-\tuint64_t sqe_way_mask : 16;\n-\tuint64_t sqb_aura : 20;\n-\tuint64_t gbl_rsvd1 : 5;\n-\tuint64_t cq_id : 20;\n-\tuint64_t cq_ena : 1;\n-\tuint64_t qint_idx : 6;\n-\tuint64_t gbl_rsvd2 : 1;\n-\tuint64_t sq_int : 8;\n-\tuint64_t sq_int_ena : 8;\n-\tuint64_t xoff : 1;\n-\tuint64_t sqe_stype : 2;\n-\tuint64_t gbl_rsvd : 17;\n-\tuint64_t head_sqb : 64;/* W2 */\n-\tuint64_t head_offset : 6;\n-\tuint64_t sqb_dequeue_count : 16;\n-\tuint64_t default_chan : 12;\n-\tuint64_t sdp_mcast : 1;\n-\tuint64_t sso_ena : 1;\n-\tuint64_t dse_rsvd1 : 28;\n-\tuint64_t sqb_enqueue_count : 16;\n-\tuint64_t tail_offset : 6;\n-\tuint64_t lmt_dis : 1;\n-\tuint64_t smq_rr_quantum : 24;\n-\tuint64_t dnq_rsvd1 : 17;\n-\tuint64_t tail_sqb : 64;/* W5 */\n-\tuint64_t next_sqb : 64;/* W6 */\n-\tuint64_t mnq_dis : 1;\n-\tuint64_t smq : 9;\n-\tuint64_t smq_pend : 1;\n-\tuint64_t smq_next_sq : 20;\n-\tuint64_t smq_next_sq_vld : 1;\n-\tuint64_t scm1_rsvd2 : 32;\n-\tuint64_t smenq_sqb : 64;/* W8 */\n-\tuint64_t smenq_offset : 6;\n-\tuint64_t cq_limit : 8;\n-\tuint64_t smq_rr_count : 25;\n-\tuint64_t scm_lso_rem : 18;\n-\tuint64_t scm_dq_rsvd0 : 7;\n-\tuint64_t smq_lso_segnum : 8;\n-\tuint64_t vfi_lso_total : 18;\n-\tuint64_t vfi_lso_sizem1 : 3;\n-\tuint64_t vfi_lso_sb : 8;\n-\tuint64_t vfi_lso_mps : 14;\n-\tuint64_t vfi_lso_vlan0_ins_ena : 1;\n-\tuint64_t vfi_lso_vlan1_ins_ena : 1;\n-\tuint64_t vfi_lso_vld : 1;\n-\tuint64_t smenq_next_sqb_vld : 1;\n-\tuint64_t scm_dq_rsvd1 : 9;\n-\tuint64_t smenq_next_sqb : 64;/* W11 */\n-\tuint64_t seb_rsvd1 : 64;/* W12 */\n-\tuint64_t drop_pkts : 48;\n-\tuint64_t drop_octs_lsw : 16;\n-\tuint64_t drop_octs_msw : 32;\n-\tuint64_t pkts_lsw : 32;\n-\tuint64_t pkts_msw : 16;\n-\tuint64_t octs : 48;\n-};\n-\n-/* NIX send queue context structure */\n-struct nix_sq_ctx_s {\n-\tuint64_t ena : 1;\n-\tuint64_t qint_idx : 6;\n-\tuint64_t substream : 20;\n-\tuint64_t sdp_mcast : 1;\n-\tuint64_t cq : 20;\n-\tuint64_t sqe_way_mask : 16;\n-\tuint64_t smq : 9;\n-\tuint64_t cq_ena : 1;\n-\tuint64_t xoff : 1;\n-\tuint64_t sso_ena : 1;\n-\tuint64_t smq_rr_quantum : 24;\n-\tuint64_t default_chan : 12;\n-\tuint64_t sqb_count : 16;\n-\tuint64_t smq_rr_count : 25;\n-\tuint64_t sqb_aura : 20;\n-\tuint64_t sq_int : 8;\n-\tuint64_t sq_int_ena : 8;\n-\tuint64_t sqe_stype : 2;\n-\tuint64_t rsvd_191 : 1;\n-\tuint64_t max_sqe_size : 2;\n-\tuint64_t cq_limit : 8;\n-\tuint64_t lmt_dis : 1;\n-\tuint64_t mnq_dis : 1;\n-\tuint64_t smq_next_sq : 20;\n-\tuint64_t smq_lso_segnum : 8;\n-\tuint64_t tail_offset : 6;\n-\tuint64_t smenq_offset : 6;\n-\tuint64_t head_offset : 6;\n-\tuint64_t smenq_next_sqb_vld : 1;\n-\tuint64_t smq_pend : 1;\n-\tuint64_t smq_next_sq_vld : 1;\n-\tuint64_t rsvd_255_253 : 3;\n-\tuint64_t next_sqb : 64;/* W4 */\n-\tuint64_t tail_sqb : 64;/* W5 */\n-\tuint64_t smenq_sqb : 64;/* W6 */\n-\tuint64_t smenq_next_sqb : 64;/* W7 */\n-\tuint64_t head_sqb : 64;/* W8 */\n-\tuint64_t rsvd_583_576 : 8;\n-\tuint64_t vfi_lso_total : 18;\n-\tuint64_t vfi_lso_sizem1 : 3;\n-\tuint64_t vfi_lso_sb : 8;\n-\tuint64_t vfi_lso_mps : 14;\n-\tuint64_t vfi_lso_vlan0_ins_ena : 1;\n-\tuint64_t vfi_lso_vlan1_ins_ena : 1;\n-\tuint64_t vfi_lso_vld : 1;\n-\tuint64_t rsvd_639_630 : 10;\n-\tuint64_t scm_lso_rem : 18;\n-\tuint64_t rsvd_703_658 : 46;\n-\tuint64_t octs : 48;\n-\tuint64_t rsvd_767_752 : 16;\n-\tuint64_t pkts : 48;\n-\tuint64_t rsvd_831_816 : 16;\n-\tuint64_t rsvd_895_832 : 64;/* W13 */\n-\tuint64_t drop_octs : 48;\n-\tuint64_t rsvd_959_944 : 16;\n-\tuint64_t drop_pkts : 48;\n-\tuint64_t rsvd_1023_1008 : 16;\n-};\n-\n-/* NIX transmit action structure */\n-struct nix_tx_action_s {\n-\tuint64_t op : 4;\n-\tuint64_t rsvd_11_4 : 8;\n-\tuint64_t index : 20;\n-\tuint64_t match_id : 16;\n-\tuint64_t rsvd_63_48 : 16;\n-};\n-\n-/* NIX transmit vtag action structure */\n-struct nix_tx_vtag_action_s {\n-\tuint64_t vtag0_relptr : 8;\n-\tuint64_t vtag0_lid : 3;\n-\tuint64_t rsvd_11 : 1;\n-\tuint64_t vtag0_op : 2;\n-\tuint64_t rsvd_15_14 : 2;\n-\tuint64_t vtag0_def : 10;\n-\tuint64_t rsvd_31_26 : 6;\n-\tuint64_t vtag1_relptr : 8;\n-\tuint64_t vtag1_lid : 3;\n-\tuint64_t rsvd_43 : 1;\n-\tuint64_t vtag1_op : 2;\n-\tuint64_t rsvd_47_46 : 2;\n-\tuint64_t vtag1_def : 10;\n-\tuint64_t rsvd_63_58 : 6;\n-};\n-\n-/* NIX work queue entry header structure */\n-struct nix_wqe_hdr_s {\n-\tuint64_t tag : 32;\n-\tuint64_t tt : 2;\n-\tuint64_t grp : 10;\n-\tuint64_t node : 2;\n-\tuint64_t q : 14;\n-\tuint64_t wqe_type : 4;\n-};\n-\n-/* NIX Rx flow key algorithm field structure */\n-struct nix_rx_flowkey_alg {\n-\tuint64_t key_offset :6;\n-\tuint64_t ln_mask :1;\n-\tuint64_t fn_mask :1;\n-\tuint64_t hdr_offset :8;\n-\tuint64_t bytesm1 :5;\n-\tuint64_t lid :3;\n-\tuint64_t reserved_24_24 :1;\n-\tuint64_t ena :1;\n-\tuint64_t sel_chan :1;\n-\tuint64_t ltype_mask :4;\n-\tuint64_t ltype_match :4;\n-\tuint64_t reserved_35_63 :29;\n-};\n-\n-/* NIX LSO format field structure */\n-struct nix_lso_format {\n-\tuint64_t offset : 8;\n-\tuint64_t layer : 2;\n-\tuint64_t rsvd_10_11 : 2;\n-\tuint64_t sizem1 : 2;\n-\tuint64_t rsvd_14_15 : 2;\n-\tuint64_t alg : 3;\n-\tuint64_t rsvd_19_63 : 45;\n-};\n-\n-#define NIX_LSO_FIELD_MAX\t(8)\n-#define NIX_LSO_FIELD_ALG_MASK\tGENMASK(18, 16)\n-#define NIX_LSO_FIELD_SZ_MASK\tGENMASK(13, 12)\n-#define NIX_LSO_FIELD_LY_MASK\tGENMASK(9, 8)\n-#define NIX_LSO_FIELD_OFF_MASK\tGENMASK(7, 0)\n-\n-#define NIX_LSO_FIELD_MASK\t\t\t\\\n-\t\t(NIX_LSO_FIELD_OFF_MASK |\t\\\n-\t\t NIX_LSO_FIELD_LY_MASK |\t\\\n-\t\t NIX_LSO_FIELD_SZ_MASK |\t\\\n-\t\t NIX_LSO_FIELD_ALG_MASK)\n-\n-#endif /* __OTX2_NIX_HW_H__ */\ndiff --git a/drivers/common/octeontx2/hw/otx2_npa.h b/drivers/common/octeontx2/hw/otx2_npa.h\ndeleted file mode 100644\nindex 2224216c96..0000000000\n--- a/drivers/common/octeontx2/hw/otx2_npa.h\n+++ /dev/null\n@@ -1,305 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_NPA_HW_H__\n-#define __OTX2_NPA_HW_H__\n-\n-/* Register offsets */\n-\n-#define NPA_AF_BLK_RST (0x0ull)\n-#define NPA_AF_CONST (0x10ull)\n-#define NPA_AF_CONST1 (0x18ull)\n-#define NPA_AF_LF_RST (0x20ull)\n-#define NPA_AF_GEN_CFG (0x30ull)\n-#define NPA_AF_NDC_CFG (0x40ull)\n-#define NPA_AF_NDC_SYNC (0x50ull)\n-#define NPA_AF_INP_CTL (0xd0ull)\n-#define NPA_AF_ACTIVE_CYCLES_PC (0xf0ull)\n-#define NPA_AF_AVG_DELAY (0x100ull)\n-#define NPA_AF_GEN_INT (0x140ull)\n-#define NPA_AF_GEN_INT_W1S (0x148ull)\n-#define NPA_AF_GEN_INT_ENA_W1S (0x150ull)\n-#define NPA_AF_GEN_INT_ENA_W1C (0x158ull)\n-#define NPA_AF_RVU_INT (0x160ull)\n-#define NPA_AF_RVU_INT_W1S (0x168ull)\n-#define NPA_AF_RVU_INT_ENA_W1S (0x170ull)\n-#define NPA_AF_RVU_INT_ENA_W1C (0x178ull)\n-#define NPA_AF_ERR_INT (0x180ull)\n-#define NPA_AF_ERR_INT_W1S (0x188ull)\n-#define NPA_AF_ERR_INT_ENA_W1S (0x190ull)\n-#define NPA_AF_ERR_INT_ENA_W1C (0x198ull)\n-#define NPA_AF_RAS (0x1a0ull)\n-#define NPA_AF_RAS_W1S (0x1a8ull)\n-#define NPA_AF_RAS_ENA_W1S (0x1b0ull)\n-#define NPA_AF_RAS_ENA_W1C (0x1b8ull)\n-#define NPA_AF_AQ_CFG (0x600ull)\n-#define NPA_AF_AQ_BASE (0x610ull)\n-#define NPA_AF_AQ_STATUS (0x620ull)\n-#define NPA_AF_AQ_DOOR (0x630ull)\n-#define NPA_AF_AQ_DONE_WAIT (0x640ull)\n-#define NPA_AF_AQ_DONE (0x650ull)\n-#define NPA_AF_AQ_DONE_ACK (0x660ull)\n-#define NPA_AF_AQ_DONE_TIMER (0x670ull)\n-#define NPA_AF_AQ_DONE_INT (0x680ull)\n-#define NPA_AF_AQ_DONE_ENA_W1S (0x690ull)\n-#define NPA_AF_AQ_DONE_ENA_W1C (0x698ull)\n-#define NPA_AF_LFX_AURAS_CFG(a) (0x4000ull | (uint64_t)(a) << 18)\n-#define NPA_AF_LFX_LOC_AURAS_BASE(a) (0x4010ull | (uint64_t)(a) << 18)\n-#define NPA_AF_LFX_QINTS_CFG(a) (0x4100ull | (uint64_t)(a) << 18)\n-#define NPA_AF_LFX_QINTS_BASE(a) (0x4110ull | (uint64_t)(a) << 18)\n-#define NPA_PRIV_AF_INT_CFG (0x10000ull)\n-#define NPA_PRIV_LFX_CFG(a) (0x10010ull | (uint64_t)(a) << 8)\n-#define NPA_PRIV_LFX_INT_CFG(a) (0x10020ull | (uint64_t)(a) << 8)\n-#define NPA_AF_RVU_LF_CFG_DEBUG (0x10030ull)\n-#define NPA_AF_DTX_FILTER_CTL (0x10040ull)\n-\n-#define NPA_LF_AURA_OP_ALLOCX(a) (0x10ull | (uint64_t)(a) << 3)\n-#define NPA_LF_AURA_OP_FREE0 (0x20ull)\n-#define NPA_LF_AURA_OP_FREE1 (0x28ull)\n-#define NPA_LF_AURA_OP_CNT (0x30ull)\n-#define NPA_LF_AURA_OP_LIMIT (0x50ull)\n-#define NPA_LF_AURA_OP_INT (0x60ull)\n-#define NPA_LF_AURA_OP_THRESH (0x70ull)\n-#define NPA_LF_POOL_OP_PC (0x100ull)\n-#define NPA_LF_POOL_OP_AVAILABLE (0x110ull)\n-#define NPA_LF_POOL_OP_PTR_START0 (0x120ull)\n-#define NPA_LF_POOL_OP_PTR_START1 (0x128ull)\n-#define NPA_LF_POOL_OP_PTR_END0 (0x130ull)\n-#define NPA_LF_POOL_OP_PTR_END1 (0x138ull)\n-#define NPA_LF_POOL_OP_INT (0x160ull)\n-#define NPA_LF_POOL_OP_THRESH (0x170ull)\n-#define NPA_LF_ERR_INT (0x200ull)\n-#define NPA_LF_ERR_INT_W1S (0x208ull)\n-#define NPA_LF_ERR_INT_ENA_W1C (0x210ull)\n-#define NPA_LF_ERR_INT_ENA_W1S (0x218ull)\n-#define NPA_LF_RAS (0x220ull)\n-#define NPA_LF_RAS_W1S (0x228ull)\n-#define NPA_LF_RAS_ENA_W1C (0x230ull)\n-#define NPA_LF_RAS_ENA_W1S (0x238ull)\n-#define NPA_LF_QINTX_CNT(a) (0x300ull | (uint64_t)(a) << 12)\n-#define NPA_LF_QINTX_INT(a) (0x310ull | (uint64_t)(a) << 12)\n-#define NPA_LF_QINTX_ENA_W1S(a) (0x320ull | (uint64_t)(a) << 12)\n-#define NPA_LF_QINTX_ENA_W1C(a) (0x330ull | (uint64_t)(a) << 12)\n-\n-\n-/* Enum offsets */\n-\n-#define NPA_AQ_COMP_NOTDONE (0x0ull)\n-#define NPA_AQ_COMP_GOOD (0x1ull)\n-#define NPA_AQ_COMP_SWERR (0x2ull)\n-#define NPA_AQ_COMP_CTX_POISON (0x3ull)\n-#define NPA_AQ_COMP_CTX_FAULT (0x4ull)\n-#define NPA_AQ_COMP_LOCKERR (0x5ull)\n-\n-#define NPA_AF_INT_VEC_RVU (0x0ull)\n-#define NPA_AF_INT_VEC_GEN (0x1ull)\n-#define NPA_AF_INT_VEC_AQ_DONE (0x2ull)\n-#define NPA_AF_INT_VEC_AF_ERR (0x3ull)\n-#define NPA_AF_INT_VEC_POISON (0x4ull)\n-\n-#define NPA_AQ_INSTOP_NOP (0x0ull)\n-#define NPA_AQ_INSTOP_INIT (0x1ull)\n-#define NPA_AQ_INSTOP_WRITE (0x2ull)\n-#define NPA_AQ_INSTOP_READ (0x3ull)\n-#define NPA_AQ_INSTOP_LOCK (0x4ull)\n-#define NPA_AQ_INSTOP_UNLOCK (0x5ull)\n-\n-#define NPA_AQ_CTYPE_AURA (0x0ull)\n-#define NPA_AQ_CTYPE_POOL (0x1ull)\n-\n-#define NPA_BPINTF_NIX0_RX (0x0ull)\n-#define NPA_BPINTF_NIX1_RX (0x1ull)\n-\n-#define NPA_AURA_ERR_INT_AURA_FREE_UNDER (0x0ull)\n-#define NPA_AURA_ERR_INT_AURA_ADD_OVER (0x1ull)\n-#define NPA_AURA_ERR_INT_AURA_ADD_UNDER (0x2ull)\n-#define NPA_AURA_ERR_INT_POOL_DIS (0x3ull)\n-#define NPA_AURA_ERR_INT_R4 (0x4ull)\n-#define NPA_AURA_ERR_INT_R5 (0x5ull)\n-#define NPA_AURA_ERR_INT_R6 (0x6ull)\n-#define NPA_AURA_ERR_INT_R7 (0x7ull)\n-\n-#define NPA_LF_INT_VEC_ERR_INT (0x40ull)\n-#define NPA_LF_INT_VEC_POISON (0x41ull)\n-#define NPA_LF_INT_VEC_QINT_END (0x3full)\n-#define NPA_LF_INT_VEC_QINT_START (0x0ull)\n-\n-#define NPA_INPQ_SSO (0x4ull)\n-#define NPA_INPQ_TIM (0x5ull)\n-#define NPA_INPQ_DPI (0x6ull)\n-#define NPA_INPQ_AURA_OP (0xeull)\n-#define NPA_INPQ_INTERNAL_RSV (0xfull)\n-#define NPA_INPQ_NIX0_RX (0x0ull)\n-#define NPA_INPQ_NIX1_RX (0x2ull)\n-#define NPA_INPQ_NIX0_TX (0x1ull)\n-#define NPA_INPQ_NIX1_TX (0x3ull)\n-#define NPA_INPQ_R_END (0xdull)\n-#define NPA_INPQ_R_START (0x7ull)\n-\n-#define NPA_POOL_ERR_INT_OVFLS (0x0ull)\n-#define NPA_POOL_ERR_INT_RANGE (0x1ull)\n-#define NPA_POOL_ERR_INT_PERR (0x2ull)\n-#define NPA_POOL_ERR_INT_R3 (0x3ull)\n-#define NPA_POOL_ERR_INT_R4 (0x4ull)\n-#define NPA_POOL_ERR_INT_R5 (0x5ull)\n-#define NPA_POOL_ERR_INT_R6 (0x6ull)\n-#define NPA_POOL_ERR_INT_R7 (0x7ull)\n-\n-#define NPA_NDC0_PORT_AURA0 (0x0ull)\n-#define NPA_NDC0_PORT_AURA1 (0x1ull)\n-#define NPA_NDC0_PORT_POOL0 (0x2ull)\n-#define NPA_NDC0_PORT_POOL1 (0x3ull)\n-#define NPA_NDC0_PORT_STACK0 (0x4ull)\n-#define NPA_NDC0_PORT_STACK1 (0x5ull)\n-\n-#define NPA_LF_ERR_INT_AURA_DIS (0x0ull)\n-#define NPA_LF_ERR_INT_AURA_OOR (0x1ull)\n-#define NPA_LF_ERR_INT_AURA_FAULT (0xcull)\n-#define NPA_LF_ERR_INT_POOL_FAULT (0xdull)\n-#define NPA_LF_ERR_INT_STACK_FAULT (0xeull)\n-#define NPA_LF_ERR_INT_QINT_FAULT (0xfull)\n-\n-/* Structures definitions */\n-\n-/* NPA admin queue instruction structure */\n-struct npa_aq_inst_s {\n-\tuint64_t op : 4;\n-\tuint64_t ctype : 4;\n-\tuint64_t lf : 9;\n-\tuint64_t rsvd_23_17 : 7;\n-\tuint64_t cindex : 20;\n-\tuint64_t rsvd_62_44 : 19;\n-\tuint64_t doneint : 1;\n-\tuint64_t res_addr : 64; /* W1 */\n-};\n-\n-/* NPA admin queue result structure */\n-struct npa_aq_res_s {\n-\tuint64_t op : 4;\n-\tuint64_t ctype : 4;\n-\tuint64_t compcode : 8;\n-\tuint64_t doneint : 1;\n-\tuint64_t rsvd_63_17 : 47;\n-\tuint64_t rsvd_127_64 : 64; /* W1 */\n-};\n-\n-/* NPA aura operation write data structure */\n-struct npa_aura_op_wdata_s {\n-\tuint64_t aura : 20;\n-\tuint64_t rsvd_62_20 : 43;\n-\tuint64_t drop : 1;\n-};\n-\n-/* NPA aura context structure */\n-struct npa_aura_s {\n-\tuint64_t pool_addr : 64;/* W0 */\n-\tuint64_t ena : 1;\n-\tuint64_t rsvd_66_65 : 2;\n-\tuint64_t pool_caching : 1;\n-\tuint64_t pool_way_mask : 16;\n-\tuint64_t avg_con : 9;\n-\tuint64_t rsvd_93 : 1;\n-\tuint64_t pool_drop_ena : 1;\n-\tuint64_t aura_drop_ena : 1;\n-\tuint64_t bp_ena : 2;\n-\tuint64_t rsvd_103_98 : 6;\n-\tuint64_t aura_drop : 8;\n-\tuint64_t shift : 6;\n-\tuint64_t rsvd_119_118 : 2;\n-\tuint64_t avg_level : 8;\n-\tuint64_t count : 36;\n-\tuint64_t rsvd_167_164 : 4;\n-\tuint64_t nix0_bpid : 9;\n-\tuint64_t rsvd_179_177 : 3;\n-\tuint64_t nix1_bpid : 9;\n-\tuint64_t rsvd_191_189 : 3;\n-\tuint64_t limit : 36;\n-\tuint64_t rsvd_231_228 : 4;\n-\tuint64_t bp : 8;\n-\tuint64_t rsvd_243_240 : 4;\n-\tuint64_t fc_ena : 1;\n-\tuint64_t fc_up_crossing : 1;\n-\tuint64_t fc_stype : 2;\n-\tuint64_t fc_hyst_bits : 4;\n-\tuint64_t rsvd_255_252 : 4;\n-\tuint64_t fc_addr : 64;/* W4 */\n-\tuint64_t pool_drop : 8;\n-\tuint64_t update_time : 16;\n-\tuint64_t err_int : 8;\n-\tuint64_t err_int_ena : 8;\n-\tuint64_t thresh_int : 1;\n-\tuint64_t thresh_int_ena : 1;\n-\tuint64_t thresh_up : 1;\n-\tuint64_t rsvd_363 : 1;\n-\tuint64_t thresh_qint_idx : 7;\n-\tuint64_t rsvd_371 : 1;\n-\tuint64_t err_qint_idx : 7;\n-\tuint64_t rsvd_383_379 : 5;\n-\tuint64_t thresh : 36;\n-\tuint64_t rsvd_447_420 : 28;\n-\tuint64_t rsvd_511_448 : 64;/* W7 */\n-};\n-\n-/* NPA pool context structure */\n-struct npa_pool_s {\n-\tuint64_t stack_base : 64;/* W0 */\n-\tuint64_t ena : 1;\n-\tuint64_t nat_align : 1;\n-\tuint64_t rsvd_67_66 : 2;\n-\tuint64_t stack_caching : 1;\n-\tuint64_t rsvd_71_69 : 3;\n-\tuint64_t stack_way_mask : 16;\n-\tuint64_t buf_offset : 12;\n-\tuint64_t rsvd_103_100 : 4;\n-\tuint64_t buf_size : 11;\n-\tuint64_t rsvd_127_115 : 13;\n-\tuint64_t stack_max_pages : 32;\n-\tuint64_t stack_pages : 32;\n-\tuint64_t op_pc : 48;\n-\tuint64_t rsvd_255_240 : 16;\n-\tuint64_t stack_offset : 4;\n-\tuint64_t rsvd_263_260 : 4;\n-\tuint64_t shift : 6;\n-\tuint64_t rsvd_271_270 : 2;\n-\tuint64_t avg_level : 8;\n-\tuint64_t avg_con : 9;\n-\tuint64_t fc_ena : 1;\n-\tuint64_t fc_stype : 2;\n-\tuint64_t fc_hyst_bits : 4;\n-\tuint64_t fc_up_crossing : 1;\n-\tuint64_t rsvd_299_297 : 3;\n-\tuint64_t update_time : 16;\n-\tuint64_t rsvd_319_316 : 4;\n-\tuint64_t fc_addr : 64;/* W5 */\n-\tuint64_t ptr_start : 64;/* W6 */\n-\tuint64_t ptr_end : 64;/* W7 */\n-\tuint64_t rsvd_535_512 : 24;\n-\tuint64_t err_int : 8;\n-\tuint64_t err_int_ena : 8;\n-\tuint64_t thresh_int : 1;\n-\tuint64_t thresh_int_ena : 1;\n-\tuint64_t thresh_up : 1;\n-\tuint64_t rsvd_555 : 1;\n-\tuint64_t thresh_qint_idx : 7;\n-\tuint64_t rsvd_563 : 1;\n-\tuint64_t err_qint_idx : 7;\n-\tuint64_t rsvd_575_571 : 5;\n-\tuint64_t thresh : 36;\n-\tuint64_t rsvd_639_612 : 28;\n-\tuint64_t rsvd_703_640 : 64;/* W10 */\n-\tuint64_t rsvd_767_704 : 64;/* W11 */\n-\tuint64_t rsvd_831_768 : 64;/* W12 */\n-\tuint64_t rsvd_895_832 : 64;/* W13 */\n-\tuint64_t rsvd_959_896 : 64;/* W14 */\n-\tuint64_t rsvd_1023_960 : 64;/* W15 */\n-};\n-\n-/* NPA queue interrupt context hardware structure */\n-struct npa_qint_hw_s {\n-\tuint32_t count : 22;\n-\tuint32_t rsvd_30_22 : 9;\n-\tuint32_t ena : 1;\n-};\n-\n-#endif /* __OTX2_NPA_HW_H__ */\ndiff --git a/drivers/common/octeontx2/hw/otx2_npc.h b/drivers/common/octeontx2/hw/otx2_npc.h\ndeleted file mode 100644\nindex b4e3c1eedc..0000000000\n--- a/drivers/common/octeontx2/hw/otx2_npc.h\n+++ /dev/null\n@@ -1,503 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_NPC_HW_H__\n-#define __OTX2_NPC_HW_H__\n-\n-/* Register offsets */\n-\n-#define NPC_AF_CFG (0x0ull)\n-#define NPC_AF_ACTIVE_PC (0x10ull)\n-#define NPC_AF_CONST (0x20ull)\n-#define NPC_AF_CONST1 (0x30ull)\n-#define NPC_AF_BLK_RST (0x40ull)\n-#define NPC_AF_MCAM_SCRUB_CTL (0xa0ull)\n-#define NPC_AF_KCAM_SCRUB_CTL (0xb0ull)\n-#define NPC_AF_KPUX_CFG(a) \\\n-\t(0x500ull | (uint64_t)(a) << 3)\n-#define NPC_AF_PCK_CFG (0x600ull)\n-#define NPC_AF_PCK_DEF_OL2 (0x610ull)\n-#define NPC_AF_PCK_DEF_OIP4 (0x620ull)\n-#define NPC_AF_PCK_DEF_OIP6 (0x630ull)\n-#define NPC_AF_PCK_DEF_IIP4 (0x640ull)\n-#define NPC_AF_KEX_LDATAX_FLAGS_CFG(a) \\\n-\t(0x800ull | (uint64_t)(a) << 3)\n-#define NPC_AF_INTFX_KEX_CFG(a) \\\n-\t(0x1010ull | (uint64_t)(a) << 8)\n-#define NPC_AF_PKINDX_ACTION0(a) \\\n-\t(0x80000ull | (uint64_t)(a) << 6)\n-#define NPC_AF_PKINDX_ACTION1(a) \\\n-\t(0x80008ull | (uint64_t)(a) << 6)\n-#define NPC_AF_PKINDX_CPI_DEFX(a, b) \\\n-\t(0x80020ull | (uint64_t)(a) << 6 | (uint64_t)(b) << 3)\n-#define NPC_AF_CHLEN90B_PKIND (0x3bull)\n-#define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \\\n-\t(0x100000ull | (uint64_t)(a) << 14 | (uint64_t)(b) << 6 | \\\n-\t(uint64_t)(c) << 3)\n-#define NPC_AF_KPUX_ENTRYX_ACTION0(a, b) \\\n-\t(0x100020ull | (uint64_t)(a) << 14 | (uint64_t)(b) << 6)\n-#define NPC_AF_KPUX_ENTRYX_ACTION1(a, b) \\\n-\t(0x100028ull | (uint64_t)(a) << 14 | (uint64_t)(b) << 6)\n-#define NPC_AF_KPUX_ENTRY_DISX(a, b) \\\n-\t(0x180000ull | (uint64_t)(a) << 6 | (uint64_t)(b) << 3)\n-#define NPC_AF_CPIX_CFG(a) \\\n-\t(0x200000ull | (uint64_t)(a) << 3)\n-#define NPC_AF_INTFX_LIDX_LTX_LDX_CFG(a, b, c, d) \\\n-\t(0x900000ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 12 | \\\n-\t(uint64_t)(c) << 5 | (uint64_t)(d) << 3)\n-#define NPC_AF_INTFX_LDATAX_FLAGSX_CFG(a, b, c) \\\n-\t(0x980000ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 12 | \\\n-\t(uint64_t)(c) << 3)\n-#define NPC_AF_MCAMEX_BANKX_CAMX_INTF(a, b, c) \\\n-\t(0x1000000ull | (uint64_t)(a) << 10 | (uint64_t)(b) << 6 | \\\n-\t(uint64_t)(c) << 3)\n-#define NPC_AF_MCAMEX_BANKX_CAMX_W0(a, b, c) \\\n-\t(0x1000010ull | (uint64_t)(a) << 10 | (uint64_t)(b) << 6 | \\\n-\t(uint64_t)(c) << 3)\n-#define NPC_AF_MCAMEX_BANKX_CAMX_W1(a, b, c) \\\n-\t(0x1000020ull | (uint64_t)(a) << 10 | (uint64_t)(b) << 6 | \\\n-\t(uint64_t)(c) << 3)\n-#define NPC_AF_MCAMEX_BANKX_CFG(a, b) \\\n-\t(0x1800000ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4)\n-#define NPC_AF_MCAMEX_BANKX_STAT_ACT(a, b) \\\n-\t(0x1880000ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4)\n-#define NPC_AF_MATCH_STATX(a) \\\n-\t(0x1880008ull | (uint64_t)(a) << 8)\n-#define NPC_AF_INTFX_MISS_STAT_ACT(a) \\\n-\t(0x1880040ull + (uint64_t)(a) * 0x8)\n-#define NPC_AF_MCAMEX_BANKX_ACTION(a, b) \\\n-\t(0x1900000ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4)\n-#define NPC_AF_MCAMEX_BANKX_TAG_ACT(a, b) \\\n-\t(0x1900008ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4)\n-#define NPC_AF_INTFX_MISS_ACT(a) \\\n-\t(0x1a00000ull | (uint64_t)(a) << 4)\n-#define NPC_AF_INTFX_MISS_TAG_ACT(a) \\\n-\t(0x1b00008ull | (uint64_t)(a) << 4)\n-#define NPC_AF_MCAM_BANKX_HITX(a, b) \\\n-\t(0x1c80000ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4)\n-#define NPC_AF_LKUP_CTL (0x2000000ull)\n-#define NPC_AF_LKUP_DATAX(a) \\\n-\t(0x2000200ull | (uint64_t)(a) << 4)\n-#define NPC_AF_LKUP_RESULTX(a) \\\n-\t(0x2000400ull | (uint64_t)(a) << 4)\n-#define NPC_AF_INTFX_STAT(a) \\\n-\t(0x2000800ull | (uint64_t)(a) << 4)\n-#define NPC_AF_DBG_CTL (0x3000000ull)\n-#define NPC_AF_DBG_STATUS (0x3000010ull)\n-#define NPC_AF_KPUX_DBG(a) \\\n-\t(0x3000020ull | (uint64_t)(a) << 8)\n-#define NPC_AF_IKPU_ERR_CTL (0x3000080ull)\n-#define NPC_AF_KPUX_ERR_CTL(a) \\\n-\t(0x30000a0ull | (uint64_t)(a) << 8)\n-#define NPC_AF_MCAM_DBG (0x3001000ull)\n-#define NPC_AF_DBG_DATAX(a) \\\n-\t(0x3001400ull | (uint64_t)(a) << 4)\n-#define NPC_AF_DBG_RESULTX(a) \\\n-\t(0x3001800ull | (uint64_t)(a) << 4)\n-\n-\n-/* Enum offsets */\n-\n-#define NPC_INTF_NIX0_RX (0x0ull)\n-#define NPC_INTF_NIX0_TX (0x1ull)\n-\n-#define NPC_LKUPOP_PKT (0x0ull)\n-#define NPC_LKUPOP_KEY (0x1ull)\n-\n-#define NPC_MCAM_KEY_X1 (0x0ull)\n-#define NPC_MCAM_KEY_X2 (0x1ull)\n-#define NPC_MCAM_KEY_X4 (0x2ull)\n-\n-enum NPC_ERRLEV_E {\n-\tNPC_ERRLEV_RE = 0,\n-\tNPC_ERRLEV_LA = 1,\n-\tNPC_ERRLEV_LB = 2,\n-\tNPC_ERRLEV_LC = 3,\n-\tNPC_ERRLEV_LD = 4,\n-\tNPC_ERRLEV_LE = 5,\n-\tNPC_ERRLEV_LF = 6,\n-\tNPC_ERRLEV_LG = 7,\n-\tNPC_ERRLEV_LH = 8,\n-\tNPC_ERRLEV_R9 = 9,\n-\tNPC_ERRLEV_R10 = 10,\n-\tNPC_ERRLEV_R11 = 11,\n-\tNPC_ERRLEV_R12 = 12,\n-\tNPC_ERRLEV_R13 = 13,\n-\tNPC_ERRLEV_R14 = 14,\n-\tNPC_ERRLEV_NIX = 15,\n-\tNPC_ERRLEV_ENUM_LAST = 16,\n-};\n-\n-enum npc_kpu_err_code {\n-\tNPC_EC_NOERR = 0, /* has to be zero */\n-\tNPC_EC_UNK,\n-\tNPC_EC_IH_LENGTH,\n-\tNPC_EC_EDSA_UNK,\n-\tNPC_EC_L2_K1,\n-\tNPC_EC_L2_K2,\n-\tNPC_EC_L2_K3,\n-\tNPC_EC_L2_K3_ETYPE_UNK,\n-\tNPC_EC_L2_K4,\n-\tNPC_EC_MPLS_2MANY,\n-\tNPC_EC_MPLS_UNK,\n-\tNPC_EC_NSH_UNK,\n-\tNPC_EC_IP_TTL_0,\n-\tNPC_EC_IP_FRAG_OFFSET_1,\n-\tNPC_EC_IP_VER,\n-\tNPC_EC_IP6_HOP_0,\n-\tNPC_EC_IP6_VER,\n-\tNPC_EC_TCP_FLAGS_FIN_ONLY,\n-\tNPC_EC_TCP_FLAGS_ZERO,\n-\tNPC_EC_TCP_FLAGS_RST_FIN,\n-\tNPC_EC_TCP_FLAGS_URG_SYN,\n-\tNPC_EC_TCP_FLAGS_RST_SYN,\n-\tNPC_EC_TCP_FLAGS_SYN_FIN,\n-\tNPC_EC_VXLAN,\n-\tNPC_EC_NVGRE,\n-\tNPC_EC_GRE,\n-\tNPC_EC_GRE_VER1,\n-\tNPC_EC_L4,\n-\tNPC_EC_OIP4_CSUM,\n-\tNPC_EC_IIP4_CSUM,\n-\tNPC_EC_LAST /* has to be the last item */\n-};\n-\n-enum NPC_LID_E {\n-\tNPC_LID_LA = 0,\n-\tNPC_LID_LB,\n-\tNPC_LID_LC,\n-\tNPC_LID_LD,\n-\tNPC_LID_LE,\n-\tNPC_LID_LF,\n-\tNPC_LID_LG,\n-\tNPC_LID_LH,\n-};\n-\n-#define NPC_LT_NA 0\n-\n-enum npc_kpu_la_ltype {\n-\tNPC_LT_LA_8023 = 1,\n-\tNPC_LT_LA_ETHER,\n-\tNPC_LT_LA_IH_NIX_ETHER,\n-\tNPC_LT_LA_IH_8_ETHER,\n-\tNPC_LT_LA_IH_4_ETHER,\n-\tNPC_LT_LA_IH_2_ETHER,\n-\tNPC_LT_LA_HIGIG2_ETHER,\n-\tNPC_LT_LA_IH_NIX_HIGIG2_ETHER,\n-\tNPC_LT_LA_CUSTOM_L2_90B_ETHER,\n-\tNPC_LT_LA_CPT_HDR,\n-\tNPC_LT_LA_CUSTOM_L2_24B_ETHER,\n-\tNPC_LT_LA_CUSTOM0 = 0xE,\n-\tNPC_LT_LA_CUSTOM1 = 0xF,\n-};\n-\n-enum npc_kpu_lb_ltype {\n-\tNPC_LT_LB_ETAG = 1,\n-\tNPC_LT_LB_CTAG,\n-\tNPC_LT_LB_STAG_QINQ,\n-\tNPC_LT_LB_BTAG,\n-\tNPC_LT_LB_ITAG,\n-\tNPC_LT_LB_DSA,\n-\tNPC_LT_LB_DSA_VLAN,\n-\tNPC_LT_LB_EDSA,\n-\tNPC_LT_LB_EDSA_VLAN,\n-\tNPC_LT_LB_EXDSA,\n-\tNPC_LT_LB_EXDSA_VLAN,\n-\tNPC_LT_LB_FDSA,\n-\tNPC_LT_LB_VLAN_EXDSA,\n-\tNPC_LT_LB_CUSTOM0 = 0xE,\n-\tNPC_LT_LB_CUSTOM1 = 0xF,\n-};\n-\n-enum npc_kpu_lc_ltype {\n-\tNPC_LT_LC_PTP = 1,\n-\tNPC_LT_LC_IP,\n-\tNPC_LT_LC_IP_OPT,\n-\tNPC_LT_LC_IP6,\n-\tNPC_LT_LC_IP6_EXT,\n-\tNPC_LT_LC_ARP,\n-\tNPC_LT_LC_RARP,\n-\tNPC_LT_LC_MPLS,\n-\tNPC_LT_LC_NSH,\n-\tNPC_LT_LC_FCOE,\n-\tNPC_LT_LC_NGIO,\n-\tNPC_LT_LC_CUSTOM0 = 0xE,\n-\tNPC_LT_LC_CUSTOM1 = 0xF,\n-};\n-\n-/* Don't modify Ltypes up to SCTP, otherwise it will\n- * effect flow tag calculation and thus RSS.\n- */\n-enum npc_kpu_ld_ltype {\n-\tNPC_LT_LD_TCP = 1,\n-\tNPC_LT_LD_UDP,\n-\tNPC_LT_LD_ICMP,\n-\tNPC_LT_LD_SCTP,\n-\tNPC_LT_LD_ICMP6,\n-\tNPC_LT_LD_CUSTOM0,\n-\tNPC_LT_LD_CUSTOM1,\n-\tNPC_LT_LD_IGMP = 8,\n-\tNPC_LT_LD_AH,\n-\tNPC_LT_LD_GRE,\n-\tNPC_LT_LD_NVGRE,\n-\tNPC_LT_LD_NSH,\n-\tNPC_LT_LD_TU_MPLS_IN_NSH,\n-\tNPC_LT_LD_TU_MPLS_IN_IP,\n-};\n-\n-enum npc_kpu_le_ltype {\n-\tNPC_LT_LE_VXLAN = 1,\n-\tNPC_LT_LE_GENEVE,\n-\tNPC_LT_LE_ESP,\n-\tNPC_LT_LE_GTPU = 4,\n-\tNPC_LT_LE_VXLANGPE,\n-\tNPC_LT_LE_GTPC,\n-\tNPC_LT_LE_NSH,\n-\tNPC_LT_LE_TU_MPLS_IN_GRE,\n-\tNPC_LT_LE_TU_NSH_IN_GRE,\n-\tNPC_LT_LE_TU_MPLS_IN_UDP,\n-\tNPC_LT_LE_CUSTOM0 = 0xE,\n-\tNPC_LT_LE_CUSTOM1 = 0xF,\n-};\n-\n-enum npc_kpu_lf_ltype {\n-\tNPC_LT_LF_TU_ETHER = 1,\n-\tNPC_LT_LF_TU_PPP,\n-\tNPC_LT_LF_TU_MPLS_IN_VXLANGPE,\n-\tNPC_LT_LF_TU_NSH_IN_VXLANGPE,\n-\tNPC_LT_LF_TU_MPLS_IN_NSH,\n-\tNPC_LT_LF_TU_3RD_NSH,\n-\tNPC_LT_LF_CUSTOM0 = 0xE,\n-\tNPC_LT_LF_CUSTOM1 = 0xF,\n-};\n-\n-enum npc_kpu_lg_ltype {\n-\tNPC_LT_LG_TU_IP = 1,\n-\tNPC_LT_LG_TU_IP6,\n-\tNPC_LT_LG_TU_ARP,\n-\tNPC_LT_LG_TU_ETHER_IN_NSH,\n-\tNPC_LT_LG_CUSTOM0 = 0xE,\n-\tNPC_LT_LG_CUSTOM1 = 0xF,\n-};\n-\n-/* Don't modify Ltypes up to SCTP, otherwise it will\n- * effect flow tag calculation and thus RSS.\n- */\n-enum npc_kpu_lh_ltype {\n-\tNPC_LT_LH_TU_TCP = 1,\n-\tNPC_LT_LH_TU_UDP,\n-\tNPC_LT_LH_TU_ICMP,\n-\tNPC_LT_LH_TU_SCTP,\n-\tNPC_LT_LH_TU_ICMP6,\n-\tNPC_LT_LH_TU_IGMP = 8,\n-\tNPC_LT_LH_TU_ESP,\n-\tNPC_LT_LH_TU_AH,\n-\tNPC_LT_LH_CUSTOM0 = 0xE,\n-\tNPC_LT_LH_CUSTOM1 = 0xF,\n-};\n-\n-/* Structures definitions */\n-struct npc_kpu_profile_cam {\n-\tuint8_t state;\n-\tuint8_t state_mask;\n-\tuint16_t dp0;\n-\tuint16_t dp0_mask;\n-\tuint16_t dp1;\n-\tuint16_t dp1_mask;\n-\tuint16_t dp2;\n-\tuint16_t dp2_mask;\n-};\n-\n-struct npc_kpu_profile_action {\n-\tuint8_t errlev;\n-\tuint8_t errcode;\n-\tuint8_t dp0_offset;\n-\tuint8_t dp1_offset;\n-\tuint8_t dp2_offset;\n-\tuint8_t bypass_count;\n-\tuint8_t parse_done;\n-\tuint8_t next_state;\n-\tuint8_t ptr_advance;\n-\tuint8_t cap_ena;\n-\tuint8_t lid;\n-\tuint8_t ltype;\n-\tuint8_t flags;\n-\tuint8_t offset;\n-\tuint8_t mask;\n-\tuint8_t right;\n-\tuint8_t shift;\n-};\n-\n-struct npc_kpu_profile {\n-\tint cam_entries;\n-\tint action_entries;\n-\tstruct npc_kpu_profile_cam *cam;\n-\tstruct npc_kpu_profile_action *action;\n-};\n-\n-/* NPC KPU register formats */\n-struct npc_kpu_cam {\n-\tuint64_t dp0_data : 16;\n-\tuint64_t dp1_data : 16;\n-\tuint64_t dp2_data : 16;\n-\tuint64_t state : 8;\n-\tuint64_t rsvd_63_56 : 8;\n-};\n-\n-struct npc_kpu_action0 {\n-\tuint64_t var_len_shift : 3;\n-\tuint64_t var_len_right : 1;\n-\tuint64_t var_len_mask : 8;\n-\tuint64_t var_len_offset : 8;\n-\tuint64_t ptr_advance : 8;\n-\tuint64_t capture_flags : 8;\n-\tuint64_t capture_ltype : 4;\n-\tuint64_t capture_lid : 3;\n-\tuint64_t rsvd_43 : 1;\n-\tuint64_t next_state : 8;\n-\tuint64_t parse_done : 1;\n-\tuint64_t capture_ena : 1;\n-\tuint64_t byp_count : 3;\n-\tuint64_t rsvd_63_57 : 7;\n-};\n-\n-struct npc_kpu_action1 {\n-\tuint64_t dp0_offset : 8;\n-\tuint64_t dp1_offset : 8;\n-\tuint64_t dp2_offset : 8;\n-\tuint64_t errcode : 8;\n-\tuint64_t errlev : 4;\n-\tuint64_t rsvd_63_36 : 28;\n-};\n-\n-struct npc_kpu_pkind_cpi_def {\n-\tuint64_t cpi_base : 10;\n-\tuint64_t rsvd_11_10 : 2;\n-\tuint64_t add_shift : 3;\n-\tuint64_t rsvd_15 : 1;\n-\tuint64_t add_mask : 8;\n-\tuint64_t add_offset : 8;\n-\tuint64_t flags_mask : 8;\n-\tuint64_t flags_match : 8;\n-\tuint64_t ltype_mask : 4;\n-\tuint64_t ltype_match : 4;\n-\tuint64_t lid : 3;\n-\tuint64_t rsvd_62_59 : 4;\n-\tuint64_t ena : 1;\n-};\n-\n-struct nix_rx_action {\n-\tuint64_t op :4;\n-\tuint64_t pf_func :16;\n-\tuint64_t index :20;\n-\tuint64_t match_id :16;\n-\tuint64_t flow_key_alg :5;\n-\tuint64_t rsvd_63_61 :3;\n-};\n-\n-struct nix_tx_action {\n-\tuint64_t\top\t\t:4;\n-\tuint64_t\trsvd_11_4\t:8;\n-\tuint64_t\tindex\t\t:20;\n-\tuint64_t\tmatch_id\t:16;\n-\tuint64_t\trsvd_63_48\t:16;\n-};\n-\n-/* NPC layer parse information structure */\n-struct npc_layer_info_s {\n-\tuint32_t lptr : 8;\n-\tuint32_t flags : 8;\n-\tuint32_t ltype : 4;\n-\tuint32_t rsvd_31_20 : 12;\n-};\n-\n-/* NPC layer mcam search key extract structure */\n-struct npc_layer_kex_s {\n-\tuint16_t flags : 8;\n-\tuint16_t ltype : 4;\n-\tuint16_t rsvd_15_12 : 4;\n-};\n-\n-/* NPC mcam search key x1 structure */\n-struct npc_mcam_key_x1_s {\n-\tuint64_t intf : 2;\n-\tuint64_t rsvd_63_2 : 62;\n-\tuint64_t kw0 : 64; /* W1 */\n-\tuint64_t kw1 : 48;\n-\tuint64_t rsvd_191_176 : 16;\n-};\n-\n-/* NPC mcam search key x2 structure */\n-struct npc_mcam_key_x2_s {\n-\tuint64_t intf : 2;\n-\tuint64_t rsvd_63_2 : 62;\n-\tuint64_t kw0 : 64; /* W1 */\n-\tuint64_t kw1 : 64; /* W2 */\n-\tuint64_t kw2 : 64; /* W3 */\n-\tuint64_t kw3 : 32;\n-\tuint64_t rsvd_319_288 : 32;\n-};\n-\n-/* NPC mcam search key x4 structure */\n-struct npc_mcam_key_x4_s {\n-\tuint64_t intf : 2;\n-\tuint64_t rsvd_63_2 : 62;\n-\tuint64_t kw0 : 64; /* W1 */\n-\tuint64_t kw1 : 64; /* W2 */\n-\tuint64_t kw2 : 64; /* W3 */\n-\tuint64_t kw3 : 64; /* W4 */\n-\tuint64_t kw4 : 64; /* W5 */\n-\tuint64_t kw5 : 64; /* W6 */\n-\tuint64_t kw6 : 64; /* W7 */\n-};\n-\n-/* NPC parse key extract structure */\n-struct npc_parse_kex_s {\n-\tuint64_t chan : 12;\n-\tuint64_t errlev : 4;\n-\tuint64_t errcode : 8;\n-\tuint64_t l2m : 1;\n-\tuint64_t l2b : 1;\n-\tuint64_t l3m : 1;\n-\tuint64_t l3b : 1;\n-\tuint64_t la : 12;\n-\tuint64_t lb : 12;\n-\tuint64_t lc : 12;\n-\tuint64_t ld : 12;\n-\tuint64_t le : 12;\n-\tuint64_t lf : 12;\n-\tuint64_t lg : 12;\n-\tuint64_t lh : 12;\n-\tuint64_t rsvd_127_124 : 4;\n-};\n-\n-/* NPC result structure */\n-struct npc_result_s {\n-\tuint64_t intf : 2;\n-\tuint64_t pkind : 6;\n-\tuint64_t chan : 12;\n-\tuint64_t errlev : 4;\n-\tuint64_t errcode : 8;\n-\tuint64_t l2m : 1;\n-\tuint64_t l2b : 1;\n-\tuint64_t l3m : 1;\n-\tuint64_t l3b : 1;\n-\tuint64_t eoh_ptr : 8;\n-\tuint64_t rsvd_63_44 : 20;\n-\tuint64_t action : 64; /* W1 */\n-\tuint64_t vtag_action : 64; /* W2 */\n-\tuint64_t la : 20;\n-\tuint64_t lb : 20;\n-\tuint64_t lc : 20;\n-\tuint64_t rsvd_255_252 : 4;\n-\tuint64_t ld : 20;\n-\tuint64_t le : 20;\n-\tuint64_t lf : 20;\n-\tuint64_t rsvd_319_316 : 4;\n-\tuint64_t lg : 20;\n-\tuint64_t lh : 20;\n-\tuint64_t rsvd_383_360 : 24;\n-};\n-\n-#endif /* __OTX2_NPC_HW_H__ */\ndiff --git a/drivers/common/octeontx2/hw/otx2_ree.h b/drivers/common/octeontx2/hw/otx2_ree.h\ndeleted file mode 100644\nindex b7481f125f..0000000000\n--- a/drivers/common/octeontx2/hw/otx2_ree.h\n+++ /dev/null\n@@ -1,27 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_REE_HW_H__\n-#define __OTX2_REE_HW_H__\n-\n-/* REE BAR0*/\n-#define REE_AF_REEXM_MAX_MATCH\t\t(0x80c8)\n-\n-/* REE BAR02 */\n-#define REE_LF_MISC_INT (0x300)\n-#define REE_LF_DONE_INT (0x120)\n-\n-#define REE_AF_QUEX_GMCTL(a) (0x800 | (a) << 3)\n-\n-#define REE_AF_INT_VEC_RAS (0x0ull)\n-#define REE_AF_INT_VEC_RVU (0x1ull)\n-#define REE_AF_INT_VEC_QUE_DONE (0x2ull)\n-#define REE_AF_INT_VEC_AQ (0x3ull)\n-\n-/* ENUMS */\n-\n-#define REE_LF_INT_VEC_QUE_DONE\t(0x0ull)\n-#define REE_LF_INT_VEC_MISC\t\t(0x1ull)\n-\n-#endif /* __OTX2_REE_HW_H__*/\ndiff --git a/drivers/common/octeontx2/hw/otx2_rvu.h b/drivers/common/octeontx2/hw/otx2_rvu.h\ndeleted file mode 100644\nindex b98dbcb1cd..0000000000\n--- a/drivers/common/octeontx2/hw/otx2_rvu.h\n+++ /dev/null\n@@ -1,219 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_RVU_HW_H__\n-#define __OTX2_RVU_HW_H__\n-\n-/* Register offsets */\n-\n-#define RVU_AF_MSIXTR_BASE (0x10ull)\n-#define RVU_AF_BLK_RST (0x30ull)\n-#define RVU_AF_PF_BAR4_ADDR (0x40ull)\n-#define RVU_AF_RAS (0x100ull)\n-#define RVU_AF_RAS_W1S (0x108ull)\n-#define RVU_AF_RAS_ENA_W1S (0x110ull)\n-#define RVU_AF_RAS_ENA_W1C (0x118ull)\n-#define RVU_AF_GEN_INT (0x120ull)\n-#define RVU_AF_GEN_INT_W1S (0x128ull)\n-#define RVU_AF_GEN_INT_ENA_W1S (0x130ull)\n-#define RVU_AF_GEN_INT_ENA_W1C (0x138ull)\n-#define RVU_AF_AFPFX_MBOXX(a, b) \\\n-\t(0x2000ull | (uint64_t)(a) << 4 | (uint64_t)(b) << 3)\n-#define RVU_AF_PFME_STATUS (0x2800ull)\n-#define RVU_AF_PFTRPEND (0x2810ull)\n-#define RVU_AF_PFTRPEND_W1S (0x2820ull)\n-#define RVU_AF_PF_RST (0x2840ull)\n-#define RVU_AF_HWVF_RST (0x2850ull)\n-#define RVU_AF_PFAF_MBOX_INT (0x2880ull)\n-#define RVU_AF_PFAF_MBOX_INT_W1S (0x2888ull)\n-#define RVU_AF_PFAF_MBOX_INT_ENA_W1S (0x2890ull)\n-#define RVU_AF_PFAF_MBOX_INT_ENA_W1C (0x2898ull)\n-#define RVU_AF_PFFLR_INT (0x28a0ull)\n-#define RVU_AF_PFFLR_INT_W1S (0x28a8ull)\n-#define RVU_AF_PFFLR_INT_ENA_W1S (0x28b0ull)\n-#define RVU_AF_PFFLR_INT_ENA_W1C (0x28b8ull)\n-#define RVU_AF_PFME_INT (0x28c0ull)\n-#define RVU_AF_PFME_INT_W1S (0x28c8ull)\n-#define RVU_AF_PFME_INT_ENA_W1S (0x28d0ull)\n-#define RVU_AF_PFME_INT_ENA_W1C (0x28d8ull)\n-#define RVU_PRIV_CONST (0x8000000ull)\n-#define RVU_PRIV_GEN_CFG (0x8000010ull)\n-#define RVU_PRIV_CLK_CFG (0x8000020ull)\n-#define RVU_PRIV_ACTIVE_PC (0x8000030ull)\n-#define RVU_PRIV_PFX_CFG(a) (0x8000100ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_PFX_MSIX_CFG(a) (0x8000110ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_PFX_ID_CFG(a) (0x8000120ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_PFX_INT_CFG(a) (0x8000200ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_PFX_NIXX_CFG(a, b) \\\n-\t(0x8000300ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3)\n-#define RVU_PRIV_PFX_NPA_CFG(a) (0x8000310ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_PFX_SSO_CFG(a) (0x8000320ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_PFX_SSOW_CFG(a) (0x8000330ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_PFX_TIM_CFG(a) (0x8000340ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_PFX_CPTX_CFG(a, b) \\\n-\t(0x8000350ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3)\n-#define RVU_PRIV_BLOCK_TYPEX_REV(a) (0x8000400ull | (uint64_t)(a) << 3)\n-#define RVU_PRIV_HWVFX_INT_CFG(a) (0x8001280ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_HWVFX_NIXX_CFG(a, b) \\\n-\t(0x8001300ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3)\n-#define RVU_PRIV_HWVFX_NPA_CFG(a) (0x8001310ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_HWVFX_SSO_CFG(a) (0x8001320ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_HWVFX_SSOW_CFG(a) (0x8001330ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_HWVFX_TIM_CFG(a) (0x8001340ull | (uint64_t)(a) << 16)\n-#define RVU_PRIV_HWVFX_CPTX_CFG(a, b) \\\n-\t(0x8001350ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3)\n-\n-#define RVU_PF_VFX_PFVF_MBOXX(a, b) \\\n-\t(0x0ull | (uint64_t)(a) << 12 | (uint64_t)(b) << 3)\n-#define RVU_PF_VF_BAR4_ADDR (0x10ull)\n-#define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFME_STATUSX(a) (0x800ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFTRPENDX(a) (0x820ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFTRPEND_W1SX(a) (0x840ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFPF_MBOX_INTX(a) (0x880ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8a0ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8c0ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8e0ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFFLR_INTX(a) (0x900ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFFLR_INT_W1SX(a) (0x920ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFME_INTX(a) (0x980ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFME_INT_W1SX(a) (0x9a0ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9c0ull | (uint64_t)(a) << 3)\n-#define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9e0ull | (uint64_t)(a) << 3)\n-#define RVU_PF_PFAF_MBOXX(a) (0xc00ull | (uint64_t)(a) << 3)\n-#define RVU_PF_INT (0xc20ull)\n-#define RVU_PF_INT_W1S (0xc28ull)\n-#define RVU_PF_INT_ENA_W1S (0xc30ull)\n-#define RVU_PF_INT_ENA_W1C (0xc38ull)\n-#define RVU_PF_MSIX_VECX_ADDR(a) (0x80000ull | (uint64_t)(a) << 4)\n-#define RVU_PF_MSIX_VECX_CTL(a) (0x80008ull | (uint64_t)(a) << 4)\n-#define RVU_PF_MSIX_PBAX(a) (0xf0000ull | (uint64_t)(a) << 3)\n-#define RVU_VF_VFPF_MBOXX(a) (0x0ull | (uint64_t)(a) << 3)\n-#define RVU_VF_INT (0x20ull)\n-#define RVU_VF_INT_W1S (0x28ull)\n-#define RVU_VF_INT_ENA_W1S (0x30ull)\n-#define RVU_VF_INT_ENA_W1C (0x38ull)\n-#define RVU_VF_BLOCK_ADDRX_DISC(a) (0x200ull | (uint64_t)(a) << 3)\n-#define RVU_VF_MSIX_VECX_ADDR(a) (0x80000ull | (uint64_t)(a) << 4)\n-#define RVU_VF_MSIX_VECX_CTL(a) (0x80008ull | (uint64_t)(a) << 4)\n-#define RVU_VF_MSIX_PBAX(a) (0xf0000ull | (uint64_t)(a) << 3)\n-\n-\n-/* Enum offsets */\n-\n-#define RVU_BAR_RVU_PF_END_BAR0 (0x84f000000000ull)\n-#define RVU_BAR_RVU_PF_START_BAR0 (0x840000000000ull)\n-#define RVU_BAR_RVU_PFX_FUNCX_BAR2(a, b) \\\n-\t(0x840200000000ull | ((uint64_t)(a) << 36) | ((uint64_t)(b) << 25))\n-\n-#define RVU_AF_INT_VEC_POISON (0x0ull)\n-#define RVU_AF_INT_VEC_PFFLR (0x1ull)\n-#define RVU_AF_INT_VEC_PFME (0x2ull)\n-#define RVU_AF_INT_VEC_GEN (0x3ull)\n-#define RVU_AF_INT_VEC_MBOX (0x4ull)\n-\n-#define RVU_BLOCK_TYPE_RVUM (0x0ull)\n-#define RVU_BLOCK_TYPE_LMT (0x2ull)\n-#define RVU_BLOCK_TYPE_NIX (0x3ull)\n-#define RVU_BLOCK_TYPE_NPA (0x4ull)\n-#define RVU_BLOCK_TYPE_NPC (0x5ull)\n-#define RVU_BLOCK_TYPE_SSO (0x6ull)\n-#define RVU_BLOCK_TYPE_SSOW (0x7ull)\n-#define RVU_BLOCK_TYPE_TIM (0x8ull)\n-#define RVU_BLOCK_TYPE_CPT (0x9ull)\n-#define RVU_BLOCK_TYPE_NDC (0xaull)\n-#define RVU_BLOCK_TYPE_DDF (0xbull)\n-#define RVU_BLOCK_TYPE_ZIP (0xcull)\n-#define RVU_BLOCK_TYPE_RAD (0xdull)\n-#define RVU_BLOCK_TYPE_DFA (0xeull)\n-#define RVU_BLOCK_TYPE_HNA (0xfull)\n-#define RVU_BLOCK_TYPE_REE (0xeull)\n-\n-#define RVU_BLOCK_ADDR_RVUM (0x0ull)\n-#define RVU_BLOCK_ADDR_LMT (0x1ull)\n-#define RVU_BLOCK_ADDR_NPA (0x3ull)\n-#define RVU_BLOCK_ADDR_NIX0 (0x4ull)\n-#define RVU_BLOCK_ADDR_NIX1 (0x5ull)\n-#define RVU_BLOCK_ADDR_NPC (0x6ull)\n-#define RVU_BLOCK_ADDR_SSO (0x7ull)\n-#define RVU_BLOCK_ADDR_SSOW (0x8ull)\n-#define RVU_BLOCK_ADDR_TIM (0x9ull)\n-#define RVU_BLOCK_ADDR_CPT0 (0xaull)\n-#define RVU_BLOCK_ADDR_CPT1 (0xbull)\n-#define RVU_BLOCK_ADDR_NDC0 (0xcull)\n-#define RVU_BLOCK_ADDR_NDC1 (0xdull)\n-#define RVU_BLOCK_ADDR_NDC2 (0xeull)\n-#define RVU_BLOCK_ADDR_R_END (0x1full)\n-#define RVU_BLOCK_ADDR_R_START (0x14ull)\n-#define RVU_BLOCK_ADDR_REE0 (0x14ull)\n-#define RVU_BLOCK_ADDR_REE1 (0x15ull)\n-\n-#define RVU_VF_INT_VEC_MBOX (0x0ull)\n-\n-#define RVU_PF_INT_VEC_AFPF_MBOX (0x6ull)\n-#define RVU_PF_INT_VEC_VFFLR0 (0x0ull)\n-#define RVU_PF_INT_VEC_VFFLR1 (0x1ull)\n-#define RVU_PF_INT_VEC_VFME0 (0x2ull)\n-#define RVU_PF_INT_VEC_VFME1 (0x3ull)\n-#define RVU_PF_INT_VEC_VFPF_MBOX0 (0x4ull)\n-#define RVU_PF_INT_VEC_VFPF_MBOX1 (0x5ull)\n-\n-\n-#define AF_BAR2_ALIASX_SIZE\t\t(0x100000ull)\n-\n-#define TIM_AF_BAR2_SEL\t\t\t(0x9000000ull)\n-#define SSO_AF_BAR2_SEL\t\t\t(0x9000000ull)\n-#define NIX_AF_BAR2_SEL\t\t\t(0x9000000ull)\n-#define SSOW_AF_BAR2_SEL\t\t(0x9000000ull)\n-#define NPA_AF_BAR2_SEL\t\t\t(0x9000000ull)\n-#define CPT_AF_BAR2_SEL\t\t\t(0x9000000ull)\n-#define RVU_AF_BAR2_SEL\t\t\t(0x9000000ull)\n-#define REE_AF_BAR2_SEL\t\t\t(0x9000000ull)\n-\n-#define AF_BAR2_ALIASX(a, b) \\\n-\t(0x9100000ull | (uint64_t)(a) << 12 | (uint64_t)(b))\n-#define TIM_AF_BAR2_ALIASX(a, b)\t\tAF_BAR2_ALIASX(a, b)\n-#define SSO_AF_BAR2_ALIASX(a, b)\t\tAF_BAR2_ALIASX(a, b)\n-#define NIX_AF_BAR2_ALIASX(a, b)\t\tAF_BAR2_ALIASX(0, b)\n-#define SSOW_AF_BAR2_ALIASX(a, b)\t\tAF_BAR2_ALIASX(a, b)\n-#define NPA_AF_BAR2_ALIASX(a, b)\t\tAF_BAR2_ALIASX(0, b)\n-#define CPT_AF_BAR2_ALIASX(a, b)\t\tAF_BAR2_ALIASX(a, b)\n-#define RVU_AF_BAR2_ALIASX(a, b)\t\tAF_BAR2_ALIASX(a, b)\n-#define REE_AF_BAR2_ALIASX(a, b)\t\tAF_BAR2_ALIASX(a, b)\n-\n-/* Structures definitions */\n-\n-/* RVU admin function register address structure */\n-struct rvu_af_addr_s {\n-\tuint64_t addr : 28;\n-\tuint64_t block : 5;\n-\tuint64_t rsvd_63_33 : 31;\n-};\n-\n-/* RVU function-unique address structure */\n-struct rvu_func_addr_s {\n-\tuint32_t addr : 12;\n-\tuint32_t lf_slot : 8;\n-\tuint32_t block : 5;\n-\tuint32_t rsvd_31_25 : 7;\n-};\n-\n-/* RVU msi-x vector structure */\n-struct rvu_msix_vec_s {\n-\tuint64_t addr : 64; /* W0 */\n-\tuint64_t data : 32;\n-\tuint64_t mask : 1;\n-\tuint64_t pend : 1;\n-\tuint64_t rsvd_127_98 : 30;\n-};\n-\n-/* RVU pf function identification structure */\n-struct rvu_pf_func_s {\n-\tuint16_t func : 10;\n-\tuint16_t pf : 6;\n-};\n-\n-#endif /* __OTX2_RVU_HW_H__ */\ndiff --git a/drivers/common/octeontx2/hw/otx2_sdp.h b/drivers/common/octeontx2/hw/otx2_sdp.h\ndeleted file mode 100644\nindex 1e690f8b32..0000000000\n--- a/drivers/common/octeontx2/hw/otx2_sdp.h\n+++ /dev/null\n@@ -1,184 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_SDP_HW_H_\n-#define __OTX2_SDP_HW_H_\n-\n-/* SDP VF IOQs */\n-#define SDP_MIN_RINGS_PER_VF (1)\n-#define SDP_MAX_RINGS_PER_VF (8)\n-\n-/* SDP VF IQ configuration */\n-#define SDP_VF_MAX_IQ_DESCRIPTORS (512)\n-#define SDP_VF_MIN_IQ_DESCRIPTORS (128)\n-\n-#define SDP_VF_DB_MIN (1)\n-#define SDP_VF_DB_TIMEOUT (1)\n-#define SDP_VF_INTR_THRESHOLD (0xFFFFFFFF)\n-\n-#define SDP_VF_64BYTE_INSTR (64)\n-#define SDP_VF_32BYTE_INSTR (32)\n-\n-/* SDP VF OQ configuration */\n-#define SDP_VF_MAX_OQ_DESCRIPTORS (512)\n-#define SDP_VF_MIN_OQ_DESCRIPTORS (128)\n-#define SDP_VF_OQ_BUF_SIZE (2048)\n-#define SDP_VF_OQ_REFIL_THRESHOLD (16)\n-\n-#define SDP_VF_OQ_INFOPTR_MODE (1)\n-#define SDP_VF_OQ_BUFPTR_MODE (0)\n-\n-#define SDP_VF_OQ_INTR_PKT (1)\n-#define SDP_VF_OQ_INTR_TIME (10)\n-#define SDP_VF_CFG_IO_QUEUES SDP_MAX_RINGS_PER_VF\n-\n-/* Wait time in milliseconds for FLR */\n-#define SDP_VF_PCI_FLR_WAIT (100)\n-#define SDP_VF_BUSY_LOOP_COUNT (10000)\n-\n-#define SDP_VF_MAX_IO_QUEUES SDP_MAX_RINGS_PER_VF\n-#define SDP_VF_MIN_IO_QUEUES SDP_MIN_RINGS_PER_VF\n-\n-/* SDP VF IOQs per rawdev */\n-#define SDP_VF_MAX_IOQS_PER_RAWDEV SDP_VF_MAX_IO_QUEUES\n-#define SDP_VF_DEFAULT_IOQS_PER_RAWDEV SDP_VF_MIN_IO_QUEUES\n-\n-/* SDP VF Register definitions */\n-#define SDP_VF_RING_OFFSET (0x1ull << 17)\n-\n-/* SDP VF IQ Registers */\n-#define SDP_VF_R_IN_CONTROL_START (0x10000)\n-#define SDP_VF_R_IN_ENABLE_START (0x10010)\n-#define SDP_VF_R_IN_INSTR_BADDR_START (0x10020)\n-#define SDP_VF_R_IN_INSTR_RSIZE_START (0x10030)\n-#define SDP_VF_R_IN_INSTR_DBELL_START (0x10040)\n-#define SDP_VF_R_IN_CNTS_START (0x10050)\n-#define SDP_VF_R_IN_INT_LEVELS_START (0x10060)\n-#define SDP_VF_R_IN_PKT_CNT_START (0x10080)\n-#define SDP_VF_R_IN_BYTE_CNT_START (0x10090)\n-\n-#define SDP_VF_R_IN_CONTROL(ring) \\\n-\t(SDP_VF_R_IN_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_IN_ENABLE(ring) \\\n-\t(SDP_VF_R_IN_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_IN_INSTR_BADDR(ring) \\\n-\t(SDP_VF_R_IN_INSTR_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_IN_INSTR_RSIZE(ring) \\\n-\t(SDP_VF_R_IN_INSTR_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_IN_INSTR_DBELL(ring) \\\n-\t(SDP_VF_R_IN_INSTR_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_IN_CNTS(ring) \\\n-\t(SDP_VF_R_IN_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_IN_INT_LEVELS(ring) \\\n-\t(SDP_VF_R_IN_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_IN_PKT_CNT(ring) \\\n-\t(SDP_VF_R_IN_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_IN_BYTE_CNT(ring) \\\n-\t(SDP_VF_R_IN_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-/* SDP VF IQ Masks */\n-#define SDP_VF_R_IN_CTL_RPVF_MASK (0xF)\n-#define\tSDP_VF_R_IN_CTL_RPVF_POS (48)\n-\n-#define SDP_VF_R_IN_CTL_IDLE (0x1ull << 28)\n-#define SDP_VF_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */\n-#define SDP_VF_R_IN_CTL_IS_64B (0x1ull << 24)\n-#define SDP_VF_R_IN_CTL_D_NSR (0x1ull << 8)\n-#define SDP_VF_R_IN_CTL_D_ESR (0x1ull << 6)\n-#define SDP_VF_R_IN_CTL_D_ROR (0x1ull << 5)\n-#define SDP_VF_R_IN_CTL_NSR (0x1ull << 3)\n-#define SDP_VF_R_IN_CTL_ESR (0x1ull << 1)\n-#define SDP_VF_R_IN_CTL_ROR (0x1ull << 0)\n-\n-#define SDP_VF_R_IN_CTL_MASK \\\n-\t(SDP_VF_R_IN_CTL_RDSIZE | SDP_VF_R_IN_CTL_IS_64B)\n-\n-/* SDP VF OQ Registers */\n-#define SDP_VF_R_OUT_CNTS_START (0x10100)\n-#define SDP_VF_R_OUT_INT_LEVELS_START (0x10110)\n-#define SDP_VF_R_OUT_SLIST_BADDR_START (0x10120)\n-#define SDP_VF_R_OUT_SLIST_RSIZE_START (0x10130)\n-#define SDP_VF_R_OUT_SLIST_DBELL_START (0x10140)\n-#define SDP_VF_R_OUT_CONTROL_START (0x10150)\n-#define SDP_VF_R_OUT_ENABLE_START (0x10160)\n-#define SDP_VF_R_OUT_PKT_CNT_START (0x10180)\n-#define SDP_VF_R_OUT_BYTE_CNT_START (0x10190)\n-\n-#define SDP_VF_R_OUT_CONTROL(ring) \\\n-\t(SDP_VF_R_OUT_CONTROL_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_OUT_ENABLE(ring) \\\n-\t(SDP_VF_R_OUT_ENABLE_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_OUT_SLIST_BADDR(ring) \\\n-\t(SDP_VF_R_OUT_SLIST_BADDR_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_OUT_SLIST_RSIZE(ring) \\\n-\t(SDP_VF_R_OUT_SLIST_RSIZE_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_OUT_SLIST_DBELL(ring) \\\n-\t(SDP_VF_R_OUT_SLIST_DBELL_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_OUT_CNTS(ring) \\\n-\t(SDP_VF_R_OUT_CNTS_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_OUT_INT_LEVELS(ring) \\\n-\t(SDP_VF_R_OUT_INT_LEVELS_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_OUT_PKT_CNT(ring) \\\n-\t(SDP_VF_R_OUT_PKT_CNT_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-#define SDP_VF_R_OUT_BYTE_CNT(ring) \\\n-\t(SDP_VF_R_OUT_BYTE_CNT_START + ((ring) * SDP_VF_RING_OFFSET))\n-\n-/* SDP VF OQ Masks */\n-#define SDP_VF_R_OUT_CTL_IDLE (1ull << 40)\n-#define SDP_VF_R_OUT_CTL_ES_I (1ull << 34)\n-#define SDP_VF_R_OUT_CTL_NSR_I (1ull << 33)\n-#define SDP_VF_R_OUT_CTL_ROR_I (1ull << 32)\n-#define SDP_VF_R_OUT_CTL_ES_D (1ull << 30)\n-#define SDP_VF_R_OUT_CTL_NSR_D (1ull << 29)\n-#define SDP_VF_R_OUT_CTL_ROR_D (1ull << 28)\n-#define SDP_VF_R_OUT_CTL_ES_P (1ull << 26)\n-#define SDP_VF_R_OUT_CTL_NSR_P (1ull << 25)\n-#define SDP_VF_R_OUT_CTL_ROR_P (1ull << 24)\n-#define SDP_VF_R_OUT_CTL_IMODE (1ull << 23)\n-\n-#define SDP_VF_R_OUT_INT_LEVELS_BMODE (1ull << 63)\n-#define SDP_VF_R_OUT_INT_LEVELS_TIMET (32)\n-\n-/* SDP Instruction Header */\n-struct sdp_instr_ih {\n-\t/* Data Len */\n-\tuint64_t tlen:16;\n-\n-\t/* Reserved1 */\n-\tuint64_t rsvd1:20;\n-\n-\t/* PKIND for SDP */\n-\tuint64_t pkind:6;\n-\n-\t/* Front Data size */\n-\tuint64_t fsz:6;\n-\n-\t/* No. of entries in gather list */\n-\tuint64_t gsz:14;\n-\n-\t/* Gather indicator */\n-\tuint64_t gather:1;\n-\n-\t/* Reserved2 */\n-\tuint64_t rsvd2:1;\n-} __rte_packed;\n-\n-#endif /* __OTX2_SDP_HW_H_ */\n-\ndiff --git a/drivers/common/octeontx2/hw/otx2_sso.h b/drivers/common/octeontx2/hw/otx2_sso.h\ndeleted file mode 100644\nindex 98a8130b16..0000000000\n--- a/drivers/common/octeontx2/hw/otx2_sso.h\n+++ /dev/null\n@@ -1,209 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_SSO_HW_H__\n-#define __OTX2_SSO_HW_H__\n-\n-/* Register offsets */\n-\n-#define SSO_AF_CONST (0x1000ull)\n-#define SSO_AF_CONST1 (0x1008ull)\n-#define SSO_AF_WQ_INT_PC (0x1020ull)\n-#define SSO_AF_NOS_CNT (0x1050ull)\n-#define SSO_AF_AW_WE (0x1080ull)\n-#define SSO_AF_WS_CFG (0x1088ull)\n-#define SSO_AF_GWE_CFG (0x1098ull)\n-#define SSO_AF_GWE_RANDOM (0x10b0ull)\n-#define SSO_AF_LF_HWGRP_RST (0x10e0ull)\n-#define SSO_AF_AW_CFG (0x10f0ull)\n-#define SSO_AF_BLK_RST (0x10f8ull)\n-#define SSO_AF_ACTIVE_CYCLES0 (0x1100ull)\n-#define SSO_AF_ACTIVE_CYCLES1 (0x1108ull)\n-#define SSO_AF_ACTIVE_CYCLES2 (0x1110ull)\n-#define SSO_AF_ERR0 (0x1220ull)\n-#define SSO_AF_ERR0_W1S (0x1228ull)\n-#define SSO_AF_ERR0_ENA_W1C (0x1230ull)\n-#define SSO_AF_ERR0_ENA_W1S (0x1238ull)\n-#define SSO_AF_ERR2 (0x1260ull)\n-#define SSO_AF_ERR2_W1S (0x1268ull)\n-#define SSO_AF_ERR2_ENA_W1C (0x1270ull)\n-#define SSO_AF_ERR2_ENA_W1S (0x1278ull)\n-#define SSO_AF_UNMAP_INFO (0x12f0ull)\n-#define SSO_AF_UNMAP_INFO2 (0x1300ull)\n-#define SSO_AF_UNMAP_INFO3 (0x1310ull)\n-#define SSO_AF_RAS (0x1420ull)\n-#define SSO_AF_RAS_W1S (0x1430ull)\n-#define SSO_AF_RAS_ENA_W1C (0x1460ull)\n-#define SSO_AF_RAS_ENA_W1S (0x1470ull)\n-#define SSO_AF_AW_INP_CTL (0x2070ull)\n-#define SSO_AF_AW_ADD (0x2080ull)\n-#define SSO_AF_AW_READ_ARB (0x2090ull)\n-#define SSO_AF_XAQ_REQ_PC (0x20b0ull)\n-#define SSO_AF_XAQ_LATENCY_PC (0x20b8ull)\n-#define SSO_AF_TAQ_CNT (0x20c0ull)\n-#define SSO_AF_TAQ_ADD (0x20e0ull)\n-#define SSO_AF_POISONX(a) (0x2100ull | (uint64_t)(a) << 3)\n-#define SSO_AF_POISONX_W1S(a) (0x2200ull | (uint64_t)(a) << 3)\n-#define SSO_PRIV_AF_INT_CFG (0x3000ull)\n-#define SSO_AF_RVU_LF_CFG_DEBUG (0x3800ull)\n-#define SSO_PRIV_LFX_HWGRP_CFG(a) (0x10000ull | (uint64_t)(a) << 3)\n-#define SSO_PRIV_LFX_HWGRP_INT_CFG(a) (0x20000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_IU_ACCNTX_CFG(a) (0x50000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_IU_ACCNTX_RST(a) (0x60000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_XAQX_HEAD_PTR(a) (0x80000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_XAQX_TAIL_PTR(a) (0x90000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_XAQX_HEAD_NEXT(a) (0xa0000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_XAQX_TAIL_NEXT(a) (0xb0000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_TIAQX_STATUS(a) (0xc0000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_TOAQX_STATUS(a) (0xd0000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_XAQX_GMCTL(a) (0xe0000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_HWGRPX_IAQ_THR(a) (0x200000ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_TAQ_THR(a) (0x200010ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_PRI(a) (0x200020ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_WS_PC(a) (0x200050ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_EXT_PC(a) (0x200060ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_WA_PC(a) (0x200070ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_TS_PC(a) (0x200080ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_DS_PC(a) (0x200090ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_DQ_PC(a) (0x2000A0ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_PAGE_CNT(a) (0x200100ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_AW_STATUS(a) (0x200110ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_AW_CFG(a) (0x200120ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_AW_TAGSPACE(a) (0x200130ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_XAQ_AURA(a) (0x200140ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_XAQ_LIMIT(a) (0x200220ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWGRPX_IU_ACCNT(a) (0x200230ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWSX_ARB(a) (0x400100ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWSX_INV(a) (0x400180ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWSX_GMCTL(a) (0x400200ull | (uint64_t)(a) << 12)\n-#define SSO_AF_HWSX_SX_GRPMSKX(a, b, c) \\\n-\t(0x400400ull | (uint64_t)(a) << 12 | (uint64_t)(b) << 5 | \\\n-\t(uint64_t)(c) << 3)\n-#define SSO_AF_IPL_FREEX(a) (0x800000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_IPL_IAQX(a) (0x840000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_IPL_DESCHEDX(a) (0x860000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_IPL_CONFX(a) (0x880000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_NPA_DIGESTX(a) (0x900000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_NPA_DIGESTX_W1S(a) (0x900100ull | (uint64_t)(a) << 3)\n-#define SSO_AF_BFP_DIGESTX(a) (0x900200ull | (uint64_t)(a) << 3)\n-#define SSO_AF_BFP_DIGESTX_W1S(a) (0x900300ull | (uint64_t)(a) << 3)\n-#define SSO_AF_BFPN_DIGESTX(a) (0x900400ull | (uint64_t)(a) << 3)\n-#define SSO_AF_BFPN_DIGESTX_W1S(a) (0x900500ull | (uint64_t)(a) << 3)\n-#define SSO_AF_GRPDIS_DIGESTX(a) (0x900600ull | (uint64_t)(a) << 3)\n-#define SSO_AF_GRPDIS_DIGESTX_W1S(a) (0x900700ull | (uint64_t)(a) << 3)\n-#define SSO_AF_AWEMPTY_DIGESTX(a) (0x900800ull | (uint64_t)(a) << 3)\n-#define SSO_AF_AWEMPTY_DIGESTX_W1S(a) (0x900900ull | (uint64_t)(a) << 3)\n-#define SSO_AF_WQP0_DIGESTX(a) (0x900a00ull | (uint64_t)(a) << 3)\n-#define SSO_AF_WQP0_DIGESTX_W1S(a) (0x900b00ull | (uint64_t)(a) << 3)\n-#define SSO_AF_AW_DROPPED_DIGESTX(a) (0x900c00ull | (uint64_t)(a) << 3)\n-#define SSO_AF_AW_DROPPED_DIGESTX_W1S(a) (0x900d00ull | (uint64_t)(a) << 3)\n-#define SSO_AF_QCTLDIS_DIGESTX(a) (0x900e00ull | (uint64_t)(a) << 3)\n-#define SSO_AF_QCTLDIS_DIGESTX_W1S(a) (0x900f00ull | (uint64_t)(a) << 3)\n-#define SSO_AF_XAQDIS_DIGESTX(a) (0x901000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_XAQDIS_DIGESTX_W1S(a) (0x901100ull | (uint64_t)(a) << 3)\n-#define SSO_AF_FLR_AQ_DIGESTX(a) (0x901200ull | (uint64_t)(a) << 3)\n-#define SSO_AF_FLR_AQ_DIGESTX_W1S(a) (0x901300ull | (uint64_t)(a) << 3)\n-#define SSO_AF_WS_GMULTI_DIGESTX(a) (0x902000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_WS_GMULTI_DIGESTX_W1S(a) (0x902100ull | (uint64_t)(a) << 3)\n-#define SSO_AF_WS_GUNMAP_DIGESTX(a) (0x902200ull | (uint64_t)(a) << 3)\n-#define SSO_AF_WS_GUNMAP_DIGESTX_W1S(a) (0x902300ull | (uint64_t)(a) << 3)\n-#define SSO_AF_WS_AWE_DIGESTX(a) (0x902400ull | (uint64_t)(a) << 3)\n-#define SSO_AF_WS_AWE_DIGESTX_W1S(a) (0x902500ull | (uint64_t)(a) << 3)\n-#define SSO_AF_WS_GWI_DIGESTX(a) (0x902600ull | (uint64_t)(a) << 3)\n-#define SSO_AF_WS_GWI_DIGESTX_W1S(a) (0x902700ull | (uint64_t)(a) << 3)\n-#define SSO_AF_WS_NE_DIGESTX(a) (0x902800ull | (uint64_t)(a) << 3)\n-#define SSO_AF_WS_NE_DIGESTX_W1S(a) (0x902900ull | (uint64_t)(a) << 3)\n-#define SSO_AF_IENTX_TAG(a) (0xa00000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_IENTX_GRP(a) (0xa20000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_IENTX_PENDTAG(a) (0xa40000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_IENTX_LINKS(a) (0xa60000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_IENTX_QLINKS(a) (0xa80000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_IENTX_WQP(a) (0xaa0000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_TAQX_LINK(a) (0xc00000ull | (uint64_t)(a) << 3)\n-#define SSO_AF_TAQX_WAEX_TAG(a, b) \\\n-\t(0xe00000ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4)\n-#define SSO_AF_TAQX_WAEX_WQP(a, b) \\\n-\t(0xe00008ull | (uint64_t)(a) << 8 | (uint64_t)(b) << 4)\n-\n-#define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull)\n-#define SSO_LF_GGRP_OP_ADD_WORK1 (0x8ull)\n-#define SSO_LF_GGRP_QCTL (0x20ull)\n-#define SSO_LF_GGRP_EXE_DIS (0x80ull)\n-#define SSO_LF_GGRP_INT (0x100ull)\n-#define SSO_LF_GGRP_INT_W1S (0x108ull)\n-#define SSO_LF_GGRP_INT_ENA_W1S (0x110ull)\n-#define SSO_LF_GGRP_INT_ENA_W1C (0x118ull)\n-#define SSO_LF_GGRP_INT_THR (0x140ull)\n-#define SSO_LF_GGRP_INT_CNT (0x180ull)\n-#define SSO_LF_GGRP_XAQ_CNT (0x1b0ull)\n-#define SSO_LF_GGRP_AQ_CNT (0x1c0ull)\n-#define SSO_LF_GGRP_AQ_THR (0x1e0ull)\n-#define SSO_LF_GGRP_MISC_CNT (0x200ull)\n-\n-#define SSO_AF_IAQ_FREE_CNT_MASK 0x3FFFull\n-#define SSO_AF_IAQ_RSVD_FREE_MASK 0x3FFFull\n-#define SSO_AF_IAQ_RSVD_FREE_SHIFT 16\n-#define SSO_AF_IAQ_FREE_CNT_MAX SSO_AF_IAQ_FREE_CNT_MASK\n-#define SSO_AF_AW_ADD_RSVD_FREE_MASK 0x3FFFull\n-#define SSO_AF_AW_ADD_RSVD_FREE_SHIFT 16\n-#define SSO_HWGRP_IAQ_MAX_THR_MASK 0x3FFFull\n-#define SSO_HWGRP_IAQ_RSVD_THR_MASK 0x3FFFull\n-#define SSO_HWGRP_IAQ_MAX_THR_SHIFT 32\n-#define SSO_HWGRP_IAQ_RSVD_THR 0x2\n-\n-#define SSO_AF_TAQ_FREE_CNT_MASK 0x7FFull\n-#define SSO_AF_TAQ_RSVD_FREE_MASK 0x7FFull\n-#define SSO_AF_TAQ_RSVD_FREE_SHIFT 16\n-#define SSO_AF_TAQ_FREE_CNT_MAX SSO_AF_TAQ_FREE_CNT_MASK\n-#define SSO_AF_TAQ_ADD_RSVD_FREE_MASK 0x1FFFull\n-#define SSO_AF_TAQ_ADD_RSVD_FREE_SHIFT 16\n-#define SSO_HWGRP_TAQ_MAX_THR_MASK 0x7FFull\n-#define SSO_HWGRP_TAQ_RSVD_THR_MASK 0x7FFull\n-#define SSO_HWGRP_TAQ_MAX_THR_SHIFT 32\n-#define SSO_HWGRP_TAQ_RSVD_THR 0x3\n-\n-#define SSO_HWGRP_PRI_AFF_MASK 0xFull\n-#define SSO_HWGRP_PRI_AFF_SHIFT 8\n-#define SSO_HWGRP_PRI_WGT_MASK 0x3Full\n-#define SSO_HWGRP_PRI_WGT_SHIFT 16\n-#define SSO_HWGRP_PRI_WGT_LEFT_MASK 0x3Full\n-#define SSO_HWGRP_PRI_WGT_LEFT_SHIFT 24\n-\n-#define SSO_HWGRP_AW_CFG_RWEN BIT_ULL(0)\n-#define SSO_HWGRP_AW_CFG_LDWB BIT_ULL(1)\n-#define SSO_HWGRP_AW_CFG_LDT BIT_ULL(2)\n-#define SSO_HWGRP_AW_CFG_STT BIT_ULL(3)\n-#define SSO_HWGRP_AW_CFG_XAQ_BYP_DIS BIT_ULL(4)\n-\n-#define SSO_HWGRP_AW_STS_TPTR_VLD BIT_ULL(8)\n-#define SSO_HWGRP_AW_STS_NPA_FETCH BIT_ULL(9)\n-#define SSO_HWGRP_AW_STS_XAQ_BUFSC_MASK 0x7ull\n-#define SSO_HWGRP_AW_STS_INIT_STS 0x18ull\n-\n-/* Enum offsets */\n-\n-#define SSO_LF_INT_VEC_GRP (0x0ull)\n-\n-#define SSO_AF_INT_VEC_ERR0 (0x0ull)\n-#define SSO_AF_INT_VEC_ERR2 (0x1ull)\n-#define SSO_AF_INT_VEC_RAS (0x2ull)\n-\n-#define SSO_WA_IOBN (0x0ull)\n-#define SSO_WA_NIXRX (0x1ull)\n-#define SSO_WA_CPT (0x2ull)\n-#define SSO_WA_ADDWQ (0x3ull)\n-#define SSO_WA_DPI (0x4ull)\n-#define SSO_WA_NIXTX (0x5ull)\n-#define SSO_WA_TIM (0x6ull)\n-#define SSO_WA_ZIP (0x7ull)\n-\n-#define SSO_TT_ORDERED (0x0ull)\n-#define SSO_TT_ATOMIC (0x1ull)\n-#define SSO_TT_UNTAGGED (0x2ull)\n-#define SSO_TT_EMPTY (0x3ull)\n-\n-\n-/* Structures definitions */\n-\n-#endif /* __OTX2_SSO_HW_H__ */\ndiff --git a/drivers/common/octeontx2/hw/otx2_ssow.h b/drivers/common/octeontx2/hw/otx2_ssow.h\ndeleted file mode 100644\nindex 8a44578036..0000000000\n--- a/drivers/common/octeontx2/hw/otx2_ssow.h\n+++ /dev/null\n@@ -1,56 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_SSOW_HW_H__\n-#define __OTX2_SSOW_HW_H__\n-\n-/* Register offsets */\n-\n-#define SSOW_AF_RVU_LF_HWS_CFG_DEBUG (0x10ull)\n-#define SSOW_AF_LF_HWS_RST (0x30ull)\n-#define SSOW_PRIV_LFX_HWS_CFG(a) (0x1000ull | (uint64_t)(a) << 3)\n-#define SSOW_PRIV_LFX_HWS_INT_CFG(a) (0x2000ull | (uint64_t)(a) << 3)\n-#define SSOW_AF_SCRATCH_WS (0x100000ull)\n-#define SSOW_AF_SCRATCH_GW (0x200000ull)\n-#define SSOW_AF_SCRATCH_AW (0x300000ull)\n-\n-#define SSOW_LF_GWS_LINKS (0x10ull)\n-#define SSOW_LF_GWS_PENDWQP (0x40ull)\n-#define SSOW_LF_GWS_PENDSTATE (0x50ull)\n-#define SSOW_LF_GWS_NW_TIM (0x70ull)\n-#define SSOW_LF_GWS_GRPMSK_CHG (0x80ull)\n-#define SSOW_LF_GWS_INT (0x100ull)\n-#define SSOW_LF_GWS_INT_W1S (0x108ull)\n-#define SSOW_LF_GWS_INT_ENA_W1S (0x110ull)\n-#define SSOW_LF_GWS_INT_ENA_W1C (0x118ull)\n-#define SSOW_LF_GWS_TAG (0x200ull)\n-#define SSOW_LF_GWS_WQP (0x210ull)\n-#define SSOW_LF_GWS_SWTP (0x220ull)\n-#define SSOW_LF_GWS_PENDTAG (0x230ull)\n-#define SSOW_LF_GWS_OP_ALLOC_WE (0x400ull)\n-#define SSOW_LF_GWS_OP_GET_WORK (0x600ull)\n-#define SSOW_LF_GWS_OP_SWTAG_FLUSH (0x800ull)\n-#define SSOW_LF_GWS_OP_SWTAG_UNTAG (0x810ull)\n-#define SSOW_LF_GWS_OP_SWTP_CLR (0x820ull)\n-#define SSOW_LF_GWS_OP_UPD_WQP_GRP0 (0x830ull)\n-#define SSOW_LF_GWS_OP_UPD_WQP_GRP1 (0x838ull)\n-#define SSOW_LF_GWS_OP_DESCHED (0x880ull)\n-#define SSOW_LF_GWS_OP_DESCHED_NOSCH (0x8c0ull)\n-#define SSOW_LF_GWS_OP_SWTAG_DESCHED (0x980ull)\n-#define SSOW_LF_GWS_OP_SWTAG_NOSCHED (0x9c0ull)\n-#define SSOW_LF_GWS_OP_CLR_NSCHED0 (0xa00ull)\n-#define SSOW_LF_GWS_OP_CLR_NSCHED1 (0xa08ull)\n-#define SSOW_LF_GWS_OP_SWTP_SET (0xc00ull)\n-#define SSOW_LF_GWS_OP_SWTAG_NORM (0xc10ull)\n-#define SSOW_LF_GWS_OP_SWTAG_FULL0 (0xc20ull)\n-#define SSOW_LF_GWS_OP_SWTAG_FULL1 (0xc28ull)\n-#define SSOW_LF_GWS_OP_GWC_INVAL (0xe00ull)\n-\n-\n-/* Enum offsets */\n-\n-#define SSOW_LF_INT_VEC_IOP (0x0ull)\n-\n-\n-#endif /* __OTX2_SSOW_HW_H__ */\ndiff --git a/drivers/common/octeontx2/hw/otx2_tim.h b/drivers/common/octeontx2/hw/otx2_tim.h\ndeleted file mode 100644\nindex 41442ad0a8..0000000000\n--- a/drivers/common/octeontx2/hw/otx2_tim.h\n+++ /dev/null\n@@ -1,34 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_TIM_HW_H__\n-#define __OTX2_TIM_HW_H__\n-\n-/* TIM */\n-#define TIM_AF_CONST (0x90)\n-#define TIM_PRIV_LFX_CFG(a) (0x20000 | (a) << 3)\n-#define TIM_PRIV_LFX_INT_CFG(a) (0x24000 | (a) << 3)\n-#define TIM_AF_RVU_LF_CFG_DEBUG (0x30000)\n-#define TIM_AF_BLK_RST (0x10)\n-#define TIM_AF_LF_RST (0x20)\n-#define TIM_AF_BLK_RST (0x10)\n-#define TIM_AF_RINGX_GMCTL(a) (0x2000 | (a) << 3)\n-#define TIM_AF_RINGX_CTL0(a) (0x4000 | (a) << 3)\n-#define TIM_AF_RINGX_CTL1(a) (0x6000 | (a) << 3)\n-#define TIM_AF_RINGX_CTL2(a) (0x8000 | (a) << 3)\n-#define TIM_AF_FLAGS_REG (0x80)\n-#define TIM_AF_FLAGS_REG_ENA_TIM BIT_ULL(0)\n-#define TIM_AF_RINGX_CTL1_ENA BIT_ULL(47)\n-#define TIM_AF_RINGX_CTL1_RCF_BUSY BIT_ULL(50)\n-#define TIM_AF_RINGX_CLT1_CLK_10NS (0)\n-#define TIM_AF_RINGX_CLT1_CLK_GPIO (1)\n-#define TIM_AF_RINGX_CLT1_CLK_GTI (2)\n-#define TIM_AF_RINGX_CLT1_CLK_PTP (3)\n-\n-/* ENUMS */\n-\n-#define TIM_LF_INT_VEC_NRSPERR_INT\t(0x0ull)\n-#define TIM_LF_INT_VEC_RAS_INT\t\t(0x1ull)\n-\n-#endif /* __OTX2_TIM_HW_H__ */\ndiff --git a/drivers/common/octeontx2/meson.build b/drivers/common/octeontx2/meson.build\ndeleted file mode 100644\nindex 223ba5ef51..0000000000\n--- a/drivers/common/octeontx2/meson.build\n+++ /dev/null\n@@ -1,24 +0,0 @@\n-# SPDX-License-Identifier: BSD-3-Clause\n-# Copyright(C) 2019 Marvell International Ltd.\n-#\n-\n-if not is_linux or not dpdk_conf.get('RTE_ARCH_64')\n- build = false\n- reason = 'only supported on 64-bit Linux'\n- subdir_done()\n-endif\n-\n-sources= files(\n- 'otx2_common.c',\n- 'otx2_dev.c',\n- 'otx2_irq.c',\n- 'otx2_mbox.c',\n- 'otx2_sec_idev.c',\n-)\n-\n-deps = ['eal', 'pci', 'ethdev', 'kvargs']\n-includes += include_directories(\n- '../../common/octeontx2',\n- '../../mempool/octeontx2',\n- '../../bus/pci',\n-)\ndiff --git a/drivers/common/octeontx2/otx2_common.c b/drivers/common/octeontx2/otx2_common.c\ndeleted file mode 100644\nindex d23c50242e..0000000000\n--- a/drivers/common/octeontx2/otx2_common.c\n+++ /dev/null\n@@ -1,216 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_atomic.h>\n-#include <rte_malloc.h>\n-#include <rte_log.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_dev.h\"\n-#include \"otx2_mbox.h\"\n-\n-/**\n- * @internal\n- * Set default NPA configuration.\n- */\n-void\n-otx2_npa_set_defaults(struct otx2_idev_cfg *idev)\n-{\n-\tidev->npa_pf_func = 0;\n-\trte_atomic16_set(&idev->npa_refcnt, 0);\n-}\n-\n-/**\n- * @internal\n- * Get intra device config structure.\n- */\n-struct otx2_idev_cfg *\n-otx2_intra_dev_get_cfg(void)\n-{\n-\tconst char name[] = \"octeontx2_intra_device_conf\";\n-\tconst struct rte_memzone *mz;\n-\tstruct otx2_idev_cfg *idev;\n-\n-\tmz = rte_memzone_lookup(name);\n-\tif (mz != NULL)\n-\t\treturn mz->addr;\n-\n-\t/* Request for the first time */\n-\tmz = rte_memzone_reserve_aligned(name, sizeof(struct otx2_idev_cfg),\n-\t\t\t\t\t SOCKET_ID_ANY, 0, OTX2_ALIGN);\n-\tif (mz != NULL) {\n-\t\tidev = mz->addr;\n-\t\tidev->sso_pf_func = 0;\n-\t\tidev->npa_lf = NULL;\n-\t\totx2_npa_set_defaults(idev);\n-\t\treturn idev;\n-\t}\n-\treturn NULL;\n-}\n-\n-/**\n- * @internal\n- * Get SSO PF_FUNC.\n- */\n-uint16_t\n-otx2_sso_pf_func_get(void)\n-{\n-\tstruct otx2_idev_cfg *idev;\n-\tuint16_t sso_pf_func;\n-\n-\tsso_pf_func = 0;\n-\tidev = otx2_intra_dev_get_cfg();\n-\n-\tif (idev != NULL)\n-\t\tsso_pf_func = idev->sso_pf_func;\n-\n-\treturn sso_pf_func;\n-}\n-\n-/**\n- * @internal\n- * Set SSO PF_FUNC.\n- */\n-void\n-otx2_sso_pf_func_set(uint16_t sso_pf_func)\n-{\n-\tstruct otx2_idev_cfg *idev;\n-\n-\tidev = otx2_intra_dev_get_cfg();\n-\n-\tif (idev != NULL) {\n-\t\tidev->sso_pf_func = sso_pf_func;\n-\t\trte_smp_wmb();\n-\t}\n-}\n-\n-/**\n- * @internal\n- * Get NPA PF_FUNC.\n- */\n-uint16_t\n-otx2_npa_pf_func_get(void)\n-{\n-\tstruct otx2_idev_cfg *idev;\n-\tuint16_t npa_pf_func;\n-\n-\tnpa_pf_func = 0;\n-\tidev = otx2_intra_dev_get_cfg();\n-\n-\tif (idev != NULL)\n-\t\tnpa_pf_func = idev->npa_pf_func;\n-\n-\treturn npa_pf_func;\n-}\n-\n-/**\n- * @internal\n- * Get NPA lf object.\n- */\n-struct otx2_npa_lf *\n-otx2_npa_lf_obj_get(void)\n-{\n-\tstruct otx2_idev_cfg *idev;\n-\n-\tidev = otx2_intra_dev_get_cfg();\n-\n-\tif (idev != NULL && rte_atomic16_read(&idev->npa_refcnt))\n-\t\treturn idev->npa_lf;\n-\n-\treturn NULL;\n-}\n-\n-/**\n- * @internal\n- * Is NPA lf active for the given device?.\n- */\n-int\n-otx2_npa_lf_active(void *otx2_dev)\n-{\n-\tstruct otx2_dev *dev = otx2_dev;\n-\tstruct otx2_idev_cfg *idev;\n-\n-\t/* Check if npalf is actively used on this dev */\n-\tidev = otx2_intra_dev_get_cfg();\n-\tif (!idev || !idev->npa_lf || idev->npa_lf->mbox != dev->mbox)\n-\t\treturn 0;\n-\n-\treturn rte_atomic16_read(&idev->npa_refcnt);\n-}\n-\n-/*\n- * @internal\n- * Gets reference only to existing NPA LF object.\n- */\n-int otx2_npa_lf_obj_ref(void)\n-{\n-\tstruct otx2_idev_cfg *idev;\n-\tuint16_t cnt;\n-\tint rc;\n-\n-\tidev = otx2_intra_dev_get_cfg();\n-\n-\t/* Check if ref not possible */\n-\tif (idev == NULL)\n-\t\treturn -EINVAL;\n-\n-\n-\t/* Get ref only if > 0 */\n-\tcnt = rte_atomic16_read(&idev->npa_refcnt);\n-\twhile (cnt != 0) {\n-\t\trc = rte_atomic16_cmpset(&idev->npa_refcnt_u16, cnt, cnt + 1);\n-\t\tif (rc)\n-\t\t\tbreak;\n-\n-\t\tcnt = rte_atomic16_read(&idev->npa_refcnt);\n-\t}\n-\n-\treturn cnt ? 0 : -EINVAL;\n-}\n-\n-static int\n-parse_npa_lock_mask(const char *key, const char *value, void *extra_args)\n-{\n-\tRTE_SET_USED(key);\n-\tuint64_t val;\n-\n-\tval = strtoull(value, NULL, 16);\n-\n-\t*(uint64_t *)extra_args = val;\n-\n-\treturn 0;\n-}\n-\n-/*\n- * @internal\n- * Parse common device arguments\n- */\n-void otx2_parse_common_devargs(struct rte_kvargs *kvlist)\n-{\n-\n-\tstruct otx2_idev_cfg *idev;\n-\tuint64_t npa_lock_mask = 0;\n-\n-\tidev = otx2_intra_dev_get_cfg();\n-\n-\tif (idev == NULL)\n-\t\treturn;\n-\n-\trte_kvargs_process(kvlist, OTX2_NPA_LOCK_MASK,\n-\t\t\t&parse_npa_lock_mask, &npa_lock_mask);\n-\n-\tidev->npa_lock_mask = npa_lock_mask;\n-}\n-\n-RTE_LOG_REGISTER(otx2_logtype_base, pmd.octeontx2.base, NOTICE);\n-RTE_LOG_REGISTER(otx2_logtype_mbox, pmd.octeontx2.mbox, NOTICE);\n-RTE_LOG_REGISTER(otx2_logtype_npa, pmd.mempool.octeontx2, NOTICE);\n-RTE_LOG_REGISTER(otx2_logtype_nix, pmd.net.octeontx2, NOTICE);\n-RTE_LOG_REGISTER(otx2_logtype_npc, pmd.net.octeontx2.flow, NOTICE);\n-RTE_LOG_REGISTER(otx2_logtype_tm, pmd.net.octeontx2.tm, NOTICE);\n-RTE_LOG_REGISTER(otx2_logtype_sso, pmd.event.octeontx2, NOTICE);\n-RTE_LOG_REGISTER(otx2_logtype_tim, pmd.event.octeontx2.timer, NOTICE);\n-RTE_LOG_REGISTER(otx2_logtype_dpi, pmd.raw.octeontx2.dpi, NOTICE);\n-RTE_LOG_REGISTER(otx2_logtype_ep, pmd.raw.octeontx2.ep, NOTICE);\n-RTE_LOG_REGISTER(otx2_logtype_ree, pmd.regex.octeontx2, NOTICE);\ndiff --git a/drivers/common/octeontx2/otx2_common.h b/drivers/common/octeontx2/otx2_common.h\ndeleted file mode 100644\nindex cd52e098e6..0000000000\n--- a/drivers/common/octeontx2/otx2_common.h\n+++ /dev/null\n@@ -1,179 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_COMMON_H_\n-#define _OTX2_COMMON_H_\n-\n-#include <rte_atomic.h>\n-#include <rte_common.h>\n-#include <rte_cycles.h>\n-#include <rte_kvargs.h>\n-#include <rte_memory.h>\n-#include <rte_memzone.h>\n-#include <rte_io.h>\n-\n-#include \"hw/otx2_rvu.h\"\n-#include \"hw/otx2_nix.h\"\n-#include \"hw/otx2_npc.h\"\n-#include \"hw/otx2_npa.h\"\n-#include \"hw/otx2_sdp.h\"\n-#include \"hw/otx2_sso.h\"\n-#include \"hw/otx2_ssow.h\"\n-#include \"hw/otx2_tim.h\"\n-#include \"hw/otx2_ree.h\"\n-\n-/* Alignment */\n-#define OTX2_ALIGN 128\n-\n-/* Bits manipulation */\n-#ifndef BIT_ULL\n-#define BIT_ULL(nr) (1ULL << (nr))\n-#endif\n-#ifndef BIT\n-#define BIT(nr) (1UL << (nr))\n-#endif\n-\n-#ifndef BITS_PER_LONG\n-#define BITS_PER_LONG\t(__SIZEOF_LONG__ * 8)\n-#endif\n-#ifndef BITS_PER_LONG_LONG\n-#define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)\n-#endif\n-\n-#ifndef GENMASK\n-#define GENMASK(h, l) \\\n-\t\t(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))\n-#endif\n-#ifndef GENMASK_ULL\n-#define GENMASK_ULL(h, l) \\\n-\t(((~0ULL) - (1ULL << (l)) + 1) & \\\n-\t (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))\n-#endif\n-\n-#define OTX2_NPA_LOCK_MASK \"npa_lock_mask\"\n-\n-/* Intra device related functions */\n-struct otx2_npa_lf;\n-struct otx2_idev_cfg {\n-\tuint16_t sso_pf_func;\n-\tuint16_t npa_pf_func;\n-\tstruct otx2_npa_lf *npa_lf;\n-\tRTE_STD_C11\n-\tunion {\n-\t\trte_atomic16_t npa_refcnt;\n-\t\tuint16_t npa_refcnt_u16;\n-\t};\n-\tuint64_t npa_lock_mask;\n-};\n-\n-__rte_internal\n-struct otx2_idev_cfg *otx2_intra_dev_get_cfg(void);\n-__rte_internal\n-void otx2_sso_pf_func_set(uint16_t sso_pf_func);\n-__rte_internal\n-uint16_t otx2_sso_pf_func_get(void);\n-__rte_internal\n-uint16_t otx2_npa_pf_func_get(void);\n-__rte_internal\n-struct otx2_npa_lf *otx2_npa_lf_obj_get(void);\n-__rte_internal\n-void otx2_npa_set_defaults(struct otx2_idev_cfg *idev);\n-__rte_internal\n-int otx2_npa_lf_active(void *dev);\n-__rte_internal\n-int otx2_npa_lf_obj_ref(void);\n-__rte_internal\n-void otx2_parse_common_devargs(struct rte_kvargs *kvlist);\n-\n-/* Log */\n-extern int otx2_logtype_base;\n-extern int otx2_logtype_mbox;\n-extern int otx2_logtype_npa;\n-extern int otx2_logtype_nix;\n-extern int otx2_logtype_sso;\n-extern int otx2_logtype_npc;\n-extern int otx2_logtype_tm;\n-extern int otx2_logtype_tim;\n-extern int otx2_logtype_dpi;\n-extern int otx2_logtype_ep;\n-extern int otx2_logtype_ree;\n-\n-#define otx2_err(fmt, args...)\t\t\t\\\n-\tRTE_LOG(ERR, PMD, \"%s():%u \" fmt \"\\n\",\t\\\n-\t\t__func__, __LINE__, ## args)\n-\n-#define otx2_info(fmt, args...)\t\t\t\t\t\t\\\n-\tRTE_LOG(INFO, PMD, fmt\"\\n\", ## args)\n-\n-#define otx2_dbg(subsystem, fmt, args...)\t\t\t\t\\\n-\trte_log(RTE_LOG_DEBUG, otx2_logtype_ ## subsystem,\t\t\\\n-\t\t\"[%s] %s():%u \" fmt \"\\n\",\t\t\t\t\\\n-\t\t #subsystem, __func__, __LINE__, ##args)\n-\n-#define otx2_base_dbg(fmt, ...) otx2_dbg(base, fmt, ##__VA_ARGS__)\n-#define otx2_mbox_dbg(fmt, ...) otx2_dbg(mbox, fmt, ##__VA_ARGS__)\n-#define otx2_npa_dbg(fmt, ...) otx2_dbg(npa, fmt, ##__VA_ARGS__)\n-#define otx2_nix_dbg(fmt, ...) otx2_dbg(nix, fmt, ##__VA_ARGS__)\n-#define otx2_sso_dbg(fmt, ...) otx2_dbg(sso, fmt, ##__VA_ARGS__)\n-#define otx2_npc_dbg(fmt, ...) otx2_dbg(npc, fmt, ##__VA_ARGS__)\n-#define otx2_tm_dbg(fmt, ...) otx2_dbg(tm, fmt, ##__VA_ARGS__)\n-#define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)\n-#define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)\n-#define otx2_sdp_dbg(fmt, ...) otx2_dbg(ep, fmt, ##__VA_ARGS__)\n-#define otx2_ree_dbg(fmt, ...) otx2_dbg(ree, fmt, ##__VA_ARGS__)\n-\n-/* PCI IDs */\n-#define PCI_VENDOR_ID_CAVIUM\t\t\t0x177D\n-#define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063\n-#define PCI_DEVID_OCTEONTX2_RVU_VF\t\t0xA064\n-#define PCI_DEVID_OCTEONTX2_RVU_AF\t\t0xA065\n-#define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF\t0xA0F9\n-#define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF\t0xA0FA\n-#define PCI_DEVID_OCTEONTX2_RVU_NPA_PF\t\t0xA0FB\n-#define PCI_DEVID_OCTEONTX2_RVU_NPA_VF\t\t0xA0FC\n-#define PCI_DEVID_OCTEONTX2_RVU_CPT_PF\t\t0xA0FD\n-#define PCI_DEVID_OCTEONTX2_RVU_CPT_VF\t\t0xA0FE\n-#define PCI_DEVID_OCTEONTX2_RVU_AF_VF\t\t0xA0f8\n-#define PCI_DEVID_OCTEONTX2_DPI_VF\t\t0xA081\n-#define PCI_DEVID_OCTEONTX2_EP_NET_VF\t\t0xB203 /* OCTEON TX2 EP mode */\n-/* OCTEON TX2 98xx EP mode */\n-#define PCI_DEVID_CN98XX_EP_NET_VF\t\t0xB103\n-#define PCI_DEVID_OCTEONTX2_EP_RAW_VF\t\t0xB204 /* OCTEON TX2 EP mode */\n-#define PCI_DEVID_OCTEONTX2_RVU_SDP_PF\t\t0xA0f6\n-#define PCI_DEVID_OCTEONTX2_RVU_SDP_VF\t\t0xA0f7\n-#define PCI_DEVID_OCTEONTX2_RVU_REE_PF\t\t0xA0f4\n-#define PCI_DEVID_OCTEONTX2_RVU_REE_VF\t\t0xA0f5\n-\n-/*\n- * REVID for RVU PCIe devices.\n- * Bits 0..1: minor pass\n- * Bits 3..2: major pass\n- * Bits 7..4: midr id, 0:96, 1:95, 2:loki, f:unknown\n- */\n-\n-#define RVU_PCI_REV_MIDR_ID(rev_id)\t\t(rev_id >> 4)\n-#define RVU_PCI_REV_MAJOR(rev_id)\t\t((rev_id >> 2) & 0x3)\n-#define RVU_PCI_REV_MINOR(rev_id)\t\t(rev_id & 0x3)\n-\n-#define RVU_PCI_CN96XX_MIDR_ID\t\t\t0x0\n-#define RVU_PCI_CNF95XX_MIDR_ID\t\t\t0x1\n-\n-/* PCI Config offsets */\n-#define RVU_PCI_REVISION_ID\t\t\t0x08\n-\n-/* IO Access */\n-#define otx2_read64(addr) rte_read64_relaxed((void *)(addr))\n-#define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))\n-\n-#if defined(RTE_ARCH_ARM64)\n-#include \"otx2_io_arm64.h\"\n-#else\n-#include \"otx2_io_generic.h\"\n-#endif\n-\n-/* Fastpath lookup */\n-#define OTX2_NIX_FASTPATH_LOOKUP_MEM\t\"otx2_nix_fastpath_lookup_mem\"\n-#define OTX2_NIX_SA_TBL_START\t\t(4096*4 + 69632*2)\n-\n-#endif /* _OTX2_COMMON_H_ */\ndiff --git a/drivers/common/octeontx2/otx2_dev.c b/drivers/common/octeontx2/otx2_dev.c\ndeleted file mode 100644\nindex 08dca87848..0000000000\n--- a/drivers/common/octeontx2/otx2_dev.c\n+++ /dev/null\n@@ -1,1074 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <fcntl.h>\n-#include <inttypes.h>\n-#include <sys/mman.h>\n-#include <unistd.h>\n-\n-#include <rte_alarm.h>\n-#include <rte_common.h>\n-#include <rte_eal.h>\n-#include <rte_memcpy.h>\n-#include <rte_eal_paging.h>\n-\n-#include \"otx2_dev.h\"\n-#include \"otx2_mbox.h\"\n-\n-#define RVU_MAX_VF\t\t64 /* RVU_PF_VFPF_MBOX_INT(0..1) */\n-#define RVU_MAX_INT_RETRY\t3\n-\n-/* PF/VF message handling timer */\n-#define VF_PF_MBOX_TIMER_MS\t(20 * 1000)\n-\n-static void *\n-mbox_mem_map(off_t off, size_t size)\n-{\n-\tvoid *va = MAP_FAILED;\n-\tint mem_fd;\n-\n-\tif (size <= 0)\n-\t\tgoto error;\n-\n-\tmem_fd = open(\"/dev/mem\", O_RDWR);\n-\tif (mem_fd < 0)\n-\t\tgoto error;\n-\n-\tva = rte_mem_map(NULL, size, RTE_PROT_READ | RTE_PROT_WRITE,\n-\t\t\tRTE_MAP_SHARED, mem_fd, off);\n-\tclose(mem_fd);\n-\n-\tif (va == NULL)\n-\t\totx2_err(\"Failed to mmap sz=0x%zx, fd=%d, off=%jd\",\n-\t\t\t size, mem_fd, (intmax_t)off);\n-error:\n-\treturn va;\n-}\n-\n-static void\n-mbox_mem_unmap(void *va, size_t size)\n-{\n-\tif (va)\n-\t\trte_mem_unmap(va, size);\n-}\n-\n-static int\n-pf_af_sync_msg(struct otx2_dev *dev, struct mbox_msghdr **rsp)\n-{\n-\tuint32_t timeout = 0, sleep = 1; struct otx2_mbox *mbox = dev->mbox;\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];\n-\tvolatile uint64_t int_status;\n-\tstruct mbox_msghdr *msghdr;\n-\tuint64_t off;\n-\tint rc = 0;\n-\n-\t/* We need to disable PF interrupts. We are in timer interrupt */\n-\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);\n-\n-\t/* Send message */\n-\totx2_mbox_msg_send(mbox, 0);\n-\n-\tdo {\n-\t\trte_delay_ms(sleep);\n-\t\ttimeout += sleep;\n-\t\tif (timeout >= MBOX_RSP_TIMEOUT) {\n-\t\t\totx2_err(\"Message timeout: %dms\", MBOX_RSP_TIMEOUT);\n-\t\t\trc = -EIO;\n-\t\t\tbreak;\n-\t\t}\n-\t\tint_status = otx2_read64(dev->bar2 + RVU_PF_INT);\n-\t} while ((int_status & 0x1) != 0x1);\n-\n-\t/* Clear */\n-\totx2_write64(int_status, dev->bar2 + RVU_PF_INT);\n-\n-\t/* Enable interrupts */\n-\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);\n-\n-\tif (rc == 0) {\n-\t\t/* Get message */\n-\t\toff = mbox->rx_start +\n-\t\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n-\t\tmsghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + off);\n-\t\tif (rsp)\n-\t\t\t*rsp = msghdr;\n-\t\trc = msghdr->rc;\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static int\n-af_pf_wait_msg(struct otx2_dev *dev, uint16_t vf, int num_msg)\n-{\n-\tuint32_t timeout = 0, sleep = 1; struct otx2_mbox *mbox = dev->mbox;\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];\n-\tvolatile uint64_t int_status;\n-\tstruct mbox_hdr *req_hdr;\n-\tstruct mbox_msghdr *msg;\n-\tstruct mbox_msghdr *rsp;\n-\tuint64_t offset;\n-\tsize_t size;\n-\tint i;\n-\n-\t/* We need to disable PF interrupts. We are in timer interrupt */\n-\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);\n-\n-\t/* Send message */\n-\totx2_mbox_msg_send(mbox, 0);\n-\n-\tdo {\n-\t\trte_delay_ms(sleep);\n-\t\ttimeout++;\n-\t\tif (timeout >= MBOX_RSP_TIMEOUT) {\n-\t\t\totx2_err(\"Routed messages %d timeout: %dms\",\n-\t\t\t\t num_msg, MBOX_RSP_TIMEOUT);\n-\t\t\tbreak;\n-\t\t}\n-\t\tint_status = otx2_read64(dev->bar2 + RVU_PF_INT);\n-\t} while ((int_status & 0x1) != 0x1);\n-\n-\t/* Clear */\n-\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT);\n-\n-\t/* Enable interrupts */\n-\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);\n-\n-\trte_spinlock_lock(&mdev->mbox_lock);\n-\n-\treq_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n-\tif (req_hdr->num_msgs != num_msg)\n-\t\totx2_err(\"Routed messages: %d received: %d\", num_msg,\n-\t\t\t req_hdr->num_msgs);\n-\n-\t/* Get messages from mbox */\n-\toffset = mbox->rx_start +\n-\t\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n-\tfor (i = 0; i < req_hdr->num_msgs; i++) {\n-\t\tmsg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n-\t\tsize = mbox->rx_start + msg->next_msgoff - offset;\n-\n-\t\t/* Reserve PF/VF mbox message */\n-\t\tsize = RTE_ALIGN(size, MBOX_MSG_ALIGN);\n-\t\trsp = otx2_mbox_alloc_msg(&dev->mbox_vfpf, vf, size);\n-\t\totx2_mbox_rsp_init(msg->id, rsp);\n-\n-\t\t/* Copy message from AF<->PF mbox to PF<->VF mbox */\n-\t\totx2_mbox_memcpy((uint8_t *)rsp + sizeof(struct mbox_msghdr),\n-\t\t\t\t (uint8_t *)msg + sizeof(struct mbox_msghdr),\n-\t\t\t\t size - sizeof(struct mbox_msghdr));\n-\n-\t\t/* Set status and sender pf_func data */\n-\t\trsp->rc = msg->rc;\n-\t\trsp->pcifunc = msg->pcifunc;\n-\n-\t\t/* Whenever a PF comes up, AF sends the link status to it but\n-\t\t * when VF comes up no such event is sent to respective VF.\n-\t\t * Using MBOX_MSG_NIX_LF_START_RX response from AF for the\n-\t\t * purpose and send the link status of PF to VF.\n-\t\t */\n-\t\tif (msg->id == MBOX_MSG_NIX_LF_START_RX) {\n-\t\t\t/* Send link status to VF */\n-\t\t\tstruct cgx_link_user_info linfo;\n-\t\t\tstruct mbox_msghdr *vf_msg;\n-\t\t\tsize_t sz;\n-\n-\t\t\t/* Get the link status */\n-\t\t\tif (dev->ops && dev->ops->link_status_get)\n-\t\t\t\tdev->ops->link_status_get(dev, &linfo);\n-\n-\t\t\tsz = RTE_ALIGN(otx2_mbox_id2size(\n-\t\t\t\tMBOX_MSG_CGX_LINK_EVENT), MBOX_MSG_ALIGN);\n-\t\t\t/* Prepare the message to be sent */\n-\t\t\tvf_msg = otx2_mbox_alloc_msg(&dev->mbox_vfpf_up, vf,\n-\t\t\t\t\t\t sz);\n-\t\t\totx2_mbox_req_init(MBOX_MSG_CGX_LINK_EVENT, vf_msg);\n-\t\t\tmemcpy((uint8_t *)vf_msg + sizeof(struct mbox_msghdr),\n-\t\t\t &linfo, sizeof(struct cgx_link_user_info));\n-\n-\t\t\tvf_msg->rc = msg->rc;\n-\t\t\tvf_msg->pcifunc = msg->pcifunc;\n-\t\t\t/* Send to VF */\n-\t\t\totx2_mbox_msg_send(&dev->mbox_vfpf_up, vf);\n-\t\t}\n-\t\toffset = mbox->rx_start + msg->next_msgoff;\n-\t}\n-\trte_spinlock_unlock(&mdev->mbox_lock);\n-\n-\treturn req_hdr->num_msgs;\n-}\n-\n-static int\n-vf_pf_process_msgs(struct otx2_dev *dev, uint16_t vf)\n-{\n-\tint offset, routed = 0; struct otx2_mbox *mbox = &dev->mbox_vfpf;\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[vf];\n-\tstruct mbox_hdr *req_hdr;\n-\tstruct mbox_msghdr *msg;\n-\tsize_t size;\n-\tuint16_t i;\n-\n-\treq_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n-\tif (!req_hdr->num_msgs)\n-\t\treturn 0;\n-\n-\toffset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);\n-\n-\tfor (i = 0; i < req_hdr->num_msgs; i++) {\n-\n-\t\tmsg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n-\t\tsize = mbox->rx_start + msg->next_msgoff - offset;\n-\n-\t\t/* RVU_PF_FUNC_S */\n-\t\tmsg->pcifunc = otx2_pfvf_func(dev->pf, vf);\n-\n-\t\tif (msg->id == MBOX_MSG_READY) {\n-\t\t\tstruct ready_msg_rsp *rsp;\n-\t\t\tuint16_t max_bits = sizeof(dev->active_vfs[0]) * 8;\n-\n-\t\t\t/* Handle READY message in PF */\n-\t\t\tdev->active_vfs[vf / max_bits] |=\n-\t\t\t\t\t\tBIT_ULL(vf % max_bits);\n-\t\t\trsp = (struct ready_msg_rsp *)\n-\t\t\t otx2_mbox_alloc_msg(mbox, vf, sizeof(*rsp));\n-\t\t\totx2_mbox_rsp_init(msg->id, rsp);\n-\n-\t\t\t/* PF/VF function ID */\n-\t\t\trsp->hdr.pcifunc = msg->pcifunc;\n-\t\t\trsp->hdr.rc = 0;\n-\t\t} else {\n-\t\t\tstruct mbox_msghdr *af_req;\n-\t\t\t/* Reserve AF/PF mbox message */\n-\t\t\tsize = RTE_ALIGN(size, MBOX_MSG_ALIGN);\n-\t\t\taf_req = otx2_mbox_alloc_msg(dev->mbox, 0, size);\n-\t\t\totx2_mbox_req_init(msg->id, af_req);\n-\n-\t\t\t/* Copy message from VF<->PF mbox to PF<->AF mbox */\n-\t\t\totx2_mbox_memcpy((uint8_t *)af_req +\n-\t\t\t\t sizeof(struct mbox_msghdr),\n-\t\t\t\t (uint8_t *)msg + sizeof(struct mbox_msghdr),\n-\t\t\t\t size - sizeof(struct mbox_msghdr));\n-\t\t\taf_req->pcifunc = msg->pcifunc;\n-\t\t\trouted++;\n-\t\t}\n-\t\toffset = mbox->rx_start + msg->next_msgoff;\n-\t}\n-\n-\tif (routed > 0) {\n-\t\totx2_base_dbg(\"pf:%d routed %d messages from vf:%d to AF\",\n-\t\t\t dev->pf, routed, vf);\n-\t\taf_pf_wait_msg(dev, vf, routed);\n-\t\totx2_mbox_reset(dev->mbox, 0);\n-\t}\n-\n-\t/* Send mbox responses to VF */\n-\tif (mdev->num_msgs) {\n-\t\totx2_base_dbg(\"pf:%d reply %d messages to vf:%d\",\n-\t\t\t dev->pf, mdev->num_msgs, vf);\n-\t\totx2_mbox_msg_send(mbox, vf);\n-\t}\n-\n-\treturn i;\n-}\n-\n-static int\n-vf_pf_process_up_msgs(struct otx2_dev *dev, uint16_t vf)\n-{\n-\tstruct otx2_mbox *mbox = &dev->mbox_vfpf_up;\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[vf];\n-\tstruct mbox_hdr *req_hdr;\n-\tstruct mbox_msghdr *msg;\n-\tint msgs_acked = 0;\n-\tint offset;\n-\tuint16_t i;\n-\n-\treq_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n-\tif (req_hdr->num_msgs == 0)\n-\t\treturn 0;\n-\n-\toffset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);\n-\n-\tfor (i = 0; i < req_hdr->num_msgs; i++) {\n-\t\tmsg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n-\n-\t\tmsgs_acked++;\n-\t\t/* RVU_PF_FUNC_S */\n-\t\tmsg->pcifunc = otx2_pfvf_func(dev->pf, vf);\n-\n-\t\tswitch (msg->id) {\n-\t\tcase MBOX_MSG_CGX_LINK_EVENT:\n-\t\t\totx2_base_dbg(\"PF: Msg 0x%x (%s) fn:0x%x (pf:%d,vf:%d)\",\n-\t\t\t\t msg->id, otx2_mbox_id2name(msg->id),\n-\t\t\t\t msg->pcifunc, otx2_get_pf(msg->pcifunc),\n-\t\t\t\t otx2_get_vf(msg->pcifunc));\n-\t\t\tbreak;\n-\t\tcase MBOX_MSG_CGX_PTP_RX_INFO:\n-\t\t\totx2_base_dbg(\"PF: Msg 0x%x (%s) fn:0x%x (pf:%d,vf:%d)\",\n-\t\t\t\t msg->id, otx2_mbox_id2name(msg->id),\n-\t\t\t\t msg->pcifunc, otx2_get_pf(msg->pcifunc),\n-\t\t\t\t otx2_get_vf(msg->pcifunc));\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\totx2_err(\"Not handled UP msg 0x%x (%s) func:0x%x\",\n-\t\t\t\t msg->id, otx2_mbox_id2name(msg->id),\n-\t\t\t\t msg->pcifunc);\n-\t\t}\n-\t\toffset = mbox->rx_start + msg->next_msgoff;\n-\t}\n-\totx2_mbox_reset(mbox, vf);\n-\tmdev->msgs_acked = msgs_acked;\n-\trte_wmb();\n-\n-\treturn i;\n-}\n-\n-static void\n-otx2_vf_pf_mbox_handle_msg(void *param)\n-{\n-\tuint16_t vf, max_vf, max_bits;\n-\tstruct otx2_dev *dev = param;\n-\n-\tmax_bits = sizeof(dev->intr.bits[0]) * sizeof(uint64_t);\n-\tmax_vf = max_bits * MAX_VFPF_DWORD_BITS;\n-\n-\tfor (vf = 0; vf < max_vf; vf++) {\n-\t\tif (dev->intr.bits[vf/max_bits] & BIT_ULL(vf%max_bits)) {\n-\t\t\totx2_base_dbg(\"Process vf:%d request (pf:%d, vf:%d)\",\n-\t\t\t\t vf, dev->pf, dev->vf);\n-\t\t\tvf_pf_process_msgs(dev, vf);\n-\t\t\t/* UP messages */\n-\t\t\tvf_pf_process_up_msgs(dev, vf);\n-\t\t\tdev->intr.bits[vf/max_bits] &= ~(BIT_ULL(vf%max_bits));\n-\t\t}\n-\t}\n-\tdev->timer_set = 0;\n-}\n-\n-static void\n-otx2_vf_pf_mbox_irq(void *param)\n-{\n-\tstruct otx2_dev *dev = param;\n-\tbool alarm_set = false;\n-\tuint64_t intr;\n-\tint vfpf;\n-\n-\tfor (vfpf = 0; vfpf < MAX_VFPF_DWORD_BITS; ++vfpf) {\n-\t\tintr = otx2_read64(dev->bar2 + RVU_PF_VFPF_MBOX_INTX(vfpf));\n-\t\tif (!intr)\n-\t\t\tcontinue;\n-\n-\t\totx2_base_dbg(\"vfpf: %d intr: 0x%\" PRIx64 \" (pf:%d, vf:%d)\",\n-\t\t\t vfpf, intr, dev->pf, dev->vf);\n-\n-\t\t/* Save and clear intr bits */\n-\t\tdev->intr.bits[vfpf] |= intr;\n-\t\totx2_write64(intr, dev->bar2 + RVU_PF_VFPF_MBOX_INTX(vfpf));\n-\t\talarm_set = true;\n-\t}\n-\n-\tif (!dev->timer_set && alarm_set) {\n-\t\tdev->timer_set = 1;\n-\t\t/* Start timer to handle messages */\n-\t\trte_eal_alarm_set(VF_PF_MBOX_TIMER_MS,\n-\t\t\t\t otx2_vf_pf_mbox_handle_msg, dev);\n-\t}\n-}\n-\n-static void\n-otx2_process_msgs(struct otx2_dev *dev, struct otx2_mbox *mbox)\n-{\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];\n-\tstruct mbox_hdr *req_hdr;\n-\tstruct mbox_msghdr *msg;\n-\tint msgs_acked = 0;\n-\tint offset;\n-\tuint16_t i;\n-\n-\treq_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n-\tif (req_hdr->num_msgs == 0)\n-\t\treturn;\n-\n-\toffset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);\n-\tfor (i = 0; i < req_hdr->num_msgs; i++) {\n-\t\tmsg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n-\n-\t\tmsgs_acked++;\n-\t\totx2_base_dbg(\"Message 0x%x (%s) pf:%d/vf:%d\",\n-\t\t\t msg->id, otx2_mbox_id2name(msg->id),\n-\t\t\t otx2_get_pf(msg->pcifunc),\n-\t\t\t otx2_get_vf(msg->pcifunc));\n-\n-\t\tswitch (msg->id) {\n-\t\t\t/* Add message id's that are handled here */\n-\t\tcase MBOX_MSG_READY:\n-\t\t\t/* Get our identity */\n-\t\t\tdev->pf_func = msg->pcifunc;\n-\t\t\tbreak;\n-\n-\t\tdefault:\n-\t\t\tif (msg->rc)\n-\t\t\t\totx2_err(\"Message (%s) response has err=%d\",\n-\t\t\t\t\t otx2_mbox_id2name(msg->id), msg->rc);\n-\t\t\tbreak;\n-\t\t}\n-\t\toffset = mbox->rx_start + msg->next_msgoff;\n-\t}\n-\n-\totx2_mbox_reset(mbox, 0);\n-\t/* Update acked if someone is waiting a message */\n-\tmdev->msgs_acked = msgs_acked;\n-\trte_wmb();\n-}\n-\n-/* Copies the message received from AF and sends it to VF */\n-static void\n-pf_vf_mbox_send_up_msg(struct otx2_dev *dev, void *rec_msg)\n-{\n-\tuint16_t max_bits = sizeof(dev->active_vfs[0]) * sizeof(uint64_t);\n-\tstruct otx2_mbox *vf_mbox = &dev->mbox_vfpf_up;\n-\tstruct msg_req *msg = rec_msg;\n-\tstruct mbox_msghdr *vf_msg;\n-\tuint16_t vf;\n-\tsize_t size;\n-\n-\tsize = RTE_ALIGN(otx2_mbox_id2size(msg->hdr.id), MBOX_MSG_ALIGN);\n-\t/* Send UP message to all VF's */\n-\tfor (vf = 0; vf < vf_mbox->ndevs; vf++) {\n-\t\t/* VF active */\n-\t\tif (!(dev->active_vfs[vf / max_bits] & (BIT_ULL(vf))))\n-\t\t\tcontinue;\n-\n-\t\totx2_base_dbg(\"(%s) size: %zx to VF: %d\",\n-\t\t\t otx2_mbox_id2name(msg->hdr.id), size, vf);\n-\n-\t\t/* Reserve PF/VF mbox message */\n-\t\tvf_msg = otx2_mbox_alloc_msg(vf_mbox, vf, size);\n-\t\tif (!vf_msg) {\n-\t\t\totx2_err(\"Failed to alloc VF%d UP message\", vf);\n-\t\t\tcontinue;\n-\t\t}\n-\t\totx2_mbox_req_init(msg->hdr.id, vf_msg);\n-\n-\t\t/*\n-\t\t * Copy message from AF<->PF UP mbox\n-\t\t * to PF<->VF UP mbox\n-\t\t */\n-\t\totx2_mbox_memcpy((uint8_t *)vf_msg +\n-\t\t\t\t sizeof(struct mbox_msghdr), (uint8_t *)msg\n-\t\t\t\t + sizeof(struct mbox_msghdr), size -\n-\t\t\t\t sizeof(struct mbox_msghdr));\n-\n-\t\tvf_msg->rc = msg->hdr.rc;\n-\t\t/* Set PF to be a sender */\n-\t\tvf_msg->pcifunc = dev->pf_func;\n-\n-\t\t/* Send to VF */\n-\t\totx2_mbox_msg_send(vf_mbox, vf);\n-\t}\n-}\n-\n-static int\n-otx2_mbox_up_handler_cgx_link_event(struct otx2_dev *dev,\n-\t\t\t\t struct cgx_link_info_msg *msg,\n-\t\t\t\t struct msg_rsp *rsp)\n-{\n-\tstruct cgx_link_user_info *linfo = &msg->link_info;\n-\n-\totx2_base_dbg(\"pf:%d/vf:%d NIC Link %s --> 0x%x (%s) from: pf:%d/vf:%d\",\n-\t\t otx2_get_pf(dev->pf_func), otx2_get_vf(dev->pf_func),\n-\t\t linfo->link_up ? \"UP\" : \"DOWN\", msg->hdr.id,\n-\t\t otx2_mbox_id2name(msg->hdr.id),\n-\t\t otx2_get_pf(msg->hdr.pcifunc),\n-\t\t otx2_get_vf(msg->hdr.pcifunc));\n-\n-\t/* PF gets link notification from AF */\n-\tif (otx2_get_pf(msg->hdr.pcifunc) == 0) {\n-\t\tif (dev->ops && dev->ops->link_status_update)\n-\t\t\tdev->ops->link_status_update(dev, linfo);\n-\n-\t\t/* Forward the same message as received from AF to VF */\n-\t\tpf_vf_mbox_send_up_msg(dev, msg);\n-\t} else {\n-\t\t/* VF gets link up notification */\n-\t\tif (dev->ops && dev->ops->link_status_update)\n-\t\t\tdev->ops->link_status_update(dev, linfo);\n-\t}\n-\n-\trsp->hdr.rc = 0;\n-\treturn 0;\n-}\n-\n-static int\n-otx2_mbox_up_handler_cgx_ptp_rx_info(struct otx2_dev *dev,\n-\t\t\t\t struct cgx_ptp_rx_info_msg *msg,\n-\t\t\t\t struct msg_rsp *rsp)\n-{\n-\totx2_nix_dbg(\"pf:%d/vf:%d PTP mode %s --> 0x%x (%s) from: pf:%d/vf:%d\",\n-\t\t otx2_get_pf(dev->pf_func),\n-\t\t otx2_get_vf(dev->pf_func),\n-\t\t msg->ptp_en ? \"ENABLED\" : \"DISABLED\",\n-\t\t msg->hdr.id, otx2_mbox_id2name(msg->hdr.id),\n-\t\t otx2_get_pf(msg->hdr.pcifunc),\n-\t\t otx2_get_vf(msg->hdr.pcifunc));\n-\n-\t/* PF gets PTP notification from AF */\n-\tif (otx2_get_pf(msg->hdr.pcifunc) == 0) {\n-\t\tif (dev->ops && dev->ops->ptp_info_update)\n-\t\t\tdev->ops->ptp_info_update(dev, msg->ptp_en);\n-\n-\t\t/* Forward the same message as received from AF to VF */\n-\t\tpf_vf_mbox_send_up_msg(dev, msg);\n-\t} else {\n-\t\t/* VF gets PTP notification */\n-\t\tif (dev->ops && dev->ops->ptp_info_update)\n-\t\t\tdev->ops->ptp_info_update(dev, msg->ptp_en);\n-\t}\n-\n-\trsp->hdr.rc = 0;\n-\treturn 0;\n-}\n-\n-static int\n-mbox_process_msgs_up(struct otx2_dev *dev, struct mbox_msghdr *req)\n-{\n-\t/* Check if valid, if not reply with a invalid msg */\n-\tif (req->sig != OTX2_MBOX_REQ_SIG)\n-\t\treturn -EIO;\n-\n-\tswitch (req->id) {\n-#define M(_name, _id, _fn_name, _req_type, _rsp_type)\t\t\\\n-\tcase _id: {\t\t\t\t\t\t\\\n-\t\tstruct _rsp_type *rsp;\t\t\t\t\\\n-\t\tint err;\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\\\n-\t\trsp = (struct _rsp_type *)otx2_mbox_alloc_msg(\t\\\n-\t\t\t&dev->mbox_up, 0,\t\t\t\\\n-\t\t\tsizeof(struct _rsp_type));\t\t\\\n-\t\tif (!rsp)\t\t\t\t\t\\\n-\t\t\treturn -ENOMEM;\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\\\n-\t\trsp->hdr.id = _id;\t\t\t\t\\\n-\t\trsp->hdr.sig = OTX2_MBOX_RSP_SIG;\t\t\\\n-\t\trsp->hdr.pcifunc = dev->pf_func;\t\t\\\n-\t\trsp->hdr.rc = 0;\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\\\n-\t\terr = otx2_mbox_up_handler_ ## _fn_name(\t\\\n-\t\t\tdev, (struct _req_type *)req, rsp);\t\\\n-\t\treturn err;\t\t\t\t\t\\\n-\t}\n-MBOX_UP_CGX_MESSAGES\n-#undef M\n-\n-\tdefault :\n-\t\totx2_reply_invalid_msg(&dev->mbox_up, 0, 0, req->id);\n-\t}\n-\n-\treturn -ENODEV;\n-}\n-\n-static void\n-otx2_process_msgs_up(struct otx2_dev *dev, struct otx2_mbox *mbox)\n-{\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];\n-\tstruct mbox_hdr *req_hdr;\n-\tstruct mbox_msghdr *msg;\n-\tint i, err, offset;\n-\n-\treq_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n-\tif (req_hdr->num_msgs == 0)\n-\t\treturn;\n-\n-\toffset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);\n-\tfor (i = 0; i < req_hdr->num_msgs; i++) {\n-\t\tmsg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n-\n-\t\totx2_base_dbg(\"Message 0x%x (%s) pf:%d/vf:%d\",\n-\t\t\t\tmsg->id, otx2_mbox_id2name(msg->id),\n-\t\t\t\totx2_get_pf(msg->pcifunc),\n-\t\t\t\totx2_get_vf(msg->pcifunc));\n-\t\terr = mbox_process_msgs_up(dev, msg);\n-\t\tif (err)\n-\t\t\totx2_err(\"Error %d handling 0x%x (%s)\",\n-\t\t\t\t err, msg->id, otx2_mbox_id2name(msg->id));\n-\t\toffset = mbox->rx_start + msg->next_msgoff;\n-\t}\n-\t/* Send mbox responses */\n-\tif (mdev->num_msgs) {\n-\t\totx2_base_dbg(\"Reply num_msgs:%d\", mdev->num_msgs);\n-\t\totx2_mbox_msg_send(mbox, 0);\n-\t}\n-}\n-\n-static void\n-otx2_pf_vf_mbox_irq(void *param)\n-{\n-\tstruct otx2_dev *dev = param;\n-\tuint64_t intr;\n-\n-\tintr = otx2_read64(dev->bar2 + RVU_VF_INT);\n-\tif (intr == 0)\n-\t\totx2_base_dbg(\"Proceeding to check mbox UP messages if any\");\n-\n-\totx2_write64(intr, dev->bar2 + RVU_VF_INT);\n-\totx2_base_dbg(\"Irq 0x%\" PRIx64 \"(pf:%d,vf:%d)\", intr, dev->pf, dev->vf);\n-\n-\t/* First process all configuration messages */\n-\totx2_process_msgs(dev, dev->mbox);\n-\n-\t/* Process Uplink messages */\n-\totx2_process_msgs_up(dev, &dev->mbox_up);\n-}\n-\n-static void\n-otx2_af_pf_mbox_irq(void *param)\n-{\n-\tstruct otx2_dev *dev = param;\n-\tuint64_t intr;\n-\n-\tintr = otx2_read64(dev->bar2 + RVU_PF_INT);\n-\tif (intr == 0)\n-\t\totx2_base_dbg(\"Proceeding to check mbox UP messages if any\");\n-\n-\totx2_write64(intr, dev->bar2 + RVU_PF_INT);\n-\totx2_base_dbg(\"Irq 0x%\" PRIx64 \"(pf:%d,vf:%d)\", intr, dev->pf, dev->vf);\n-\n-\t/* First process all configuration messages */\n-\totx2_process_msgs(dev, dev->mbox);\n-\n-\t/* Process Uplink messages */\n-\totx2_process_msgs_up(dev, &dev->mbox_up);\n-}\n-\n-static int\n-mbox_register_pf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n-{\n-\tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n-\tint i, rc;\n-\n-\t/* HW clear irq */\n-\tfor (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)\n-\t\totx2_write64(~0ull, dev->bar2 +\n-\t\t\t RVU_PF_VFPF_MBOX_INT_ENA_W1CX(i));\n-\n-\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);\n-\n-\tdev->timer_set = 0;\n-\n-\t/* MBOX interrupt for VF(0...63) <-> PF */\n-\trc = otx2_register_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,\n-\t\t\t RVU_PF_INT_VEC_VFPF_MBOX0);\n-\n-\tif (rc) {\n-\t\totx2_err(\"Fail to register PF(VF0-63) mbox irq\");\n-\t\treturn rc;\n-\t}\n-\t/* MBOX interrupt for VF(64...128) <-> PF */\n-\trc = otx2_register_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,\n-\t\t\t RVU_PF_INT_VEC_VFPF_MBOX1);\n-\n-\tif (rc) {\n-\t\totx2_err(\"Fail to register PF(VF64-128) mbox irq\");\n-\t\treturn rc;\n-\t}\n-\t/* MBOX interrupt AF <-> PF */\n-\trc = otx2_register_irq(intr_handle, otx2_af_pf_mbox_irq,\n-\t\t\t dev, RVU_PF_INT_VEC_AFPF_MBOX);\n-\tif (rc) {\n-\t\totx2_err(\"Fail to register AF<->PF mbox irq\");\n-\t\treturn rc;\n-\t}\n-\n-\t/* HW enable intr */\n-\tfor (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)\n-\t\totx2_write64(~0ull, dev->bar2 +\n-\t\t\tRVU_PF_VFPF_MBOX_INT_ENA_W1SX(i));\n-\n-\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT);\n-\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);\n-\n-\treturn rc;\n-}\n-\n-static int\n-mbox_register_vf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n-{\n-\tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n-\tint rc;\n-\n-\t/* Clear irq */\n-\totx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);\n-\n-\t/* MBOX interrupt PF <-> VF */\n-\trc = otx2_register_irq(intr_handle, otx2_pf_vf_mbox_irq,\n-\t\t\t dev, RVU_VF_INT_VEC_MBOX);\n-\tif (rc) {\n-\t\totx2_err(\"Fail to register PF<->VF mbox irq\");\n-\t\treturn rc;\n-\t}\n-\n-\t/* HW enable intr */\n-\totx2_write64(~0ull, dev->bar2 + RVU_VF_INT);\n-\totx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1S);\n-\n-\treturn rc;\n-}\n-\n-static int\n-mbox_register_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n-{\n-\tif (otx2_dev_is_vf(dev))\n-\t\treturn mbox_register_vf_irq(pci_dev, dev);\n-\telse\n-\t\treturn mbox_register_pf_irq(pci_dev, dev);\n-}\n-\n-static void\n-mbox_unregister_pf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n-{\n-\tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n-\tint i;\n-\n-\t/* HW clear irq */\n-\tfor (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)\n-\t\totx2_write64(~0ull, dev->bar2 +\n-\t\t\t RVU_PF_VFPF_MBOX_INT_ENA_W1CX(i));\n-\n-\totx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);\n-\n-\tdev->timer_set = 0;\n-\n-\trte_eal_alarm_cancel(otx2_vf_pf_mbox_handle_msg, dev);\n-\n-\t/* Unregister the interrupt handler for each vectors */\n-\t/* MBOX interrupt for VF(0...63) <-> PF */\n-\totx2_unregister_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,\n-\t\t\t RVU_PF_INT_VEC_VFPF_MBOX0);\n-\n-\t/* MBOX interrupt for VF(64...128) <-> PF */\n-\totx2_unregister_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,\n-\t\t\t RVU_PF_INT_VEC_VFPF_MBOX1);\n-\n-\t/* MBOX interrupt AF <-> PF */\n-\totx2_unregister_irq(intr_handle, otx2_af_pf_mbox_irq, dev,\n-\t\t\t RVU_PF_INT_VEC_AFPF_MBOX);\n-\n-}\n-\n-static void\n-mbox_unregister_vf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n-{\n-\tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n-\n-\t/* Clear irq */\n-\totx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);\n-\n-\t/* Unregister the interrupt handler */\n-\totx2_unregister_irq(intr_handle, otx2_pf_vf_mbox_irq, dev,\n-\t\t\t RVU_VF_INT_VEC_MBOX);\n-}\n-\n-static void\n-mbox_unregister_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n-{\n-\tif (otx2_dev_is_vf(dev))\n-\t\tmbox_unregister_vf_irq(pci_dev, dev);\n-\telse\n-\t\tmbox_unregister_pf_irq(pci_dev, dev);\n-}\n-\n-static int\n-vf_flr_send_msg(struct otx2_dev *dev, uint16_t vf)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct msg_req *req;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_vf_flr(mbox);\n-\t/* Overwrite pcifunc to indicate VF */\n-\treq->hdr.pcifunc = otx2_pfvf_func(dev->pf, vf);\n-\n-\t/* Sync message in interrupt context */\n-\trc = pf_af_sync_msg(dev, NULL);\n-\tif (rc)\n-\t\totx2_err(\"Failed to send VF FLR mbox msg, rc=%d\", rc);\n-\n-\treturn rc;\n-}\n-\n-static void\n-otx2_pf_vf_flr_irq(void *param)\n-{\n-\tstruct otx2_dev *dev = (struct otx2_dev *)param;\n-\tuint16_t max_vf = 64, vf;\n-\tuintptr_t bar2;\n-\tuint64_t intr;\n-\tint i;\n-\n-\tmax_vf = (dev->maxvf > 0) ? dev->maxvf : 64;\n-\tbar2 = dev->bar2;\n-\n-\totx2_base_dbg(\"FLR VF interrupt: max_vf: %d\", max_vf);\n-\n-\tfor (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) {\n-\t\tintr = otx2_read64(bar2 + RVU_PF_VFFLR_INTX(i));\n-\t\tif (!intr)\n-\t\t\tcontinue;\n-\n-\t\tfor (vf = 0; vf < max_vf; vf++) {\n-\t\t\tif (!(intr & (1ULL << vf)))\n-\t\t\t\tcontinue;\n-\n-\t\t\totx2_base_dbg(\"FLR: i :%d intr: 0x%\" PRIx64 \", vf-%d\",\n-\t\t\t\t i, intr, (64 * i + vf));\n-\t\t\t/* Clear interrupt */\n-\t\t\totx2_write64(BIT_ULL(vf), bar2 + RVU_PF_VFFLR_INTX(i));\n-\t\t\t/* Disable the interrupt */\n-\t\t\totx2_write64(BIT_ULL(vf),\n-\t\t\t\t bar2 + RVU_PF_VFFLR_INT_ENA_W1CX(i));\n-\t\t\t/* Inform AF about VF reset */\n-\t\t\tvf_flr_send_msg(dev, vf);\n-\n-\t\t\t/* Signal FLR finish */\n-\t\t\totx2_write64(BIT_ULL(vf), bar2 + RVU_PF_VFTRPENDX(i));\n-\t\t\t/* Enable interrupt */\n-\t\t\totx2_write64(~0ull,\n-\t\t\t\t bar2 + RVU_PF_VFFLR_INT_ENA_W1SX(i));\n-\t\t}\n-\t}\n-}\n-\n-static int\n-vf_flr_unregister_irqs(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n-{\n-\tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n-\tint i;\n-\n-\totx2_base_dbg(\"Unregister VF FLR interrupts for %s\", pci_dev->name);\n-\n-\t/* HW clear irq */\n-\tfor (i = 0; i < MAX_VFPF_DWORD_BITS; i++)\n-\t\totx2_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INT_ENA_W1CX(i));\n-\n-\totx2_unregister_irq(intr_handle, otx2_pf_vf_flr_irq, dev,\n-\t\t\t RVU_PF_INT_VEC_VFFLR0);\n-\n-\totx2_unregister_irq(intr_handle, otx2_pf_vf_flr_irq, dev,\n-\t\t\t RVU_PF_INT_VEC_VFFLR1);\n-\n-\treturn 0;\n-}\n-\n-static int\n-vf_flr_register_irqs(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n-{\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tint i, rc;\n-\n-\totx2_base_dbg(\"Register VF FLR interrupts for %s\", pci_dev->name);\n-\n-\trc = otx2_register_irq(handle, otx2_pf_vf_flr_irq, dev,\n-\t\t\t RVU_PF_INT_VEC_VFFLR0);\n-\tif (rc)\n-\t\totx2_err(\"Failed to init RVU_PF_INT_VEC_VFFLR0 rc=%d\", rc);\n-\n-\trc = otx2_register_irq(handle, otx2_pf_vf_flr_irq, dev,\n-\t\t\t RVU_PF_INT_VEC_VFFLR1);\n-\tif (rc)\n-\t\totx2_err(\"Failed to init RVU_PF_INT_VEC_VFFLR1 rc=%d\", rc);\n-\n-\t/* Enable HW interrupt */\n-\tfor (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) {\n-\t\totx2_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INTX(i));\n-\t\totx2_write64(~0ull, dev->bar2 + RVU_PF_VFTRPENDX(i));\n-\t\totx2_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INT_ENA_W1SX(i));\n-\t}\n-\treturn 0;\n-}\n-\n-/**\n- * @internal\n- * Get number of active VFs for the given PF device.\n- */\n-int\n-otx2_dev_active_vfs(void *otx2_dev)\n-{\n-\tstruct otx2_dev *dev = otx2_dev;\n-\tint i, count = 0;\n-\n-\tfor (i = 0; i < MAX_VFPF_DWORD_BITS; i++)\n-\t\tcount += __builtin_popcount(dev->active_vfs[i]);\n-\n-\treturn count;\n-}\n-\n-static void\n-otx2_update_vf_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)\n-{\n-\tswitch (pci_dev->id.device_id) {\n-\tcase PCI_DEVID_OCTEONTX2_RVU_PF:\n-\t\tbreak;\n-\tcase PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF:\n-\tcase PCI_DEVID_OCTEONTX2_RVU_NPA_VF:\n-\tcase PCI_DEVID_OCTEONTX2_RVU_CPT_VF:\n-\tcase PCI_DEVID_OCTEONTX2_RVU_AF_VF:\n-\tcase PCI_DEVID_OCTEONTX2_RVU_VF:\n-\tcase PCI_DEVID_OCTEONTX2_RVU_SDP_VF:\n-\t\tdev->hwcap |= OTX2_HWCAP_F_VF;\n-\t\tbreak;\n-\t}\n-}\n-\n-/**\n- * @internal\n- * Initialize the otx2 device\n- */\n-int\n-otx2_dev_priv_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n-{\n-\tint up_direction = MBOX_DIR_PFAF_UP;\n-\tint rc, direction = MBOX_DIR_PFAF;\n-\tuint64_t intr_offset = RVU_PF_INT;\n-\tstruct otx2_dev *dev = otx2_dev;\n-\tuintptr_t bar2, bar4;\n-\tuint64_t bar4_addr;\n-\tvoid *hwbase;\n-\n-\tbar2 = (uintptr_t)pci_dev->mem_resource[2].addr;\n-\tbar4 = (uintptr_t)pci_dev->mem_resource[4].addr;\n-\n-\tif (bar2 == 0 || bar4 == 0) {\n-\t\totx2_err(\"Failed to get pci bars\");\n-\t\trc = -ENODEV;\n-\t\tgoto error;\n-\t}\n-\n-\tdev->node = pci_dev->device.numa_node;\n-\tdev->maxvf = pci_dev->max_vfs;\n-\tdev->bar2 = bar2;\n-\tdev->bar4 = bar4;\n-\n-\totx2_update_vf_hwcap(pci_dev, dev);\n-\n-\tif (otx2_dev_is_vf(dev)) {\n-\t\tdirection = MBOX_DIR_VFPF;\n-\t\tup_direction = MBOX_DIR_VFPF_UP;\n-\t\tintr_offset = RVU_VF_INT;\n-\t}\n-\n-\t/* Initialize the local mbox */\n-\trc = otx2_mbox_init(&dev->mbox_local, bar4, bar2, direction, 1,\n-\t\t\t intr_offset);\n-\tif (rc)\n-\t\tgoto error;\n-\tdev->mbox = &dev->mbox_local;\n-\n-\trc = otx2_mbox_init(&dev->mbox_up, bar4, bar2, up_direction, 1,\n-\t\t\t intr_offset);\n-\tif (rc)\n-\t\tgoto error;\n-\n-\t/* Register mbox interrupts */\n-\trc = mbox_register_irq(pci_dev, dev);\n-\tif (rc)\n-\t\tgoto mbox_fini;\n-\n-\t/* Check the readiness of PF/VF */\n-\trc = otx2_send_ready_msg(dev->mbox, &dev->pf_func);\n-\tif (rc)\n-\t\tgoto mbox_unregister;\n-\n-\tdev->pf = otx2_get_pf(dev->pf_func);\n-\tdev->vf = otx2_get_vf(dev->pf_func);\n-\tmemset(&dev->active_vfs, 0, sizeof(dev->active_vfs));\n-\n-\t/* Found VF devices in a PF device */\n-\tif (pci_dev->max_vfs > 0) {\n-\n-\t\t/* Remap mbox area for all vf's */\n-\t\tbar4_addr = otx2_read64(bar2 + RVU_PF_VF_BAR4_ADDR);\n-\t\tif (bar4_addr == 0) {\n-\t\t\trc = -ENODEV;\n-\t\t\tgoto mbox_fini;\n-\t\t}\n-\n-\t\thwbase = mbox_mem_map(bar4_addr, MBOX_SIZE * pci_dev->max_vfs);\n-\t\tif (hwbase == MAP_FAILED) {\n-\t\t\trc = -ENOMEM;\n-\t\t\tgoto mbox_fini;\n-\t\t}\n-\t\t/* Init mbox object */\n-\t\trc = otx2_mbox_init(&dev->mbox_vfpf, (uintptr_t)hwbase,\n-\t\t\t\t bar2, MBOX_DIR_PFVF, pci_dev->max_vfs,\n-\t\t\t\t intr_offset);\n-\t\tif (rc)\n-\t\t\tgoto iounmap;\n-\n-\t\t/* PF -> VF UP messages */\n-\t\trc = otx2_mbox_init(&dev->mbox_vfpf_up, (uintptr_t)hwbase,\n-\t\t\t\t bar2, MBOX_DIR_PFVF_UP, pci_dev->max_vfs,\n-\t\t\t\t intr_offset);\n-\t\tif (rc)\n-\t\t\tgoto mbox_fini;\n-\t}\n-\n-\t/* Register VF-FLR irq handlers */\n-\tif (otx2_dev_is_pf(dev)) {\n-\t\trc = vf_flr_register_irqs(pci_dev, dev);\n-\t\tif (rc)\n-\t\t\tgoto iounmap;\n-\t}\n-\tdev->mbox_active = 1;\n-\treturn rc;\n-\n-iounmap:\n-\tmbox_mem_unmap(hwbase, MBOX_SIZE * pci_dev->max_vfs);\n-mbox_unregister:\n-\tmbox_unregister_irq(pci_dev, dev);\n-mbox_fini:\n-\totx2_mbox_fini(dev->mbox);\n-\totx2_mbox_fini(&dev->mbox_up);\n-error:\n-\treturn rc;\n-}\n-\n-/**\n- * @internal\n- * Finalize the otx2 device\n- */\n-void\n-otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev)\n-{\n-\tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n-\tstruct otx2_dev *dev = otx2_dev;\n-\tstruct otx2_idev_cfg *idev;\n-\tstruct otx2_mbox *mbox;\n-\n-\t/* Clear references to this pci dev */\n-\tidev = otx2_intra_dev_get_cfg();\n-\tif (idev->npa_lf && idev->npa_lf->pci_dev == pci_dev)\n-\t\tidev->npa_lf = NULL;\n-\n-\tmbox_unregister_irq(pci_dev, dev);\n-\n-\tif (otx2_dev_is_pf(dev))\n-\t\tvf_flr_unregister_irqs(pci_dev, dev);\n-\t/* Release PF - VF */\n-\tmbox = &dev->mbox_vfpf;\n-\tif (mbox->hwbase && mbox->dev)\n-\t\tmbox_mem_unmap((void *)mbox->hwbase,\n-\t\t\t MBOX_SIZE * pci_dev->max_vfs);\n-\totx2_mbox_fini(mbox);\n-\tmbox = &dev->mbox_vfpf_up;\n-\totx2_mbox_fini(mbox);\n-\n-\t/* Release PF - AF */\n-\tmbox = dev->mbox;\n-\totx2_mbox_fini(mbox);\n-\tmbox = &dev->mbox_up;\n-\totx2_mbox_fini(mbox);\n-\tdev->mbox_active = 0;\n-\n-\t/* Disable MSIX vectors */\n-\totx2_disable_irqs(intr_handle);\n-}\ndiff --git a/drivers/common/octeontx2/otx2_dev.h b/drivers/common/octeontx2/otx2_dev.h\ndeleted file mode 100644\nindex d5b2b0d9af..0000000000\n--- a/drivers/common/octeontx2/otx2_dev.h\n+++ /dev/null\n@@ -1,161 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_DEV_H\n-#define _OTX2_DEV_H\n-\n-#include <rte_bus_pci.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_irq.h\"\n-#include \"otx2_mbox.h\"\n-#include \"otx2_mempool.h\"\n-\n-/* Common HWCAP flags. Use from LSB bits */\n-#define OTX2_HWCAP_F_VF\t\tBIT_ULL(8) /* VF device */\n-#define otx2_dev_is_vf(dev)\t(dev->hwcap & OTX2_HWCAP_F_VF)\n-#define otx2_dev_is_pf(dev)\t(!(dev->hwcap & OTX2_HWCAP_F_VF))\n-#define otx2_dev_is_lbk(dev)\t((dev->hwcap & OTX2_HWCAP_F_VF) && \\\n-\t\t\t\t (dev->tx_chan_base < 0x700))\n-#define otx2_dev_revid(dev)\t(dev->hwcap & 0xFF)\n-#define otx2_dev_is_sdp(dev)\t(dev->sdp_link)\n-\n-#define otx2_dev_is_vf_or_sdp(dev)\t\t\t\t\\\n-\t(otx2_dev_is_vf(dev) || otx2_dev_is_sdp(dev))\n-\n-#define otx2_dev_is_A0(dev)\t\t\t\t\t\\\n-\t((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) &&\t\\\n-\t (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0))\n-#define otx2_dev_is_Ax(dev)\t\t\t\t\t\\\n-\t((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0))\n-\n-#define otx2_dev_is_95xx_A0(dev)\t\t\t\t\\\n-\t((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) &&\t\\\n-\t (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0) &&\t\\\n-\t (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x1))\n-#define otx2_dev_is_95xx_Ax(dev)\t\t\t\t\\\n-\t((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) &&\t\\\n-\t (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x1))\n-\n-#define otx2_dev_is_96xx_A0(dev)\t\t\t\t\\\n-\t((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) &&\t\\\n-\t (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0) &&\t\\\n-\t (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x0))\n-#define otx2_dev_is_96xx_Ax(dev)\t\t\t\t\\\n-\t((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) &&\t\\\n-\t (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x0))\n-\n-#define otx2_dev_is_96xx_Cx(dev)\t\t\t\t\\\n-\t((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x2) &&\t\\\n-\t (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x0))\n-\n-#define otx2_dev_is_96xx_C0(dev)\t\t\t\t\\\n-\t((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x2) &&\t\\\n-\t (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0) &&\t\\\n-\t (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x0))\n-\n-#define otx2_dev_is_98xx(dev) \\\n-\t (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x3)\n-\n-struct otx2_dev;\n-\n-/* Link status update callback */\n-typedef void (*otx2_link_status_update_t)(struct otx2_dev *dev,\n-\t\t\t\t struct cgx_link_user_info *link);\n-/* PTP info callback */\n-typedef int (*otx2_ptp_info_t)(struct otx2_dev *dev, bool ptp_en);\n-/* Link status get callback */\n-typedef void (*otx2_link_status_get_t)(struct otx2_dev *dev,\n-\t\t\t\t struct cgx_link_user_info *link);\n-\n-struct otx2_dev_ops {\n-\totx2_link_status_update_t link_status_update;\n-\totx2_ptp_info_t ptp_info_update;\n-\totx2_link_status_get_t link_status_get;\n-};\n-\n-#define OTX2_DEV\t\t\t\t\t\\\n-\tint node __rte_cache_aligned;\t\t\t\\\n-\tuint16_t pf;\t\t\t\t\t\\\n-\tint16_t vf;\t\t\t\t\t\\\n-\tuint16_t pf_func;\t\t\t\t\\\n-\tuint8_t mbox_active;\t\t\t\t\\\n-\tbool drv_inited;\t\t\t\t\\\n-\tuint64_t active_vfs[MAX_VFPF_DWORD_BITS];\t\\\n-\tuintptr_t bar2;\t\t\t\t\t\\\n-\tuintptr_t bar4;\t\t\t\t\t\\\n-\tstruct otx2_mbox mbox_local;\t\t\t\\\n-\tstruct otx2_mbox mbox_up;\t\t\t\\\n-\tstruct otx2_mbox mbox_vfpf;\t\t\t\\\n-\tstruct otx2_mbox mbox_vfpf_up;\t\t\t\\\n-\totx2_intr_t intr;\t\t\t\t\\\n-\tint timer_set;\t/* ~0 : no alarm handling */\t\\\n-\tuint64_t hwcap;\t\t\t\t\t\\\n-\tstruct otx2_npa_lf npalf;\t\t\t\\\n-\tstruct otx2_mbox *mbox;\t\t\t\t\\\n-\tuint16_t maxvf;\t\t\t\t\t\\\n-\tconst struct otx2_dev_ops *ops\n-\n-struct otx2_dev {\n-\tOTX2_DEV;\n-};\n-\n-__rte_internal\n-int otx2_dev_priv_init(struct rte_pci_device *pci_dev, void *otx2_dev);\n-\n-/* Common dev init and fini routines */\n-\n-static __rte_always_inline int\n-otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n-{\n-\tstruct otx2_dev *dev = otx2_dev;\n-\tuint8_t rev_id;\n-\tint rc;\n-\n-\trc = rte_pci_read_config(pci_dev, &rev_id,\n-\t\t\t\t 1, RVU_PCI_REVISION_ID);\n-\tif (rc != 1) {\n-\t\totx2_err(\"Failed to read pci revision id, rc=%d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\tdev->hwcap = rev_id;\n-\treturn otx2_dev_priv_init(pci_dev, otx2_dev);\n-}\n-\n-__rte_internal\n-void otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev);\n-__rte_internal\n-int otx2_dev_active_vfs(void *otx2_dev);\n-\n-#define RVU_PFVF_PF_SHIFT\t10\n-#define RVU_PFVF_PF_MASK\t0x3F\n-#define RVU_PFVF_FUNC_SHIFT\t0\n-#define RVU_PFVF_FUNC_MASK\t0x3FF\n-\n-static inline int\n-otx2_get_vf(uint16_t pf_func)\n-{\n-\treturn (((pf_func >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK) - 1);\n-}\n-\n-static inline int\n-otx2_get_pf(uint16_t pf_func)\n-{\n-\treturn (pf_func >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;\n-}\n-\n-static inline int\n-otx2_pfvf_func(int pf, int vf)\n-{\n-\treturn (pf << RVU_PFVF_PF_SHIFT) | ((vf << RVU_PFVF_FUNC_SHIFT) + 1);\n-}\n-\n-static inline int\n-otx2_is_afvf(uint16_t pf_func)\n-{\n-\treturn !(pf_func & ~RVU_PFVF_FUNC_MASK);\n-}\n-\n-#endif /* _OTX2_DEV_H */\ndiff --git a/drivers/common/octeontx2/otx2_io_arm64.h b/drivers/common/octeontx2/otx2_io_arm64.h\ndeleted file mode 100644\nindex 34268e3af3..0000000000\n--- a/drivers/common/octeontx2/otx2_io_arm64.h\n+++ /dev/null\n@@ -1,114 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_IO_ARM64_H_\n-#define _OTX2_IO_ARM64_H_\n-\n-#define otx2_load_pair(val0, val1, addr) ({\t\t\\\n-\tasm volatile(\t\t\t\t\t\\\n-\t\"ldp %x[x0], %x[x1], [%x[p1]]\"\t\t\t\\\n-\t:[x0]\"=r\"(val0), [x1]\"=r\"(val1)\t\t\t\\\n-\t:[p1]\"r\"(addr)\t\t\t\t\t\\\n-\t); })\n-\n-#define otx2_store_pair(val0, val1, addr) ({\t\t\\\n-\tasm volatile(\t\t\t\t\t\\\n-\t\"stp %x[x0], %x[x1], [%x[p1],#0]!\"\t\t\\\n-\t::[x0]\"r\"(val0), [x1]\"r\"(val1), [p1]\"r\"(addr)\t\\\n-\t); })\n-\n-#define otx2_prefetch_store_keep(ptr) ({\\\n-\tasm volatile(\"prfm pstl1keep, [%x0]\\n\" : : \"r\" (ptr)); })\n-\n-#if defined(__ARM_FEATURE_SVE)\n-#define __LSE_PREAMBLE \" .cpu generic+lse+sve\\n\"\n-#else\n-#define __LSE_PREAMBLE \" .cpu generic+lse\\n\"\n-#endif\n-\n-static __rte_always_inline uint64_t\n-otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr)\n-{\n-\tuint64_t result;\n-\n-\t/* Atomic add with no ordering */\n-\tasm volatile (\n-\t\t__LSE_PREAMBLE\n-\t\t\"ldadd %x[i], %x[r], [%[b]]\"\n-\t\t: [r] \"=r\" (result), \"+m\" (*ptr)\n-\t\t: [i] \"r\" (incr), [b] \"r\" (ptr)\n-\t\t: \"memory\");\n-\treturn result;\n-}\n-\n-static __rte_always_inline uint64_t\n-otx2_atomic64_add_sync(int64_t incr, int64_t *ptr)\n-{\n-\tuint64_t result;\n-\n-\t/* Atomic add with ordering */\n-\tasm volatile (\n-\t\t__LSE_PREAMBLE\n-\t\t\"ldadda %x[i], %x[r], [%[b]]\"\n-\t\t: [r] \"=r\" (result), \"+m\" (*ptr)\n-\t\t: [i] \"r\" (incr), [b] \"r\" (ptr)\n-\t\t: \"memory\");\n-\treturn result;\n-}\n-\n-static __rte_always_inline uint64_t\n-otx2_lmt_submit(rte_iova_t io_address)\n-{\n-\tuint64_t result;\n-\n-\tasm volatile (\n-\t\t__LSE_PREAMBLE\n-\t\t\"ldeor xzr,%x[rf],[%[rs]]\" :\n-\t\t [rf] \"=r\"(result): [rs] \"r\"(io_address));\n-\treturn result;\n-}\n-\n-static __rte_always_inline uint64_t\n-otx2_lmt_submit_release(rte_iova_t io_address)\n-{\n-\tuint64_t result;\n-\n-\tasm volatile (\n-\t\t__LSE_PREAMBLE\n-\t\t\"ldeorl xzr,%x[rf],[%[rs]]\" :\n-\t\t [rf] \"=r\"(result) : [rs] \"r\"(io_address));\n-\treturn result;\n-}\n-\n-static __rte_always_inline void\n-otx2_lmt_mov(void *out, const void *in, const uint32_t lmtext)\n-{\n-\tvolatile const __uint128_t *src128 = (const __uint128_t *)in;\n-\tvolatile __uint128_t *dst128 = (__uint128_t *)out;\n-\tdst128[0] = src128[0];\n-\tdst128[1] = src128[1];\n-\t/* lmtext receives following value:\n-\t * 1: NIX_SUBDC_EXT needed i.e. tx vlan case\n-\t * 2: NIX_SUBDC_EXT + NIX_SUBDC_MEM i.e. tstamp case\n-\t */\n-\tif (lmtext) {\n-\t\tdst128[2] = src128[2];\n-\t\tif (lmtext > 1)\n-\t\t\tdst128[3] = src128[3];\n-\t}\n-}\n-\n-static __rte_always_inline void\n-otx2_lmt_mov_seg(void *out, const void *in, const uint16_t segdw)\n-{\n-\tvolatile const __uint128_t *src128 = (const __uint128_t *)in;\n-\tvolatile __uint128_t *dst128 = (__uint128_t *)out;\n-\tuint8_t i;\n-\n-\tfor (i = 0; i < segdw; i++)\n-\t\tdst128[i] = src128[i];\n-}\n-\n-#undef __LSE_PREAMBLE\n-#endif /* _OTX2_IO_ARM64_H_ */\ndiff --git a/drivers/common/octeontx2/otx2_io_generic.h b/drivers/common/octeontx2/otx2_io_generic.h\ndeleted file mode 100644\nindex 3436a6c3d5..0000000000\n--- a/drivers/common/octeontx2/otx2_io_generic.h\n+++ /dev/null\n@@ -1,75 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_IO_GENERIC_H_\n-#define _OTX2_IO_GENERIC_H_\n-\n-#include <string.h>\n-\n-#define otx2_load_pair(val0, val1, addr)\t\t\t\\\n-do {\t\t\t\t\t\t\t\t\\\n-\tval0 = rte_read64_relaxed((void *)(addr));\t\t\\\n-\tval1 = rte_read64_relaxed((uint8_t *)(addr) + 8);\t\\\n-} while (0)\n-\n-#define otx2_store_pair(val0, val1, addr)\t\t\t\\\n-do {\t\t\t\t\t\t\t\t\\\n-\trte_write64_relaxed(val0, (void *)(addr));\t\t\\\n-\trte_write64_relaxed(val1, (((uint8_t *)(addr)) + 8));\t\\\n-} while (0)\n-\n-#define otx2_prefetch_store_keep(ptr) do {} while (0)\n-\n-static inline uint64_t\n-otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr)\n-{\n-\tRTE_SET_USED(ptr);\n-\tRTE_SET_USED(incr);\n-\n-\treturn 0;\n-}\n-\n-static inline uint64_t\n-otx2_atomic64_add_sync(int64_t incr, int64_t *ptr)\n-{\n-\tRTE_SET_USED(ptr);\n-\tRTE_SET_USED(incr);\n-\n-\treturn 0;\n-}\n-\n-static inline int64_t\n-otx2_lmt_submit(uint64_t io_address)\n-{\n-\tRTE_SET_USED(io_address);\n-\n-\treturn 0;\n-}\n-\n-static inline int64_t\n-otx2_lmt_submit_release(uint64_t io_address)\n-{\n-\tRTE_SET_USED(io_address);\n-\n-\treturn 0;\n-}\n-\n-static __rte_always_inline void\n-otx2_lmt_mov(void *out, const void *in, const uint32_t lmtext)\n-{\n-\t/* Copy four words if lmtext = 0\n-\t * six words if lmtext = 1\n-\t * eight words if lmtext =2\n-\t */\n-\tmemcpy(out, in, (4 + (2 * lmtext)) * sizeof(uint64_t));\n-}\n-\n-static __rte_always_inline void\n-otx2_lmt_mov_seg(void *out, const void *in, const uint16_t segdw)\n-{\n-\tRTE_SET_USED(out);\n-\tRTE_SET_USED(in);\n-\tRTE_SET_USED(segdw);\n-}\n-#endif /* _OTX2_IO_GENERIC_H_ */\ndiff --git a/drivers/common/octeontx2/otx2_irq.c b/drivers/common/octeontx2/otx2_irq.c\ndeleted file mode 100644\nindex 93fc95c0e1..0000000000\n--- a/drivers/common/octeontx2/otx2_irq.c\n+++ /dev/null\n@@ -1,288 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_alarm.h>\n-#include <rte_common.h>\n-#include <rte_eal.h>\n-#include <rte_interrupts.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_irq.h\"\n-\n-#ifdef RTE_EAL_VFIO\n-\n-#include <inttypes.h>\n-#include <linux/vfio.h>\n-#include <sys/eventfd.h>\n-#include <sys/ioctl.h>\n-#include <unistd.h>\n-\n-#define MAX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID\n-#define MSIX_IRQ_SET_BUF_LEN (sizeof(struct vfio_irq_set) + \\\n-\t\t\t sizeof(int) * (MAX_INTR_VEC_ID))\n-\n-static int\n-irq_get_info(struct rte_intr_handle *intr_handle)\n-{\n-\tstruct vfio_irq_info irq = { .argsz = sizeof(irq) };\n-\tint rc, vfio_dev_fd;\n-\n-\tirq.index = VFIO_PCI_MSIX_IRQ_INDEX;\n-\n-\tvfio_dev_fd = rte_intr_dev_fd_get(intr_handle);\n-\trc = ioctl(vfio_dev_fd, VFIO_DEVICE_GET_IRQ_INFO, &irq);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to get IRQ info rc=%d errno=%d\", rc, errno);\n-\t\treturn rc;\n-\t}\n-\n-\totx2_base_dbg(\"Flags=0x%x index=0x%x count=0x%x max_intr_vec_id=0x%x\",\n-\t\t irq.flags, irq.index, irq.count, MAX_INTR_VEC_ID);\n-\n-\tif (irq.count > MAX_INTR_VEC_ID) {\n-\t\totx2_err(\"HW max=%d > MAX_INTR_VEC_ID: %d\",\n-\t\t\t rte_intr_max_intr_get(intr_handle),\n-\t\t\t MAX_INTR_VEC_ID);\n-\t\tif (rte_intr_max_intr_set(intr_handle, MAX_INTR_VEC_ID))\n-\t\t\treturn -1;\n-\t} else {\n-\t\tif (rte_intr_max_intr_set(intr_handle, irq.count))\n-\t\t\treturn -1;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-irq_config(struct rte_intr_handle *intr_handle, unsigned int vec)\n-{\n-\tchar irq_set_buf[MSIX_IRQ_SET_BUF_LEN];\n-\tstruct vfio_irq_set *irq_set;\n-\tint len, rc, vfio_dev_fd;\n-\tint32_t *fd_ptr;\n-\n-\tif (vec > (uint32_t)rte_intr_max_intr_get(intr_handle)) {\n-\t\totx2_err(\"vector=%d greater than max_intr=%d\", vec,\n-\t\t\t rte_intr_max_intr_get(intr_handle));\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tlen = sizeof(struct vfio_irq_set) + sizeof(int32_t);\n-\n-\tirq_set = (struct vfio_irq_set *)irq_set_buf;\n-\tirq_set->argsz = len;\n-\n-\tirq_set->start = vec;\n-\tirq_set->count = 1;\n-\tirq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |\n-\t\t\tVFIO_IRQ_SET_ACTION_TRIGGER;\n-\tirq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;\n-\n-\t/* Use vec fd to set interrupt vectors */\n-\tfd_ptr = (int32_t *)&irq_set->data[0];\n-\tfd_ptr[0] = rte_intr_efds_index_get(intr_handle, vec);\n-\n-\tvfio_dev_fd = rte_intr_dev_fd_get(intr_handle);\n-\trc = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n-\tif (rc)\n-\t\totx2_err(\"Failed to set_irqs vector=0x%x rc=%d\", vec, rc);\n-\n-\treturn rc;\n-}\n-\n-static int\n-irq_init(struct rte_intr_handle *intr_handle)\n-{\n-\tchar irq_set_buf[MSIX_IRQ_SET_BUF_LEN];\n-\tstruct vfio_irq_set *irq_set;\n-\tint len, rc, vfio_dev_fd;\n-\tint32_t *fd_ptr;\n-\tuint32_t i;\n-\n-\tif (rte_intr_max_intr_get(intr_handle) > MAX_INTR_VEC_ID) {\n-\t\totx2_err(\"Max_intr=%d greater than MAX_INTR_VEC_ID=%d\",\n-\t\t\t rte_intr_max_intr_get(intr_handle),\n-\t\t\t MAX_INTR_VEC_ID);\n-\t\treturn -ERANGE;\n-\t}\n-\n-\tlen = sizeof(struct vfio_irq_set) +\n-\t\tsizeof(int32_t) * rte_intr_max_intr_get(intr_handle);\n-\n-\tirq_set = (struct vfio_irq_set *)irq_set_buf;\n-\tirq_set->argsz = len;\n-\tirq_set->start = 0;\n-\tirq_set->count = rte_intr_max_intr_get(intr_handle);\n-\tirq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |\n-\t\t\tVFIO_IRQ_SET_ACTION_TRIGGER;\n-\tirq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;\n-\n-\tfd_ptr = (int32_t *)&irq_set->data[0];\n-\tfor (i = 0; i < irq_set->count; i++)\n-\t\tfd_ptr[i] = -1;\n-\n-\tvfio_dev_fd = rte_intr_dev_fd_get(intr_handle);\n-\trc = ioctl(vfio_dev_fd, VFIO_DEVICE_SET_IRQS, irq_set);\n-\tif (rc)\n-\t\totx2_err(\"Failed to set irqs vector rc=%d\", rc);\n-\n-\treturn rc;\n-}\n-\n-/**\n- * @internal\n- * Disable IRQ\n- */\n-int\n-otx2_disable_irqs(struct rte_intr_handle *intr_handle)\n-{\n-\t/* Clear max_intr to indicate re-init next time */\n-\tif (rte_intr_max_intr_set(intr_handle, 0))\n-\t\treturn -1;\n-\treturn rte_intr_disable(intr_handle);\n-}\n-\n-/**\n- * @internal\n- * Register IRQ\n- */\n-int\n-otx2_register_irq(struct rte_intr_handle *intr_handle,\n-\t\t rte_intr_callback_fn cb, void *data, unsigned int vec)\n-{\n-\tstruct rte_intr_handle *tmp_handle;\n-\tuint32_t nb_efd, tmp_nb_efd;\n-\tint rc, fd;\n-\n-\t/* If no max_intr read from VFIO */\n-\tif (rte_intr_max_intr_get(intr_handle) == 0) {\n-\t\tirq_get_info(intr_handle);\n-\t\tirq_init(intr_handle);\n-\t}\n-\n-\tif (vec > (uint32_t)rte_intr_max_intr_get(intr_handle)) {\n-\t\totx2_err(\"Vector=%d greater than max_intr=%d\", vec,\n-\t\t\trte_intr_max_intr_get(intr_handle));\n-\t\treturn -EINVAL;\n-\t}\n-\n-\ttmp_handle = intr_handle;\n-\t/* Create new eventfd for interrupt vector */\n-\tfd = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC);\n-\tif (fd == -1)\n-\t\treturn -ENODEV;\n-\n-\tif (rte_intr_fd_set(tmp_handle, fd))\n-\t\treturn errno;\n-\n-\t/* Register vector interrupt callback */\n-\trc = rte_intr_callback_register(tmp_handle, cb, data);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to register vector:0x%x irq callback.\", vec);\n-\t\treturn rc;\n-\t}\n-\n-\trte_intr_efds_index_set(intr_handle, vec, fd);\n-\tnb_efd = (vec > (uint32_t)rte_intr_nb_efd_get(intr_handle)) ?\n-\t\tvec : (uint32_t)rte_intr_nb_efd_get(intr_handle);\n-\trte_intr_nb_efd_set(intr_handle, nb_efd);\n-\n-\ttmp_nb_efd = rte_intr_nb_efd_get(intr_handle) + 1;\n-\tif (tmp_nb_efd > (uint32_t)rte_intr_max_intr_get(intr_handle))\n-\t\trte_intr_max_intr_set(intr_handle, tmp_nb_efd);\n-\n-\totx2_base_dbg(\"Enable vector:0x%x for vfio (efds: %d, max:%d)\", vec,\n-\t\t rte_intr_nb_efd_get(intr_handle),\n-\t\t rte_intr_max_intr_get(intr_handle));\n-\n-\t/* Enable MSIX vectors to VFIO */\n-\treturn irq_config(intr_handle, vec);\n-}\n-\n-/**\n- * @internal\n- * Unregister IRQ\n- */\n-void\n-otx2_unregister_irq(struct rte_intr_handle *intr_handle,\n-\t\t rte_intr_callback_fn cb, void *data, unsigned int vec)\n-{\n-\tstruct rte_intr_handle *tmp_handle;\n-\tuint8_t retries = 5; /* 5 ms */\n-\tint rc, fd;\n-\n-\tif (vec > (uint32_t)rte_intr_max_intr_get(intr_handle)) {\n-\t\totx2_err(\"Error unregistering MSI-X interrupts vec:%d > %d\",\n-\t\t\t vec, rte_intr_max_intr_get(intr_handle));\n-\t\treturn;\n-\t}\n-\n-\ttmp_handle = intr_handle;\n-\tfd = rte_intr_efds_index_get(intr_handle, vec);\n-\tif (fd == -1)\n-\t\treturn;\n-\n-\tif (rte_intr_fd_set(tmp_handle, fd))\n-\t\treturn;\n-\n-\tdo {\n-\t\t/* Un-register callback func from platform lib */\n-\t\trc = rte_intr_callback_unregister(tmp_handle, cb, data);\n-\t\t/* Retry only if -EAGAIN */\n-\t\tif (rc != -EAGAIN)\n-\t\t\tbreak;\n-\t\trte_delay_ms(1);\n-\t\tretries--;\n-\t} while (retries);\n-\n-\tif (rc < 0) {\n-\t\totx2_err(\"Error unregistering MSI-X vec %d cb, rc=%d\", vec, rc);\n-\t\treturn;\n-\t}\n-\n-\totx2_base_dbg(\"Disable vector:0x%x for vfio (efds: %d, max:%d)\", vec,\n-\t\t rte_intr_nb_efd_get(intr_handle),\n-\t\t rte_intr_max_intr_get(intr_handle));\n-\n-\tif (rte_intr_efds_index_get(intr_handle, vec) != -1)\n-\t\tclose(rte_intr_efds_index_get(intr_handle, vec));\n-\t/* Disable MSIX vectors from VFIO */\n-\trte_intr_efds_index_set(intr_handle, vec, -1);\n-\tirq_config(intr_handle, vec);\n-}\n-\n-#else\n-\n-/**\n- * @internal\n- * Register IRQ\n- */\n-int otx2_register_irq(__rte_unused struct rte_intr_handle *intr_handle,\n-\t\t __rte_unused rte_intr_callback_fn cb,\n-\t\t __rte_unused void *data, __rte_unused unsigned int vec)\n-{\n-\treturn -ENOTSUP;\n-}\n-\n-\n-/**\n- * @internal\n- * Unregister IRQ\n- */\n-void otx2_unregister_irq(__rte_unused struct rte_intr_handle *intr_handle,\n-\t\t\t __rte_unused rte_intr_callback_fn cb,\n-\t\t\t __rte_unused void *data, __rte_unused unsigned int vec)\n-{\n-}\n-\n-/**\n- * @internal\n- * Disable IRQ\n- */\n-int otx2_disable_irqs(__rte_unused struct rte_intr_handle *intr_handle)\n-{\n-\treturn -ENOTSUP;\n-}\n-\n-#endif /* RTE_EAL_VFIO */\ndiff --git a/drivers/common/octeontx2/otx2_irq.h b/drivers/common/octeontx2/otx2_irq.h\ndeleted file mode 100644\nindex 0683cf5543..0000000000\n--- a/drivers/common/octeontx2/otx2_irq.h\n+++ /dev/null\n@@ -1,28 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_IRQ_H_\n-#define _OTX2_IRQ_H_\n-\n-#include <rte_pci.h>\n-#include <rte_interrupts.h>\n-\n-#include \"otx2_common.h\"\n-\n-typedef struct {\n-/* 128 devices translate to two 64 bits dwords */\n-#define MAX_VFPF_DWORD_BITS 2\n-\tuint64_t bits[MAX_VFPF_DWORD_BITS];\n-} otx2_intr_t;\n-\n-__rte_internal\n-int otx2_register_irq(struct rte_intr_handle *intr_handle,\n-\t\t rte_intr_callback_fn cb, void *data, unsigned int vec);\n-__rte_internal\n-void otx2_unregister_irq(struct rte_intr_handle *intr_handle,\n-\t\t\t rte_intr_callback_fn cb, void *data, unsigned int vec);\n-__rte_internal\n-int otx2_disable_irqs(struct rte_intr_handle *intr_handle);\n-\n-#endif /* _OTX2_IRQ_H_ */\ndiff --git a/drivers/common/octeontx2/otx2_mbox.c b/drivers/common/octeontx2/otx2_mbox.c\ndeleted file mode 100644\nindex 6df1e8ea63..0000000000\n--- a/drivers/common/octeontx2/otx2_mbox.c\n+++ /dev/null\n@@ -1,465 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <errno.h>\n-#include <stdio.h>\n-#include <stdlib.h>\n-#include <string.h>\n-\n-#include <rte_atomic.h>\n-#include <rte_cycles.h>\n-#include <rte_malloc.h>\n-\n-#include \"otx2_mbox.h\"\n-#include \"otx2_dev.h\"\n-\n-#define RVU_AF_AFPF_MBOX0\t(0x02000)\n-#define RVU_AF_AFPF_MBOX1\t(0x02008)\n-\n-#define RVU_PF_PFAF_MBOX0\t(0xC00)\n-#define RVU_PF_PFAF_MBOX1\t(0xC08)\n-\n-#define RVU_PF_VFX_PFVF_MBOX0\t(0x0000)\n-#define RVU_PF_VFX_PFVF_MBOX1\t(0x0008)\n-\n-#define\tRVU_VF_VFPF_MBOX0\t(0x0000)\n-#define\tRVU_VF_VFPF_MBOX1\t(0x0008)\n-\n-static inline uint16_t\n-msgs_offset(void)\n-{\n-\treturn RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n-}\n-\n-void\n-otx2_mbox_fini(struct otx2_mbox *mbox)\n-{\n-\tmbox->reg_base = 0;\n-\tmbox->hwbase = 0;\n-\trte_free(mbox->dev);\n-\tmbox->dev = NULL;\n-}\n-\n-void\n-otx2_mbox_reset(struct otx2_mbox *mbox, int devid)\n-{\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n-\tstruct mbox_hdr *tx_hdr =\n-\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->tx_start);\n-\tstruct mbox_hdr *rx_hdr =\n-\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n-\n-\trte_spinlock_lock(&mdev->mbox_lock);\n-\tmdev->msg_size = 0;\n-\tmdev->rsp_size = 0;\n-\ttx_hdr->msg_size = 0;\n-\ttx_hdr->num_msgs = 0;\n-\trx_hdr->msg_size = 0;\n-\trx_hdr->num_msgs = 0;\n-\trte_spinlock_unlock(&mdev->mbox_lock);\n-}\n-\n-int\n-otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,\n-\t int direction, int ndevs, uint64_t intr_offset)\n-{\n-\tstruct otx2_mbox_dev *mdev;\n-\tint devid;\n-\n-\tmbox->intr_offset = intr_offset;\n-\tmbox->reg_base = reg_base;\n-\tmbox->hwbase = hwbase;\n-\n-\tswitch (direction) {\n-\tcase MBOX_DIR_AFPF:\n-\tcase MBOX_DIR_PFVF:\n-\t\tmbox->tx_start = MBOX_DOWN_TX_START;\n-\t\tmbox->rx_start = MBOX_DOWN_RX_START;\n-\t\tmbox->tx_size = MBOX_DOWN_TX_SIZE;\n-\t\tmbox->rx_size = MBOX_DOWN_RX_SIZE;\n-\t\tbreak;\n-\tcase MBOX_DIR_PFAF:\n-\tcase MBOX_DIR_VFPF:\n-\t\tmbox->tx_start = MBOX_DOWN_RX_START;\n-\t\tmbox->rx_start = MBOX_DOWN_TX_START;\n-\t\tmbox->tx_size = MBOX_DOWN_RX_SIZE;\n-\t\tmbox->rx_size = MBOX_DOWN_TX_SIZE;\n-\t\tbreak;\n-\tcase MBOX_DIR_AFPF_UP:\n-\tcase MBOX_DIR_PFVF_UP:\n-\t\tmbox->tx_start = MBOX_UP_TX_START;\n-\t\tmbox->rx_start = MBOX_UP_RX_START;\n-\t\tmbox->tx_size = MBOX_UP_TX_SIZE;\n-\t\tmbox->rx_size = MBOX_UP_RX_SIZE;\n-\t\tbreak;\n-\tcase MBOX_DIR_PFAF_UP:\n-\tcase MBOX_DIR_VFPF_UP:\n-\t\tmbox->tx_start = MBOX_UP_RX_START;\n-\t\tmbox->rx_start = MBOX_UP_TX_START;\n-\t\tmbox->tx_size = MBOX_UP_RX_SIZE;\n-\t\tmbox->rx_size = MBOX_UP_TX_SIZE;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tswitch (direction) {\n-\tcase MBOX_DIR_AFPF:\n-\tcase MBOX_DIR_AFPF_UP:\n-\t\tmbox->trigger = RVU_AF_AFPF_MBOX0;\n-\t\tmbox->tr_shift = 4;\n-\t\tbreak;\n-\tcase MBOX_DIR_PFAF:\n-\tcase MBOX_DIR_PFAF_UP:\n-\t\tmbox->trigger = RVU_PF_PFAF_MBOX1;\n-\t\tmbox->tr_shift = 0;\n-\t\tbreak;\n-\tcase MBOX_DIR_PFVF:\n-\tcase MBOX_DIR_PFVF_UP:\n-\t\tmbox->trigger = RVU_PF_VFX_PFVF_MBOX0;\n-\t\tmbox->tr_shift = 12;\n-\t\tbreak;\n-\tcase MBOX_DIR_VFPF:\n-\tcase MBOX_DIR_VFPF_UP:\n-\t\tmbox->trigger = RVU_VF_VFPF_MBOX1;\n-\t\tmbox->tr_shift = 0;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tmbox->dev = rte_zmalloc(\"mbox dev\",\n-\t\t\t\tndevs * sizeof(struct otx2_mbox_dev),\n-\t\t\t\tOTX2_ALIGN);\n-\tif (!mbox->dev) {\n-\t\totx2_mbox_fini(mbox);\n-\t\treturn -ENOMEM;\n-\t}\n-\tmbox->ndevs = ndevs;\n-\tfor (devid = 0; devid < ndevs; devid++) {\n-\t\tmdev = &mbox->dev[devid];\n-\t\tmdev->mbase = (void *)(mbox->hwbase + (devid * MBOX_SIZE));\n-\t\trte_spinlock_init(&mdev->mbox_lock);\n-\t\t/* Init header to reset value */\n-\t\totx2_mbox_reset(mbox, devid);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-/**\n- * @internal\n- * Allocate a message response\n- */\n-struct mbox_msghdr *\n-otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid, int size,\n-\t\t\tint size_rsp)\n-{\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n-\tstruct mbox_msghdr *msghdr = NULL;\n-\n-\trte_spinlock_lock(&mdev->mbox_lock);\n-\tsize = RTE_ALIGN(size, MBOX_MSG_ALIGN);\n-\tsize_rsp = RTE_ALIGN(size_rsp, MBOX_MSG_ALIGN);\n-\t/* Check if there is space in mailbox */\n-\tif ((mdev->msg_size + size) > mbox->tx_size - msgs_offset())\n-\t\tgoto exit;\n-\tif ((mdev->rsp_size + size_rsp) > mbox->rx_size - msgs_offset())\n-\t\tgoto exit;\n-\tif (mdev->msg_size == 0)\n-\t\tmdev->num_msgs = 0;\n-\tmdev->num_msgs++;\n-\n-\tmsghdr = (struct mbox_msghdr *)(((uintptr_t)mdev->mbase +\n-\t\t\tmbox->tx_start + msgs_offset() + mdev->msg_size));\n-\n-\t/* Clear the whole msg region */\n-\totx2_mbox_memset(msghdr, 0, sizeof(*msghdr) + size);\n-\t/* Init message header with reset values */\n-\tmsghdr->ver = OTX2_MBOX_VERSION;\n-\tmdev->msg_size += size;\n-\tmdev->rsp_size += size_rsp;\n-\tmsghdr->next_msgoff = mdev->msg_size + msgs_offset();\n-exit:\n-\trte_spinlock_unlock(&mdev->mbox_lock);\n-\n-\treturn msghdr;\n-}\n-\n-/**\n- * @internal\n- * Send a mailbox message\n- */\n-void\n-otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid)\n-{\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n-\tstruct mbox_hdr *tx_hdr =\n-\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->tx_start);\n-\tstruct mbox_hdr *rx_hdr =\n-\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);\n-\n-\t/* Reset header for next messages */\n-\ttx_hdr->msg_size = mdev->msg_size;\n-\tmdev->msg_size = 0;\n-\tmdev->rsp_size = 0;\n-\tmdev->msgs_acked = 0;\n-\n-\t/* num_msgs != 0 signals to the peer that the buffer has a number of\n-\t * messages. So this should be written after copying txmem\n-\t */\n-\ttx_hdr->num_msgs = mdev->num_msgs;\n-\trx_hdr->num_msgs = 0;\n-\n-\t/* Sync mbox data into memory */\n-\trte_wmb();\n-\n-\t/* The interrupt should be fired after num_msgs is written\n-\t * to the shared memory\n-\t */\n-\trte_write64(1, (volatile void *)(mbox->reg_base +\n-\t\t(mbox->trigger | (devid << mbox->tr_shift))));\n-}\n-\n-/**\n- * @internal\n- * Wait and get mailbox response\n- */\n-int\n-otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, void **msg)\n-{\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n-\tstruct mbox_msghdr *msghdr;\n-\tuint64_t offset;\n-\tint rc;\n-\n-\trc = otx2_mbox_wait_for_rsp(mbox, devid);\n-\tif (rc != 1)\n-\t\treturn -EIO;\n-\n-\trte_rmb();\n-\n-\toffset = mbox->rx_start +\n-\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n-\tmsghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n-\tif (msg != NULL)\n-\t\t*msg = msghdr;\n-\n-\treturn msghdr->rc;\n-}\n-\n-/**\n- * Polling for given wait time to get mailbox response\n- */\n-static int\n-mbox_poll(struct otx2_mbox *mbox, uint32_t wait)\n-{\n-\tuint32_t timeout = 0, sleep = 1;\n-\tuint32_t wait_us = wait * 1000;\n-\tuint64_t rsp_reg = 0;\n-\tuintptr_t reg_addr;\n-\n-\treg_addr = mbox->reg_base + mbox->intr_offset;\n-\tdo {\n-\t\trsp_reg = otx2_read64(reg_addr);\n-\n-\t\tif (timeout >= wait_us)\n-\t\t\treturn -ETIMEDOUT;\n-\n-\t\trte_delay_us(sleep);\n-\t\ttimeout += sleep;\n-\t} while (!rsp_reg);\n-\n-\trte_smp_rmb();\n-\n-\t/* Clear interrupt */\n-\totx2_write64(rsp_reg, reg_addr);\n-\n-\t/* Reset mbox */\n-\totx2_mbox_reset(mbox, 0);\n-\n-\treturn 0;\n-}\n-\n-/**\n- * @internal\n- * Wait and get mailbox response with timeout\n- */\n-int\n-otx2_mbox_get_rsp_tmo(struct otx2_mbox *mbox, int devid, void **msg,\n-\t\t uint32_t tmo)\n-{\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n-\tstruct mbox_msghdr *msghdr;\n-\tuint64_t offset;\n-\tint rc;\n-\n-\trc = otx2_mbox_wait_for_rsp_tmo(mbox, devid, tmo);\n-\tif (rc != 1)\n-\t\treturn -EIO;\n-\n-\trte_rmb();\n-\n-\toffset = mbox->rx_start +\n-\t\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n-\tmsghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);\n-\tif (msg != NULL)\n-\t\t*msg = msghdr;\n-\n-\treturn msghdr->rc;\n-}\n-\n-static int\n-mbox_wait(struct otx2_mbox *mbox, int devid, uint32_t rst_timo)\n-{\n-\tvolatile struct otx2_mbox_dev *mdev = &mbox->dev[devid];\n-\tuint32_t timeout = 0, sleep = 1;\n-\n-\trst_timo = rst_timo * 1000; /* Milli seconds to micro seconds */\n-\twhile (mdev->num_msgs > mdev->msgs_acked) {\n-\t\trte_delay_us(sleep);\n-\t\ttimeout += sleep;\n-\t\tif (timeout >= rst_timo) {\n-\t\t\tstruct mbox_hdr *tx_hdr =\n-\t\t\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase +\n-\t\t\t\t\t\t\tmbox->tx_start);\n-\t\t\tstruct mbox_hdr *rx_hdr =\n-\t\t\t\t(struct mbox_hdr *)((uintptr_t)mdev->mbase +\n-\t\t\t\t\t\t\tmbox->rx_start);\n-\n-\t\t\totx2_err(\"MBOX[devid: %d] message wait timeout %d, \"\n-\t\t\t\t \"num_msgs: %d, msgs_acked: %d \"\n-\t\t\t\t \"(tx/rx num_msgs: %d/%d), msg_size: %d, \"\n-\t\t\t\t \"rsp_size: %d\",\n-\t\t\t\t devid, timeout, mdev->num_msgs,\n-\t\t\t\t mdev->msgs_acked, tx_hdr->num_msgs,\n-\t\t\t\t rx_hdr->num_msgs, mdev->msg_size,\n-\t\t\t\t mdev->rsp_size);\n-\n-\t\t\treturn -EIO;\n-\t\t}\n-\t\trte_rmb();\n-\t}\n-\treturn 0;\n-}\n-\n-int\n-otx2_mbox_wait_for_rsp_tmo(struct otx2_mbox *mbox, int devid, uint32_t tmo)\n-{\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n-\tint rc = 0;\n-\n-\t/* Sync with mbox region */\n-\trte_rmb();\n-\n-\tif (mbox->trigger == RVU_PF_VFX_PFVF_MBOX1 ||\n-\t\tmbox->trigger == RVU_PF_VFX_PFVF_MBOX0) {\n-\t\t/* In case of VF, Wait a bit more to account round trip delay */\n-\t\ttmo = tmo * 2;\n-\t}\n-\n-\t/* Wait message */\n-\tif (rte_thread_is_intr())\n-\t\trc = mbox_poll(mbox, tmo);\n-\telse\n-\t\trc = mbox_wait(mbox, devid, tmo);\n-\n-\tif (!rc)\n-\t\trc = mdev->num_msgs;\n-\n-\treturn rc;\n-}\n-\n-/**\n- * @internal\n- * Wait for the mailbox response\n- */\n-int\n-otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid)\n-{\n-\treturn otx2_mbox_wait_for_rsp_tmo(mbox, devid, MBOX_RSP_TIMEOUT);\n-}\n-\n-int\n-otx2_mbox_get_availmem(struct otx2_mbox *mbox, int devid)\n-{\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n-\tint avail;\n-\n-\trte_spinlock_lock(&mdev->mbox_lock);\n-\tavail = mbox->tx_size - mdev->msg_size - msgs_offset();\n-\trte_spinlock_unlock(&mdev->mbox_lock);\n-\n-\treturn avail;\n-}\n-\n-int\n-otx2_send_ready_msg(struct otx2_mbox *mbox, uint16_t *pcifunc)\n-{\n-\tstruct ready_msg_rsp *rsp;\n-\tint rc;\n-\n-\totx2_mbox_alloc_msg_ready(mbox);\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_get_rsp(mbox, 0, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tif (rsp->hdr.ver != OTX2_MBOX_VERSION) {\n-\t\totx2_err(\"Incompatible MBox versions(AF: 0x%04x DPDK: 0x%04x)\",\n-\t\t\t rsp->hdr.ver, OTX2_MBOX_VERSION);\n-\t\treturn -EPIPE;\n-\t}\n-\n-\tif (pcifunc)\n-\t\t*pcifunc = rsp->hdr.pcifunc;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, uint16_t pcifunc,\n-\t\t uint16_t id)\n-{\n-\tstruct msg_rsp *rsp;\n-\n-\trsp = (struct msg_rsp *)otx2_mbox_alloc_msg(mbox, devid, sizeof(*rsp));\n-\tif (!rsp)\n-\t\treturn -ENOMEM;\n-\trsp->hdr.id = id;\n-\trsp->hdr.sig = OTX2_MBOX_RSP_SIG;\n-\trsp->hdr.rc = MBOX_MSG_INVALID;\n-\trsp->hdr.pcifunc = pcifunc;\n-\n-\treturn 0;\n-}\n-\n-/**\n- * @internal\n- * Convert mail box ID to name\n- */\n-const char *otx2_mbox_id2name(uint16_t id)\n-{\n-\tswitch (id) {\n-#define M(_name, _id, _1, _2, _3) case _id: return # _name;\n-\tMBOX_MESSAGES\n-\tMBOX_UP_CGX_MESSAGES\n-#undef M\n-\tdefault :\n-\t\treturn \"INVALID ID\";\n-\t}\n-}\n-\n-int otx2_mbox_id2size(uint16_t id)\n-{\n-\tswitch (id) {\n-#define M(_1, _id, _2, _req_type, _3) case _id: return sizeof(struct _req_type);\n-\tMBOX_MESSAGES\n-\tMBOX_UP_CGX_MESSAGES\n-#undef M\n-\tdefault :\n-\t\treturn 0;\n-\t}\n-}\ndiff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h\ndeleted file mode 100644\nindex 25b521a7fa..0000000000\n--- a/drivers/common/octeontx2/otx2_mbox.h\n+++ /dev/null\n@@ -1,1958 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_MBOX_H__\n-#define __OTX2_MBOX_H__\n-\n-#include <errno.h>\n-#include <stdbool.h>\n-\n-#include <rte_ether.h>\n-#include <rte_spinlock.h>\n-\n-#include <otx2_common.h>\n-\n-#define SZ_64K\t\t\t(64ULL * 1024ULL)\n-#define SZ_1K\t\t\t(1ULL * 1024ULL)\n-#define MBOX_SIZE\t\tSZ_64K\n-\n-/* AF/PF: PF initiated, PF/VF VF initiated */\n-#define MBOX_DOWN_RX_START\t0\n-#define MBOX_DOWN_RX_SIZE\t(46 * SZ_1K)\n-#define MBOX_DOWN_TX_START\t(MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)\n-#define MBOX_DOWN_TX_SIZE\t(16 * SZ_1K)\n-/* AF/PF: AF initiated, PF/VF PF initiated */\n-#define MBOX_UP_RX_START\t(MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)\n-#define MBOX_UP_RX_SIZE\t\tSZ_1K\n-#define MBOX_UP_TX_START\t(MBOX_UP_RX_START + MBOX_UP_RX_SIZE)\n-#define MBOX_UP_TX_SIZE\t\tSZ_1K\n-\n-#if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE\n-# error \"Incorrect mailbox area sizes\"\n-#endif\n-\n-#define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))\n-\n-#define MBOX_RSP_TIMEOUT\t3000 /* Time to wait for mbox response in ms */\n-\n-#define MBOX_MSG_ALIGN\t\t16 /* Align mbox msg start to 16bytes */\n-\n-/* Mailbox directions */\n-#define MBOX_DIR_AFPF\t\t0 /* AF replies to PF */\n-#define MBOX_DIR_PFAF\t\t1 /* PF sends messages to AF */\n-#define MBOX_DIR_PFVF\t\t2 /* PF replies to VF */\n-#define MBOX_DIR_VFPF\t\t3 /* VF sends messages to PF */\n-#define MBOX_DIR_AFPF_UP\t4 /* AF sends messages to PF */\n-#define MBOX_DIR_PFAF_UP\t5 /* PF replies to AF */\n-#define MBOX_DIR_PFVF_UP\t6 /* PF sends messages to VF */\n-#define MBOX_DIR_VFPF_UP\t7 /* VF replies to PF */\n-\n-/* Device memory does not support unaligned access, instruct compiler to\n- * not optimize the memory access when working with mailbox memory.\n- */\n-#define __otx2_io volatile\n-\n-struct otx2_mbox_dev {\n-\tvoid\t *mbase; /* This dev's mbox region */\n-\trte_spinlock_t mbox_lock;\n-\tuint16_t msg_size; /* Total msg size to be sent */\n-\tuint16_t rsp_size; /* Total rsp size to be sure the reply is ok */\n-\tuint16_t num_msgs; /* No of msgs sent or waiting for response */\n-\tuint16_t msgs_acked; /* No of msgs for which response is received */\n-};\n-\n-struct otx2_mbox {\n-\tuintptr_t hwbase; /* Mbox region advertised by HW */\n-\tuintptr_t reg_base;/* CSR base for this dev */\n-\tuint64_t trigger; /* Trigger mbox notification */\n-\tuint16_t tr_shift; /* Mbox trigger shift */\n-\tuint64_t rx_start; /* Offset of Rx region in mbox memory */\n-\tuint64_t tx_start; /* Offset of Tx region in mbox memory */\n-\tuint16_t rx_size; /* Size of Rx region */\n-\tuint16_t tx_size; /* Size of Tx region */\n-\tuint16_t ndevs; /* The number of peers */\n-\tstruct otx2_mbox_dev *dev;\n-\tuint64_t intr_offset; /* Offset to interrupt register */\n-};\n-\n-/* Header which precedes all mbox messages */\n-struct mbox_hdr {\n-\tuint64_t __otx2_io msg_size; /* Total msgs size embedded */\n-\tuint16_t __otx2_io num_msgs; /* No of msgs embedded */\n-};\n-\n-/* Header which precedes every msg and is also part of it */\n-struct mbox_msghdr {\n-\tuint16_t __otx2_io pcifunc; /* Who's sending this msg */\n-\tuint16_t __otx2_io id; /* Mbox message ID */\n-#define OTX2_MBOX_REQ_SIG (0xdead)\n-#define OTX2_MBOX_RSP_SIG (0xbeef)\n-\t/* Signature, for validating corrupted msgs */\n-\tuint16_t __otx2_io sig;\n-#define OTX2_MBOX_VERSION (0x000b)\n-\t/* Version of msg's structure for this ID */\n-\tuint16_t __otx2_io ver;\n-\t/* Offset of next msg within mailbox region */\n-\tuint16_t __otx2_io next_msgoff;\n-\tint __otx2_io rc; /* Msg processed response code */\n-};\n-\n-/* Mailbox message types */\n-#define MBOX_MSG_MASK\t\t\t\t0xFFFF\n-#define MBOX_MSG_INVALID\t\t\t0xFFFE\n-#define MBOX_MSG_MAX\t\t\t\t0xFFFF\n-\n-#define MBOX_MESSAGES\t\t\t\t\t\t\t\\\n-/* Generic mbox IDs (range 0x000 - 0x1FF) */\t\t\t\t\\\n-M(READY,\t\t0x001, ready, msg_req, ready_msg_rsp)\t\t\\\n-M(ATTACH_RESOURCES,\t0x002, attach_resources, rsrc_attach_req, msg_rsp)\\\n-M(DETACH_RESOURCES,\t0x003, detach_resources, rsrc_detach_req, msg_rsp)\\\n-M(FREE_RSRC_CNT,\t0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp)\t\\\n-M(MSIX_OFFSET,\t\t0x005, msix_offset, msg_req, msix_offset_rsp)\t\\\n-M(VF_FLR,\t\t0x006, vf_flr, msg_req, msg_rsp)\t\t\\\n-M(PTP_OP,\t\t0x007, ptp_op, ptp_req, ptp_rsp)\t\t\\\n-M(GET_HW_CAP,\t\t0x008, get_hw_cap, msg_req, get_hw_cap_rsp)\t\\\n-M(NDC_SYNC_OP,\t\t0x009, ndc_sync_op, ndc_sync_op, msg_rsp)\t\\\n-/* CGX mbox IDs (range 0x200 - 0x3FF) */\t\t\t\t\\\n-M(CGX_START_RXTX,\t0x200, cgx_start_rxtx, msg_req, msg_rsp)\t\\\n-M(CGX_STOP_RXTX,\t0x201, cgx_stop_rxtx, msg_req, msg_rsp)\t\t\\\n-M(CGX_STATS,\t\t0x202, cgx_stats, msg_req, cgx_stats_rsp)\t\\\n-M(CGX_MAC_ADDR_SET,\t0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,\\\n-\t\t\t\tcgx_mac_addr_set_or_get)\t\t\\\n-M(CGX_MAC_ADDR_GET,\t0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,\\\n-\t\t\t\tcgx_mac_addr_set_or_get)\t\t\\\n-M(CGX_PROMISC_ENABLE,\t0x205, cgx_promisc_enable, msg_req, msg_rsp)\t\\\n-M(CGX_PROMISC_DISABLE,\t0x206, cgx_promisc_disable, msg_req, msg_rsp)\t\\\n-M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp)\t\\\n-M(CGX_STOP_LINKEVENTS,\t0x208, cgx_stop_linkevents, msg_req, msg_rsp)\t\\\n-M(CGX_GET_LINKINFO,\t0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg)\\\n-M(CGX_INTLBK_ENABLE,\t0x20A, cgx_intlbk_enable, msg_req, msg_rsp)\t\\\n-M(CGX_INTLBK_DISABLE,\t0x20B, cgx_intlbk_disable, msg_req, msg_rsp)\t\\\n-M(CGX_PTP_RX_ENABLE,\t0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp)\t\\\n-M(CGX_PTP_RX_DISABLE,\t0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp)\t\\\n-M(CGX_CFG_PAUSE_FRM,\t0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg,\t\\\n-\t\t\t\tcgx_pause_frm_cfg)\t\t\t\\\n-M(CGX_FW_DATA_GET,\t0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \\\n-M(CGX_FEC_SET,\t\t0x210, cgx_set_fec_param, fec_mode, fec_mode) \\\n-M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req,\t\\\n-\t\t\t\tcgx_mac_addr_add_rsp)\t\t\t\\\n-M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req,\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req,\t\\\n-\t\t\t\t cgx_max_dmac_entries_get_rsp)\t\t\\\n-M(CGX_SET_LINK_STATE,\t0x214, cgx_set_link_state,\t\t\\\n-\t\t\tcgx_set_link_state_msg, msg_rsp)\t\t\\\n-M(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req,\t\t\\\n-\t\t\t\tcgx_phy_mod_type)\t\t\t\\\n-M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type,\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(CGX_FEC_STATS,\t0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \\\n-M(CGX_SET_LINK_MODE,\t0x218, cgx_set_link_mode, cgx_set_link_mode_req,\\\n-\t\t\t cgx_set_link_mode_rsp)\t\t\t\\\n-M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \\\n-M(CGX_STATS_RST,\t0x21A, cgx_stats_rst, msg_req, msg_rsp)\t\t\\\n-/* NPA mbox IDs (range 0x400 - 0x5FF) */\t\t\t\t\\\n-M(NPA_LF_ALLOC,\t\t0x400, npa_lf_alloc, npa_lf_alloc_req,\t\t\\\n-\t\t\t\tnpa_lf_alloc_rsp)\t\t\t\\\n-M(NPA_LF_FREE,\t\t0x401, npa_lf_free, msg_req, msg_rsp)\t\t\\\n-M(NPA_AQ_ENQ,\t\t0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)\\\n-M(NPA_HWCTX_DISABLE,\t0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\\\n-/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */\t\t\t\t\\\n-M(SSO_LF_ALLOC,\t\t0x600, sso_lf_alloc, sso_lf_alloc_req,\t\t\\\n-\t\t\t\tsso_lf_alloc_rsp)\t\t\t\\\n-M(SSO_LF_FREE,\t\t0x601, sso_lf_free, sso_lf_free_req, msg_rsp)\t\\\n-M(SSOW_LF_ALLOC,\t0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp)\\\n-M(SSOW_LF_FREE,\t\t0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp)\t\\\n-M(SSO_HW_SETCONFIG,\t0x604, sso_hw_setconfig, sso_hw_setconfig,\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(SSO_GRP_SET_PRIORITY,\t0x605, sso_grp_set_priority, sso_grp_priority,\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(SSO_GRP_GET_PRIORITY,\t0x606, sso_grp_get_priority, sso_info_req,\t\\\n-\t\t\t\tsso_grp_priority)\t\t\t\\\n-M(SSO_WS_CACHE_INV,\t0x607, sso_ws_cache_inv, msg_req, msg_rsp)\t\\\n-M(SSO_GRP_QOS_CONFIG,\t0x608, sso_grp_qos_config, sso_grp_qos_cfg,\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(SSO_GRP_GET_STATS,\t0x609, sso_grp_get_stats, sso_info_req,\t\t\\\n-\t\t\t\tsso_grp_stats)\t\t\t\t\\\n-M(SSO_HWS_GET_STATS,\t0x610, sso_hws_get_stats, sso_info_req,\t\t\\\n-\t\t\t\tsso_hws_stats)\t\t\t\t\\\n-M(SSO_HW_RELEASE_XAQ,\t0x611, sso_hw_release_xaq_aura,\t\t\t\\\n-\t\t\t\tsso_release_xaq, msg_rsp)\t\t\\\n-/* TIM mbox IDs (range 0x800 - 0x9FF) */\t\t\t\t\\\n-M(TIM_LF_ALLOC,\t\t0x800, tim_lf_alloc, tim_lf_alloc_req,\t\t\\\n-\t\t\t\ttim_lf_alloc_rsp)\t\t\t\\\n-M(TIM_LF_FREE,\t\t0x801, tim_lf_free, tim_ring_req, msg_rsp)\t\\\n-M(TIM_CONFIG_RING,\t0x802, tim_config_ring, tim_config_req, msg_rsp)\\\n-M(TIM_ENABLE_RING,\t0x803, tim_enable_ring, tim_ring_req,\t\t\\\n-\t\t\t\ttim_enable_rsp)\t\t\t\t\\\n-M(TIM_DISABLE_RING,\t0x804, tim_disable_ring, tim_ring_req, msg_rsp)\t\\\n-/* CPT mbox IDs (range 0xA00 - 0xBFF) */\t\t\t\t\\\n-M(CPT_LF_ALLOC,\t\t0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg,\t\\\n-\t\t\t cpt_lf_alloc_rsp_msg)\t\t\t\\\n-M(CPT_LF_FREE,\t\t0xA01, cpt_lf_free, msg_req, msg_rsp)\t\t\\\n-M(CPT_RD_WR_REGISTER,\t0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg,\t\\\n-\t\t\t cpt_rd_wr_reg_msg)\t\t\t\\\n-M(CPT_SET_CRYPTO_GRP,\t0xA03, cpt_set_crypto_grp,\t\t\t\\\n-\t\t\t cpt_set_crypto_grp_req_msg,\t\t\\\n-\t\t\t msg_rsp)\t\t\t\t\t\\\n-M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg,\t\t\t\\\n-\t\t\t cpt_inline_ipsec_cfg_msg, msg_rsp)\t\\\n-M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg,\t\t\t\\\n-\t\t\t cpt_rx_inline_lf_cfg_msg, msg_rsp)\t\\\n-M(CPT_GET_CAPS,\t\t0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg)\t\\\n-/* REE mbox IDs (range 0xE00 - 0xFFF) */\t\t\t\t\\\n-M(REE_CONFIG_LF,\t0xE01, ree_config_lf, ree_lf_req_msg,\t\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(REE_RD_WR_REGISTER,\t0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg,\t\\\n-\t\t\t\tree_rd_wr_reg_msg)\t\t\t\\\n-M(REE_RULE_DB_PROG,\t0xE03, ree_rule_db_prog,\t\t\t\\\n-\t\t\t\tree_rule_db_prog_req_msg,\t\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(REE_RULE_DB_LEN_GET,\t0xE04, ree_rule_db_len_get, ree_req_msg,\t\\\n-\t\t\t\tree_rule_db_len_rsp_msg)\t\t\\\n-M(REE_RULE_DB_GET,\t0xE05, ree_rule_db_get,\t\t\t\t\\\n-\t\t\t\tree_rule_db_get_req_msg,\t\t\\\n-\t\t\t\tree_rule_db_get_rsp_msg)\t\t\\\n-/* NPC mbox IDs (range 0x6000 - 0x7FFF) */\t\t\t\t\\\n-M(NPC_MCAM_ALLOC_ENTRY,\t0x6000, npc_mcam_alloc_entry,\t\t\t\\\n-\t\t\t\tnpc_mcam_alloc_entry_req,\t\t\\\n-\t\t\t\tnpc_mcam_alloc_entry_rsp)\t\t\\\n-M(NPC_MCAM_FREE_ENTRY,\t0x6001, npc_mcam_free_entry,\t\t\t\\\n-\t\t\t\tnpc_mcam_free_entry_req, msg_rsp)\t\\\n-M(NPC_MCAM_WRITE_ENTRY,\t0x6002, npc_mcam_write_entry,\t\t\t\\\n-\t\t\t\tnpc_mcam_write_entry_req, msg_rsp)\t\\\n-M(NPC_MCAM_ENA_ENTRY,\t0x6003, npc_mcam_ena_entry,\t\t\t\\\n-\t\t\t\tnpc_mcam_ena_dis_entry_req, msg_rsp)\t\\\n-M(NPC_MCAM_DIS_ENTRY,\t0x6004, npc_mcam_dis_entry,\t\t\t\\\n-\t\t\t\tnpc_mcam_ena_dis_entry_req, msg_rsp)\t\\\n-M(NPC_MCAM_SHIFT_ENTRY,\t0x6005, npc_mcam_shift_entry,\t\t\t\\\n-\t\t\t\tnpc_mcam_shift_entry_req,\t\t\\\n-\t\t\t\tnpc_mcam_shift_entry_rsp)\t\t\\\n-M(NPC_MCAM_ALLOC_COUNTER,\t0x6006, npc_mcam_alloc_counter,\t\t\\\n-\t\t\t\tnpc_mcam_alloc_counter_req,\t\t\\\n-\t\t\t\tnpc_mcam_alloc_counter_rsp)\t\t\\\n-M(NPC_MCAM_FREE_COUNTER,\t0x6007, npc_mcam_free_counter,\t\t\\\n-\t\t\t\tnpc_mcam_oper_counter_req,\t\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(NPC_MCAM_UNMAP_COUNTER,\t0x6008, npc_mcam_unmap_counter,\t\t\\\n-\t\t\t\tnpc_mcam_unmap_counter_req,\t\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(NPC_MCAM_CLEAR_COUNTER,\t0x6009, npc_mcam_clear_counter,\t\t\\\n-\t\t\t\tnpc_mcam_oper_counter_req,\t\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(NPC_MCAM_COUNTER_STATS,\t0x600a, npc_mcam_counter_stats,\t\t\\\n-\t\t\t\tnpc_mcam_oper_counter_req,\t\t\\\n-\t\t\t\tnpc_mcam_oper_counter_rsp)\t\t\\\n-M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,\\\n-\t\t\t\tnpc_mcam_alloc_and_write_entry_req,\t\\\n-\t\t\t\tnpc_mcam_alloc_and_write_entry_rsp)\t\\\n-M(NPC_GET_KEX_CFG,\t 0x600c, npc_get_kex_cfg, msg_req,\t\t\\\n-\t\t\t\tnpc_get_kex_cfg_rsp)\t\t\t\\\n-M(NPC_INSTALL_FLOW,\t 0x600d, npc_install_flow,\t\t\t\\\n-\t\t\t\t npc_install_flow_req,\t\t\t\\\n-\t\t\t\t npc_install_flow_rsp)\t\t\t\\\n-M(NPC_DELETE_FLOW,\t 0x600e, npc_delete_flow,\t\t\t\\\n-\t\t\t\t npc_delete_flow_req, msg_rsp)\t\t\\\n-M(NPC_MCAM_READ_ENTRY,\t 0x600f, npc_mcam_read_entry,\t\t\t\\\n-\t\t\t\t npc_mcam_read_entry_req,\t\t\\\n-\t\t\t\t npc_mcam_read_entry_rsp)\t\t\\\n-M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \\\n-\t\t\t\t npc_set_pkind, \\\n-\t\t\t\t msg_rsp) \\\n-M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, msg_req, \\\n-\t\t\t\t npc_mcam_read_base_rule_rsp) \\\n-/* NIX mbox IDs (range 0x8000 - 0xFFFF) */\t\t\t\t\\\n-M(NIX_LF_ALLOC,\t\t0x8000, nix_lf_alloc, nix_lf_alloc_req,\t\t\\\n-\t\t\t\tnix_lf_alloc_rsp)\t\t\t\\\n-M(NIX_LF_FREE,\t\t0x8001, nix_lf_free, nix_lf_free_req, msg_rsp)\t\\\n-M(NIX_AQ_ENQ,\t\t0x8002, nix_aq_enq, nix_aq_enq_req,\t\t\\\n-\t\t\t\tnix_aq_enq_rsp)\t\t\t\t\\\n-M(NIX_HWCTX_DISABLE,\t0x8003, nix_hwctx_disable, hwctx_disable_req,\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(NIX_TXSCH_ALLOC,\t0x8004, nix_txsch_alloc, nix_txsch_alloc_req,\t\\\n-\t\t\t\tnix_txsch_alloc_rsp)\t\t\t\\\n-M(NIX_TXSCH_FREE,\t0x8005, nix_txsch_free,\tnix_txsch_free_req,\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(NIX_TXSCHQ_CFG,\t0x8006, nix_txschq_cfg, nix_txschq_config,\t\\\n-\t\t\t\tnix_txschq_config)\t\t\t\\\n-M(NIX_STATS_RST,\t0x8007, nix_stats_rst, msg_req, msg_rsp)\t\\\n-M(NIX_VTAG_CFG,\t\t0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp)\t\\\n-M(NIX_RSS_FLOWKEY_CFG,\t0x8009, nix_rss_flowkey_cfg,\t\t\t\\\n-\t\t\t\tnix_rss_flowkey_cfg,\t\t\t\\\n-\t\t\t\tnix_rss_flowkey_cfg_rsp)\t\t\\\n-M(NIX_SET_MAC_ADDR,\t0x800a, nix_set_mac_addr, nix_set_mac_addr,\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(NIX_SET_RX_MODE,\t0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp)\t\\\n-M(NIX_SET_HW_FRS,\t0x800c, nix_set_hw_frs,\tnix_frs_cfg, msg_rsp)\t\\\n-M(NIX_LF_START_RX,\t0x800d, nix_lf_start_rx, msg_req, msg_rsp)\t\\\n-M(NIX_LF_STOP_RX,\t0x800e, nix_lf_stop_rx,\tmsg_req, msg_rsp)\t\\\n-M(NIX_MARK_FORMAT_CFG,\t0x800f, nix_mark_format_cfg,\t\t\t\\\n-\t\t\t\tnix_mark_format_cfg,\t\t\t\\\n-\t\t\t\tnix_mark_format_cfg_rsp)\t\t\\\n-M(NIX_SET_RX_CFG,\t0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp)\t\\\n-M(NIX_LSO_FORMAT_CFG,\t0x8011, nix_lso_format_cfg, nix_lso_format_cfg,\t\\\n-\t\t\t\tnix_lso_format_cfg_rsp)\t\t\t\\\n-M(NIX_LF_PTP_TX_ENABLE,\t0x8013, nix_lf_ptp_tx_enable, msg_req,\t\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(NIX_LF_PTP_TX_DISABLE,\t0x8014, nix_lf_ptp_tx_disable, msg_req,\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(NIX_SET_VLAN_TPID,\t0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid,\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(NIX_BP_ENABLE,\t0x8016, nix_bp_enable, nix_bp_cfg_req,\t\t\\\n-\t\t\t\tnix_bp_cfg_rsp)\t\t\t\t\\\n-M(NIX_BP_DISABLE,\t0x8017, nix_bp_disable,\tnix_bp_cfg_req, msg_rsp)\\\n-M(NIX_GET_MAC_ADDR,\t0x8018, nix_get_mac_addr, msg_req,\t\t\\\n-\t\t\t\tnix_get_mac_addr_rsp)\t\t\t\\\n-M(NIX_INLINE_IPSEC_CFG,\t0x8019, nix_inline_ipsec_cfg,\t\t\t\\\n-\t\t\t\tnix_inline_ipsec_cfg, msg_rsp)\t\t\\\n-M(NIX_INLINE_IPSEC_LF_CFG,\t\t\t\t\t\t\\\n-\t\t\t0x801a, nix_inline_ipsec_lf_cfg,\t\t\\\n-\t\t\t\tnix_inline_ipsec_lf_cfg, msg_rsp)\n-\n-/* Messages initiated by AF (range 0xC00 - 0xDFF) */\n-#define MBOX_UP_CGX_MESSAGES\t\t\t\t\t\t\\\n-M(CGX_LINK_EVENT,\t0xC00, cgx_link_event, cgx_link_info_msg,\t\\\n-\t\t\t\tmsg_rsp)\t\t\t\t\\\n-M(CGX_PTP_RX_INFO,\t0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg,\t\\\n-\t\t\t\tmsg_rsp)\n-\n-enum {\n-#define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,\n-MBOX_MESSAGES\n-MBOX_UP_CGX_MESSAGES\n-#undef M\n-};\n-\n-/* Mailbox message formats */\n-\n-#define RVU_DEFAULT_PF_FUNC 0xFFFF\n-\n-/* Generic request msg used for those mbox messages which\n- * don't send any data in the request.\n- */\n-struct msg_req {\n-\tstruct mbox_msghdr hdr;\n-};\n-\n-/* Generic response msg used a ack or response for those mbox\n- * messages which doesn't have a specific rsp msg format.\n- */\n-struct msg_rsp {\n-\tstruct mbox_msghdr hdr;\n-};\n-\n-/* RVU mailbox error codes\n- * Range 256 - 300.\n- */\n-enum rvu_af_status {\n-\tRVU_INVALID_VF_ID = -256,\n-};\n-\n-struct ready_msg_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io sclk_feq; /* SCLK frequency */\n-\tuint16_t __otx2_io rclk_freq; /* RCLK frequency */\n-};\n-\n-enum npc_pkind_type {\n-\tNPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL,\n-\tNPC_RX_VLAN_EXDSA_PKIND = 56ULL,\n-\tNPC_RX_CHLEN24B_PKIND,\n-\tNPC_RX_CPT_HDR_PKIND,\n-\tNPC_RX_CHLEN90B_PKIND,\n-\tNPC_TX_HIGIG_PKIND,\n-\tNPC_RX_HIGIG_PKIND,\n-\tNPC_RX_EXDSA_PKIND,\n-\tNPC_RX_EDSA_PKIND,\n-\tNPC_TX_DEF_PKIND,\n-};\n-\n-#define OTX2_PRIV_FLAGS_CH_LEN_90B 254\n-#define OTX2_PRIV_FLAGS_CH_LEN_24B 255\n-\n-/* Struct to set pkind */\n-struct npc_set_pkind {\n-\tstruct mbox_msghdr hdr;\n-#define OTX2_PRIV_FLAGS_DEFAULT\t BIT_ULL(0)\n-#define OTX2_PRIV_FLAGS_EDSA\t BIT_ULL(1)\n-#define OTX2_PRIV_FLAGS_HIGIG\t BIT_ULL(2)\n-#define OTX2_PRIV_FLAGS_FDSA\t BIT_ULL(3)\n-#define OTX2_PRIV_FLAGS_EXDSA\t BIT_ULL(4)\n-#define OTX2_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)\n-#define OTX2_PRIV_FLAGS_CUSTOM\t BIT_ULL(63)\n-\tuint64_t __otx2_io mode;\n-#define PKIND_TX BIT_ULL(0)\n-#define PKIND_RX BIT_ULL(1)\n-\tuint8_t __otx2_io dir;\n-\tuint8_t __otx2_io pkind; /* valid only in case custom flag */\n-\tuint8_t __otx2_io var_len_off;\n-\t/* Offset of custom header length field.\n-\t * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND\n-\t */\n-\tuint8_t __otx2_io var_len_off_mask; /* Mask for length with in offset */\n-\tuint8_t __otx2_io shift_dir;\n-\t/* Shift direction to get length of the\n-\t * header at var_len_off\n-\t */\n-};\n-\n-/* Structure for requesting resource provisioning.\n- * 'modify' flag to be used when either requesting more\n- * or to detach partial of a certain resource type.\n- * Rest of the fields specify how many of what type to\n- * be attached.\n- * To request LFs from two blocks of same type this mailbox\n- * can be sent twice as below:\n- * struct rsrc_attach *attach;\n- * .. Allocate memory for message ..\n- * attach->cptlfs = 3; <3 LFs from CPT0>\n- * .. Send message ..\n- * .. Allocate memory for message ..\n- * attach->modify = 1;\n- * attach->cpt_blkaddr = BLKADDR_CPT1;\n- * attach->cptlfs = 2; <2 LFs from CPT1>\n- * .. Send message ..\n- */\n-struct rsrc_attach_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io modify:1;\n-\tuint8_t __otx2_io npalf:1;\n-\tuint8_t __otx2_io nixlf:1;\n-\tuint16_t __otx2_io sso;\n-\tuint16_t __otx2_io ssow;\n-\tuint16_t __otx2_io timlfs;\n-\tuint16_t __otx2_io cptlfs;\n-\tuint16_t __otx2_io reelfs;\n-\t/* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */\n-\tint __otx2_io cpt_blkaddr;\n-\t/* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */\n-\tint __otx2_io ree_blkaddr;\n-};\n-\n-/* Structure for relinquishing resources.\n- * 'partial' flag to be used when relinquishing all resources\n- * but only of a certain type. If not set, all resources of all\n- * types provisioned to the RVU function will be detached.\n- */\n-struct rsrc_detach_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io partial:1;\n-\tuint8_t __otx2_io npalf:1;\n-\tuint8_t __otx2_io nixlf:1;\n-\tuint8_t __otx2_io sso:1;\n-\tuint8_t __otx2_io ssow:1;\n-\tuint8_t __otx2_io timlfs:1;\n-\tuint8_t __otx2_io cptlfs:1;\n-\tuint8_t __otx2_io reelfs:1;\n-};\n-\n-/* NIX Transmit schedulers */\n-#define\tNIX_TXSCH_LVL_SMQ 0x0\n-#define\tNIX_TXSCH_LVL_MDQ 0x0\n-#define\tNIX_TXSCH_LVL_TL4 0x1\n-#define\tNIX_TXSCH_LVL_TL3 0x2\n-#define\tNIX_TXSCH_LVL_TL2 0x3\n-#define\tNIX_TXSCH_LVL_TL1 0x4\n-#define\tNIX_TXSCH_LVL_CNT 0x5\n-\n-/*\n- * Number of resources available to the caller.\n- * In reply to MBOX_MSG_FREE_RSRC_CNT.\n- */\n-struct free_rsrcs_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT];\n-\tuint16_t __otx2_io sso;\n-\tuint16_t __otx2_io tim;\n-\tuint16_t __otx2_io ssow;\n-\tuint16_t __otx2_io cpt;\n-\tuint8_t __otx2_io npa;\n-\tuint8_t __otx2_io nix;\n-\tuint16_t __otx2_io schq_nix1[NIX_TXSCH_LVL_CNT];\n-\tuint8_t __otx2_io nix1;\n-\tuint8_t __otx2_io cpt1;\n-\tuint8_t __otx2_io ree0;\n-\tuint8_t __otx2_io ree1;\n-};\n-\n-#define MSIX_VECTOR_INVALID\t0xFFFF\n-#define MAX_RVU_BLKLF_CNT\t256\n-\n-struct msix_offset_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io npa_msixoff;\n-\tuint16_t __otx2_io nix_msixoff;\n-\tuint16_t __otx2_io sso;\n-\tuint16_t __otx2_io ssow;\n-\tuint16_t __otx2_io timlfs;\n-\tuint16_t __otx2_io cptlfs;\n-\tuint16_t __otx2_io sso_msixoff[MAX_RVU_BLKLF_CNT];\n-\tuint16_t __otx2_io ssow_msixoff[MAX_RVU_BLKLF_CNT];\n-\tuint16_t __otx2_io timlf_msixoff[MAX_RVU_BLKLF_CNT];\n-\tuint16_t __otx2_io cptlf_msixoff[MAX_RVU_BLKLF_CNT];\n-\tuint16_t __otx2_io cpt1_lfs;\n-\tuint16_t __otx2_io ree0_lfs;\n-\tuint16_t __otx2_io ree1_lfs;\n-\tuint16_t __otx2_io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];\n-\tuint16_t __otx2_io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];\n-\tuint16_t __otx2_io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];\n-\n-};\n-\n-/* CGX mbox message formats */\n-\n-struct cgx_stats_rsp {\n-\tstruct mbox_msghdr hdr;\n-#define CGX_RX_STATS_COUNT\t13\n-#define CGX_TX_STATS_COUNT\t18\n-\tuint64_t __otx2_io rx_stats[CGX_RX_STATS_COUNT];\n-\tuint64_t __otx2_io tx_stats[CGX_TX_STATS_COUNT];\n-};\n-\n-struct cgx_fec_stats_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint64_t __otx2_io fec_corr_blks;\n-\tuint64_t __otx2_io fec_uncorr_blks;\n-};\n-/* Structure for requesting the operation for\n- * setting/getting mac address in the CGX interface\n- */\n-struct cgx_mac_addr_set_or_get {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];\n-};\n-\n-/* Structure for requesting the operation to\n- * add DMAC filter entry into CGX interface\n- */\n-struct cgx_mac_addr_add_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];\n-};\n-\n-/* Structure for response against the operation to\n- * add DMAC filter entry into CGX interface\n- */\n-struct cgx_mac_addr_add_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io index;\n-};\n-\n-/* Structure for requesting the operation to\n- * delete DMAC filter entry from CGX interface\n- */\n-struct cgx_mac_addr_del_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io index;\n-};\n-\n-/* Structure for response against the operation to\n- * get maximum supported DMAC filter entries\n- */\n-struct cgx_max_dmac_entries_get_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io max_dmac_filters;\n-};\n-\n-struct cgx_link_user_info {\n-\tuint64_t __otx2_io link_up:1;\n-\tuint64_t __otx2_io full_duplex:1;\n-\tuint64_t __otx2_io lmac_type_id:4;\n-\tuint64_t __otx2_io speed:20; /* speed in Mbps */\n-\tuint64_t __otx2_io an:1; /* AN supported or not */\n-\tuint64_t __otx2_io fec:2; /* FEC type if enabled else 0 */\n-\tuint64_t __otx2_io port:8;\n-#define LMACTYPE_STR_LEN 16\n-\tchar lmac_type[LMACTYPE_STR_LEN];\n-};\n-\n-struct cgx_link_info_msg {\n-\tstruct mbox_msghdr hdr;\n-\tstruct cgx_link_user_info link_info;\n-};\n-\n-struct cgx_ptp_rx_info_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io ptp_en;\n-};\n-\n-struct cgx_pause_frm_cfg {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io set;\n-\t/* set = 1 if the request is to config pause frames */\n-\t/* set = 0 if the request is to fetch pause frames config */\n-\tuint8_t __otx2_io rx_pause;\n-\tuint8_t __otx2_io tx_pause;\n-};\n-\n-struct sfp_eeprom_s {\n-#define SFP_EEPROM_SIZE 256\n-\tuint16_t __otx2_io sff_id;\n-\tuint8_t __otx2_io buf[SFP_EEPROM_SIZE];\n-\tuint64_t __otx2_io reserved;\n-};\n-\n-enum fec_type {\n-\tOTX2_FEC_NONE,\n-\tOTX2_FEC_BASER,\n-\tOTX2_FEC_RS,\n-};\n-\n-struct phy_s {\n-\tuint64_t __otx2_io can_change_mod_type : 1;\n-\tuint64_t __otx2_io mod_type : 1;\n-};\n-\n-struct cgx_lmac_fwdata_s {\n-\tuint16_t __otx2_io rw_valid;\n-\tuint64_t __otx2_io supported_fec;\n-\tuint64_t __otx2_io supported_an;\n-\tuint64_t __otx2_io supported_link_modes;\n-\t/* Only applicable if AN is supported */\n-\tuint64_t __otx2_io advertised_fec;\n-\tuint64_t __otx2_io advertised_link_modes;\n-\t/* Only applicable if SFP/QSFP slot is present */\n-\tstruct sfp_eeprom_s sfp_eeprom;\n-\tstruct phy_s phy;\n-#define LMAC_FWDATA_RESERVED_MEM 1023\n-\tuint64_t __otx2_io reserved[LMAC_FWDATA_RESERVED_MEM];\n-};\n-\n-struct cgx_fw_data {\n-\tstruct mbox_msghdr hdr;\n-\tstruct cgx_lmac_fwdata_s fwdata;\n-};\n-\n-struct fec_mode {\n-\tstruct mbox_msghdr hdr;\n-\tint __otx2_io fec;\n-};\n-\n-struct cgx_set_link_state_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io enable;\n-};\n-\n-struct cgx_phy_mod_type {\n-\tstruct mbox_msghdr hdr;\n-\tint __otx2_io mod;\n-};\n-\n-struct cgx_set_link_mode_args {\n-\tuint32_t __otx2_io speed;\n-\tuint8_t __otx2_io duplex;\n-\tuint8_t __otx2_io an;\n-\tuint8_t __otx2_io ports;\n-\tuint64_t __otx2_io mode;\n-};\n-\n-struct cgx_set_link_mode_req {\n-\tstruct mbox_msghdr hdr;\n-\tstruct cgx_set_link_mode_args args;\n-};\n-\n-struct cgx_set_link_mode_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tint __otx2_io status;\n-};\n-/* NPA mbox message formats */\n-\n-/* NPA mailbox error codes\n- * Range 301 - 400.\n- */\n-enum npa_af_status {\n-\tNPA_AF_ERR_PARAM = -301,\n-\tNPA_AF_ERR_AQ_FULL = -302,\n-\tNPA_AF_ERR_AQ_ENQUEUE = -303,\n-\tNPA_AF_ERR_AF_LF_INVALID = -304,\n-\tNPA_AF_ERR_AF_LF_ALLOC = -305,\n-\tNPA_AF_ERR_LF_RESET = -306,\n-};\n-\n-#define NPA_AURA_SZ_0\t\t0\n-#define NPA_AURA_SZ_128\t\t1\n-#define\tNPA_AURA_SZ_256\t\t2\n-#define\tNPA_AURA_SZ_512\t\t3\n-#define\tNPA_AURA_SZ_1K\t\t4\n-#define\tNPA_AURA_SZ_2K\t\t5\n-#define\tNPA_AURA_SZ_4K\t\t6\n-#define\tNPA_AURA_SZ_8K\t\t7\n-#define\tNPA_AURA_SZ_16K\t\t8\n-#define\tNPA_AURA_SZ_32K\t\t9\n-#define\tNPA_AURA_SZ_64K\t\t10\n-#define\tNPA_AURA_SZ_128K\t11\n-#define\tNPA_AURA_SZ_256K\t12\n-#define\tNPA_AURA_SZ_512K\t13\n-#define\tNPA_AURA_SZ_1M\t\t14\n-#define\tNPA_AURA_SZ_MAX\t\t15\n-\n-/* For NPA LF context alloc and init */\n-struct npa_lf_alloc_req {\n-\tstruct mbox_msghdr hdr;\n-\tint __otx2_io node;\n-\tint __otx2_io aura_sz; /* No of auras. See NPA_AURA_SZ_* */\n-\tuint32_t __otx2_io nr_pools; /* No of pools */\n-\tuint64_t __otx2_io way_mask;\n-};\n-\n-struct npa_lf_alloc_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint32_t __otx2_io stack_pg_ptrs; /* No of ptrs per stack page */\n-\tuint32_t __otx2_io stack_pg_bytes; /* Size of stack page */\n-\tuint16_t __otx2_io qints; /* NPA_AF_CONST::QINTS */\n-};\n-\n-/* NPA AQ enqueue msg */\n-struct npa_aq_enq_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint32_t __otx2_io aura_id;\n-\tuint8_t __otx2_io ctype;\n-\tuint8_t __otx2_io op;\n-\tunion {\n-\t\t/* Valid when op == WRITE/INIT and ctype == AURA.\n-\t\t * LF fills the pool_id in aura.pool_addr. AF will translate\n-\t\t * the pool_id to pool context pointer.\n-\t\t */\n-\t\t__otx2_io struct npa_aura_s aura;\n-\t\t/* Valid when op == WRITE/INIT and ctype == POOL */\n-\t\t__otx2_io struct npa_pool_s pool;\n-\t};\n-\t/* Mask data when op == WRITE (1=write, 0=don't write) */\n-\tunion {\n-\t\t/* Valid when op == WRITE and ctype == AURA */\n-\t\t__otx2_io struct npa_aura_s aura_mask;\n-\t\t/* Valid when op == WRITE and ctype == POOL */\n-\t\t__otx2_io struct npa_pool_s pool_mask;\n-\t};\n-};\n-\n-struct npa_aq_enq_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tunion {\n-\t\t/* Valid when op == READ and ctype == AURA */\n-\t\t__otx2_io struct npa_aura_s aura;\n-\t\t/* Valid when op == READ and ctype == POOL */\n-\t\t__otx2_io struct npa_pool_s pool;\n-\t};\n-};\n-\n-/* Disable all contexts of type 'ctype' */\n-struct hwctx_disable_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io ctype;\n-};\n-\n-/* NIX mbox message formats */\n-\n-/* NIX mailbox error codes\n- * Range 401 - 500.\n- */\n-enum nix_af_status {\n-\tNIX_AF_ERR_PARAM = -401,\n-\tNIX_AF_ERR_AQ_FULL = -402,\n-\tNIX_AF_ERR_AQ_ENQUEUE = -403,\n-\tNIX_AF_ERR_AF_LF_INVALID = -404,\n-\tNIX_AF_ERR_AF_LF_ALLOC = -405,\n-\tNIX_AF_ERR_TLX_ALLOC_FAIL = -406,\n-\tNIX_AF_ERR_TLX_INVALID = -407,\n-\tNIX_AF_ERR_RSS_SIZE_INVALID = -408,\n-\tNIX_AF_ERR_RSS_GRPS_INVALID = -409,\n-\tNIX_AF_ERR_FRS_INVALID = -410,\n-\tNIX_AF_ERR_RX_LINK_INVALID = -411,\n-\tNIX_AF_INVAL_TXSCHQ_CFG = -412,\n-\tNIX_AF_SMQ_FLUSH_FAILED = -413,\n-\tNIX_AF_ERR_LF_RESET = -414,\n-\tNIX_AF_ERR_RSS_NOSPC_FIELD = -415,\n-\tNIX_AF_ERR_RSS_NOSPC_ALGO = -416,\n-\tNIX_AF_ERR_MARK_CFG_FAIL = -417,\n-\tNIX_AF_ERR_LSO_CFG_FAIL = -418,\n-\tNIX_AF_INVAL_NPA_PF_FUNC = -419,\n-\tNIX_AF_INVAL_SSO_PF_FUNC = -420,\n-\tNIX_AF_ERR_TX_VTAG_NOSPC = -421,\n-\tNIX_AF_ERR_RX_VTAG_INUSE = -422,\n-\tNIX_AF_ERR_PTP_CONFIG_FAIL = -423,\n-};\n-\n-/* For NIX LF context alloc and init */\n-struct nix_lf_alloc_req {\n-\tstruct mbox_msghdr hdr;\n-\tint __otx2_io node;\n-\tuint32_t __otx2_io rq_cnt; /* No of receive queues */\n-\tuint32_t __otx2_io sq_cnt; /* No of send queues */\n-\tuint32_t __otx2_io cq_cnt; /* No of completion queues */\n-\tuint8_t __otx2_io xqe_sz;\n-\tuint16_t __otx2_io rss_sz;\n-\tuint8_t __otx2_io rss_grps;\n-\tuint16_t __otx2_io npa_func;\n-\t/* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */\n-\tuint16_t __otx2_io sso_func;\n-\tuint64_t __otx2_io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */\n-\tuint64_t __otx2_io way_mask;\n-#define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)\n-\tuint64_t flags;\n-};\n-\n-struct nix_lf_alloc_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io sqb_size;\n-\tuint16_t __otx2_io rx_chan_base;\n-\tuint16_t __otx2_io tx_chan_base;\n-\tuint8_t __otx2_io rx_chan_cnt; /* Total number of RX channels */\n-\tuint8_t __otx2_io tx_chan_cnt; /* Total number of TX channels */\n-\tuint8_t __otx2_io lso_tsov4_idx;\n-\tuint8_t __otx2_io lso_tsov6_idx;\n-\tuint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];\n-\tuint8_t __otx2_io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */\n-\tuint8_t __otx2_io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */\n-\tuint16_t __otx2_io cints; /* NIX_AF_CONST2::CINTS */\n-\tuint16_t __otx2_io qints; /* NIX_AF_CONST2::QINTS */\n-\tuint8_t __otx2_io hw_rx_tstamp_en; /*set if rx timestamping enabled */\n-\tuint8_t __otx2_io cgx_links; /* No. of CGX links present in HW */\n-\tuint8_t __otx2_io lbk_links; /* No. of LBK links present in HW */\n-\tuint8_t __otx2_io sdp_links; /* No. of SDP links present in HW */\n-\tuint8_t __otx2_io tx_link; /* Transmit channel link number */\n-};\n-\n-struct nix_lf_free_req {\n-\tstruct mbox_msghdr hdr;\n-#define NIX_LF_DISABLE_FLOWS\t\tBIT_ULL(0)\n-#define NIX_LF_DONT_FREE_TX_VTAG\tBIT_ULL(1)\n-\tuint64_t __otx2_io flags;\n-};\n-\n-/* NIX AQ enqueue msg */\n-struct nix_aq_enq_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint32_t __otx2_io qidx;\n-\tuint8_t __otx2_io ctype;\n-\tuint8_t __otx2_io op;\n-\tunion {\n-\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */\n-\t\t__otx2_io struct nix_rq_ctx_s rq;\n-\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */\n-\t\t__otx2_io struct nix_sq_ctx_s sq;\n-\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */\n-\t\t__otx2_io struct nix_cq_ctx_s cq;\n-\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */\n-\t\t__otx2_io struct nix_rsse_s rss;\n-\t\t/* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */\n-\t\t__otx2_io struct nix_rx_mce_s mce;\n-\t};\n-\t/* Mask data when op == WRITE (1=write, 0=don't write) */\n-\tunion {\n-\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */\n-\t\t__otx2_io struct nix_rq_ctx_s rq_mask;\n-\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */\n-\t\t__otx2_io struct nix_sq_ctx_s sq_mask;\n-\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */\n-\t\t__otx2_io struct nix_cq_ctx_s cq_mask;\n-\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */\n-\t\t__otx2_io struct nix_rsse_s rss_mask;\n-\t\t/* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */\n-\t\t__otx2_io struct nix_rx_mce_s mce_mask;\n-\t};\n-};\n-\n-struct nix_aq_enq_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tunion {\n-\t\t__otx2_io struct nix_rq_ctx_s rq;\n-\t\t__otx2_io struct nix_sq_ctx_s sq;\n-\t\t__otx2_io struct nix_cq_ctx_s cq;\n-\t\t__otx2_io struct nix_rsse_s rss;\n-\t\t__otx2_io struct nix_rx_mce_s mce;\n-\t};\n-};\n-\n-/* Tx scheduler/shaper mailbox messages */\n-\n-#define MAX_TXSCHQ_PER_FUNC\t128\n-\n-struct nix_txsch_alloc_req {\n-\tstruct mbox_msghdr hdr;\n-\t/* Scheduler queue count request at each level */\n-\tuint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */\n-\tuint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */\n-};\n-\n-struct nix_txsch_alloc_rsp {\n-\tstruct mbox_msghdr hdr;\n-\t/* Scheduler queue count allocated at each level */\n-\tuint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */\n-\tuint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */\n-\t/* Scheduler queue list allocated at each level */\n-\tuint16_t __otx2_io\n-\t\tschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];\n-\tuint16_t __otx2_io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];\n-\t/* Traffic aggregation scheduler level */\n-\tuint8_t __otx2_io aggr_level;\n-\t/* Aggregation lvl's RR_PRIO config */\n-\tuint8_t __otx2_io aggr_lvl_rr_prio;\n-\t/* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */\n-\tuint8_t __otx2_io link_cfg_lvl;\n-};\n-\n-struct nix_txsch_free_req {\n-\tstruct mbox_msghdr hdr;\n-#define TXSCHQ_FREE_ALL BIT_ULL(0)\n-\tuint16_t __otx2_io flags;\n-\t/* Scheduler queue level to be freed */\n-\tuint16_t __otx2_io schq_lvl;\n-\t/* List of scheduler queues to be freed */\n-\tuint16_t __otx2_io schq;\n-};\n-\n-struct nix_txschq_config {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */\n-\tuint8_t __otx2_io read;\n-#define TXSCHQ_IDX_SHIFT 16\n-#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)\n-#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)\n-\tuint8_t __otx2_io num_regs;\n-#define MAX_REGS_PER_MBOX_MSG 20\n-\tuint64_t __otx2_io reg[MAX_REGS_PER_MBOX_MSG];\n-\tuint64_t __otx2_io regval[MAX_REGS_PER_MBOX_MSG];\n-\t/* All 0's => overwrite with new value */\n-\tuint64_t __otx2_io regval_mask[MAX_REGS_PER_MBOX_MSG];\n-};\n-\n-struct nix_vtag_config {\n-\tstruct mbox_msghdr hdr;\n-\t/* '0' for 4 octet VTAG, '1' for 8 octet VTAG */\n-\tuint8_t __otx2_io vtag_size;\n-\t/* cfg_type is '0' for tx vlan cfg\n-\t * cfg_type is '1' for rx vlan cfg\n-\t */\n-\tuint8_t __otx2_io cfg_type;\n-\tunion {\n-\t\t/* Valid when cfg_type is '0' */\n-\t\tstruct {\n-\t\t\tuint64_t __otx2_io vtag0;\n-\t\t\tuint64_t __otx2_io vtag1;\n-\n-\t\t\t/* cfg_vtag0 & cfg_vtag1 fields are valid\n-\t\t\t * when free_vtag0 & free_vtag1 are '0's.\n-\t\t\t */\n-\t\t\t/* cfg_vtag0 = 1 to configure vtag0 */\n-\t\t\tuint8_t __otx2_io cfg_vtag0 :1;\n-\t\t\t/* cfg_vtag1 = 1 to configure vtag1 */\n-\t\t\tuint8_t __otx2_io cfg_vtag1 :1;\n-\n-\t\t\t/* vtag0_idx & vtag1_idx are only valid when\n-\t\t\t * both cfg_vtag0 & cfg_vtag1 are '0's,\n-\t\t\t * these fields are used along with free_vtag0\n-\t\t\t * & free_vtag1 to free the nix lf's tx_vlan\n-\t\t\t * configuration.\n-\t\t\t *\n-\t\t\t * Denotes the indices of tx_vtag def registers\n-\t\t\t * that needs to be cleared and freed.\n-\t\t\t */\n-\t\t\tint __otx2_io vtag0_idx;\n-\t\t\tint __otx2_io vtag1_idx;\n-\n-\t\t\t/* Free_vtag0 & free_vtag1 fields are valid\n-\t\t\t * when cfg_vtag0 & cfg_vtag1 are '0's.\n-\t\t\t */\n-\t\t\t/* Free_vtag0 = 1 clears vtag0 configuration\n-\t\t\t * vtag0_idx denotes the index to be cleared.\n-\t\t\t */\n-\t\t\tuint8_t __otx2_io free_vtag0 :1;\n-\t\t\t/* Free_vtag1 = 1 clears vtag1 configuration\n-\t\t\t * vtag1_idx denotes the index to be cleared.\n-\t\t\t */\n-\t\t\tuint8_t __otx2_io free_vtag1 :1;\n-\t\t} tx;\n-\n-\t\t/* Valid when cfg_type is '1' */\n-\t\tstruct {\n-\t\t\t/* Rx vtag type index, valid values are in 0..7 range */\n-\t\t\tuint8_t __otx2_io vtag_type;\n-\t\t\t/* Rx vtag strip */\n-\t\t\tuint8_t __otx2_io strip_vtag :1;\n-\t\t\t/* Rx vtag capture */\n-\t\t\tuint8_t __otx2_io capture_vtag :1;\n-\t\t} rx;\n-\t};\n-};\n-\n-struct nix_vtag_config_rsp {\n-\tstruct mbox_msghdr hdr;\n-\t/* Indices of tx_vtag def registers used to configure\n-\t * tx vtag0 & vtag1 headers, these indices are valid\n-\t * when nix_vtag_config mbox requested for vtag0 and/\n-\t * or vtag1 configuration.\n-\t */\n-\tint __otx2_io vtag0_idx;\n-\tint __otx2_io vtag1_idx;\n-};\n-\n-struct nix_rss_flowkey_cfg {\n-\tstruct mbox_msghdr hdr;\n-\tint __otx2_io mcam_index; /* MCAM entry index to modify */\n-\tuint32_t __otx2_io flowkey_cfg; /* Flowkey types selected */\n-#define FLOW_KEY_TYPE_PORT BIT(0)\n-#define FLOW_KEY_TYPE_IPV4 BIT(1)\n-#define FLOW_KEY_TYPE_IPV6 BIT(2)\n-#define FLOW_KEY_TYPE_TCP BIT(3)\n-#define FLOW_KEY_TYPE_UDP BIT(4)\n-#define FLOW_KEY_TYPE_SCTP BIT(5)\n-#define FLOW_KEY_TYPE_NVGRE BIT(6)\n-#define FLOW_KEY_TYPE_VXLAN BIT(7)\n-#define FLOW_KEY_TYPE_GENEVE BIT(8)\n-#define FLOW_KEY_TYPE_ETH_DMAC BIT(9)\n-#define FLOW_KEY_TYPE_IPV6_EXT BIT(10)\n-#define FLOW_KEY_TYPE_GTPU BIT(11)\n-#define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)\n-#define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)\n-#define FLOW_KEY_TYPE_INNR_TCP BIT(14)\n-#define FLOW_KEY_TYPE_INNR_UDP BIT(15)\n-#define FLOW_KEY_TYPE_INNR_SCTP BIT(16)\n-#define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)\n-#define FLOW_KEY_TYPE_CH_LEN_90B\tBIT(18)\n-#define FLOW_KEY_TYPE_CUSTOM0\t\tBIT(19)\n-#define FLOW_KEY_TYPE_VLAN\t\tBIT(20)\n-#define FLOW_KEY_TYPE_L4_DST BIT(28)\n-#define FLOW_KEY_TYPE_L4_SRC BIT(29)\n-#define FLOW_KEY_TYPE_L3_DST BIT(30)\n-#define FLOW_KEY_TYPE_L3_SRC BIT(31)\n-\tuint8_t\t__otx2_io group; /* RSS context or group */\n-};\n-\n-struct nix_rss_flowkey_cfg_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io alg_idx; /* Selected algo index */\n-};\n-\n-struct nix_set_mac_addr {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];\n-};\n-\n-struct nix_get_mac_addr_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];\n-};\n-\n-struct nix_mark_format_cfg {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io offset;\n-\tuint8_t __otx2_io y_mask;\n-\tuint8_t __otx2_io y_val;\n-\tuint8_t __otx2_io r_mask;\n-\tuint8_t __otx2_io r_val;\n-};\n-\n-struct nix_mark_format_cfg_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io mark_format_idx;\n-};\n-\n-struct nix_lso_format_cfg {\n-\tstruct mbox_msghdr hdr;\n-\tuint64_t __otx2_io field_mask;\n-\tuint64_t __otx2_io fields[NIX_LSO_FIELD_MAX];\n-};\n-\n-struct nix_lso_format_cfg_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io lso_format_idx;\n-};\n-\n-struct nix_rx_mode {\n-\tstruct mbox_msghdr hdr;\n-#define NIX_RX_MODE_UCAST BIT(0)\n-#define NIX_RX_MODE_PROMISC BIT(1)\n-#define NIX_RX_MODE_ALLMULTI BIT(2)\n-\tuint16_t __otx2_io mode;\n-};\n-\n-struct nix_rx_cfg {\n-\tstruct mbox_msghdr hdr;\n-#define NIX_RX_OL3_VERIFY BIT(0)\n-#define NIX_RX_OL4_VERIFY BIT(1)\n-\tuint8_t __otx2_io len_verify; /* Outer L3/L4 len check */\n-#define NIX_RX_CSUM_OL4_VERIFY BIT(0)\n-\tuint8_t __otx2_io csum_verify; /* Outer L4 checksum verification */\n-};\n-\n-struct nix_frs_cfg {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io update_smq; /* Update SMQ's min/max lens */\n-\tuint8_t __otx2_io update_minlen; /* Set minlen also */\n-\tuint8_t __otx2_io sdp_link; /* Set SDP RX link */\n-\tuint16_t __otx2_io maxlen;\n-\tuint16_t __otx2_io minlen;\n-};\n-\n-struct nix_set_vlan_tpid {\n-\tstruct mbox_msghdr hdr;\n-#define NIX_VLAN_TYPE_INNER 0\n-#define NIX_VLAN_TYPE_OUTER 1\n-\tuint8_t __otx2_io vlan_type;\n-\tuint16_t __otx2_io tpid;\n-};\n-\n-struct nix_bp_cfg_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io chan_base; /* Starting channel number */\n-\tuint8_t __otx2_io chan_cnt; /* Number of channels */\n-\tuint8_t __otx2_io bpid_per_chan;\n-\t/* bpid_per_chan = 0 assigns single bp id for range of channels */\n-\t/* bpid_per_chan = 1 assigns separate bp id for each channel */\n-};\n-\n-/* PF can be mapped to either CGX or LBK interface,\n- * so maximum 64 channels are possible.\n- */\n-#define NIX_MAX_CHAN\t64\n-struct nix_bp_cfg_rsp {\n-\tstruct mbox_msghdr hdr;\n-\t/* Channel and bpid mapping */\n-\tuint16_t __otx2_io chan_bpid[NIX_MAX_CHAN];\n-\t/* Number of channel for which bpids are assigned */\n-\tuint8_t __otx2_io chan_cnt;\n-};\n-\n-/* Global NIX inline IPSec configuration */\n-struct nix_inline_ipsec_cfg {\n-\tstruct mbox_msghdr hdr;\n-\tuint32_t __otx2_io cpt_credit;\n-\tstruct {\n-\t\tuint8_t __otx2_io egrp;\n-\t\tuint8_t __otx2_io opcode;\n-\t} gen_cfg;\n-\tstruct {\n-\t\tuint16_t __otx2_io cpt_pf_func;\n-\t\tuint8_t __otx2_io cpt_slot;\n-\t} inst_qsel;\n-\tuint8_t __otx2_io enable;\n-};\n-\n-/* Per NIX LF inline IPSec configuration */\n-struct nix_inline_ipsec_lf_cfg {\n-\tstruct mbox_msghdr hdr;\n-\tuint64_t __otx2_io sa_base_addr;\n-\tstruct {\n-\t\tuint32_t __otx2_io tag_const;\n-\t\tuint16_t __otx2_io lenm1_max;\n-\t\tuint8_t __otx2_io sa_pow2_size;\n-\t\tuint8_t __otx2_io tt;\n-\t} ipsec_cfg0;\n-\tstruct {\n-\t\tuint32_t __otx2_io sa_idx_max;\n-\t\tuint8_t __otx2_io sa_idx_w;\n-\t} ipsec_cfg1;\n-\tuint8_t __otx2_io enable;\n-};\n-\n-/* SSO mailbox error codes\n- * Range 501 - 600.\n- */\n-enum sso_af_status {\n-\tSSO_AF_ERR_PARAM\t= -501,\n-\tSSO_AF_ERR_LF_INVALID\t= -502,\n-\tSSO_AF_ERR_AF_LF_ALLOC\t= -503,\n-\tSSO_AF_ERR_GRP_EBUSY\t= -504,\n-\tSSO_AF_INVAL_NPA_PF_FUNC = -505,\n-};\n-\n-struct sso_lf_alloc_req {\n-\tstruct mbox_msghdr hdr;\n-\tint __otx2_io node;\n-\tuint16_t __otx2_io hwgrps;\n-};\n-\n-struct sso_lf_alloc_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint32_t __otx2_io xaq_buf_size;\n-\tuint32_t __otx2_io xaq_wq_entries;\n-\tuint32_t __otx2_io in_unit_entries;\n-\tuint16_t __otx2_io hwgrps;\n-};\n-\n-struct sso_lf_free_req {\n-\tstruct mbox_msghdr hdr;\n-\tint __otx2_io node;\n-\tuint16_t __otx2_io hwgrps;\n-};\n-\n-/* SSOW mailbox error codes\n- * Range 601 - 700.\n- */\n-enum ssow_af_status {\n-\tSSOW_AF_ERR_PARAM\t= -601,\n-\tSSOW_AF_ERR_LF_INVALID\t= -602,\n-\tSSOW_AF_ERR_AF_LF_ALLOC\t= -603,\n-};\n-\n-struct ssow_lf_alloc_req {\n-\tstruct mbox_msghdr hdr;\n-\tint __otx2_io node;\n-\tuint16_t __otx2_io hws;\n-};\n-\n-struct ssow_lf_free_req {\n-\tstruct mbox_msghdr hdr;\n-\tint __otx2_io node;\n-\tuint16_t __otx2_io hws;\n-};\n-\n-struct sso_hw_setconfig {\n-\tstruct mbox_msghdr hdr;\n-\tuint32_t __otx2_io npa_aura_id;\n-\tuint16_t __otx2_io npa_pf_func;\n-\tuint16_t __otx2_io hwgrps;\n-};\n-\n-struct sso_release_xaq {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io hwgrps;\n-};\n-\n-struct sso_info_req {\n-\tstruct mbox_msghdr hdr;\n-\tunion {\n-\t\tuint16_t __otx2_io grp;\n-\t\tuint16_t __otx2_io hws;\n-\t};\n-};\n-\n-struct sso_grp_priority {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io grp;\n-\tuint8_t __otx2_io priority;\n-\tuint8_t __otx2_io affinity;\n-\tuint8_t __otx2_io weight;\n-};\n-\n-struct sso_grp_qos_cfg {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io grp;\n-\tuint32_t __otx2_io xaq_limit;\n-\tuint16_t __otx2_io taq_thr;\n-\tuint16_t __otx2_io iaq_thr;\n-};\n-\n-struct sso_grp_stats {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io grp;\n-\tuint64_t __otx2_io ws_pc;\n-\tuint64_t __otx2_io ext_pc;\n-\tuint64_t __otx2_io wa_pc;\n-\tuint64_t __otx2_io ts_pc;\n-\tuint64_t __otx2_io ds_pc;\n-\tuint64_t __otx2_io dq_pc;\n-\tuint64_t __otx2_io aw_status;\n-\tuint64_t __otx2_io page_cnt;\n-};\n-\n-struct sso_hws_stats {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io hws;\n-\tuint64_t __otx2_io arbitration;\n-};\n-\n-/* CPT mailbox error codes\n- * Range 901 - 1000.\n- */\n-enum cpt_af_status {\n-\tCPT_AF_ERR_PARAM\t\t= -901,\n-\tCPT_AF_ERR_GRP_INVALID\t\t= -902,\n-\tCPT_AF_ERR_LF_INVALID\t\t= -903,\n-\tCPT_AF_ERR_ACCESS_DENIED\t= -904,\n-\tCPT_AF_ERR_SSO_PF_FUNC_INVALID\t= -905,\n-\tCPT_AF_ERR_NIX_PF_FUNC_INVALID\t= -906,\n-\tCPT_AF_ERR_INLINE_IPSEC_INB_ENA\t= -907,\n-\tCPT_AF_ERR_INLINE_IPSEC_OUT_ENA\t= -908\n-};\n-\n-/* CPT mbox message formats */\n-\n-struct cpt_rd_wr_reg_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint64_t __otx2_io reg_offset;\n-\tuint64_t __otx2_io *ret_val;\n-\tuint64_t __otx2_io val;\n-\tuint8_t __otx2_io is_write;\n-\t/* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */\n-\tuint8_t __otx2_io blkaddr;\n-};\n-\n-struct cpt_set_crypto_grp_req_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io crypto_eng_grp;\n-};\n-\n-struct cpt_lf_alloc_req_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io nix_pf_func;\n-\tuint16_t __otx2_io sso_pf_func;\n-\tuint16_t __otx2_io eng_grpmask;\n-\t/* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */\n-\tuint8_t __otx2_io blkaddr;\n-};\n-\n-struct cpt_lf_alloc_rsp_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io eng_grpmsk;\n-};\n-\n-#define CPT_INLINE_INBOUND\t0\n-#define CPT_INLINE_OUTBOUND\t1\n-\n-struct cpt_inline_ipsec_cfg_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io enable;\n-\tuint8_t __otx2_io slot;\n-\tuint8_t __otx2_io dir;\n-\tuint16_t __otx2_io sso_pf_func; /* Inbound path SSO_PF_FUNC */\n-\tuint16_t __otx2_io nix_pf_func; /* Outbound path NIX_PF_FUNC */\n-};\n-\n-struct cpt_rx_inline_lf_cfg_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io sso_pf_func;\n-};\n-\n-enum cpt_eng_type {\n-\tCPT_ENG_TYPE_AE = 1,\n-\tCPT_ENG_TYPE_SE = 2,\n-\tCPT_ENG_TYPE_IE = 3,\n-\tCPT_MAX_ENG_TYPES,\n-};\n-\n-/* CPT HW capabilities */\n-union cpt_eng_caps {\n-\tuint64_t __otx2_io u;\n-\tstruct {\n-\t\tuint64_t __otx2_io reserved_0_4:5;\n-\t\tuint64_t __otx2_io mul:1;\n-\t\tuint64_t __otx2_io sha1_sha2:1;\n-\t\tuint64_t __otx2_io chacha20:1;\n-\t\tuint64_t __otx2_io zuc_snow3g:1;\n-\t\tuint64_t __otx2_io sha3:1;\n-\t\tuint64_t __otx2_io aes:1;\n-\t\tuint64_t __otx2_io kasumi:1;\n-\t\tuint64_t __otx2_io des:1;\n-\t\tuint64_t __otx2_io crc:1;\n-\t\tuint64_t __otx2_io reserved_14_63:50;\n-\t};\n-};\n-\n-struct cpt_caps_rsp_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io cpt_pf_drv_version;\n-\tuint8_t __otx2_io cpt_revision;\n-\tunion cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];\n-};\n-\n-/* NPC mbox message structs */\n-\n-#define NPC_MCAM_ENTRY_INVALID\t0xFFFF\n-#define NPC_MCAM_INVALID_MAP\t0xFFFF\n-\n-/* NPC mailbox error codes\n- * Range 701 - 800.\n- */\n-enum npc_af_status {\n-\tNPC_MCAM_INVALID_REQ\t= -701,\n-\tNPC_MCAM_ALLOC_DENIED\t= -702,\n-\tNPC_MCAM_ALLOC_FAILED\t= -703,\n-\tNPC_MCAM_PERM_DENIED\t= -704,\n-\tNPC_AF_ERR_HIGIG_CONFIG_FAIL\t= -705,\n-};\n-\n-struct npc_mcam_alloc_entry_req {\n-\tstruct mbox_msghdr hdr;\n-#define NPC_MAX_NONCONTIG_ENTRIES\t256\n-\tuint8_t __otx2_io contig; /* Contiguous entries ? */\n-#define NPC_MCAM_ANY_PRIO\t\t0\n-#define NPC_MCAM_LOWER_PRIO\t\t1\n-#define NPC_MCAM_HIGHER_PRIO\t\t2\n-\tuint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */\n-\tuint16_t __otx2_io ref_entry;\n-\tuint16_t __otx2_io count; /* Number of entries requested */\n-};\n-\n-struct npc_mcam_alloc_entry_rsp {\n-\tstruct mbox_msghdr hdr;\n-\t/* Entry alloc'ed or start index if contiguous.\n-\t * Invalid in case of non-contiguous.\n-\t */\n-\tuint16_t __otx2_io entry;\n-\tuint16_t __otx2_io count; /* Number of entries allocated */\n-\tuint16_t __otx2_io free_count; /* Number of entries available */\n-\tuint16_t __otx2_io entry_list[NPC_MAX_NONCONTIG_ENTRIES];\n-};\n-\n-struct npc_mcam_free_entry_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io entry; /* Entry index to be freed */\n-\tuint8_t __otx2_io all; /* Free all entries alloc'ed to this PFVF */\n-};\n-\n-struct mcam_entry {\n-#define NPC_MAX_KWS_IN_KEY\t7 /* Number of keywords in max key width */\n-\tuint64_t __otx2_io kw[NPC_MAX_KWS_IN_KEY];\n-\tuint64_t __otx2_io kw_mask[NPC_MAX_KWS_IN_KEY];\n-\tuint64_t __otx2_io action;\n-\tuint64_t __otx2_io vtag_action;\n-};\n-\n-struct npc_mcam_write_entry_req {\n-\tstruct mbox_msghdr hdr;\n-\tstruct mcam_entry entry_data;\n-\tuint16_t __otx2_io entry; /* MCAM entry to write this match key */\n-\tuint16_t __otx2_io cntr;\t /* Counter for this MCAM entry */\n-\tuint8_t __otx2_io intf;\t /* Rx or Tx interface */\n-\tuint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */\n-\tuint8_t __otx2_io set_cntr; /* Set counter for this entry ? */\n-};\n-\n-/* Enable/Disable a given entry */\n-struct npc_mcam_ena_dis_entry_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io entry;\n-};\n-\n-struct npc_mcam_shift_entry_req {\n-\tstruct mbox_msghdr hdr;\n-#define NPC_MCAM_MAX_SHIFTS\t64\n-\tuint16_t __otx2_io curr_entry[NPC_MCAM_MAX_SHIFTS];\n-\tuint16_t __otx2_io new_entry[NPC_MCAM_MAX_SHIFTS];\n-\tuint16_t __otx2_io shift_count; /* Number of entries to shift */\n-};\n-\n-struct npc_mcam_shift_entry_rsp {\n-\tstruct mbox_msghdr hdr;\n-\t/* Index in 'curr_entry', not entry itself */\n-\tuint16_t __otx2_io failed_entry_idx;\n-};\n-\n-struct npc_mcam_alloc_counter_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io contig;\t/* Contiguous counters ? */\n-#define NPC_MAX_NONCONTIG_COUNTERS 64\n-\tuint16_t __otx2_io count;\t/* Number of counters requested */\n-};\n-\n-struct npc_mcam_alloc_counter_rsp {\n-\tstruct mbox_msghdr hdr;\n-\t/* Counter alloc'ed or start idx if contiguous.\n-\t * Invalid incase of non-contiguous.\n-\t */\n-\tuint16_t __otx2_io cntr;\n-\tuint16_t __otx2_io count; /* Number of counters allocated */\n-\tuint16_t __otx2_io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];\n-};\n-\n-struct npc_mcam_oper_counter_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io cntr; /* Free a counter or clear/fetch it's stats */\n-};\n-\n-struct npc_mcam_oper_counter_rsp {\n-\tstruct mbox_msghdr hdr;\n-\t/* valid only while fetching counter's stats */\n-\tuint64_t __otx2_io stat;\n-};\n-\n-struct npc_mcam_unmap_counter_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io cntr;\n-\tuint16_t __otx2_io entry; /* Entry and counter to be unmapped */\n-\tuint8_t __otx2_io all; /* Unmap all entries using this counter ? */\n-};\n-\n-struct npc_mcam_alloc_and_write_entry_req {\n-\tstruct mbox_msghdr hdr;\n-\tstruct mcam_entry entry_data;\n-\tuint16_t __otx2_io ref_entry;\n-\tuint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */\n-\tuint8_t __otx2_io intf;\t /* Rx or Tx interface */\n-\tuint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */\n-\tuint8_t __otx2_io alloc_cntr; /* Allocate counter and map ? */\n-};\n-\n-struct npc_mcam_alloc_and_write_entry_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io entry;\n-\tuint16_t __otx2_io cntr;\n-};\n-\n-struct npc_get_kex_cfg_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint64_t __otx2_io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */\n-\tuint64_t __otx2_io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */\n-#define NPC_MAX_INTF\t2\n-#define NPC_MAX_LID\t8\n-#define NPC_MAX_LT\t16\n-#define NPC_MAX_LD\t2\n-#define NPC_MAX_LFL\t16\n-\t/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */\n-\tuint64_t __otx2_io kex_ld_flags[NPC_MAX_LD];\n-\t/* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */\n-\tuint64_t __otx2_io\n-\tintf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];\n-\t/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */\n-\tuint64_t __otx2_io\n-\tintf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];\n-#define MKEX_NAME_LEN 128\n-\tuint8_t __otx2_io mkex_pfl_name[MKEX_NAME_LEN];\n-};\n-\n-enum header_fields {\n-\tNPC_DMAC,\n-\tNPC_SMAC,\n-\tNPC_ETYPE,\n-\tNPC_OUTER_VID,\n-\tNPC_TOS,\n-\tNPC_SIP_IPV4,\n-\tNPC_DIP_IPV4,\n-\tNPC_SIP_IPV6,\n-\tNPC_DIP_IPV6,\n-\tNPC_SPORT_TCP,\n-\tNPC_DPORT_TCP,\n-\tNPC_SPORT_UDP,\n-\tNPC_DPORT_UDP,\n-\tNPC_FDSA_VAL,\n-\tNPC_HEADER_FIELDS_MAX,\n-};\n-\n-struct flow_msg {\n-\tunsigned char __otx2_io dmac[6];\n-\tunsigned char __otx2_io smac[6];\n-\tuint16_t __otx2_io etype;\n-\tuint16_t __otx2_io vlan_etype;\n-\tuint16_t __otx2_io vlan_tci;\n-\tunion {\n-\t\tuint32_t __otx2_io ip4src;\n-\t\tuint32_t __otx2_io ip6src[4];\n-\t};\n-\tunion {\n-\t\tuint32_t __otx2_io ip4dst;\n-\t\tuint32_t __otx2_io ip6dst[4];\n-\t};\n-\tuint8_t __otx2_io tos;\n-\tuint8_t __otx2_io ip_ver;\n-\tuint8_t __otx2_io ip_proto;\n-\tuint8_t __otx2_io tc;\n-\tuint16_t __otx2_io sport;\n-\tuint16_t __otx2_io dport;\n-};\n-\n-struct npc_install_flow_req {\n-\tstruct mbox_msghdr hdr;\n-\tstruct flow_msg packet;\n-\tstruct flow_msg mask;\n-\tuint64_t __otx2_io features;\n-\tuint16_t __otx2_io entry;\n-\tuint16_t __otx2_io channel;\n-\tuint8_t __otx2_io intf;\n-\tuint8_t __otx2_io set_cntr;\n-\tuint8_t __otx2_io default_rule;\n-\t/* Overwrite(0) or append(1) flow to default rule? */\n-\tuint8_t __otx2_io append;\n-\tuint16_t __otx2_io vf;\n-\t/* action */\n-\tuint32_t __otx2_io index;\n-\tuint16_t __otx2_io match_id;\n-\tuint8_t __otx2_io flow_key_alg;\n-\tuint8_t __otx2_io op;\n-\t/* vtag action */\n-\tuint8_t __otx2_io vtag0_type;\n-\tuint8_t __otx2_io vtag0_valid;\n-\tuint8_t __otx2_io vtag1_type;\n-\tuint8_t __otx2_io vtag1_valid;\n-\n-\t/* vtag tx action */\n-\tuint16_t __otx2_io vtag0_def;\n-\tuint8_t __otx2_io vtag0_op;\n-\tuint16_t __otx2_io vtag1_def;\n-\tuint8_t __otx2_io vtag1_op;\n-};\n-\n-struct npc_install_flow_rsp {\n-\tstruct mbox_msghdr hdr;\n-\t/* Negative if no counter else counter number */\n-\tint __otx2_io counter;\n-};\n-\n-struct npc_delete_flow_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io entry;\n-\tuint16_t __otx2_io start;/*Disable range of entries */\n-\tuint16_t __otx2_io end;\n-\tuint8_t __otx2_io all; /* PF + VFs */\n-};\n-\n-struct npc_mcam_read_entry_req {\n-\tstruct mbox_msghdr hdr;\n-\t/* MCAM entry to read */\n-\tuint16_t __otx2_io entry;\n-};\n-\n-struct npc_mcam_read_entry_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tstruct mcam_entry entry_data;\n-\tuint8_t __otx2_io intf;\n-\tuint8_t __otx2_io enable;\n-};\n-\n-struct npc_mcam_read_base_rule_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tstruct mcam_entry entry_data;\n-};\n-\n-/* TIM mailbox error codes\n- * Range 801 - 900.\n- */\n-enum tim_af_status {\n-\tTIM_AF_NO_RINGS_LEFT\t\t\t= -801,\n-\tTIM_AF_INVALID_NPA_PF_FUNC\t\t= -802,\n-\tTIM_AF_INVALID_SSO_PF_FUNC\t\t= -803,\n-\tTIM_AF_RING_STILL_RUNNING\t\t= -804,\n-\tTIM_AF_LF_INVALID\t\t\t= -805,\n-\tTIM_AF_CSIZE_NOT_ALIGNED\t\t= -806,\n-\tTIM_AF_CSIZE_TOO_SMALL\t\t\t= -807,\n-\tTIM_AF_CSIZE_TOO_BIG\t\t\t= -808,\n-\tTIM_AF_INTERVAL_TOO_SMALL\t\t= -809,\n-\tTIM_AF_INVALID_BIG_ENDIAN_VALUE\t\t= -810,\n-\tTIM_AF_INVALID_CLOCK_SOURCE\t\t= -811,\n-\tTIM_AF_GPIO_CLK_SRC_NOT_ENABLED\t\t= -812,\n-\tTIM_AF_INVALID_BSIZE\t\t\t= -813,\n-\tTIM_AF_INVALID_ENABLE_PERIODIC\t\t= -814,\n-\tTIM_AF_INVALID_ENABLE_DONTFREE\t\t= -815,\n-\tTIM_AF_ENA_DONTFRE_NSET_PERIODIC\t= -816,\n-\tTIM_AF_RING_ALREADY_DISABLED\t\t= -817,\n-};\n-\n-enum tim_clk_srcs {\n-\tTIM_CLK_SRCS_TENNS\t= 0,\n-\tTIM_CLK_SRCS_GPIO\t= 1,\n-\tTIM_CLK_SRCS_GTI\t= 2,\n-\tTIM_CLK_SRCS_PTP\t= 3,\n-\tTIM_CLK_SRSC_INVALID,\n-};\n-\n-enum tim_gpio_edge {\n-\tTIM_GPIO_NO_EDGE\t\t= 0,\n-\tTIM_GPIO_LTOH_TRANS\t\t= 1,\n-\tTIM_GPIO_HTOL_TRANS\t\t= 2,\n-\tTIM_GPIO_BOTH_TRANS\t\t= 3,\n-\tTIM_GPIO_INVALID,\n-};\n-\n-enum ptp_op {\n-\tPTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */\n-\tPTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */\n-};\n-\n-struct ptp_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io op;\n-\tint64_t __otx2_io scaled_ppm;\n-\tuint8_t __otx2_io is_pmu;\n-};\n-\n-struct ptp_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint64_t __otx2_io clk;\n-\tuint64_t __otx2_io tsc;\n-};\n-\n-struct get_hw_cap_rsp {\n-\tstruct mbox_msghdr hdr;\n-\t/* Schq mapping fixed or flexible */\n-\tuint8_t __otx2_io nix_fixed_txschq_mapping;\n-\tuint8_t __otx2_io nix_shaping; /* Is shaping and coloring supported */\n-};\n-\n-struct ndc_sync_op {\n-\tstruct mbox_msghdr hdr;\n-\tuint8_t __otx2_io nix_lf_tx_sync;\n-\tuint8_t __otx2_io nix_lf_rx_sync;\n-\tuint8_t __otx2_io npa_lf_sync;\n-};\n-\n-struct tim_lf_alloc_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io ring;\n-\tuint16_t __otx2_io npa_pf_func;\n-\tuint16_t __otx2_io sso_pf_func;\n-};\n-\n-struct tim_ring_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io ring;\n-};\n-\n-struct tim_config_req {\n-\tstruct mbox_msghdr hdr;\n-\tuint16_t __otx2_io ring;\n-\tuint8_t __otx2_io bigendian;\n-\tuint8_t __otx2_io clocksource;\n-\tuint8_t __otx2_io enableperiodic;\n-\tuint8_t __otx2_io enabledontfreebuffer;\n-\tuint32_t __otx2_io bucketsize;\n-\tuint32_t __otx2_io chunksize;\n-\tuint32_t __otx2_io interval;\n-};\n-\n-struct tim_lf_alloc_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint64_t __otx2_io tenns_clk;\n-};\n-\n-struct tim_enable_rsp {\n-\tstruct mbox_msghdr hdr;\n-\tuint64_t __otx2_io timestarted;\n-\tuint32_t __otx2_io currentbucket;\n-};\n-\n-/* REE mailbox error codes\n- * Range 1001 - 1100.\n- */\n-enum ree_af_status {\n-\tREE_AF_ERR_RULE_UNKNOWN_VALUE\t\t= -1001,\n-\tREE_AF_ERR_LF_NO_MORE_RESOURCES\t\t= -1002,\n-\tREE_AF_ERR_LF_INVALID\t\t\t= -1003,\n-\tREE_AF_ERR_ACCESS_DENIED\t\t= -1004,\n-\tREE_AF_ERR_RULE_DB_PARTIAL\t\t= -1005,\n-\tREE_AF_ERR_RULE_DB_EQ_BAD_VALUE\t\t= -1006,\n-\tREE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED\t= -1007,\n-\tREE_AF_ERR_BLOCK_NOT_IMPLEMENTED\t= -1008,\n-\tREE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG\t= -1009,\n-\tREE_AF_ERR_RULE_DB_OFFSET_TOO_BIG\t= -1010,\n-\tREE_AF_ERR_Q_IS_GRACEFUL_DIS\t\t= -1011,\n-\tREE_AF_ERR_Q_NOT_GRACEFUL_DIS\t\t= -1012,\n-\tREE_AF_ERR_RULE_DB_ALLOC_FAILED\t\t= -1013,\n-\tREE_AF_ERR_RULE_DB_TOO_BIG\t\t= -1014,\n-\tREE_AF_ERR_RULE_DB_GEQ_BAD_VALUE\t= -1015,\n-\tREE_AF_ERR_RULE_DB_LEQ_BAD_VALUE\t= -1016,\n-\tREE_AF_ERR_RULE_DB_WRONG_LENGTH\t\t= -1017,\n-\tREE_AF_ERR_RULE_DB_WRONG_OFFSET\t\t= -1018,\n-\tREE_AF_ERR_RULE_DB_BLOCK_TOO_BIG\t= -1019,\n-\tREE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST\t= -1020,\n-\tREE_AF_ERR_RULE_DBI_ALLOC_FAILED\t= -1021,\n-\tREE_AF_ERR_LF_WRONG_PRIORITY\t\t= -1022,\n-\tREE_AF_ERR_LF_SIZE_TOO_BIG\t\t= -1023,\n-};\n-\n-/* REE mbox message formats */\n-\n-struct ree_req_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint32_t __otx2_io blkaddr;\n-};\n-\n-struct ree_lf_req_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint32_t __otx2_io blkaddr;\n-\tuint32_t __otx2_io size;\n-\tuint8_t __otx2_io lf;\n-\tuint8_t __otx2_io pri;\n-};\n-\n-struct ree_rule_db_prog_req_msg {\n-\tstruct mbox_msghdr hdr;\n-#define REE_RULE_DB_REQ_BLOCK_SIZE (MBOX_SIZE >> 1)\n-\tuint8_t __otx2_io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];\n-\tuint32_t __otx2_io blkaddr; /* REE0 or REE1 */\n-\tuint32_t __otx2_io total_len; /* total len of rule db */\n-\tuint32_t __otx2_io offset; /* offset of current rule db block */\n-\tuint16_t __otx2_io len; /* length of rule db block */\n-\tuint8_t __otx2_io is_last; /* is this the last block */\n-\tuint8_t __otx2_io is_incremental; /* is incremental flow */\n-\tuint8_t __otx2_io is_dbi; /* is rule db incremental */\n-};\n-\n-struct ree_rule_db_get_req_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint32_t __otx2_io blkaddr;\n-\tuint32_t __otx2_io offset; /* retrieve db from this offset */\n-\tuint8_t __otx2_io is_dbi; /* is request for rule db incremental */\n-};\n-\n-struct ree_rd_wr_reg_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint64_t __otx2_io reg_offset;\n-\tuint64_t __otx2_io *ret_val;\n-\tuint64_t __otx2_io val;\n-\tuint32_t __otx2_io blkaddr;\n-\tuint8_t __otx2_io is_write;\n-};\n-\n-struct ree_rule_db_len_rsp_msg {\n-\tstruct mbox_msghdr hdr;\n-\tuint32_t __otx2_io blkaddr;\n-\tuint32_t __otx2_io len;\n-\tuint32_t __otx2_io inc_len;\n-};\n-\n-struct ree_rule_db_get_rsp_msg {\n-\tstruct mbox_msghdr hdr;\n-#define REE_RULE_DB_RSP_BLOCK_SIZE (MBOX_DOWN_TX_SIZE - SZ_1K)\n-\tuint8_t __otx2_io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];\n-\tuint32_t __otx2_io total_len; /* total len of rule db */\n-\tuint32_t __otx2_io offset; /* offset of current rule db block */\n-\tuint16_t __otx2_io len; /* length of rule db block */\n-\tuint8_t __otx2_io is_last; /* is this the last block */\n-};\n-\n-__rte_internal\n-const char *otx2_mbox_id2name(uint16_t id);\n-int otx2_mbox_id2size(uint16_t id);\n-void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);\n-int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,\n-\t\t int direction, int ndevsi, uint64_t intr_offset);\n-void otx2_mbox_fini(struct otx2_mbox *mbox);\n-__rte_internal\n-void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);\n-__rte_internal\n-int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);\n-int otx2_mbox_wait_for_rsp_tmo(struct otx2_mbox *mbox, int devid, uint32_t tmo);\n-__rte_internal\n-int otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, void **msg);\n-__rte_internal\n-int otx2_mbox_get_rsp_tmo(struct otx2_mbox *mbox, int devid, void **msg,\n-\t\t\t uint32_t tmo);\n-int otx2_mbox_get_availmem(struct otx2_mbox *mbox, int devid);\n-__rte_internal\n-struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,\n-\t\t\t\t\t int size, int size_rsp);\n-\n-static inline struct mbox_msghdr *\n-otx2_mbox_alloc_msg(struct otx2_mbox *mbox, int devid, int size)\n-{\n-\treturn otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);\n-}\n-\n-static inline void\n-otx2_mbox_req_init(uint16_t mbox_id, void *msghdr)\n-{\n-\tstruct mbox_msghdr *hdr = msghdr;\n-\n-\thdr->sig = OTX2_MBOX_REQ_SIG;\n-\thdr->ver = OTX2_MBOX_VERSION;\n-\thdr->id = mbox_id;\n-\thdr->pcifunc = 0;\n-}\n-\n-static inline void\n-otx2_mbox_rsp_init(uint16_t mbox_id, void *msghdr)\n-{\n-\tstruct mbox_msghdr *hdr = msghdr;\n-\n-\thdr->sig = OTX2_MBOX_RSP_SIG;\n-\thdr->rc = -ETIMEDOUT;\n-\thdr->id = mbox_id;\n-}\n-\n-static inline bool\n-otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid)\n-{\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[devid];\n-\tbool ret;\n-\n-\trte_spinlock_lock(&mdev->mbox_lock);\n-\tret = mdev->num_msgs != 0;\n-\trte_spinlock_unlock(&mdev->mbox_lock);\n-\n-\treturn ret;\n-}\n-\n-static inline int\n-otx2_mbox_process(struct otx2_mbox *mbox)\n-{\n-\totx2_mbox_msg_send(mbox, 0);\n-\treturn otx2_mbox_get_rsp(mbox, 0, NULL);\n-}\n-\n-static inline int\n-otx2_mbox_process_msg(struct otx2_mbox *mbox, void **msg)\n-{\n-\totx2_mbox_msg_send(mbox, 0);\n-\treturn otx2_mbox_get_rsp(mbox, 0, msg);\n-}\n-\n-static inline int\n-otx2_mbox_process_tmo(struct otx2_mbox *mbox, uint32_t tmo)\n-{\n-\totx2_mbox_msg_send(mbox, 0);\n-\treturn otx2_mbox_get_rsp_tmo(mbox, 0, NULL, tmo);\n-}\n-\n-static inline int\n-otx2_mbox_process_msg_tmo(struct otx2_mbox *mbox, void **msg, uint32_t tmo)\n-{\n-\totx2_mbox_msg_send(mbox, 0);\n-\treturn otx2_mbox_get_rsp_tmo(mbox, 0, msg, tmo);\n-}\n-\n-int otx2_send_ready_msg(struct otx2_mbox *mbox, uint16_t *pf_func /* out */);\n-int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, uint16_t pf_func,\n-\t\t\tuint16_t id);\n-\n-#define M(_name, _id, _fn_name, _req_type, _rsp_type)\t\t\t\\\n-static inline struct _req_type\t\t\t\t\t\t\\\n-*otx2_mbox_alloc_msg_ ## _fn_name(struct otx2_mbox *mbox)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tstruct _req_type *req;\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treq = (struct _req_type *)otx2_mbox_alloc_msg_rsp(\t\t\\\n-\t\tmbox, 0, sizeof(struct _req_type),\t\t\t\\\n-\t\tsizeof(struct _rsp_type));\t\t\t\t\\\n-\tif (!req)\t\t\t\t\t\t\t\\\n-\t\treturn NULL;\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treq->hdr.sig = OTX2_MBOX_REQ_SIG;\t\t\t\t\\\n-\treq->hdr.id = _id;\t\t\t\t\t\t\\\n-\totx2_mbox_dbg(\"id=0x%x (%s)\",\t\t\t\t\t\\\n-\t\t\treq->hdr.id, otx2_mbox_id2name(req->hdr.id));\t\\\n-\treturn req;\t\t\t\t\t\t\t\\\n-}\n-\n-MBOX_MESSAGES\n-#undef M\n-\n-/* This is required for copy operations from device memory which do not work on\n- * addresses which are unaligned to 16B. This is because of specific\n- * optimizations to libc memcpy.\n- */\n-static inline volatile void *\n-otx2_mbox_memcpy(volatile void *d, const volatile void *s, size_t l)\n-{\n-\tconst volatile uint8_t *sb;\n-\tvolatile uint8_t *db;\n-\tsize_t i;\n-\n-\tif (!d || !s)\n-\t\treturn NULL;\n-\tdb = (volatile uint8_t *)d;\n-\tsb = (const volatile uint8_t *)s;\n-\tfor (i = 0; i < l; i++)\n-\t\tdb[i] = sb[i];\n-\treturn d;\n-}\n-\n-/* This is required for memory operations from device memory which do not\n- * work on addresses which are unaligned to 16B. This is because of specific\n- * optimizations to libc memset.\n- */\n-static inline void\n-otx2_mbox_memset(volatile void *d, uint8_t val, size_t l)\n-{\n-\tvolatile uint8_t *db;\n-\tsize_t i = 0;\n-\n-\tif (!d || !l)\n-\t\treturn;\n-\tdb = (volatile uint8_t *)d;\n-\tfor (i = 0; i < l; i++)\n-\t\tdb[i] = val;\n-}\n-\n-#endif /* __OTX2_MBOX_H__ */\ndiff --git a/drivers/common/octeontx2/otx2_sec_idev.c b/drivers/common/octeontx2/otx2_sec_idev.c\ndeleted file mode 100644\nindex b561b67174..0000000000\n--- a/drivers/common/octeontx2/otx2_sec_idev.c\n+++ /dev/null\n@@ -1,183 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2020 Marvell International Ltd.\n- */\n-\n-#include <rte_atomic.h>\n-#include <rte_bus_pci.h>\n-#include <ethdev_driver.h>\n-#include <rte_spinlock.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_sec_idev.h\"\n-\n-static struct otx2_sec_idev_cfg sec_cfg[OTX2_MAX_INLINE_PORTS];\n-\n-/**\n- * @internal\n- * Check if rte_eth_dev is security offload capable otx2_eth_dev\n- */\n-uint8_t\n-otx2_eth_dev_is_sec_capable(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct rte_pci_device *pci_dev;\n-\n-\tpci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\n-\tif (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_PF ||\n-\t pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_VF ||\n-\t pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_AF_VF)\n-\t\treturn 1;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_sec_idev_cfg_init(int port_id)\n-{\n-\tstruct otx2_sec_idev_cfg *cfg;\n-\tint i;\n-\n-\tcfg = &sec_cfg[port_id];\n-\tcfg->tx_cpt_idx = 0;\n-\trte_spinlock_init(&cfg->tx_cpt_lock);\n-\n-\tfor (i = 0; i < OTX2_MAX_CPT_QP_PER_PORT; i++) {\n-\t\tcfg->tx_cpt[i].qp = NULL;\n-\t\trte_atomic16_set(&cfg->tx_cpt[i].ref_cnt, 0);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_sec_idev_tx_cpt_qp_add(uint16_t port_id, struct otx2_cpt_qp *qp)\n-{\n-\tstruct otx2_sec_idev_cfg *cfg;\n-\tint i, ret;\n-\n-\tif (qp == NULL || port_id >= OTX2_MAX_INLINE_PORTS)\n-\t\treturn -EINVAL;\n-\n-\tcfg = &sec_cfg[port_id];\n-\n-\t/* Find a free slot to save CPT LF */\n-\n-\trte_spinlock_lock(&cfg->tx_cpt_lock);\n-\n-\tfor (i = 0; i < OTX2_MAX_CPT_QP_PER_PORT; i++) {\n-\t\tif (cfg->tx_cpt[i].qp == NULL) {\n-\t\t\tcfg->tx_cpt[i].qp = qp;\n-\t\t\tret = 0;\n-\t\t\tgoto unlock;\n-\t\t}\n-\t}\n-\n-\tret = -EINVAL;\n-\n-unlock:\n-\trte_spinlock_unlock(&cfg->tx_cpt_lock);\n-\treturn ret;\n-}\n-\n-int\n-otx2_sec_idev_tx_cpt_qp_remove(struct otx2_cpt_qp *qp)\n-{\n-\tstruct otx2_sec_idev_cfg *cfg;\n-\tuint16_t port_id;\n-\tint i, ret;\n-\n-\tif (qp == NULL)\n-\t\treturn -EINVAL;\n-\n-\tfor (port_id = 0; port_id < OTX2_MAX_INLINE_PORTS; port_id++) {\n-\t\tcfg = &sec_cfg[port_id];\n-\n-\t\trte_spinlock_lock(&cfg->tx_cpt_lock);\n-\n-\t\tfor (i = 0; i < OTX2_MAX_CPT_QP_PER_PORT; i++) {\n-\t\t\tif (cfg->tx_cpt[i].qp != qp)\n-\t\t\t\tcontinue;\n-\n-\t\t\t/* Don't free if the QP is in use by any sec session */\n-\t\t\tif (rte_atomic16_read(&cfg->tx_cpt[i].ref_cnt)) {\n-\t\t\t\tret = -EBUSY;\n-\t\t\t} else {\n-\t\t\t\tcfg->tx_cpt[i].qp = NULL;\n-\t\t\t\tret = 0;\n-\t\t\t}\n-\n-\t\t\tgoto unlock;\n-\t\t}\n-\n-\t\trte_spinlock_unlock(&cfg->tx_cpt_lock);\n-\t}\n-\n-\treturn -ENOENT;\n-\n-unlock:\n-\trte_spinlock_unlock(&cfg->tx_cpt_lock);\n-\treturn ret;\n-}\n-\n-int\n-otx2_sec_idev_tx_cpt_qp_get(uint16_t port_id, struct otx2_cpt_qp **qp)\n-{\n-\tstruct otx2_sec_idev_cfg *cfg;\n-\tuint16_t index;\n-\tint i, ret;\n-\n-\tif (port_id >= OTX2_MAX_INLINE_PORTS || qp == NULL)\n-\t\treturn -EINVAL;\n-\n-\tcfg = &sec_cfg[port_id];\n-\n-\trte_spinlock_lock(&cfg->tx_cpt_lock);\n-\n-\tindex = cfg->tx_cpt_idx;\n-\n-\t/* Get the next index with valid data */\n-\tfor (i = 0; i < OTX2_MAX_CPT_QP_PER_PORT; i++) {\n-\t\tif (cfg->tx_cpt[index].qp != NULL)\n-\t\t\tbreak;\n-\t\tindex = (index + 1) % OTX2_MAX_CPT_QP_PER_PORT;\n-\t}\n-\n-\tif (i >= OTX2_MAX_CPT_QP_PER_PORT) {\n-\t\tret = -EINVAL;\n-\t\tgoto unlock;\n-\t}\n-\n-\t*qp = cfg->tx_cpt[index].qp;\n-\trte_atomic16_inc(&cfg->tx_cpt[index].ref_cnt);\n-\n-\tcfg->tx_cpt_idx = (index + 1) % OTX2_MAX_CPT_QP_PER_PORT;\n-\n-\tret = 0;\n-\n-unlock:\n-\trte_spinlock_unlock(&cfg->tx_cpt_lock);\n-\treturn ret;\n-}\n-\n-int\n-otx2_sec_idev_tx_cpt_qp_put(struct otx2_cpt_qp *qp)\n-{\n-\tstruct otx2_sec_idev_cfg *cfg;\n-\tuint16_t port_id;\n-\tint i;\n-\n-\tif (qp == NULL)\n-\t\treturn -EINVAL;\n-\n-\tfor (port_id = 0; port_id < OTX2_MAX_INLINE_PORTS; port_id++) {\n-\t\tcfg = &sec_cfg[port_id];\n-\t\tfor (i = 0; i < OTX2_MAX_CPT_QP_PER_PORT; i++) {\n-\t\t\tif (cfg->tx_cpt[i].qp == qp) {\n-\t\t\t\trte_atomic16_dec(&cfg->tx_cpt[i].ref_cnt);\n-\t\t\t\treturn 0;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\treturn -EINVAL;\n-}\ndiff --git a/drivers/common/octeontx2/otx2_sec_idev.h b/drivers/common/octeontx2/otx2_sec_idev.h\ndeleted file mode 100644\nindex 89cdaf66ab..0000000000\n--- a/drivers/common/octeontx2/otx2_sec_idev.h\n+++ /dev/null\n@@ -1,43 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_SEC_IDEV_H_\n-#define _OTX2_SEC_IDEV_H_\n-\n-#include <rte_ethdev.h>\n-\n-#define OTX2_MAX_CPT_QP_PER_PORT 64\n-#define OTX2_MAX_INLINE_PORTS 64\n-\n-struct otx2_cpt_qp;\n-\n-struct otx2_sec_idev_cfg {\n-\tstruct {\n-\t\tstruct otx2_cpt_qp *qp;\n-\t\trte_atomic16_t ref_cnt;\n-\t} tx_cpt[OTX2_MAX_CPT_QP_PER_PORT];\n-\n-\tuint16_t tx_cpt_idx;\n-\trte_spinlock_t tx_cpt_lock;\n-};\n-\n-__rte_internal\n-uint8_t otx2_eth_dev_is_sec_capable(struct rte_eth_dev *eth_dev);\n-\n-__rte_internal\n-int otx2_sec_idev_cfg_init(int port_id);\n-\n-__rte_internal\n-int otx2_sec_idev_tx_cpt_qp_add(uint16_t port_id, struct otx2_cpt_qp *qp);\n-\n-__rte_internal\n-int otx2_sec_idev_tx_cpt_qp_remove(struct otx2_cpt_qp *qp);\n-\n-__rte_internal\n-int otx2_sec_idev_tx_cpt_qp_put(struct otx2_cpt_qp *qp);\n-\n-__rte_internal\n-int otx2_sec_idev_tx_cpt_qp_get(uint16_t port_id, struct otx2_cpt_qp **qp);\n-\n-#endif /* _OTX2_SEC_IDEV_H_ */\ndiff --git a/drivers/common/octeontx2/version.map b/drivers/common/octeontx2/version.map\ndeleted file mode 100644\nindex b58f19ce32..0000000000\n--- a/drivers/common/octeontx2/version.map\n+++ /dev/null\n@@ -1,44 +0,0 @@\n-INTERNAL {\n-\tglobal:\n-\n-\totx2_dev_active_vfs;\n-\totx2_dev_fini;\n-\totx2_dev_priv_init;\n-\totx2_disable_irqs;\n-\totx2_eth_dev_is_sec_capable;\n-\totx2_intra_dev_get_cfg;\n-\totx2_logtype_base;\n-\totx2_logtype_dpi;\n-\totx2_logtype_ep;\n-\totx2_logtype_mbox;\n-\totx2_logtype_nix;\n-\totx2_logtype_npa;\n-\totx2_logtype_npc;\n-\totx2_logtype_ree;\n-\totx2_logtype_sso;\n-\totx2_logtype_tim;\n-\totx2_logtype_tm;\n-\totx2_mbox_alloc_msg_rsp;\n-\totx2_mbox_get_rsp;\n-\totx2_mbox_get_rsp_tmo;\n-\totx2_mbox_id2name;\n-\totx2_mbox_msg_send;\n-\totx2_mbox_wait_for_rsp;\n-\totx2_npa_lf_active;\n-\totx2_npa_lf_obj_get;\n-\totx2_npa_lf_obj_ref;\n-\totx2_npa_pf_func_get;\n-\totx2_npa_set_defaults;\n-\totx2_parse_common_devargs;\n-\totx2_register_irq;\n-\totx2_sec_idev_cfg_init;\n-\totx2_sec_idev_tx_cpt_qp_add;\n-\totx2_sec_idev_tx_cpt_qp_get;\n-\totx2_sec_idev_tx_cpt_qp_put;\n-\totx2_sec_idev_tx_cpt_qp_remove;\n-\totx2_sso_pf_func_get;\n-\totx2_sso_pf_func_set;\n-\totx2_unregister_irq;\n-\n-\tlocal: *;\n-};\ndiff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build\nindex 59f02ea47c..147b8cf633 100644\n--- a/drivers/crypto/meson.build\n+++ b/drivers/crypto/meson.build\n@@ -16,7 +16,6 @@ drivers = [\n 'nitrox',\n 'null',\n 'octeontx',\n- 'octeontx2',\n 'openssl',\n 'scheduler',\n 'virtio',\ndiff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build\ndeleted file mode 100644\nindex 3b387cc570..0000000000\n--- a/drivers/crypto/octeontx2/meson.build\n+++ /dev/null\n@@ -1,30 +0,0 @@\n-# SPDX-License-Identifier: BSD-3-Clause\n-# Copyright (C) 2019 Marvell International Ltd.\n-\n-if not is_linux or not dpdk_conf.get('RTE_ARCH_64')\n- build = false\n- reason = 'only supported on 64-bit Linux'\n- subdir_done()\n-endif\n-\n-deps += ['bus_pci']\n-deps += ['common_cpt']\n-deps += ['common_octeontx2']\n-deps += ['ethdev']\n-deps += ['eventdev']\n-deps += ['security']\n-\n-sources = files(\n- 'otx2_cryptodev.c',\n- 'otx2_cryptodev_capabilities.c',\n- 'otx2_cryptodev_hw_access.c',\n- 'otx2_cryptodev_mbox.c',\n- 'otx2_cryptodev_ops.c',\n- 'otx2_cryptodev_sec.c',\n-)\n-\n-includes += include_directories('../../common/cpt')\n-includes += include_directories('../../common/octeontx2')\n-includes += include_directories('../../crypto/octeontx2')\n-includes += include_directories('../../mempool/octeontx2')\n-includes += include_directories('../../net/octeontx2')\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c\ndeleted file mode 100644\nindex fc7ad05366..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev.c\n+++ /dev/null\n@@ -1,188 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_bus_pci.h>\n-#include <rte_common.h>\n-#include <rte_crypto.h>\n-#include <rte_cryptodev.h>\n-#include <cryptodev_pmd.h>\n-#include <rte_dev.h>\n-#include <rte_errno.h>\n-#include <rte_mempool.h>\n-#include <rte_pci.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_cryptodev.h\"\n-#include \"otx2_cryptodev_capabilities.h\"\n-#include \"otx2_cryptodev_mbox.h\"\n-#include \"otx2_cryptodev_ops.h\"\n-#include \"otx2_cryptodev_sec.h\"\n-#include \"otx2_dev.h\"\n-\n-/* CPT common headers */\n-#include \"cpt_common.h\"\n-#include \"cpt_pmd_logs.h\"\n-\n-uint8_t otx2_cryptodev_driver_id;\n-\n-static struct rte_pci_id pci_id_cpt_table[] = {\n-\t{\n-\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n-\t\t\t PCI_DEVID_OCTEONTX2_RVU_CPT_VF)\n-\t},\n-\t/* sentinel */\n-\t{\n-\t\t.device_id = 0\n-\t},\n-};\n-\n-uint64_t\n-otx2_cpt_default_ff_get(void)\n-{\n-\treturn RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n-\t RTE_CRYPTODEV_FF_HW_ACCELERATED |\n-\t RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n-\t RTE_CRYPTODEV_FF_IN_PLACE_SGL |\n-\t RTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT |\n-\t RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\n-\t RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT |\n-\t RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |\n-\t RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT |\n-\t RTE_CRYPTODEV_FF_SYM_SESSIONLESS |\n-\t RTE_CRYPTODEV_FF_SECURITY |\n-\t RTE_CRYPTODEV_FF_DIGEST_ENCRYPTED;\n-}\n-\n-static int\n-otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n-\t\t struct rte_pci_device *pci_dev)\n-{\n-\tstruct rte_cryptodev_pmd_init_params init_params = {\n-\t\t.name = \"\",\n-\t\t.socket_id = rte_socket_id(),\n-\t\t.private_data_size = sizeof(struct otx2_cpt_vf)\n-\t};\n-\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n-\tstruct rte_cryptodev *dev;\n-\tstruct otx2_dev *otx2_dev;\n-\tstruct otx2_cpt_vf *vf;\n-\tuint16_t nb_queues;\n-\tint ret;\n-\n-\trte_pci_device_name(&pci_dev->addr, name, sizeof(name));\n-\n-\tdev = rte_cryptodev_pmd_create(name, &pci_dev->device, &init_params);\n-\tif (dev == NULL) {\n-\t\tret = -ENODEV;\n-\t\tgoto exit;\n-\t}\n-\n-\tdev->dev_ops = &otx2_cpt_ops;\n-\n-\tdev->driver_id = otx2_cryptodev_driver_id;\n-\n-\t/* Get private data space allocated */\n-\tvf = dev->data->dev_private;\n-\n-\totx2_dev = &vf->otx2_dev;\n-\n-\tif (rte_eal_process_type() == RTE_PROC_PRIMARY) {\n-\t\t/* Initialize the base otx2_dev object */\n-\t\tret = otx2_dev_init(pci_dev, otx2_dev);\n-\t\tif (ret) {\n-\t\t\tCPT_LOG_ERR(\"Could not initialize otx2_dev\");\n-\t\t\tgoto pmd_destroy;\n-\t\t}\n-\n-\t\t/* Get number of queues available on the device */\n-\t\tret = otx2_cpt_available_queues_get(dev, &nb_queues);\n-\t\tif (ret) {\n-\t\t\tCPT_LOG_ERR(\"Could not determine the number of queues available\");\n-\t\t\tgoto otx2_dev_fini;\n-\t\t}\n-\n-\t\t/* Don't exceed the limits set per VF */\n-\t\tnb_queues = RTE_MIN(nb_queues, OTX2_CPT_MAX_QUEUES_PER_VF);\n-\n-\t\tif (nb_queues == 0) {\n-\t\t\tCPT_LOG_ERR(\"No free queues available on the device\");\n-\t\t\tgoto otx2_dev_fini;\n-\t\t}\n-\n-\t\tvf->max_queues = nb_queues;\n-\n-\t\tCPT_LOG_INFO(\"Max queues supported by device: %d\",\n-\t\t\t\tvf->max_queues);\n-\n-\t\tret = otx2_cpt_hardware_caps_get(dev, vf->hw_caps);\n-\t\tif (ret) {\n-\t\t\tCPT_LOG_ERR(\"Could not determine hardware capabilities\");\n-\t\t\tgoto otx2_dev_fini;\n-\t\t}\n-\t}\n-\n-\totx2_crypto_capabilities_init(vf->hw_caps);\n-\totx2_crypto_sec_capabilities_init(vf->hw_caps);\n-\n-\t/* Create security ctx */\n-\tret = otx2_crypto_sec_ctx_create(dev);\n-\tif (ret)\n-\t\tgoto otx2_dev_fini;\n-\n-\tdev->feature_flags = otx2_cpt_default_ff_get();\n-\n-\tif (rte_eal_process_type() == RTE_PROC_SECONDARY)\n-\t\totx2_cpt_set_enqdeq_fns(dev);\n-\n-\trte_cryptodev_pmd_probing_finish(dev);\n-\n-\treturn 0;\n-\n-otx2_dev_fini:\n-\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n-\t\totx2_dev_fini(pci_dev, otx2_dev);\n-pmd_destroy:\n-\trte_cryptodev_pmd_destroy(dev);\n-exit:\n-\tCPT_LOG_ERR(\"Could not create device (vendor_id: 0x%x device_id: 0x%x)\",\n-\t\t pci_dev->id.vendor_id, pci_dev->id.device_id);\n-\treturn ret;\n-}\n-\n-static int\n-otx2_cpt_pci_remove(struct rte_pci_device *pci_dev)\n-{\n-\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n-\tstruct rte_cryptodev *dev;\n-\n-\tif (pci_dev == NULL)\n-\t\treturn -EINVAL;\n-\n-\trte_pci_device_name(&pci_dev->addr, name, sizeof(name));\n-\n-\tdev = rte_cryptodev_pmd_get_named_dev(name);\n-\tif (dev == NULL)\n-\t\treturn -ENODEV;\n-\n-\t/* Destroy security ctx */\n-\totx2_crypto_sec_ctx_destroy(dev);\n-\n-\treturn rte_cryptodev_pmd_destroy(dev);\n-}\n-\n-static struct rte_pci_driver otx2_cryptodev_pmd = {\n-\t.id_table = pci_id_cpt_table,\n-\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n-\t.probe = otx2_cpt_pci_probe,\n-\t.remove = otx2_cpt_pci_remove,\n-};\n-\n-static struct cryptodev_driver otx2_cryptodev_drv;\n-\n-RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX2_PMD, otx2_cryptodev_pmd);\n-RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX2_PMD, pci_id_cpt_table);\n-RTE_PMD_REGISTER_KMOD_DEP(CRYPTODEV_NAME_OCTEONTX2_PMD, \"vfio-pci\");\n-RTE_PMD_REGISTER_CRYPTO_DRIVER(otx2_cryptodev_drv, otx2_cryptodev_pmd.driver,\n-\t\totx2_cryptodev_driver_id);\n-RTE_LOG_REGISTER_DEFAULT(otx2_cpt_logtype, NOTICE);\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h\ndeleted file mode 100644\nindex 15ecfe45b6..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev.h\n+++ /dev/null\n@@ -1,63 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_CRYPTODEV_H_\n-#define _OTX2_CRYPTODEV_H_\n-\n-#include \"cpt_common.h\"\n-#include \"cpt_hw_types.h\"\n-\n-#include \"otx2_dev.h\"\n-\n-/* Marvell OCTEON TX2 Crypto PMD device name */\n-#define CRYPTODEV_NAME_OCTEONTX2_PMD\tcrypto_octeontx2\n-\n-#define OTX2_CPT_MAX_LFS\t\t128\n-#define OTX2_CPT_MAX_QUEUES_PER_VF\t64\n-#define OTX2_CPT_MAX_BLKS\t\t2\n-#define OTX2_CPT_PMD_VERSION\t\t3\n-#define OTX2_CPT_REVISION_ID_3\t\t3\n-\n-/**\n- * Device private data\n- */\n-struct otx2_cpt_vf {\n-\tstruct otx2_dev otx2_dev;\n-\t/**< Base class */\n-\tuint16_t max_queues;\n-\t/**< Max queues supported */\n-\tuint8_t nb_queues;\n-\t/**< Number of crypto queues attached */\n-\tuint16_t lf_msixoff[OTX2_CPT_MAX_LFS];\n-\t/**< MSI-X offsets */\n-\tuint8_t lf_blkaddr[OTX2_CPT_MAX_LFS];\n-\t/**< CPT0/1 BLKADDR of LFs */\n-\tuint8_t cpt_revision;\n-\t/**< CPT revision */\n-\tuint8_t err_intr_registered:1;\n-\t/**< Are error interrupts registered? */\n-\tunion cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];\n-\t/**< CPT device capabilities */\n-};\n-\n-struct cpt_meta_info {\n-\tuint64_t deq_op_info[5];\n-\tuint64_t comp_code_sz;\n-\tunion cpt_res_s cpt_res __rte_aligned(16);\n-\tstruct cpt_request_info cpt_req;\n-};\n-\n-#define CPT_LOGTYPE otx2_cpt_logtype\n-\n-extern int otx2_cpt_logtype;\n-\n-/*\n- * Crypto device driver ID\n- */\n-extern uint8_t otx2_cryptodev_driver_id;\n-\n-uint64_t otx2_cpt_default_ff_get(void);\n-void otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);\n-\n-#endif /* _OTX2_CRYPTODEV_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c\ndeleted file mode 100644\nindex ba3fbbbe22..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.c\n+++ /dev/null\n@@ -1,924 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_cryptodev.h>\n-#include <rte_security.h>\n-\n-#include \"otx2_cryptodev.h\"\n-#include \"otx2_cryptodev_capabilities.h\"\n-#include \"otx2_mbox.h\"\n-\n-#define CPT_EGRP_GET(hw_caps, name, egrp) do {\t\\\n-\tif ((hw_caps[CPT_ENG_TYPE_SE].name) &&\t\\\n-\t (hw_caps[CPT_ENG_TYPE_IE].name))\t\\\n-\t\t*egrp = OTX2_CPT_EGRP_SE_IE;\t\\\n-\telse if (hw_caps[CPT_ENG_TYPE_SE].name)\t\\\n-\t\t*egrp = OTX2_CPT_EGRP_SE;\t\\\n-\telse if (hw_caps[CPT_ENG_TYPE_AE].name)\t\\\n-\t\t*egrp = OTX2_CPT_EGRP_AE;\t\\\n-\telse\t\t\t\t\t\\\n-\t\t*egrp = OTX2_CPT_EGRP_MAX;\t\\\n-} while (0)\n-\n-#define CPT_CAPS_ADD(hw_caps, name) do {\t\t\t\t\\\n-\tenum otx2_cpt_egrp egrp;\t\t\t\t\t\\\n-\tCPT_EGRP_GET(hw_caps, name, &egrp);\t\t\t\t\\\n-\tif (egrp < OTX2_CPT_EGRP_MAX)\t\t\t\t\t\\\n-\t\tcpt_caps_add(caps_##name, RTE_DIM(caps_##name));\t\\\n-} while (0)\n-\n-#define SEC_CAPS_ADD(hw_caps, name) do {\t\t\t\t\\\n-\tenum otx2_cpt_egrp egrp;\t\t\t\t\t\\\n-\tCPT_EGRP_GET(hw_caps, name, &egrp);\t\t\t\t\\\n-\tif (egrp < OTX2_CPT_EGRP_MAX)\t\t\t\t\t\\\n-\t\tsec_caps_add(sec_caps_##name, RTE_DIM(sec_caps_##name));\\\n-} while (0)\n-\n-#define OTX2_CPT_MAX_CAPS 34\n-#define OTX2_SEC_MAX_CAPS 4\n-\n-static struct rte_cryptodev_capabilities otx2_cpt_caps[OTX2_CPT_MAX_CAPS];\n-static struct rte_cryptodev_capabilities otx2_cpt_sec_caps[OTX2_SEC_MAX_CAPS];\n-\n-static const struct rte_cryptodev_capabilities caps_mul[] = {\n-\t{\t/* RSA */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n-\t\t{.asym = {\n-\t\t\t.xform_capa = {\n-\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_RSA,\n-\t\t\t\t.op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |\n-\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_OP_VERIFY) |\n-\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |\n-\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),\n-\t\t\t\t{.modlen = {\n-\t\t\t\t\t.min = 17,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t}, }\n-\t\t\t}\n-\t\t}, }\n-\t},\n-\t{\t/* MOD_EXP */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n-\t\t{.asym = {\n-\t\t\t.xform_capa = {\n-\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_MODEX,\n-\t\t\t\t.op_types = 0,\n-\t\t\t\t{.modlen = {\n-\t\t\t\t\t.min = 17,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t}, }\n-\t\t\t}\n-\t\t}, }\n-\t},\n-\t{\t/* ECDSA */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n-\t\t{.asym = {\n-\t\t\t.xform_capa = {\n-\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_ECDSA,\n-\t\t\t\t.op_types = ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |\n-\t\t\t\t\t(1 << RTE_CRYPTO_ASYM_OP_VERIFY)),\n-\t\t\t\t}\n-\t\t\t},\n-\t\t}\n-\t},\n-\t{\t/* ECPM */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\n-\t\t{.asym = {\n-\t\t\t.xform_capa = {\n-\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_ECPM,\n-\t\t\t\t.op_types = 0\n-\t\t\t\t}\n-\t\t\t},\n-\t\t}\n-\t},\n-};\n-\n-static const struct rte_cryptodev_capabilities caps_sha1_sha2[] = {\n-\t{\t/* SHA1 */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA1,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 20,\n-\t\t\t\t\t.max = 20,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* SHA1 HMAC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 1,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 12,\n-\t\t\t\t\t.max = 20,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* SHA224 */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA224,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 28,\n-\t\t\t\t\t.max = 28,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* SHA224 HMAC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA224_HMAC,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 1,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 28,\n-\t\t\t\t\t.max = 28,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* SHA256 */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA256,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 32,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* SHA256 HMAC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 1,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 16\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* SHA384 */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA384,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 48,\n-\t\t\t\t\t.max = 48,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* SHA384 HMAC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA384_HMAC,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 1,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 24,\n-\t\t\t\t\t.max = 48,\n-\t\t\t\t\t.increment = 24\n-\t\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* SHA512 */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA512,\n-\t\t\t\t.block_size = 128,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 64,\n-\t\t\t\t\t.max = 64,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* SHA512 HMAC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA512_HMAC,\n-\t\t\t\t.block_size = 128,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 1,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 32,\n-\t\t\t\t\t.max = 64,\n-\t\t\t\t\t.increment = 32\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* MD5 */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_MD5,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* MD5 HMAC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_MD5_HMAC,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 8,\n-\t\t\t\t\t.max = 64,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 12,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 4\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-};\n-\n-static const struct rte_cryptodev_capabilities caps_chacha20[] = {\n-\t{\t/* Chacha20-Poly1305 */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\n-\t\t\t{.aead = {\n-\t\t\t\t.algo = RTE_CRYPTO_AEAD_CHACHA20_POLY1305,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 32,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.aad_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 12,\n-\t\t\t\t\t.max = 12,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t}\n-};\n-\n-static const struct rte_cryptodev_capabilities caps_zuc_snow3g[] = {\n-\t{\t/* SNOW 3G (UEA2) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* ZUC (EEA3) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_ZUC_EEA3,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* SNOW 3G (UIA2) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 4,\n-\t\t\t\t\t.max = 4,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* ZUC (EIA3) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_ZUC_EIA3,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 4,\n-\t\t\t\t\t.max = 4,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-};\n-\n-static const struct rte_cryptodev_capabilities caps_aes[] = {\n-\t{\t/* AES GMAC (AUTH) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_AES_GMAC,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 8,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 4\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 12,\n-\t\t\t\t\t.max = 12,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* AES CBC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_CBC,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* AES CTR */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_CTR,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 12,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 4\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* AES XTS */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_XTS,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 32,\n-\t\t\t\t\t.max = 64,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* AES GCM */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\n-\t\t\t{.aead = {\n-\t\t\t\t.algo = RTE_CRYPTO_AEAD_AES_GCM,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 4,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t},\n-\t\t\t\t.aad_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 12,\n-\t\t\t\t\t.max = 12,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-};\n-\n-static const struct rte_cryptodev_capabilities caps_kasumi[] = {\n-\t{\t/* KASUMI (F8) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_KASUMI_F8,\n-\t\t\t\t.block_size = 8,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 8,\n-\t\t\t\t\t.max = 8,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* KASUMI (F9) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_KASUMI_F9,\n-\t\t\t\t.block_size = 8,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 4,\n-\t\t\t\t\t.max = 4,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-};\n-\n-static const struct rte_cryptodev_capabilities caps_des[] = {\n-\t{\t/* 3DES CBC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_3DES_CBC,\n-\t\t\t\t.block_size = 8,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 24,\n-\t\t\t\t\t.max = 24,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 8,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* 3DES ECB */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_3DES_ECB,\n-\t\t\t\t.block_size = 8,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 24,\n-\t\t\t\t\t.max = 24,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* DES CBC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_DES_CBC,\n-\t\t\t\t.block_size = 8,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 8,\n-\t\t\t\t\t.max = 8,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 8,\n-\t\t\t\t\t.max = 8,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-};\n-\n-static const struct rte_cryptodev_capabilities caps_null[] = {\n-\t{\t/* NULL (AUTH) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_NULL,\n-\t\t\t\t.block_size = 1,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, },\n-\t\t}, },\n-\t},\n-\t{\t/* NULL (CIPHER) */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_NULL,\n-\t\t\t\t.block_size = 1,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 0,\n-\t\t\t\t\t.max = 0,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, },\n-\t\t}, }\n-\t},\n-};\n-\n-static const struct rte_cryptodev_capabilities caps_end[] = {\n-\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n-};\n-\n-static const struct rte_cryptodev_capabilities sec_caps_aes[] = {\n-\t{\t/* AES GCM */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\n-\t\t\t{.aead = {\n-\t\t\t\t.algo = RTE_CRYPTO_AEAD_AES_GCM,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.aad_size = {\n-\t\t\t\t\t.min = 8,\n-\t\t\t\t\t.max = 12,\n-\t\t\t\t\t.increment = 4\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 12,\n-\t\t\t\t\t.max = 12,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* AES CBC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_CBC,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-};\n-\n-static const struct rte_cryptodev_capabilities sec_caps_sha1_sha2[] = {\n-\t{\t/* SHA1 HMAC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 1,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 12,\n-\t\t\t\t\t.max = 20,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* SHA256 HMAC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA256_HMAC,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 1,\n-\t\t\t\t\t.max = 1024,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 16\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-};\n-\n-static const struct rte_security_capability\n-otx2_crypto_sec_capabilities[] = {\n-\t{\t/* IPsec Lookaside Protocol ESP Tunnel Ingress */\n-\t\t.action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL,\n-\t\t.protocol = RTE_SECURITY_PROTOCOL_IPSEC,\n-\t\t.ipsec = {\n-\t\t\t.proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,\n-\t\t\t.mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,\n-\t\t\t.direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS,\n-\t\t\t.options = { 0 }\n-\t\t},\n-\t\t.crypto_capabilities = otx2_cpt_sec_caps,\n-\t\t.ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA\n-\t},\n-\t{\t/* IPsec Lookaside Protocol ESP Tunnel Egress */\n-\t\t.action = RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL,\n-\t\t.protocol = RTE_SECURITY_PROTOCOL_IPSEC,\n-\t\t.ipsec = {\n-\t\t\t.proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,\n-\t\t\t.mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,\n-\t\t\t.direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS,\n-\t\t\t.options = { 0 }\n-\t\t},\n-\t\t.crypto_capabilities = otx2_cpt_sec_caps,\n-\t\t.ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA\n-\t},\n-\t{\n-\t\t.action = RTE_SECURITY_ACTION_TYPE_NONE\n-\t}\n-};\n-\n-static void\n-cpt_caps_add(const struct rte_cryptodev_capabilities *caps, int nb_caps)\n-{\n-\tstatic int cur_pos;\n-\n-\tif (cur_pos + nb_caps > OTX2_CPT_MAX_CAPS)\n-\t\treturn;\n-\n-\tmemcpy(&otx2_cpt_caps[cur_pos], caps, nb_caps * sizeof(caps[0]));\n-\tcur_pos += nb_caps;\n-}\n-\n-void\n-otx2_crypto_capabilities_init(union cpt_eng_caps *hw_caps)\n-{\n-\tCPT_CAPS_ADD(hw_caps, mul);\n-\tCPT_CAPS_ADD(hw_caps, sha1_sha2);\n-\tCPT_CAPS_ADD(hw_caps, chacha20);\n-\tCPT_CAPS_ADD(hw_caps, zuc_snow3g);\n-\tCPT_CAPS_ADD(hw_caps, aes);\n-\tCPT_CAPS_ADD(hw_caps, kasumi);\n-\tCPT_CAPS_ADD(hw_caps, des);\n-\n-\tcpt_caps_add(caps_null, RTE_DIM(caps_null));\n-\tcpt_caps_add(caps_end, RTE_DIM(caps_end));\n-}\n-\n-const struct rte_cryptodev_capabilities *\n-otx2_cpt_capabilities_get(void)\n-{\n-\treturn otx2_cpt_caps;\n-}\n-\n-static void\n-sec_caps_add(const struct rte_cryptodev_capabilities *caps, int nb_caps)\n-{\n-\tstatic int cur_pos;\n-\n-\tif (cur_pos + nb_caps > OTX2_SEC_MAX_CAPS)\n-\t\treturn;\n-\n-\tmemcpy(&otx2_cpt_sec_caps[cur_pos], caps, nb_caps * sizeof(caps[0]));\n-\tcur_pos += nb_caps;\n-}\n-\n-void\n-otx2_crypto_sec_capabilities_init(union cpt_eng_caps *hw_caps)\n-{\n-\tSEC_CAPS_ADD(hw_caps, aes);\n-\tSEC_CAPS_ADD(hw_caps, sha1_sha2);\n-\n-\tsec_caps_add(caps_end, RTE_DIM(caps_end));\n-}\n-\n-const struct rte_security_capability *\n-otx2_crypto_sec_capabilities_get(void *device __rte_unused)\n-{\n-\treturn otx2_crypto_sec_capabilities;\n-}\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h b/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h\ndeleted file mode 100644\nindex c1e0001190..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_capabilities.h\n+++ /dev/null\n@@ -1,45 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_CRYPTODEV_CAPABILITIES_H_\n-#define _OTX2_CRYPTODEV_CAPABILITIES_H_\n-\n-#include <rte_cryptodev.h>\n-\n-#include \"otx2_mbox.h\"\n-\n-enum otx2_cpt_egrp {\n-\tOTX2_CPT_EGRP_SE = 0,\n-\tOTX2_CPT_EGRP_SE_IE = 1,\n-\tOTX2_CPT_EGRP_AE = 2,\n-\tOTX2_CPT_EGRP_MAX,\n-};\n-\n-/*\n- * Initialize crypto capabilities for the device\n- *\n- */\n-void otx2_crypto_capabilities_init(union cpt_eng_caps *hw_caps);\n-\n-/*\n- * Get capabilities list for the device\n- *\n- */\n-const struct rte_cryptodev_capabilities *\n-otx2_cpt_capabilities_get(void);\n-\n-/*\n- * Initialize security capabilities for the device\n- *\n- */\n-void otx2_crypto_sec_capabilities_init(union cpt_eng_caps *hw_caps);\n-\n-/*\n- * Get security capabilities list for the device\n- *\n- */\n-const struct rte_security_capability *\n-otx2_crypto_sec_capabilities_get(void *device __rte_unused);\n-\n-#endif /* _OTX2_CRYPTODEV_CAPABILITIES_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c\ndeleted file mode 100644\nindex d5d6b5bad7..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c\n+++ /dev/null\n@@ -1,225 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2019 Marvell International Ltd.\n- */\n-#include <rte_cryptodev.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_cryptodev.h\"\n-#include \"otx2_cryptodev_hw_access.h\"\n-#include \"otx2_cryptodev_mbox.h\"\n-#include \"otx2_cryptodev_ops.h\"\n-#include \"otx2_dev.h\"\n-\n-#include \"cpt_pmd_logs.h\"\n-\n-static void\n-otx2_cpt_lf_err_intr_handler(void *param)\n-{\n-\tuintptr_t base = (uintptr_t)param;\n-\tuint8_t lf_id;\n-\tuint64_t intr;\n-\n-\tlf_id = (base >> 12) & 0xFF;\n-\n-\tintr = otx2_read64(base + OTX2_CPT_LF_MISC_INT);\n-\tif (intr == 0)\n-\t\treturn;\n-\n-\tCPT_LOG_ERR(\"LF %d MISC_INT: 0x%\" PRIx64 \"\", lf_id, intr);\n-\n-\t/* Clear interrupt */\n-\totx2_write64(intr, base + OTX2_CPT_LF_MISC_INT);\n-}\n-\n-static void\n-otx2_cpt_lf_err_intr_unregister(const struct rte_cryptodev *dev,\n-\t\t\t\tuint16_t msix_off, uintptr_t base)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\n-\t/* Disable error interrupts */\n-\totx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C);\n-\n-\totx2_unregister_irq(handle, otx2_cpt_lf_err_intr_handler, (void *)base,\n-\t\t\t msix_off);\n-}\n-\n-void\n-otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tuintptr_t base;\n-\tuint32_t i;\n-\n-\tfor (i = 0; i < vf->nb_queues; i++) {\n-\t\tbase = OTX2_CPT_LF_BAR2(vf, vf->lf_blkaddr[i], i);\n-\t\totx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[i], base);\n-\t}\n-\n-\tvf->err_intr_registered = 0;\n-}\n-\n-static int\n-otx2_cpt_lf_err_intr_register(const struct rte_cryptodev *dev,\n-\t\t\t uint16_t msix_off, uintptr_t base)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tint ret;\n-\n-\t/* Disable error interrupts */\n-\totx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1C);\n-\n-\t/* Register error interrupt handler */\n-\tret = otx2_register_irq(handle, otx2_cpt_lf_err_intr_handler,\n-\t\t\t\t(void *)base, msix_off);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t/* Enable error interrupts */\n-\totx2_write64(~0ull, base + OTX2_CPT_LF_MISC_INT_ENA_W1S);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_cpt_err_intr_register(const struct rte_cryptodev *dev)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tuint32_t i, j, ret;\n-\tuintptr_t base;\n-\n-\tfor (i = 0; i < vf->nb_queues; i++) {\n-\t\tif (vf->lf_msixoff[i] == MSIX_VECTOR_INVALID) {\n-\t\t\tCPT_LOG_ERR(\"Invalid CPT LF MSI-X offset: 0x%x\",\n-\t\t\t\t vf->lf_msixoff[i]);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\tfor (i = 0; i < vf->nb_queues; i++) {\n-\t\tbase = OTX2_CPT_LF_BAR2(vf, vf->lf_blkaddr[i], i);\n-\t\tret = otx2_cpt_lf_err_intr_register(dev, vf->lf_msixoff[i],\n-\t\t\t\t\t\t base);\n-\t\tif (ret)\n-\t\t\tgoto intr_unregister;\n-\t}\n-\n-\tvf->err_intr_registered = 1;\n-\treturn 0;\n-\n-intr_unregister:\n-\t/* Unregister the ones already registered */\n-\tfor (j = 0; j < i; j++) {\n-\t\tbase = OTX2_CPT_LF_BAR2(vf, vf->lf_blkaddr[j], j);\n-\t\totx2_cpt_lf_err_intr_unregister(dev, vf->lf_msixoff[j], base);\n-\t}\n-\n-\t/*\n-\t * Failed to register error interrupt. Not returning error as this would\n-\t * prevent application from enabling larger number of devs.\n-\t *\n-\t * This failure is a known issue because otx2_dev_init() initializes\n-\t * interrupts based on static values from ATF, and the actual number\n-\t * of interrupts needed (which is based on LFs) can be determined only\n-\t * after otx2_dev_init() sets up interrupts which includes mbox\n-\t * interrupts.\n-\t */\n-\treturn 0;\n-}\n-\n-int\n-otx2_cpt_iq_enable(const struct rte_cryptodev *dev,\n-\t\t const struct otx2_cpt_qp *qp, uint8_t grp_mask, uint8_t pri,\n-\t\t uint32_t size_div40)\n-{\n-\tunion otx2_cpt_af_lf_ctl af_lf_ctl;\n-\tunion otx2_cpt_lf_inprog inprog;\n-\tunion otx2_cpt_lf_q_base base;\n-\tunion otx2_cpt_lf_q_size size;\n-\tunion otx2_cpt_lf_ctl lf_ctl;\n-\tint ret;\n-\n-\t/* Set engine group mask and priority */\n-\n-\tret = otx2_cpt_af_reg_read(dev, OTX2_CPT_AF_LF_CTL(qp->id),\n-\t\t\t\t qp->blkaddr, &af_lf_ctl.u);\n-\tif (ret)\n-\t\treturn ret;\n-\taf_lf_ctl.s.grp = grp_mask;\n-\taf_lf_ctl.s.pri = pri ? 1 : 0;\n-\tret = otx2_cpt_af_reg_write(dev, OTX2_CPT_AF_LF_CTL(qp->id),\n-\t\t\t\t qp->blkaddr, af_lf_ctl.u);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t/* Set instruction queue base address */\n-\n-\tbase.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_BASE);\n-\tbase.s.fault = 0;\n-\tbase.s.stopped = 0;\n-\tbase.s.addr = qp->iq_dma_addr >> 7;\n-\totx2_write64(base.u, qp->base + OTX2_CPT_LF_Q_BASE);\n-\n-\t/* Set instruction queue size */\n-\n-\tsize.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_SIZE);\n-\tsize.s.size_div40 = size_div40;\n-\totx2_write64(size.u, qp->base + OTX2_CPT_LF_Q_SIZE);\n-\n-\t/* Enable instruction queue */\n-\n-\tlf_ctl.u = otx2_read64(qp->base + OTX2_CPT_LF_CTL);\n-\tlf_ctl.s.ena = 1;\n-\totx2_write64(lf_ctl.u, qp->base + OTX2_CPT_LF_CTL);\n-\n-\t/* Start instruction execution */\n-\n-\tinprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);\n-\tinprog.s.eena = 1;\n-\totx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG);\n-\n-\treturn 0;\n-}\n-\n-void\n-otx2_cpt_iq_disable(struct otx2_cpt_qp *qp)\n-{\n-\tunion otx2_cpt_lf_q_grp_ptr grp_ptr;\n-\tunion otx2_cpt_lf_inprog inprog;\n-\tunion otx2_cpt_lf_ctl ctl;\n-\tint cnt;\n-\n-\t/* Stop instruction execution */\n-\tinprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);\n-\tinprog.s.eena = 0x0;\n-\totx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG);\n-\n-\t/* Disable instructions enqueuing */\n-\tctl.u = otx2_read64(qp->base + OTX2_CPT_LF_CTL);\n-\tctl.s.ena = 0;\n-\totx2_write64(ctl.u, qp->base + OTX2_CPT_LF_CTL);\n-\n-\t/* Wait for instruction queue to become empty */\n-\tcnt = 0;\n-\tdo {\n-\t\tinprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);\n-\t\tif (inprog.s.grb_partial)\n-\t\t\tcnt = 0;\n-\t\telse\n-\t\t\tcnt++;\n-\t\tgrp_ptr.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_GRP_PTR);\n-\t} while ((cnt < 10) && (grp_ptr.s.nq_ptr != grp_ptr.s.dq_ptr));\n-\n-\tcnt = 0;\n-\tdo {\n-\t\tinprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);\n-\t\tif ((inprog.s.inflight == 0) &&\n-\t\t (inprog.s.gwb_cnt < 40) &&\n-\t\t ((inprog.s.grb_cnt == 0) || (inprog.s.grb_cnt == 40)))\n-\t\t\tcnt++;\n-\t\telse\n-\t\t\tcnt = 0;\n-\t} while (cnt < 10);\n-}\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\ndeleted file mode 100644\nindex 90a338e05a..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n+++ /dev/null\n@@ -1,161 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_CRYPTODEV_HW_ACCESS_H_\n-#define _OTX2_CRYPTODEV_HW_ACCESS_H_\n-\n-#include <stdint.h>\n-\n-#include <rte_cryptodev.h>\n-#include <rte_memory.h>\n-\n-#include \"cpt_common.h\"\n-#include \"cpt_hw_types.h\"\n-#include \"cpt_mcode_defines.h\"\n-\n-#include \"otx2_dev.h\"\n-#include \"otx2_cryptodev_qp.h\"\n-\n-/* CPT instruction queue length.\n- * Use queue size as power of 2 for aiding in pending queue calculations.\n- */\n-#define OTX2_CPT_DEFAULT_CMD_QLEN\t8192\n-\n-/* Mask which selects all engine groups */\n-#define OTX2_CPT_ENG_GRPS_MASK\t\t0xFF\n-\n-/* Register offsets */\n-\n-/* LMT LF registers */\n-#define OTX2_LMT_LF_LMTLINE(a)\t\t(0x0ull | (uint64_t)(a) << 3)\n-\n-/* CPT LF registers */\n-#define OTX2_CPT_LF_CTL\t\t\t0x10ull\n-#define OTX2_CPT_LF_INPROG\t\t0x40ull\n-#define OTX2_CPT_LF_MISC_INT\t\t0xb0ull\n-#define OTX2_CPT_LF_MISC_INT_ENA_W1S\t0xd0ull\n-#define OTX2_CPT_LF_MISC_INT_ENA_W1C\t0xe0ull\n-#define OTX2_CPT_LF_Q_BASE\t\t0xf0ull\n-#define OTX2_CPT_LF_Q_SIZE\t\t0x100ull\n-#define OTX2_CPT_LF_Q_GRP_PTR\t\t0x120ull\n-#define OTX2_CPT_LF_NQ(a)\t\t(0x400ull | (uint64_t)(a) << 3)\n-\n-#define OTX2_CPT_AF_LF_CTL(a)\t\t(0x27000ull | (uint64_t)(a) << 3)\n-#define OTX2_CPT_AF_LF_CTL2(a)\t\t(0x29000ull | (uint64_t)(a) << 3)\n-\n-#define OTX2_CPT_LF_BAR2(vf, blk_addr, q_id) \\\n-\t\t((vf)->otx2_dev.bar2 + \\\n-\t\t ((blk_addr << 20) | ((q_id) << 12)))\n-\n-#define OTX2_CPT_QUEUE_HI_PRIO 0x1\n-\n-union otx2_cpt_lf_ctl {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t ena : 1;\n-\t\tuint64_t fc_ena : 1;\n-\t\tuint64_t fc_up_crossing : 1;\n-\t\tuint64_t reserved_3_3 : 1;\n-\t\tuint64_t fc_hyst_bits : 4;\n-\t\tuint64_t reserved_8_63 : 56;\n-\t} s;\n-};\n-\n-union otx2_cpt_lf_inprog {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t inflight : 9;\n-\t\tuint64_t reserved_9_15 : 7;\n-\t\tuint64_t eena : 1;\n-\t\tuint64_t grp_drp : 1;\n-\t\tuint64_t reserved_18_30 : 13;\n-\t\tuint64_t grb_partial : 1;\n-\t\tuint64_t grb_cnt : 8;\n-\t\tuint64_t gwb_cnt : 8;\n-\t\tuint64_t reserved_48_63 : 16;\n-\t} s;\n-};\n-\n-union otx2_cpt_lf_q_base {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t fault : 1;\n-\t\tuint64_t stopped : 1;\n-\t\tuint64_t reserved_2_6 : 5;\n-\t\tuint64_t addr : 46;\n-\t\tuint64_t reserved_53_63 : 11;\n-\t} s;\n-};\n-\n-union otx2_cpt_lf_q_size {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t size_div40 : 15;\n-\t\tuint64_t reserved_15_63 : 49;\n-\t} s;\n-};\n-\n-union otx2_cpt_af_lf_ctl {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t pri : 1;\n-\t\tuint64_t reserved_1_8 : 8;\n-\t\tuint64_t pf_func_inst : 1;\n-\t\tuint64_t cont_err : 1;\n-\t\tuint64_t reserved_11_15 : 5;\n-\t\tuint64_t nixtx_en : 1;\n-\t\tuint64_t reserved_17_47 : 31;\n-\t\tuint64_t grp : 8;\n-\t\tuint64_t reserved_56_63 : 8;\n-\t} s;\n-};\n-\n-union otx2_cpt_af_lf_ctl2 {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t exe_no_swap : 1;\n-\t\tuint64_t exe_ldwb : 1;\n-\t\tuint64_t reserved_2_31 : 30;\n-\t\tuint64_t sso_pf_func : 16;\n-\t\tuint64_t nix_pf_func : 16;\n-\t} s;\n-};\n-\n-union otx2_cpt_lf_q_grp_ptr {\n-\tuint64_t u;\n-\tstruct {\n-\t\tuint64_t dq_ptr : 15;\n-\t\tuint64_t reserved_31_15 : 17;\n-\t\tuint64_t nq_ptr : 15;\n-\t\tuint64_t reserved_47_62 : 16;\n-\t\tuint64_t xq_xor : 1;\n-\t} s;\n-};\n-\n-/*\n- * Enumeration cpt_9x_comp_e\n- *\n- * CPT 9X Completion Enumeration\n- * Enumerates the values of CPT_RES_S[COMPCODE].\n- */\n-enum cpt_9x_comp_e {\n-\tCPT_9X_COMP_E_NOTDONE = 0x00,\n-\tCPT_9X_COMP_E_GOOD = 0x01,\n-\tCPT_9X_COMP_E_FAULT = 0x02,\n-\tCPT_9X_COMP_E_HWERR = 0x04,\n-\tCPT_9X_COMP_E_INSTERR = 0x05,\n-\tCPT_9X_COMP_E_LAST_ENTRY = 0x06\n-};\n-\n-void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev);\n-\n-int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev);\n-\n-int otx2_cpt_iq_enable(const struct rte_cryptodev *dev,\n-\t\t const struct otx2_cpt_qp *qp, uint8_t grp_mask,\n-\t\t uint8_t pri, uint32_t size_div40);\n-\n-void otx2_cpt_iq_disable(struct otx2_cpt_qp *qp);\n-\n-#endif /* _OTX2_CRYPTODEV_HW_ACCESS_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\ndeleted file mode 100644\nindex f9e7b0b474..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n+++ /dev/null\n@@ -1,285 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2019 Marvell International Ltd.\n- */\n-#include <cryptodev_pmd.h>\n-#include <rte_ethdev.h>\n-\n-#include \"otx2_cryptodev.h\"\n-#include \"otx2_cryptodev_hw_access.h\"\n-#include \"otx2_cryptodev_mbox.h\"\n-#include \"otx2_dev.h\"\n-#include \"otx2_ethdev.h\"\n-#include \"otx2_sec_idev.h\"\n-#include \"otx2_mbox.h\"\n-\n-#include \"cpt_pmd_logs.h\"\n-\n-int\n-otx2_cpt_hardware_caps_get(const struct rte_cryptodev *dev,\n-\t\t\t union cpt_eng_caps *hw_caps)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tstruct otx2_dev *otx2_dev = &vf->otx2_dev;\n-\tstruct cpt_caps_rsp_msg *rsp;\n-\tint ret;\n-\n-\totx2_mbox_alloc_msg_cpt_caps_get(otx2_dev->mbox);\n-\n-\tret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);\n-\tif (ret)\n-\t\treturn -EIO;\n-\n-\tif (rsp->cpt_pf_drv_version != OTX2_CPT_PMD_VERSION) {\n-\t\totx2_err(\"Incompatible CPT PMD version\"\n-\t\t\t \"(Kernel: 0x%04x DPDK: 0x%04x)\",\n-\t\t\t rsp->cpt_pf_drv_version, OTX2_CPT_PMD_VERSION);\n-\t\treturn -EPIPE;\n-\t}\n-\n-\tvf->cpt_revision = rsp->cpt_revision;\n-\totx2_mbox_memcpy(hw_caps, rsp->eng_caps,\n-\t\tsizeof(union cpt_eng_caps) * CPT_MAX_ENG_TYPES);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,\n-\t\t\t uint16_t *nb_queues)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tstruct otx2_dev *otx2_dev = &vf->otx2_dev;\n-\tstruct free_rsrcs_rsp *rsp;\n-\tint ret;\n-\n-\totx2_mbox_alloc_msg_free_rsrc_cnt(otx2_dev->mbox);\n-\n-\tret = otx2_mbox_process_msg(otx2_dev->mbox, (void *)&rsp);\n-\tif (ret)\n-\t\treturn -EIO;\n-\n-\t*nb_queues = rsp->cpt + rsp->cpt1;\n-\treturn 0;\n-}\n-\n-int\n-otx2_cpt_queues_attach(const struct rte_cryptodev *dev, uint8_t nb_queues)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n-\tint blkaddr[OTX2_CPT_MAX_BLKS];\n-\tstruct rsrc_attach_req *req;\n-\tint blknum = 0;\n-\tint i, ret;\n-\n-\tblkaddr[0] = RVU_BLOCK_ADDR_CPT0;\n-\tblkaddr[1] = RVU_BLOCK_ADDR_CPT1;\n-\n-\t/* Ask AF to attach required LFs */\n-\n-\treq = otx2_mbox_alloc_msg_attach_resources(mbox);\n-\n-\tif ((vf->cpt_revision == OTX2_CPT_REVISION_ID_3) &&\n-\t (vf->otx2_dev.pf_func & 0x1))\n-\t\tblknum = (blknum + 1) % OTX2_CPT_MAX_BLKS;\n-\n-\t/* 1 LF = 1 queue */\n-\treq->cptlfs = nb_queues;\n-\treq->cpt_blkaddr = blkaddr[blknum];\n-\n-\tret = otx2_mbox_process(mbox);\n-\tif (ret == -ENOSPC) {\n-\t\tif (vf->cpt_revision == OTX2_CPT_REVISION_ID_3) {\n-\t\t\tblknum = (blknum + 1) % OTX2_CPT_MAX_BLKS;\n-\t\t\treq->cpt_blkaddr = blkaddr[blknum];\n-\t\t\tif (otx2_mbox_process(mbox) < 0)\n-\t\t\t\treturn -EIO;\n-\t\t} else {\n-\t\t\treturn -EIO;\n-\t\t}\n-\t} else if (ret < 0) {\n-\t\treturn -EIO;\n-\t}\n-\n-\t/* Update number of attached queues */\n-\tvf->nb_queues = nb_queues;\n-\tfor (i = 0; i < nb_queues; i++)\n-\t\tvf->lf_blkaddr[i] = req->cpt_blkaddr;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_cpt_queues_detach(const struct rte_cryptodev *dev)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n-\tstruct rsrc_detach_req *req;\n-\n-\treq = otx2_mbox_alloc_msg_detach_resources(mbox);\n-\treq->cptlfs = true;\n-\treq->partial = true;\n-\tif (otx2_mbox_process(mbox) < 0)\n-\t\treturn -EIO;\n-\n-\t/* Queues have been detached */\n-\tvf->nb_queues = 0;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n-\tstruct msix_offset_rsp *rsp;\n-\tuint32_t i, ret;\n-\n-\t/* Get CPT MSI-X vector offsets */\n-\n-\totx2_mbox_alloc_msg_msix_offset(mbox);\n-\n-\tret = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tfor (i = 0; i < vf->nb_queues; i++)\n-\t\tvf->lf_msixoff[i] = (vf->lf_blkaddr[i] == RVU_BLOCK_ADDR_CPT1) ?\n-\t\t\trsp->cpt1_lf_msixoff[i] : rsp->cptlf_msixoff[i];\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_cpt_send_mbox_msg(struct otx2_cpt_vf *vf)\n-{\n-\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n-\tint ret;\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\n-\tret = otx2_mbox_wait_for_rsp(mbox, 0);\n-\tif (ret < 0) {\n-\t\tCPT_LOG_ERR(\"Could not get mailbox response\");\n-\t\treturn ret;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,\n-\t\t uint8_t blkaddr, uint64_t *val)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];\n-\tstruct cpt_rd_wr_reg_msg *msg;\n-\tint ret, off;\n-\n-\tmsg = (struct cpt_rd_wr_reg_msg *)\n-\t\t\totx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*msg),\n-\t\t\t\t\t\tsizeof(*msg));\n-\tif (msg == NULL) {\n-\t\tCPT_LOG_ERR(\"Could not allocate mailbox message\");\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tmsg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;\n-\tmsg->hdr.sig = OTX2_MBOX_REQ_SIG;\n-\tmsg->hdr.pcifunc = vf->otx2_dev.pf_func;\n-\tmsg->is_write = 0;\n-\tmsg->reg_offset = reg;\n-\tmsg->ret_val = val;\n-\tmsg->blkaddr = blkaddr;\n-\n-\tret = otx2_cpt_send_mbox_msg(vf);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\toff = mbox->rx_start +\n-\t\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n-\tmsg = (struct cpt_rd_wr_reg_msg *) ((uintptr_t)mdev->mbase + off);\n-\n-\t*val = msg->val;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,\n-\t\t uint8_t blkaddr, uint64_t val)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n-\tstruct cpt_rd_wr_reg_msg *msg;\n-\n-\tmsg = (struct cpt_rd_wr_reg_msg *)\n-\t\t\totx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*msg),\n-\t\t\t\t\t\tsizeof(*msg));\n-\tif (msg == NULL) {\n-\t\tCPT_LOG_ERR(\"Could not allocate mailbox message\");\n-\t\treturn -EFAULT;\n-\t}\n-\n-\tmsg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;\n-\tmsg->hdr.sig = OTX2_MBOX_REQ_SIG;\n-\tmsg->hdr.pcifunc = vf->otx2_dev.pf_func;\n-\tmsg->is_write = 1;\n-\tmsg->reg_offset = reg;\n-\tmsg->val = val;\n-\tmsg->blkaddr = blkaddr;\n-\n-\treturn otx2_cpt_send_mbox_msg(vf);\n-}\n-\n-int\n-otx2_cpt_inline_init(const struct rte_cryptodev *dev)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n-\tstruct cpt_rx_inline_lf_cfg_msg *msg;\n-\tint ret;\n-\n-\tmsg = otx2_mbox_alloc_msg_cpt_rx_inline_lf_cfg(mbox);\n-\tmsg->sso_pf_func = otx2_sso_pf_func_get();\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\tret = otx2_mbox_process(mbox);\n-\tif (ret < 0)\n-\t\treturn -EIO;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_cpt_qp_ethdev_bind(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp,\n-\t\t\tuint16_t port_id)\n-{\n-\tstruct rte_eth_dev *eth_dev = &rte_eth_devices[port_id];\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n-\tstruct cpt_inline_ipsec_cfg_msg *msg;\n-\tstruct otx2_eth_dev *otx2_eth_dev;\n-\tint ret;\n-\n-\tif (!otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))\n-\t\treturn -EINVAL;\n-\n-\totx2_eth_dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tmsg = otx2_mbox_alloc_msg_cpt_inline_ipsec_cfg(mbox);\n-\tmsg->dir = CPT_INLINE_OUTBOUND;\n-\tmsg->enable = 1;\n-\tmsg->slot = qp->id;\n-\n-\tmsg->nix_pf_func = otx2_eth_dev->pf_func;\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\tret = otx2_mbox_process(mbox);\n-\tif (ret < 0)\n-\t\treturn -EIO;\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\ndeleted file mode 100644\nindex 03323e418c..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\n+++ /dev/null\n@@ -1,37 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_CRYPTODEV_MBOX_H_\n-#define _OTX2_CRYPTODEV_MBOX_H_\n-\n-#include <rte_cryptodev.h>\n-\n-#include \"otx2_cryptodev_hw_access.h\"\n-\n-int otx2_cpt_hardware_caps_get(const struct rte_cryptodev *dev,\n-\t\t\t union cpt_eng_caps *hw_caps);\n-\n-int otx2_cpt_available_queues_get(const struct rte_cryptodev *dev,\n-\t\t\t\t uint16_t *nb_queues);\n-\n-int otx2_cpt_queues_attach(const struct rte_cryptodev *dev, uint8_t nb_queues);\n-\n-int otx2_cpt_queues_detach(const struct rte_cryptodev *dev);\n-\n-int otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev);\n-\n-__rte_internal\n-int otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,\n-\t\t\t uint8_t blkaddr, uint64_t *val);\n-\n-__rte_internal\n-int otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,\n-\t\t\t uint8_t blkaddr, uint64_t val);\n-\n-int otx2_cpt_qp_ethdev_bind(const struct rte_cryptodev *dev,\n-\t\t\t struct otx2_cpt_qp *qp, uint16_t port_id);\n-\n-int otx2_cpt_inline_init(const struct rte_cryptodev *dev);\n-\n-#endif /* _OTX2_CRYPTODEV_MBOX_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\ndeleted file mode 100644\nindex 339b82f33e..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ /dev/null\n@@ -1,1438 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2019 Marvell International Ltd.\n- */\n-\n-#include <unistd.h>\n-\n-#include <cryptodev_pmd.h>\n-#include <rte_errno.h>\n-#include <ethdev_driver.h>\n-#include <rte_event_crypto_adapter.h>\n-\n-#include \"otx2_cryptodev.h\"\n-#include \"otx2_cryptodev_capabilities.h\"\n-#include \"otx2_cryptodev_hw_access.h\"\n-#include \"otx2_cryptodev_mbox.h\"\n-#include \"otx2_cryptodev_ops.h\"\n-#include \"otx2_cryptodev_ops_helper.h\"\n-#include \"otx2_ipsec_anti_replay.h\"\n-#include \"otx2_ipsec_po_ops.h\"\n-#include \"otx2_mbox.h\"\n-#include \"otx2_sec_idev.h\"\n-#include \"otx2_security.h\"\n-\n-#include \"cpt_hw_types.h\"\n-#include \"cpt_pmd_logs.h\"\n-#include \"cpt_pmd_ops_helper.h\"\n-#include \"cpt_ucode.h\"\n-#include \"cpt_ucode_asym.h\"\n-\n-#define METABUF_POOL_CACHE_SIZE\t512\n-\n-static uint64_t otx2_fpm_iova[CPT_EC_ID_PMAX];\n-\n-/* Forward declarations */\n-\n-static int\n-otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);\n-\n-static void\n-qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)\n-{\n-\tsnprintf(name, size, \"otx2_cpt_lf_mem_%u:%u\", dev_id, qp_id);\n-}\n-\n-static int\n-otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,\n-\t\t\t\tstruct otx2_cpt_qp *qp, uint8_t qp_id,\n-\t\t\t\tunsigned int nb_elements)\n-{\n-\tchar mempool_name[RTE_MEMPOOL_NAMESIZE];\n-\tstruct cpt_qp_meta_info *meta_info;\n-\tint lcore_cnt = rte_lcore_count();\n-\tint ret, max_mlen, mb_pool_sz;\n-\tstruct rte_mempool *pool;\n-\tint asym_mlen = 0;\n-\tint lb_mlen = 0;\n-\tint sg_mlen = 0;\n-\n-\tif (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {\n-\n-\t\t/* Get meta len for scatter gather mode */\n-\t\tsg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();\n-\n-\t\t/* Extra 32B saved for future considerations */\n-\t\tsg_mlen += 4 * sizeof(uint64_t);\n-\n-\t\t/* Get meta len for linear buffer (direct) mode */\n-\t\tlb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();\n-\n-\t\t/* Extra 32B saved for future considerations */\n-\t\tlb_mlen += 4 * sizeof(uint64_t);\n-\t}\n-\n-\tif (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {\n-\n-\t\t/* Get meta len required for asymmetric operations */\n-\t\tasym_mlen = cpt_pmd_ops_helper_asym_get_mlen();\n-\t}\n-\n-\t/*\n-\t * Check max requirement for meta buffer to\n-\t * support crypto op of any type (sym/asym).\n-\t */\n-\tmax_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);\n-\n-\t/* Allocate mempool */\n-\n-\tsnprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, \"otx2_cpt_mb_%u:%u\",\n-\t\t dev->data->dev_id, qp_id);\n-\n-\tmb_pool_sz = nb_elements;\n-\n-\t/* For poll mode, core that enqueues and core that dequeues can be\n-\t * different. For event mode, all cores are allowed to use same crypto\n-\t * queue pair.\n-\t */\n-\tmb_pool_sz += (RTE_MAX(2, lcore_cnt) * METABUF_POOL_CACHE_SIZE);\n-\n-\tpool = rte_mempool_create_empty(mempool_name, mb_pool_sz, max_mlen,\n-\t\t\t\t\tMETABUF_POOL_CACHE_SIZE, 0,\n-\t\t\t\t\trte_socket_id(), 0);\n-\n-\tif (pool == NULL) {\n-\t\tCPT_LOG_ERR(\"Could not create mempool for metabuf\");\n-\t\treturn rte_errno;\n-\t}\n-\n-\tret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,\n-\t\t\t\t\t NULL);\n-\tif (ret) {\n-\t\tCPT_LOG_ERR(\"Could not set mempool ops\");\n-\t\tgoto mempool_free;\n-\t}\n-\n-\tret = rte_mempool_populate_default(pool);\n-\tif (ret <= 0) {\n-\t\tCPT_LOG_ERR(\"Could not populate metabuf pool\");\n-\t\tgoto mempool_free;\n-\t}\n-\n-\tmeta_info = &qp->meta_info;\n-\n-\tmeta_info->pool = pool;\n-\tmeta_info->lb_mlen = lb_mlen;\n-\tmeta_info->sg_mlen = sg_mlen;\n-\n-\treturn 0;\n-\n-mempool_free:\n-\trte_mempool_free(pool);\n-\treturn ret;\n-}\n-\n-static void\n-otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)\n-{\n-\tstruct cpt_qp_meta_info *meta_info = &qp->meta_info;\n-\n-\trte_mempool_free(meta_info->pool);\n-\n-\tmeta_info->pool = NULL;\n-\tmeta_info->lb_mlen = 0;\n-\tmeta_info->sg_mlen = 0;\n-}\n-\n-static int\n-otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)\n-{\n-\tstatic rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);\n-\tuint16_t port_id, nb_ethport = rte_eth_dev_count_avail();\n-\tint i, ret;\n-\n-\tfor (i = 0; i < nb_ethport; i++) {\n-\t\tport_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;\n-\t\tif (otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))\n-\t\t\tbreak;\n-\t}\n-\n-\tif (i >= nb_ethport)\n-\t\treturn 0;\n-\n-\tret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t/* Publish inline Tx QP to eth dev security */\n-\tret = otx2_sec_idev_tx_cpt_qp_add(port_id, qp);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\treturn 0;\n-}\n-\n-static struct otx2_cpt_qp *\n-otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,\n-\t\t uint8_t group)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tuint64_t pg_sz = sysconf(_SC_PAGESIZE);\n-\tconst struct rte_memzone *lf_mem;\n-\tuint32_t len, iq_len, size_div40;\n-\tchar name[RTE_MEMZONE_NAMESIZE];\n-\tuint64_t used_len, iova;\n-\tstruct otx2_cpt_qp *qp;\n-\tuint64_t lmtline;\n-\tuint8_t *va;\n-\tint ret;\n-\n-\t/* Allocate queue pair */\n-\tqp = rte_zmalloc_socket(\"OCTEON TX2 Crypto PMD Queue Pair\", sizeof(*qp),\n-\t\t\t\tOTX2_ALIGN, 0);\n-\tif (qp == NULL) {\n-\t\tCPT_LOG_ERR(\"Could not allocate queue pair\");\n-\t\treturn NULL;\n-\t}\n-\n-\t/*\n-\t * Pending queue updates make assumption that queue size is a power\n-\t * of 2.\n-\t */\n-\tRTE_BUILD_BUG_ON(!RTE_IS_POWER_OF_2(OTX2_CPT_DEFAULT_CMD_QLEN));\n-\n-\tiq_len = OTX2_CPT_DEFAULT_CMD_QLEN;\n-\n-\t/*\n-\t * Queue size must be a multiple of 40 and effective queue size to\n-\t * software is (size_div40 - 1) * 40\n-\t */\n-\tsize_div40 = (iq_len + 40 - 1) / 40 + 1;\n-\n-\t/* For pending queue */\n-\tlen = iq_len * RTE_ALIGN(sizeof(qp->pend_q.rid_queue[0]), 8);\n-\n-\t/* Space for instruction group memory */\n-\tlen += size_div40 * 16;\n-\n-\t/* So that instruction queues start as pg size aligned */\n-\tlen = RTE_ALIGN(len, pg_sz);\n-\n-\t/* For instruction queues */\n-\tlen += OTX2_CPT_DEFAULT_CMD_QLEN * sizeof(union cpt_inst_s);\n-\n-\t/* Wastage after instruction queues */\n-\tlen = RTE_ALIGN(len, pg_sz);\n-\n-\tqp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,\n-\t\t\t qp_id);\n-\n-\tlf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,\n-\t\t\tRTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,\n-\t\t\tRTE_CACHE_LINE_SIZE);\n-\tif (lf_mem == NULL) {\n-\t\tCPT_LOG_ERR(\"Could not allocate reserved memzone\");\n-\t\tgoto qp_free;\n-\t}\n-\n-\tva = lf_mem->addr;\n-\tiova = lf_mem->iova;\n-\n-\tmemset(va, 0, len);\n-\n-\tret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);\n-\tif (ret) {\n-\t\tCPT_LOG_ERR(\"Could not create mempool for metabuf\");\n-\t\tgoto lf_mem_free;\n-\t}\n-\n-\t/* Initialize pending queue */\n-\tqp->pend_q.rid_queue = (void **)va;\n-\tqp->pend_q.tail = 0;\n-\tqp->pend_q.head = 0;\n-\n-\tused_len = iq_len * RTE_ALIGN(sizeof(qp->pend_q.rid_queue[0]), 8);\n-\tused_len += size_div40 * 16;\n-\tused_len = RTE_ALIGN(used_len, pg_sz);\n-\tiova += used_len;\n-\n-\tqp->iq_dma_addr = iova;\n-\tqp->id = qp_id;\n-\tqp->blkaddr = vf->lf_blkaddr[qp_id];\n-\tqp->base = OTX2_CPT_LF_BAR2(vf, qp->blkaddr, qp_id);\n-\n-\tlmtline = vf->otx2_dev.bar2 +\n-\t\t (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +\n-\t\t OTX2_LMT_LF_LMTLINE(0);\n-\n-\tqp->lmtline = (void *)lmtline;\n-\n-\tqp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);\n-\n-\tret = otx2_sec_idev_tx_cpt_qp_remove(qp);\n-\tif (ret && (ret != -ENOENT)) {\n-\t\tCPT_LOG_ERR(\"Could not delete inline configuration\");\n-\t\tgoto mempool_destroy;\n-\t}\n-\n-\totx2_cpt_iq_disable(qp);\n-\n-\tret = otx2_cpt_qp_inline_cfg(dev, qp);\n-\tif (ret) {\n-\t\tCPT_LOG_ERR(\"Could not configure queue for inline IPsec\");\n-\t\tgoto mempool_destroy;\n-\t}\n-\n-\tret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,\n-\t\t\t\t size_div40);\n-\tif (ret) {\n-\t\tCPT_LOG_ERR(\"Could not enable instruction queue\");\n-\t\tgoto mempool_destroy;\n-\t}\n-\n-\treturn qp;\n-\n-mempool_destroy:\n-\totx2_cpt_metabuf_mempool_destroy(qp);\n-lf_mem_free:\n-\trte_memzone_free(lf_mem);\n-qp_free:\n-\trte_free(qp);\n-\treturn NULL;\n-}\n-\n-static int\n-otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)\n-{\n-\tconst struct rte_memzone *lf_mem;\n-\tchar name[RTE_MEMZONE_NAMESIZE];\n-\tint ret;\n-\n-\tret = otx2_sec_idev_tx_cpt_qp_remove(qp);\n-\tif (ret && (ret != -ENOENT)) {\n-\t\tCPT_LOG_ERR(\"Could not delete inline configuration\");\n-\t\treturn ret;\n-\t}\n-\n-\totx2_cpt_iq_disable(qp);\n-\n-\totx2_cpt_metabuf_mempool_destroy(qp);\n-\n-\tqp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,\n-\t\t\t qp->id);\n-\n-\tlf_mem = rte_memzone_lookup(name);\n-\n-\tret = rte_memzone_free(lf_mem);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\trte_free(qp);\n-\n-\treturn 0;\n-}\n-\n-static int\n-sym_xform_verify(struct rte_crypto_sym_xform *xform)\n-{\n-\tif (xform->next) {\n-\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&\n-\t\t xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&\n-\t\t xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT &&\n-\t\t (xform->auth.algo != RTE_CRYPTO_AUTH_SHA1_HMAC ||\n-\t\t xform->next->cipher.algo != RTE_CRYPTO_CIPHER_AES_CBC))\n-\t\t\treturn -ENOTSUP;\n-\n-\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&\n-\t\t xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT &&\n-\t\t xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&\n-\t\t (xform->cipher.algo != RTE_CRYPTO_CIPHER_AES_CBC ||\n-\t\t xform->next->auth.algo != RTE_CRYPTO_AUTH_SHA1_HMAC))\n-\t\t\treturn -ENOTSUP;\n-\n-\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&\n-\t\t xform->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC &&\n-\t\t xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&\n-\t\t xform->next->auth.algo == RTE_CRYPTO_AUTH_SHA1)\n-\t\t\treturn -ENOTSUP;\n-\n-\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&\n-\t\t xform->auth.algo == RTE_CRYPTO_AUTH_SHA1 &&\n-\t\t xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&\n-\t\t xform->next->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC)\n-\t\t\treturn -ENOTSUP;\n-\n-\t} else {\n-\t\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&\n-\t\t xform->auth.algo == RTE_CRYPTO_AUTH_NULL &&\n-\t\t xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY)\n-\t\t\treturn -ENOTSUP;\n-\t}\n-\treturn 0;\n-}\n-\n-static int\n-sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,\n-\t\t struct rte_cryptodev_sym_session *sess,\n-\t\t struct rte_mempool *pool)\n-{\n-\tstruct rte_crypto_sym_xform *temp_xform = xform;\n-\tstruct cpt_sess_misc *misc;\n-\tvq_cmd_word3_t vq_cmd_w3;\n-\tvoid *priv;\n-\tint ret;\n-\n-\tret = sym_xform_verify(xform);\n-\tif (unlikely(ret))\n-\t\treturn ret;\n-\n-\tif (unlikely(rte_mempool_get(pool, &priv))) {\n-\t\tCPT_LOG_ERR(\"Could not allocate session private data\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tmemset(priv, 0, sizeof(struct cpt_sess_misc) +\n-\t\t\toffsetof(struct cpt_ctx, mc_ctx));\n-\n-\tmisc = priv;\n-\n-\tfor ( ; xform != NULL; xform = xform->next) {\n-\t\tswitch (xform->type) {\n-\t\tcase RTE_CRYPTO_SYM_XFORM_AEAD:\n-\t\t\tret = fill_sess_aead(xform, misc);\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_SYM_XFORM_CIPHER:\n-\t\t\tret = fill_sess_cipher(xform, misc);\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_SYM_XFORM_AUTH:\n-\t\t\tif (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)\n-\t\t\t\tret = fill_sess_gmac(xform, misc);\n-\t\t\telse\n-\t\t\t\tret = fill_sess_auth(xform, misc);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tret = -1;\n-\t\t}\n-\n-\t\tif (ret)\n-\t\t\tgoto priv_put;\n-\t}\n-\n-\tif ((GET_SESS_FC_TYPE(misc) == HASH_HMAC) &&\n-\t\t\tcpt_mac_len_verify(&temp_xform->auth)) {\n-\t\tCPT_LOG_ERR(\"MAC length is not supported\");\n-\t\tstruct cpt_ctx *ctx = SESS_PRIV(misc);\n-\t\tif (ctx->auth_key != NULL) {\n-\t\t\trte_free(ctx->auth_key);\n-\t\t\tctx->auth_key = NULL;\n-\t\t}\n-\t\tret = -ENOTSUP;\n-\t\tgoto priv_put;\n-\t}\n-\n-\tset_sym_session_private_data(sess, driver_id, misc);\n-\n-\tmisc->ctx_dma_addr = rte_mempool_virt2iova(misc) +\n-\t\t\t sizeof(struct cpt_sess_misc);\n-\n-\tvq_cmd_w3.u64 = 0;\n-\tvq_cmd_w3.s.cptr = misc->ctx_dma_addr + offsetof(struct cpt_ctx,\n-\t\t\t\t\t\t\t mc_ctx);\n-\n-\t/*\n-\t * IE engines support IPsec operations\n-\t * SE engines support IPsec operations, Chacha-Poly and\n-\t * Air-Crypto operations\n-\t */\n-\tif (misc->zsk_flag || misc->chacha_poly)\n-\t\tvq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE;\n-\telse\n-\t\tvq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE_IE;\n-\n-\tmisc->cpt_inst_w7 = vq_cmd_w3.u64;\n-\n-\treturn 0;\n-\n-priv_put:\n-\trte_mempool_put(pool, priv);\n-\n-\treturn -ENOTSUP;\n-}\n-\n-static __rte_always_inline int32_t __rte_hot\n-otx2_ca_enqueue_req(const struct otx2_cpt_qp *qp,\n-\t\t struct cpt_request_info *req,\n-\t\t void *lmtline,\n-\t\t struct rte_crypto_op *op,\n-\t\t uint64_t cpt_inst_w7)\n-{\n-\tunion rte_event_crypto_metadata *m_data;\n-\tunion cpt_inst_s inst;\n-\tuint64_t lmt_status;\n-\n-\tif (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {\n-\t\tm_data = rte_cryptodev_sym_session_get_user_data(\n-\t\t\t\t\t\top->sym->session);\n-\t\tif (m_data == NULL) {\n-\t\t\trte_pktmbuf_free(op->sym->m_src);\n-\t\t\trte_crypto_op_free(op);\n-\t\t\trte_errno = EINVAL;\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t} else if (op->sess_type == RTE_CRYPTO_OP_SESSIONLESS &&\n-\t\t op->private_data_offset) {\n-\t\tm_data = (union rte_event_crypto_metadata *)\n-\t\t\t ((uint8_t *)op +\n-\t\t\t op->private_data_offset);\n-\t} else {\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tinst.u[0] = 0;\n-\tinst.s9x.res_addr = req->comp_baddr;\n-\tinst.u[2] = 0;\n-\tinst.u[3] = 0;\n-\n-\tinst.s9x.ei0 = req->ist.ei0;\n-\tinst.s9x.ei1 = req->ist.ei1;\n-\tinst.s9x.ei2 = req->ist.ei2;\n-\tinst.s9x.ei3 = cpt_inst_w7;\n-\n-\tinst.u[2] = (((RTE_EVENT_TYPE_CRYPTODEV << 28) |\n-\t\t m_data->response_info.flow_id) |\n-\t\t ((uint64_t)m_data->response_info.sched_type << 32) |\n-\t\t ((uint64_t)m_data->response_info.queue_id << 34));\n-\tinst.u[3] = 1 | (((uint64_t)req >> 3) << 3);\n-\treq->qp = qp;\n-\n-\tdo {\n-\t\t/* Copy CPT command to LMTLINE */\n-\t\tmemcpy(lmtline, &inst, sizeof(inst));\n-\n-\t\t/*\n-\t\t * Make sure compiler does not reorder memcpy and ldeor.\n-\t\t * LMTST transactions are always flushed from the write\n-\t\t * buffer immediately, a DMB is not required to push out\n-\t\t * LMTSTs.\n-\t\t */\n-\t\trte_io_wmb();\n-\t\tlmt_status = otx2_lmt_submit(qp->lf_nq_reg);\n-\t} while (lmt_status == 0);\n-\n-\treturn 0;\n-}\n-\n-static __rte_always_inline int32_t __rte_hot\n-otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,\n-\t\t struct pending_queue *pend_q,\n-\t\t struct cpt_request_info *req,\n-\t\t struct rte_crypto_op *op,\n-\t\t uint64_t cpt_inst_w7,\n-\t\t unsigned int burst_index)\n-{\n-\tvoid *lmtline = qp->lmtline;\n-\tunion cpt_inst_s inst;\n-\tuint64_t lmt_status;\n-\n-\tif (qp->ca_enable)\n-\t\treturn otx2_ca_enqueue_req(qp, req, lmtline, op, cpt_inst_w7);\n-\n-\tinst.u[0] = 0;\n-\tinst.s9x.res_addr = req->comp_baddr;\n-\tinst.u[2] = 0;\n-\tinst.u[3] = 0;\n-\n-\tinst.s9x.ei0 = req->ist.ei0;\n-\tinst.s9x.ei1 = req->ist.ei1;\n-\tinst.s9x.ei2 = req->ist.ei2;\n-\tinst.s9x.ei3 = cpt_inst_w7;\n-\n-\treq->time_out = rte_get_timer_cycles() +\n-\t\t\tDEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();\n-\n-\tdo {\n-\t\t/* Copy CPT command to LMTLINE */\n-\t\tmemcpy(lmtline, &inst, sizeof(inst));\n-\n-\t\t/*\n-\t\t * Make sure compiler does not reorder memcpy and ldeor.\n-\t\t * LMTST transactions are always flushed from the write\n-\t\t * buffer immediately, a DMB is not required to push out\n-\t\t * LMTSTs.\n-\t\t */\n-\t\trte_io_wmb();\n-\t\tlmt_status = otx2_lmt_submit(qp->lf_nq_reg);\n-\t} while (lmt_status == 0);\n-\n-\tpending_queue_push(pend_q, req, burst_index, OTX2_CPT_DEFAULT_CMD_QLEN);\n-\n-\treturn 0;\n-}\n-\n-static __rte_always_inline int32_t __rte_hot\n-otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,\n-\t\t struct rte_crypto_op *op,\n-\t\t struct pending_queue *pend_q,\n-\t\t unsigned int burst_index)\n-{\n-\tstruct cpt_qp_meta_info *minfo = &qp->meta_info;\n-\tstruct rte_crypto_asym_op *asym_op = op->asym;\n-\tstruct asym_op_params params = {0};\n-\tstruct cpt_asym_sess_misc *sess;\n-\tuintptr_t *cop;\n-\tvoid *mdata;\n-\tint ret;\n-\n-\tif (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {\n-\t\tCPT_LOG_ERR(\"Could not allocate meta buffer for request\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tsess = get_asym_session_private_data(asym_op->session,\n-\t\t\t\t\t otx2_cryptodev_driver_id);\n-\n-\t/* Store IO address of the mdata to meta_buf */\n-\tparams.meta_buf = rte_mempool_virt2iova(mdata);\n-\n-\tcop = mdata;\n-\tcop[0] = (uintptr_t)mdata;\n-\tcop[1] = (uintptr_t)op;\n-\tcop[2] = cop[3] = 0ULL;\n-\n-\tparams.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));\n-\tparams.req->op = cop;\n-\n-\t/* Adjust meta_buf to point to end of cpt_request_info structure */\n-\tparams.meta_buf += (4 * sizeof(uintptr_t)) +\n-\t\t\t sizeof(struct cpt_request_info);\n-\tswitch (sess->xfrm_type) {\n-\tcase RTE_CRYPTO_ASYM_XFORM_MODEX:\n-\t\tret = cpt_modex_prep(¶ms, &sess->mod_ctx);\n-\t\tif (unlikely(ret))\n-\t\t\tgoto req_fail;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_ASYM_XFORM_RSA:\n-\t\tret = cpt_enqueue_rsa_op(op, ¶ms, sess);\n-\t\tif (unlikely(ret))\n-\t\t\tgoto req_fail;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_ASYM_XFORM_ECDSA:\n-\t\tret = cpt_enqueue_ecdsa_op(op, ¶ms, sess, otx2_fpm_iova);\n-\t\tif (unlikely(ret))\n-\t\t\tgoto req_fail;\n-\t\tbreak;\n-\tcase RTE_CRYPTO_ASYM_XFORM_ECPM:\n-\t\tret = cpt_ecpm_prep(&asym_op->ecpm, ¶ms,\n-\t\t\t\t sess->ec_ctx.curveid);\n-\t\tif (unlikely(ret))\n-\t\t\tgoto req_fail;\n-\t\tbreak;\n-\tdefault:\n-\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n-\t\tret = -EINVAL;\n-\t\tgoto req_fail;\n-\t}\n-\n-\tret = otx2_cpt_enqueue_req(qp, pend_q, params.req, op,\n-\t\t\t\t sess->cpt_inst_w7, burst_index);\n-\tif (unlikely(ret)) {\n-\t\tCPT_LOG_DP_ERR(\"Could not enqueue crypto req\");\n-\t\tgoto req_fail;\n-\t}\n-\n-\treturn 0;\n-\n-req_fail:\n-\tfree_op_meta(mdata, minfo->pool);\n-\n-\treturn ret;\n-}\n-\n-static __rte_always_inline int __rte_hot\n-otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,\n-\t\t struct pending_queue *pend_q, unsigned int burst_index)\n-{\n-\tstruct rte_crypto_sym_op *sym_op = op->sym;\n-\tstruct cpt_request_info *req;\n-\tstruct cpt_sess_misc *sess;\n-\tuint64_t cpt_op;\n-\tvoid *mdata;\n-\tint ret;\n-\n-\tsess = get_sym_session_private_data(sym_op->session,\n-\t\t\t\t\t otx2_cryptodev_driver_id);\n-\n-\tcpt_op = sess->cpt_op;\n-\n-\tif (cpt_op & CPT_OP_CIPHER_MASK)\n-\t\tret = fill_fc_params(op, sess, &qp->meta_info, &mdata,\n-\t\t\t\t (void **)&req);\n-\telse\n-\t\tret = fill_digest_params(op, sess, &qp->meta_info, &mdata,\n-\t\t\t\t\t (void **)&req);\n-\n-\tif (unlikely(ret)) {\n-\t\tCPT_LOG_DP_ERR(\"Crypto req : op %p, cpt_op 0x%x ret 0x%x\",\n-\t\t\t\top, (unsigned int)cpt_op, ret);\n-\t\treturn ret;\n-\t}\n-\n-\tret = otx2_cpt_enqueue_req(qp, pend_q, req, op, sess->cpt_inst_w7,\n-\t\t\t\t burst_index);\n-\tif (unlikely(ret)) {\n-\t\t/* Free buffer allocated by fill params routines */\n-\t\tfree_op_meta(mdata, qp->meta_info.pool);\n-\t}\n-\n-\treturn ret;\n-}\n-\n-static __rte_always_inline int __rte_hot\n-otx2_cpt_enqueue_sec(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,\n-\t\t struct pending_queue *pend_q,\n-\t\t const unsigned int burst_index)\n-{\n-\tuint32_t winsz, esn_low = 0, esn_hi = 0, seql = 0, seqh = 0;\n-\tstruct rte_mbuf *m_src = op->sym->m_src;\n-\tstruct otx2_sec_session_ipsec_lp *sess;\n-\tstruct otx2_ipsec_po_sa_ctl *ctl_wrd;\n-\tstruct otx2_ipsec_po_in_sa *sa;\n-\tstruct otx2_sec_session *priv;\n-\tstruct cpt_request_info *req;\n-\tuint64_t seq_in_sa, seq = 0;\n-\tuint8_t esn;\n-\tint ret;\n-\n-\tpriv = get_sec_session_private_data(op->sym->sec_session);\n-\tsess = &priv->ipsec.lp;\n-\tsa = &sess->in_sa;\n-\n-\tctl_wrd = &sa->ctl;\n-\tesn = ctl_wrd->esn_en;\n-\twinsz = sa->replay_win_sz;\n-\n-\tif (ctl_wrd->direction == OTX2_IPSEC_PO_SA_DIRECTION_OUTBOUND)\n-\t\tret = process_outb_sa(op, sess, &qp->meta_info, (void **)&req);\n-\telse {\n-\t\tif (winsz) {\n-\t\t\tesn_low = rte_be_to_cpu_32(sa->esn_low);\n-\t\t\tesn_hi = rte_be_to_cpu_32(sa->esn_hi);\n-\t\t\tseql = *rte_pktmbuf_mtod_offset(m_src, uint32_t *,\n-\t\t\t\tsizeof(struct rte_ipv4_hdr) + 4);\n-\t\t\tseql = rte_be_to_cpu_32(seql);\n-\n-\t\t\tif (!esn)\n-\t\t\t\tseq = (uint64_t)seql;\n-\t\t\telse {\n-\t\t\t\tseqh = anti_replay_get_seqh(winsz, seql, esn_hi,\n-\t\t\t\t\t\tesn_low);\n-\t\t\t\tseq = ((uint64_t)seqh << 32) | seql;\n-\t\t\t}\n-\n-\t\t\tif (unlikely(seq == 0))\n-\t\t\t\treturn IPSEC_ANTI_REPLAY_FAILED;\n-\n-\t\t\tret = anti_replay_check(sa->replay, seq, winsz);\n-\t\t\tif (unlikely(ret)) {\n-\t\t\t\totx2_err(\"Anti replay check failed\");\n-\t\t\t\treturn IPSEC_ANTI_REPLAY_FAILED;\n-\t\t\t}\n-\n-\t\t\tif (esn) {\n-\t\t\t\tseq_in_sa = ((uint64_t)esn_hi << 32) | esn_low;\n-\t\t\t\tif (seq > seq_in_sa) {\n-\t\t\t\t\tsa->esn_low = rte_cpu_to_be_32(seql);\n-\t\t\t\t\tsa->esn_hi = rte_cpu_to_be_32(seqh);\n-\t\t\t\t}\n-\t\t\t}\n-\t\t}\n-\n-\t\tret = process_inb_sa(op, sess, &qp->meta_info, (void **)&req);\n-\t}\n-\n-\tif (unlikely(ret)) {\n-\t\totx2_err(\"Crypto req : op %p, ret 0x%x\", op, ret);\n-\t\treturn ret;\n-\t}\n-\n-\tret = otx2_cpt_enqueue_req(qp, pend_q, req, op, sess->cpt_inst_w7,\n-\t\t\t\t burst_index);\n-\n-\treturn ret;\n-}\n-\n-static __rte_always_inline int __rte_hot\n-otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,\n-\t\t\t struct pending_queue *pend_q,\n-\t\t\t unsigned int burst_index)\n-{\n-\tconst int driver_id = otx2_cryptodev_driver_id;\n-\tstruct rte_crypto_sym_op *sym_op = op->sym;\n-\tstruct rte_cryptodev_sym_session *sess;\n-\tint ret;\n-\n-\t/* Create temporary session */\n-\tsess = rte_cryptodev_sym_session_create(qp->sess_mp);\n-\tif (sess == NULL)\n-\t\treturn -ENOMEM;\n-\n-\tret = sym_session_configure(driver_id, sym_op->xform, sess,\n-\t\t\t\t qp->sess_mp_priv);\n-\tif (ret)\n-\t\tgoto sess_put;\n-\n-\tsym_op->session = sess;\n-\n-\tret = otx2_cpt_enqueue_sym(qp, op, pend_q, burst_index);\n-\n-\tif (unlikely(ret))\n-\t\tgoto priv_put;\n-\n-\treturn 0;\n-\n-priv_put:\n-\tsym_session_clear(driver_id, sess);\n-sess_put:\n-\trte_mempool_put(qp->sess_mp, sess);\n-\treturn ret;\n-}\n-\n-static uint16_t\n-otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n-{\n-\tuint16_t nb_allowed, count = 0;\n-\tstruct otx2_cpt_qp *qp = qptr;\n-\tstruct pending_queue *pend_q;\n-\tstruct rte_crypto_op *op;\n-\tint ret;\n-\n-\tpend_q = &qp->pend_q;\n-\n-\tnb_allowed = pending_queue_free_slots(pend_q,\n-\t\t\t\tOTX2_CPT_DEFAULT_CMD_QLEN, 0);\n-\tnb_ops = RTE_MIN(nb_ops, nb_allowed);\n-\n-\tfor (count = 0; count < nb_ops; count++) {\n-\t\top = ops[count];\n-\t\tif (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n-\t\t\tif (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)\n-\t\t\t\tret = otx2_cpt_enqueue_sec(qp, op, pend_q,\n-\t\t\t\t\t\t\t count);\n-\t\t\telse if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)\n-\t\t\t\tret = otx2_cpt_enqueue_sym(qp, op, pend_q,\n-\t\t\t\t\t\t\t count);\n-\t\t\telse\n-\t\t\t\tret = otx2_cpt_enqueue_sym_sessless(qp, op,\n-\t\t\t\t\t\tpend_q, count);\n-\t\t} else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {\n-\t\t\tif (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)\n-\t\t\t\tret = otx2_cpt_enqueue_asym(qp, op, pend_q,\n-\t\t\t\t\t\t\t\tcount);\n-\t\t\telse\n-\t\t\t\tbreak;\n-\t\t} else\n-\t\t\tbreak;\n-\n-\t\tif (unlikely(ret))\n-\t\t\tbreak;\n-\t}\n-\n-\tif (unlikely(!qp->ca_enable))\n-\t\tpending_queue_commit(pend_q, count, OTX2_CPT_DEFAULT_CMD_QLEN);\n-\n-\treturn count;\n-}\n-\n-static __rte_always_inline void\n-otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,\n-\t\t struct rte_crypto_rsa_xform *rsa_ctx)\n-{\n-\tstruct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;\n-\n-\tswitch (rsa->op_type) {\n-\tcase RTE_CRYPTO_ASYM_OP_ENCRYPT:\n-\t\trsa->cipher.length = rsa_ctx->n.length;\n-\t\tmemcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);\n-\t\tbreak;\n-\tcase RTE_CRYPTO_ASYM_OP_DECRYPT:\n-\t\tif (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {\n-\t\t\trsa->message.length = rsa_ctx->n.length;\n-\t\t\tmemcpy(rsa->message.data, req->rptr,\n-\t\t\t rsa->message.length);\n-\t\t} else {\n-\t\t\t/* Get length of decrypted output */\n-\t\t\trsa->message.length = rte_cpu_to_be_16\n-\t\t\t\t\t (*((uint16_t *)req->rptr));\n-\t\t\t/*\n-\t\t\t * Offset output data pointer by length field\n-\t\t\t * (2 bytes) and copy decrypted data.\n-\t\t\t */\n-\t\t\tmemcpy(rsa->message.data, req->rptr + 2,\n-\t\t\t rsa->message.length);\n-\t\t}\n-\t\tbreak;\n-\tcase RTE_CRYPTO_ASYM_OP_SIGN:\n-\t\trsa->sign.length = rsa_ctx->n.length;\n-\t\tmemcpy(rsa->sign.data, req->rptr, rsa->sign.length);\n-\t\tbreak;\n-\tcase RTE_CRYPTO_ASYM_OP_VERIFY:\n-\t\tif (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {\n-\t\t\trsa->sign.length = rsa_ctx->n.length;\n-\t\t\tmemcpy(rsa->sign.data, req->rptr, rsa->sign.length);\n-\t\t} else {\n-\t\t\t/* Get length of signed output */\n-\t\t\trsa->sign.length = rte_cpu_to_be_16\n-\t\t\t\t\t (*((uint16_t *)req->rptr));\n-\t\t\t/*\n-\t\t\t * Offset output data pointer by length field\n-\t\t\t * (2 bytes) and copy signed data.\n-\t\t\t */\n-\t\t\tmemcpy(rsa->sign.data, req->rptr + 2,\n-\t\t\t rsa->sign.length);\n-\t\t}\n-\t\tif (memcmp(rsa->sign.data, rsa->message.data,\n-\t\t\t rsa->message.length)) {\n-\t\t\tCPT_LOG_DP_ERR(\"RSA verification failed\");\n-\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n-\t\t}\n-\t\tbreak;\n-\tdefault:\n-\t\tCPT_LOG_DP_DEBUG(\"Invalid RSA operation type\");\n-\t\tcop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n-\t\tbreak;\n-\t}\n-}\n-\n-static __rte_always_inline void\n-otx2_cpt_asym_dequeue_ecdsa_op(struct rte_crypto_ecdsa_op_param *ecdsa,\n-\t\t\t struct cpt_request_info *req,\n-\t\t\t struct cpt_asym_ec_ctx *ec)\n-{\n-\tint prime_len = ec_grp[ec->curveid].prime.length;\n-\n-\tif (ecdsa->op_type == RTE_CRYPTO_ASYM_OP_VERIFY)\n-\t\treturn;\n-\n-\t/* Separate out sign r and s components */\n-\tmemcpy(ecdsa->r.data, req->rptr, prime_len);\n-\tmemcpy(ecdsa->s.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),\n-\t prime_len);\n-\tecdsa->r.length = prime_len;\n-\tecdsa->s.length = prime_len;\n-}\n-\n-static __rte_always_inline void\n-otx2_cpt_asym_dequeue_ecpm_op(struct rte_crypto_ecpm_op_param *ecpm,\n-\t\t\t struct cpt_request_info *req,\n-\t\t\t struct cpt_asym_ec_ctx *ec)\n-{\n-\tint prime_len = ec_grp[ec->curveid].prime.length;\n-\n-\tmemcpy(ecpm->r.x.data, req->rptr, prime_len);\n-\tmemcpy(ecpm->r.y.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),\n-\t prime_len);\n-\tecpm->r.x.length = prime_len;\n-\tecpm->r.y.length = prime_len;\n-}\n-\n-static void\n-otx2_cpt_asym_post_process(struct rte_crypto_op *cop,\n-\t\t\t struct cpt_request_info *req)\n-{\n-\tstruct rte_crypto_asym_op *op = cop->asym;\n-\tstruct cpt_asym_sess_misc *sess;\n-\n-\tsess = get_asym_session_private_data(op->session,\n-\t\t\t\t\t otx2_cryptodev_driver_id);\n-\n-\tswitch (sess->xfrm_type) {\n-\tcase RTE_CRYPTO_ASYM_XFORM_RSA:\n-\t\totx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);\n-\t\tbreak;\n-\tcase RTE_CRYPTO_ASYM_XFORM_MODEX:\n-\t\top->modex.result.length = sess->mod_ctx.modulus.length;\n-\t\tmemcpy(op->modex.result.data, req->rptr,\n-\t\t op->modex.result.length);\n-\t\tbreak;\n-\tcase RTE_CRYPTO_ASYM_XFORM_ECDSA:\n-\t\totx2_cpt_asym_dequeue_ecdsa_op(&op->ecdsa, req, &sess->ec_ctx);\n-\t\tbreak;\n-\tcase RTE_CRYPTO_ASYM_XFORM_ECPM:\n-\t\totx2_cpt_asym_dequeue_ecpm_op(&op->ecpm, req, &sess->ec_ctx);\n-\t\tbreak;\n-\tdefault:\n-\t\tCPT_LOG_DP_DEBUG(\"Invalid crypto xform type\");\n-\t\tcop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n-\t\tbreak;\n-\t}\n-}\n-\n-static void\n-otx2_cpt_sec_post_process(struct rte_crypto_op *cop, uintptr_t *rsp)\n-{\n-\tstruct cpt_request_info *req = (struct cpt_request_info *)rsp[2];\n-\tvq_cmd_word0_t *word0 = (vq_cmd_word0_t *)&req->ist.ei0;\n-\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n-\tstruct rte_mbuf *m = sym_op->m_src;\n-\tstruct rte_ipv6_hdr *ip6;\n-\tstruct rte_ipv4_hdr *ip;\n-\tuint16_t m_len = 0;\n-\tint mdata_len;\n-\tchar *data;\n-\n-\tmdata_len = (int)rsp[3];\n-\trte_pktmbuf_trim(m, mdata_len);\n-\n-\tif (word0->s.opcode.major == OTX2_IPSEC_PO_PROCESS_IPSEC_INB) {\n-\t\tdata = rte_pktmbuf_mtod(m, char *);\n-\t\tip = (struct rte_ipv4_hdr *)(data +\n-\t\t\tOTX2_IPSEC_PO_INB_RPTR_HDR);\n-\n-\t\tif ((ip->version_ihl >> 4) == 4) {\n-\t\t\tm_len = rte_be_to_cpu_16(ip->total_length);\n-\t\t} else {\n-\t\t\tip6 = (struct rte_ipv6_hdr *)(data +\n-\t\t\t\tOTX2_IPSEC_PO_INB_RPTR_HDR);\n-\t\t\tm_len = rte_be_to_cpu_16(ip6->payload_len) +\n-\t\t\t\tsizeof(struct rte_ipv6_hdr);\n-\t\t}\n-\n-\t\tm->data_len = m_len;\n-\t\tm->pkt_len = m_len;\n-\t\tm->data_off += OTX2_IPSEC_PO_INB_RPTR_HDR;\n-\t}\n-}\n-\n-static inline void\n-otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,\n-\t\t\t uintptr_t *rsp, uint8_t cc)\n-{\n-\tunsigned int sz;\n-\n-\tif (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n-\t\tif (cop->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {\n-\t\t\tif (likely(cc == OTX2_IPSEC_PO_CC_SUCCESS)) {\n-\t\t\t\totx2_cpt_sec_post_process(cop, rsp);\n-\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n-\t\t\t} else\n-\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n-\n-\t\t\treturn;\n-\t\t}\n-\n-\t\tif (likely(cc == NO_ERR)) {\n-\t\t\t/* Verify authentication data if required */\n-\t\t\tif (unlikely(rsp[2]))\n-\t\t\t\tcompl_auth_verify(cop, (uint8_t *)rsp[2],\n-\t\t\t\t\t\t rsp[3]);\n-\t\t\telse\n-\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n-\t\t} else {\n-\t\t\tif (cc == ERR_GC_ICV_MISCOMPARE)\n-\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n-\t\t\telse\n-\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n-\t\t}\n-\n-\t\tif (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {\n-\t\t\tsym_session_clear(otx2_cryptodev_driver_id,\n-\t\t\t\t\t cop->sym->session);\n-\t\t\tsz = rte_cryptodev_sym_get_existing_header_session_size(\n-\t\t\t\t\tcop->sym->session);\n-\t\t\tmemset(cop->sym->session, 0, sz);\n-\t\t\trte_mempool_put(qp->sess_mp, cop->sym->session);\n-\t\t\tcop->sym->session = NULL;\n-\t\t}\n-\t}\n-\n-\tif (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {\n-\t\tif (likely(cc == NO_ERR)) {\n-\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n-\t\t\t/*\n-\t\t\t * Pass cpt_req_info stored in metabuf during\n-\t\t\t * enqueue.\n-\t\t\t */\n-\t\t\trsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));\n-\t\t\totx2_cpt_asym_post_process(cop,\n-\t\t\t\t\t(struct cpt_request_info *)rsp);\n-\t\t} else\n-\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n-\t}\n-}\n-\n-static uint16_t\n-otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n-{\n-\tint i, nb_pending, nb_completed;\n-\tstruct otx2_cpt_qp *qp = qptr;\n-\tstruct pending_queue *pend_q;\n-\tstruct cpt_request_info *req;\n-\tstruct rte_crypto_op *cop;\n-\tuint8_t cc[nb_ops];\n-\tuintptr_t *rsp;\n-\tvoid *metabuf;\n-\n-\tpend_q = &qp->pend_q;\n-\n-\tnb_pending = pending_queue_level(pend_q, OTX2_CPT_DEFAULT_CMD_QLEN);\n-\n-\t/* Ensure pcount isn't read before data lands */\n-\trte_atomic_thread_fence(__ATOMIC_ACQUIRE);\n-\n-\tnb_ops = RTE_MIN(nb_ops, nb_pending);\n-\n-\tfor (i = 0; i < nb_ops; i++) {\n-\t\tpending_queue_peek(pend_q, (void **)&req,\n-\t\t\tOTX2_CPT_DEFAULT_CMD_QLEN, 0);\n-\n-\t\tcc[i] = otx2_cpt_compcode_get(req);\n-\n-\t\tif (unlikely(cc[i] == ERR_REQ_PENDING))\n-\t\t\tbreak;\n-\n-\t\tops[i] = req->op;\n-\n-\t\tpending_queue_pop(pend_q, OTX2_CPT_DEFAULT_CMD_QLEN);\n-\t}\n-\n-\tnb_completed = i;\n-\n-\tfor (i = 0; i < nb_completed; i++) {\n-\t\trsp = (void *)ops[i];\n-\n-\t\tmetabuf = (void *)rsp[0];\n-\t\tcop = (void *)rsp[1];\n-\n-\t\tops[i] = cop;\n-\n-\t\totx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);\n-\n-\t\tfree_op_meta(metabuf, qp->meta_info.pool);\n-\t}\n-\n-\treturn nb_completed;\n-}\n-\n-void\n-otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)\n-{\n-\tdev->enqueue_burst = otx2_cpt_enqueue_burst;\n-\tdev->dequeue_burst = otx2_cpt_dequeue_burst;\n-\n-\trte_mb();\n-}\n-\n-/* PMD ops */\n-\n-static int\n-otx2_cpt_dev_config(struct rte_cryptodev *dev,\n-\t\t struct rte_cryptodev_config *conf)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tint ret;\n-\n-\tif (conf->nb_queue_pairs > vf->max_queues) {\n-\t\tCPT_LOG_ERR(\"Invalid number of queue pairs requested\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tdev->feature_flags = otx2_cpt_default_ff_get() & ~conf->ff_disable;\n-\n-\tif (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {\n-\t\t/* Initialize shared FPM table */\n-\t\tret = cpt_fpm_init(otx2_fpm_iova);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t}\n-\n-\t/* Unregister error interrupts */\n-\tif (vf->err_intr_registered)\n-\t\totx2_cpt_err_intr_unregister(dev);\n-\n-\t/* Detach queues */\n-\tif (vf->nb_queues) {\n-\t\tret = otx2_cpt_queues_detach(dev);\n-\t\tif (ret) {\n-\t\t\tCPT_LOG_ERR(\"Could not detach CPT queues\");\n-\t\t\treturn ret;\n-\t\t}\n-\t}\n-\n-\t/* Attach queues */\n-\tret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);\n-\tif (ret) {\n-\t\tCPT_LOG_ERR(\"Could not attach CPT queues\");\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tret = otx2_cpt_msix_offsets_get(dev);\n-\tif (ret) {\n-\t\tCPT_LOG_ERR(\"Could not get MSI-X offsets\");\n-\t\tgoto queues_detach;\n-\t}\n-\n-\t/* Register error interrupts */\n-\tret = otx2_cpt_err_intr_register(dev);\n-\tif (ret) {\n-\t\tCPT_LOG_ERR(\"Could not register error interrupts\");\n-\t\tgoto queues_detach;\n-\t}\n-\n-\tret = otx2_cpt_inline_init(dev);\n-\tif (ret) {\n-\t\tCPT_LOG_ERR(\"Could not enable inline IPsec\");\n-\t\tgoto intr_unregister;\n-\t}\n-\n-\totx2_cpt_set_enqdeq_fns(dev);\n-\n-\treturn 0;\n-\n-intr_unregister:\n-\totx2_cpt_err_intr_unregister(dev);\n-queues_detach:\n-\totx2_cpt_queues_detach(dev);\n-\treturn ret;\n-}\n-\n-static int\n-otx2_cpt_dev_start(struct rte_cryptodev *dev)\n-{\n-\tRTE_SET_USED(dev);\n-\n-\tCPT_PMD_INIT_FUNC_TRACE();\n-\n-\treturn 0;\n-}\n-\n-static void\n-otx2_cpt_dev_stop(struct rte_cryptodev *dev)\n-{\n-\tCPT_PMD_INIT_FUNC_TRACE();\n-\n-\tif (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)\n-\t\tcpt_fpm_clear();\n-}\n-\n-static int\n-otx2_cpt_dev_close(struct rte_cryptodev *dev)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\tint i, ret = 0;\n-\n-\tfor (i = 0; i < dev->data->nb_queue_pairs; i++) {\n-\t\tret = otx2_cpt_queue_pair_release(dev, i);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t}\n-\n-\t/* Unregister error interrupts */\n-\tif (vf->err_intr_registered)\n-\t\totx2_cpt_err_intr_unregister(dev);\n-\n-\t/* Detach queues */\n-\tif (vf->nb_queues) {\n-\t\tret = otx2_cpt_queues_detach(dev);\n-\t\tif (ret)\n-\t\t\tCPT_LOG_ERR(\"Could not detach CPT queues\");\n-\t}\n-\n-\treturn ret;\n-}\n-\n-static void\n-otx2_cpt_dev_info_get(struct rte_cryptodev *dev,\n-\t\t struct rte_cryptodev_info *info)\n-{\n-\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n-\n-\tif (info != NULL) {\n-\t\tinfo->max_nb_queue_pairs = vf->max_queues;\n-\t\tinfo->feature_flags = otx2_cpt_default_ff_get();\n-\t\tinfo->capabilities = otx2_cpt_capabilities_get();\n-\t\tinfo->sym.max_nb_sessions = 0;\n-\t\tinfo->driver_id = otx2_cryptodev_driver_id;\n-\t\tinfo->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;\n-\t\tinfo->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;\n-\t}\n-}\n-\n-static int\n-otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n-\t\t\t const struct rte_cryptodev_qp_conf *conf,\n-\t\t\t int socket_id __rte_unused)\n-{\n-\tuint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;\n-\tstruct rte_pci_device *pci_dev;\n-\tstruct otx2_cpt_qp *qp;\n-\n-\tCPT_PMD_INIT_FUNC_TRACE();\n-\n-\tif (dev->data->queue_pairs[qp_id] != NULL)\n-\t\totx2_cpt_queue_pair_release(dev, qp_id);\n-\n-\tif (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {\n-\t\tCPT_LOG_ERR(\"Could not setup queue pair for %u descriptors\",\n-\t\t\t conf->nb_descriptors);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tpci_dev = RTE_DEV_TO_PCI(dev->device);\n-\n-\tif (pci_dev->mem_resource[2].addr == NULL) {\n-\t\tCPT_LOG_ERR(\"Invalid PCI mem address\");\n-\t\treturn -EIO;\n-\t}\n-\n-\tqp = otx2_cpt_qp_create(dev, qp_id, grp_mask);\n-\tif (qp == NULL) {\n-\t\tCPT_LOG_ERR(\"Could not create queue pair %d\", qp_id);\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tqp->sess_mp = conf->mp_session;\n-\tqp->sess_mp_priv = conf->mp_session_private;\n-\tdev->data->queue_pairs[qp_id] = qp;\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)\n-{\n-\tstruct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];\n-\tint ret;\n-\n-\tCPT_PMD_INIT_FUNC_TRACE();\n-\n-\tif (qp == NULL)\n-\t\treturn -EINVAL;\n-\n-\tCPT_LOG_INFO(\"Releasing queue pair %d\", qp_id);\n-\n-\tret = otx2_cpt_qp_destroy(dev, qp);\n-\tif (ret) {\n-\t\tCPT_LOG_ERR(\"Could not destroy queue pair %d\", qp_id);\n-\t\treturn ret;\n-\t}\n-\n-\tdev->data->queue_pairs[qp_id] = NULL;\n-\n-\treturn 0;\n-}\n-\n-static unsigned int\n-otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)\n-{\n-\treturn cpt_get_session_size();\n-}\n-\n-static int\n-otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,\n-\t\t\t struct rte_crypto_sym_xform *xform,\n-\t\t\t struct rte_cryptodev_sym_session *sess,\n-\t\t\t struct rte_mempool *pool)\n-{\n-\tCPT_PMD_INIT_FUNC_TRACE();\n-\n-\treturn sym_session_configure(dev->driver_id, xform, sess, pool);\n-}\n-\n-static void\n-otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,\n-\t\t\t struct rte_cryptodev_sym_session *sess)\n-{\n-\tCPT_PMD_INIT_FUNC_TRACE();\n-\n-\treturn sym_session_clear(dev->driver_id, sess);\n-}\n-\n-static unsigned int\n-otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)\n-{\n-\treturn sizeof(struct cpt_asym_sess_misc);\n-}\n-\n-static int\n-otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,\n-\t\t\t struct rte_crypto_asym_xform *xform,\n-\t\t\t struct rte_cryptodev_asym_session *sess,\n-\t\t\t struct rte_mempool *pool)\n-{\n-\tstruct cpt_asym_sess_misc *priv;\n-\tvq_cmd_word3_t vq_cmd_w3;\n-\tint ret;\n-\n-\tCPT_PMD_INIT_FUNC_TRACE();\n-\n-\tif (rte_mempool_get(pool, (void **)&priv)) {\n-\t\tCPT_LOG_ERR(\"Could not allocate session_private_data\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tmemset(priv, 0, sizeof(struct cpt_asym_sess_misc));\n-\n-\tret = cpt_fill_asym_session_parameters(priv, xform);\n-\tif (ret) {\n-\t\tCPT_LOG_ERR(\"Could not configure session parameters\");\n-\n-\t\t/* Return session to mempool */\n-\t\trte_mempool_put(pool, priv);\n-\t\treturn ret;\n-\t}\n-\n-\tvq_cmd_w3.u64 = 0;\n-\tvq_cmd_w3.s.grp = OTX2_CPT_EGRP_AE;\n-\tpriv->cpt_inst_w7 = vq_cmd_w3.u64;\n-\n-\tset_asym_session_private_data(sess, dev->driver_id, priv);\n-\n-\treturn 0;\n-}\n-\n-static void\n-otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,\n-\t\t\t struct rte_cryptodev_asym_session *sess)\n-{\n-\tstruct cpt_asym_sess_misc *priv;\n-\tstruct rte_mempool *sess_mp;\n-\n-\tCPT_PMD_INIT_FUNC_TRACE();\n-\n-\tpriv = get_asym_session_private_data(sess, dev->driver_id);\n-\tif (priv == NULL)\n-\t\treturn;\n-\n-\t/* Free resources allocated in session_cfg */\n-\tcpt_free_asym_session_parameters(priv);\n-\n-\t/* Reset and free object back to pool */\n-\tmemset(priv, 0, otx2_cpt_asym_session_size_get(dev));\n-\tsess_mp = rte_mempool_from_obj(priv);\n-\tset_asym_session_private_data(sess, dev->driver_id, NULL);\n-\trte_mempool_put(sess_mp, priv);\n-}\n-\n-struct rte_cryptodev_ops otx2_cpt_ops = {\n-\t/* Device control ops */\n-\t.dev_configure = otx2_cpt_dev_config,\n-\t.dev_start = otx2_cpt_dev_start,\n-\t.dev_stop = otx2_cpt_dev_stop,\n-\t.dev_close = otx2_cpt_dev_close,\n-\t.dev_infos_get = otx2_cpt_dev_info_get,\n-\n-\t.stats_get = NULL,\n-\t.stats_reset = NULL,\n-\t.queue_pair_setup = otx2_cpt_queue_pair_setup,\n-\t.queue_pair_release = otx2_cpt_queue_pair_release,\n-\n-\t/* Symmetric crypto ops */\n-\t.sym_session_get_size = otx2_cpt_sym_session_get_size,\n-\t.sym_session_configure = otx2_cpt_sym_session_configure,\n-\t.sym_session_clear = otx2_cpt_sym_session_clear,\n-\n-\t/* Asymmetric crypto ops */\n-\t.asym_session_get_size = otx2_cpt_asym_session_size_get,\n-\t.asym_session_configure = otx2_cpt_asym_session_cfg,\n-\t.asym_session_clear = otx2_cpt_asym_session_clear,\n-\n-};\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h\ndeleted file mode 100644\nindex 7faf7ad034..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h\n+++ /dev/null\n@@ -1,15 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_CRYPTODEV_OPS_H_\n-#define _OTX2_CRYPTODEV_OPS_H_\n-\n-#include <cryptodev_pmd.h>\n-\n-#define OTX2_CPT_MIN_HEADROOM_REQ\t48\n-#define OTX2_CPT_MIN_TAILROOM_REQ\t208\n-\n-extern struct rte_cryptodev_ops otx2_cpt_ops;\n-\n-#endif /* _OTX2_CRYPTODEV_OPS_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops_helper.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops_helper.h\ndeleted file mode 100644\nindex 01c081a216..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops_helper.h\n+++ /dev/null\n@@ -1,82 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_CRYPTODEV_OPS_HELPER_H_\n-#define _OTX2_CRYPTODEV_OPS_HELPER_H_\n-\n-#include \"cpt_pmd_logs.h\"\n-\n-static void\n-sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess)\n-{\n-\tvoid *priv = get_sym_session_private_data(sess, driver_id);\n-\tstruct cpt_sess_misc *misc;\n-\tstruct rte_mempool *pool;\n-\tstruct cpt_ctx *ctx;\n-\n-\tif (priv == NULL)\n-\t\treturn;\n-\n-\tmisc = priv;\n-\tctx = SESS_PRIV(misc);\n-\n-\tif (ctx->auth_key != NULL)\n-\t\trte_free(ctx->auth_key);\n-\n-\tmemset(priv, 0, cpt_get_session_size());\n-\n-\tpool = rte_mempool_from_obj(priv);\n-\n-\tset_sym_session_private_data(sess, driver_id, NULL);\n-\n-\trte_mempool_put(pool, priv);\n-}\n-\n-static __rte_always_inline uint8_t\n-otx2_cpt_compcode_get(struct cpt_request_info *req)\n-{\n-\tvolatile struct cpt_res_s_9s *res;\n-\tuint8_t ret;\n-\n-\tres = (volatile struct cpt_res_s_9s *)req->completion_addr;\n-\n-\tif (unlikely(res->compcode == CPT_9X_COMP_E_NOTDONE)) {\n-\t\tif (rte_get_timer_cycles() < req->time_out)\n-\t\t\treturn ERR_REQ_PENDING;\n-\n-\t\tCPT_LOG_DP_ERR(\"Request timed out\");\n-\t\treturn ERR_REQ_TIMEOUT;\n-\t}\n-\n-\tif (likely(res->compcode == CPT_9X_COMP_E_GOOD)) {\n-\t\tret = NO_ERR;\n-\t\tif (unlikely(res->uc_compcode)) {\n-\t\t\tret = res->uc_compcode;\n-\t\t\tCPT_LOG_DP_DEBUG(\"Request failed with microcode error\");\n-\t\t\tCPT_LOG_DP_DEBUG(\"MC completion code 0x%x\",\n-\t\t\t\t\t res->uc_compcode);\n-\t\t}\n-\t} else {\n-\t\tCPT_LOG_DP_DEBUG(\"HW completion code 0x%x\", res->compcode);\n-\n-\t\tret = res->compcode;\n-\t\tswitch (res->compcode) {\n-\t\tcase CPT_9X_COMP_E_INSTERR:\n-\t\t\tCPT_LOG_DP_ERR(\"Request failed with instruction error\");\n-\t\t\tbreak;\n-\t\tcase CPT_9X_COMP_E_FAULT:\n-\t\t\tCPT_LOG_DP_ERR(\"Request failed with DMA fault\");\n-\t\t\tbreak;\n-\t\tcase CPT_9X_COMP_E_HWERR:\n-\t\t\tCPT_LOG_DP_ERR(\"Request failed with hardware error\");\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tCPT_LOG_DP_ERR(\"Request failed with unknown completion code\");\n-\t\t}\n-\t}\n-\n-\treturn ret;\n-}\n-\n-#endif /* _OTX2_CRYPTODEV_OPS_HELPER_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h b/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\ndeleted file mode 100644\nindex 95bce3621a..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_qp.h\n+++ /dev/null\n@@ -1,46 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020-2021 Marvell.\n- */\n-\n-#ifndef _OTX2_CRYPTODEV_QP_H_\n-#define _OTX2_CRYPTODEV_QP_H_\n-\n-#include <rte_common.h>\n-#include <rte_eventdev.h>\n-#include <rte_mempool.h>\n-#include <rte_spinlock.h>\n-\n-#include \"cpt_common.h\"\n-\n-struct otx2_cpt_qp {\n-\tuint32_t id;\n-\t/**< Queue pair id */\n-\tuint8_t blkaddr;\n-\t/**< CPT0/1 BLKADDR of LF */\n-\tuintptr_t base;\n-\t/**< Base address where BAR is mapped */\n-\tvoid *lmtline;\n-\t/**< Address of LMTLINE */\n-\trte_iova_t lf_nq_reg;\n-\t/**< LF enqueue register address */\n-\tstruct pending_queue pend_q;\n-\t/**< Pending queue */\n-\tstruct rte_mempool *sess_mp;\n-\t/**< Session mempool */\n-\tstruct rte_mempool *sess_mp_priv;\n-\t/**< Session private data mempool */\n-\tstruct cpt_qp_meta_info meta_info;\n-\t/**< Metabuf info required to support operations on the queue pair */\n-\trte_iova_t iq_dma_addr;\n-\t/**< Instruction queue address */\n-\tstruct rte_event ev;\n-\t/**< Event information required for binding cryptodev queue to\n-\t * eventdev queue. Used by crypto adapter.\n-\t */\n-\tuint8_t ca_enable;\n-\t/**< Set when queue pair is added to crypto adapter */\n-\tuint8_t qp_ev_bind;\n-\t/**< Set when queue pair is bound to event queue */\n-};\n-\n-#endif /* _OTX2_CRYPTODEV_QP_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_sec.c b/drivers/crypto/octeontx2/otx2_cryptodev_sec.c\ndeleted file mode 100644\nindex 9a4f84f8d8..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_sec.c\n+++ /dev/null\n@@ -1,655 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#include <rte_cryptodev.h>\n-#include <rte_esp.h>\n-#include <rte_ethdev.h>\n-#include <rte_ip.h>\n-#include <rte_malloc.h>\n-#include <rte_security.h>\n-#include <rte_security_driver.h>\n-#include <rte_udp.h>\n-\n-#include \"otx2_cryptodev.h\"\n-#include \"otx2_cryptodev_capabilities.h\"\n-#include \"otx2_cryptodev_hw_access.h\"\n-#include \"otx2_cryptodev_ops.h\"\n-#include \"otx2_cryptodev_sec.h\"\n-#include \"otx2_security.h\"\n-\n-static int\n-ipsec_lp_len_precalc(struct rte_security_ipsec_xform *ipsec,\n-\t\tstruct rte_crypto_sym_xform *xform,\n-\t\tstruct otx2_sec_session_ipsec_lp *lp)\n-{\n-\tstruct rte_crypto_sym_xform *cipher_xform, *auth_xform;\n-\n-\tlp->partial_len = 0;\n-\tif (ipsec->mode == RTE_SECURITY_IPSEC_SA_MODE_TUNNEL) {\n-\t\tif (ipsec->tunnel.type == RTE_SECURITY_IPSEC_TUNNEL_IPV4)\n-\t\t\tlp->partial_len = sizeof(struct rte_ipv4_hdr);\n-\t\telse if (ipsec->tunnel.type == RTE_SECURITY_IPSEC_TUNNEL_IPV6)\n-\t\t\tlp->partial_len = sizeof(struct rte_ipv6_hdr);\n-\t\telse\n-\t\t\treturn -EINVAL;\n-\t}\n-\n-\tif (ipsec->proto == RTE_SECURITY_IPSEC_SA_PROTO_ESP) {\n-\t\tlp->partial_len += sizeof(struct rte_esp_hdr);\n-\t\tlp->roundup_len = sizeof(struct rte_esp_tail);\n-\t} else if (ipsec->proto == RTE_SECURITY_IPSEC_SA_PROTO_AH) {\n-\t\tlp->partial_len += OTX2_SEC_AH_HDR_LEN;\n-\t} else {\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (ipsec->options.udp_encap)\n-\t\tlp->partial_len += sizeof(struct rte_udp_hdr);\n-\n-\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\tif (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM) {\n-\t\t\tlp->partial_len += OTX2_SEC_AES_GCM_IV_LEN;\n-\t\t\tlp->partial_len += OTX2_SEC_AES_GCM_MAC_LEN;\n-\t\t\tlp->roundup_byte = OTX2_SEC_AES_GCM_ROUNDUP_BYTE_LEN;\n-\t\t\treturn 0;\n-\t\t} else {\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\tif (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS) {\n-\t\tcipher_xform = xform;\n-\t\tauth_xform = xform->next;\n-\t} else if (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS) {\n-\t\tauth_xform = xform;\n-\t\tcipher_xform = xform->next;\n-\t} else {\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (cipher_xform->cipher.algo == RTE_CRYPTO_CIPHER_AES_CBC) {\n-\t\tlp->partial_len += OTX2_SEC_AES_CBC_IV_LEN;\n-\t\tlp->roundup_byte = OTX2_SEC_AES_CBC_ROUNDUP_BYTE_LEN;\n-\t} else {\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (auth_xform->auth.algo == RTE_CRYPTO_AUTH_SHA1_HMAC)\n-\t\tlp->partial_len += OTX2_SEC_SHA1_HMAC_LEN;\n-\telse if (auth_xform->auth.algo == RTE_CRYPTO_AUTH_SHA256_HMAC)\n-\t\tlp->partial_len += OTX2_SEC_SHA2_HMAC_LEN;\n-\telse\n-\t\treturn -EINVAL;\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_cpt_enq_sa_write(struct otx2_sec_session_ipsec_lp *lp,\n-\t\t struct otx2_cpt_qp *qptr, uint8_t opcode)\n-{\n-\tuint64_t lmt_status, time_out;\n-\tvoid *lmtline = qptr->lmtline;\n-\tstruct otx2_cpt_inst_s inst;\n-\tstruct otx2_cpt_res *res;\n-\tuint64_t *mdata;\n-\tint ret = 0;\n-\n-\tif (unlikely(rte_mempool_get(qptr->meta_info.pool,\n-\t\t\t\t (void **)&mdata) < 0))\n-\t\treturn -ENOMEM;\n-\n-\tres = (struct otx2_cpt_res *)RTE_PTR_ALIGN(mdata, 16);\n-\tres->compcode = CPT_9X_COMP_E_NOTDONE;\n-\n-\tinst.opcode = opcode | (lp->ctx_len << 8);\n-\tinst.param1 = 0;\n-\tinst.param2 = 0;\n-\tinst.dlen = lp->ctx_len << 3;\n-\tinst.dptr = rte_mempool_virt2iova(lp);\n-\tinst.rptr = 0;\n-\tinst.cptr = rte_mempool_virt2iova(lp);\n-\tinst.egrp = OTX2_CPT_EGRP_SE;\n-\n-\tinst.u64[0] = 0;\n-\tinst.u64[2] = 0;\n-\tinst.u64[3] = 0;\n-\tinst.res_addr = rte_mempool_virt2iova(res);\n-\n-\trte_io_wmb();\n-\n-\tdo {\n-\t\t/* Copy CPT command to LMTLINE */\n-\t\totx2_lmt_mov(lmtline, &inst, 2);\n-\t\tlmt_status = otx2_lmt_submit(qptr->lf_nq_reg);\n-\t} while (lmt_status == 0);\n-\n-\ttime_out = rte_get_timer_cycles() +\n-\t\t\tDEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();\n-\n-\twhile (res->compcode == CPT_9X_COMP_E_NOTDONE) {\n-\t\tif (rte_get_timer_cycles() > time_out) {\n-\t\t\trte_mempool_put(qptr->meta_info.pool, mdata);\n-\t\t\totx2_err(\"Request timed out\");\n-\t\t\treturn -ETIMEDOUT;\n-\t\t}\n-\t rte_io_rmb();\n-\t}\n-\n-\tif (unlikely(res->compcode != CPT_9X_COMP_E_GOOD)) {\n-\t\tret = res->compcode;\n-\t\tswitch (ret) {\n-\t\tcase CPT_9X_COMP_E_INSTERR:\n-\t\t\totx2_err(\"Request failed with instruction error\");\n-\t\t\tbreak;\n-\t\tcase CPT_9X_COMP_E_FAULT:\n-\t\t\totx2_err(\"Request failed with DMA fault\");\n-\t\t\tbreak;\n-\t\tcase CPT_9X_COMP_E_HWERR:\n-\t\t\totx2_err(\"Request failed with hardware error\");\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\totx2_err(\"Request failed with unknown hardware \"\n-\t\t\t\t \"completion code : 0x%x\", ret);\n-\t\t}\n-\t\tgoto mempool_put;\n-\t}\n-\n-\tif (unlikely(res->uc_compcode != OTX2_IPSEC_PO_CC_SUCCESS)) {\n-\t\tret = res->uc_compcode;\n-\t\tswitch (ret) {\n-\t\tcase OTX2_IPSEC_PO_CC_AUTH_UNSUPPORTED:\n-\t\t\totx2_err(\"Invalid auth type\");\n-\t\t\tbreak;\n-\t\tcase OTX2_IPSEC_PO_CC_ENCRYPT_UNSUPPORTED:\n-\t\t\totx2_err(\"Invalid encrypt type\");\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\totx2_err(\"Request failed with unknown microcode \"\n-\t\t\t\t \"completion code : 0x%x\", ret);\n-\t\t}\n-\t}\n-\n-mempool_put:\n-\trte_mempool_put(qptr->meta_info.pool, mdata);\n-\treturn ret;\n-}\n-\n-static void\n-set_session_misc_attributes(struct otx2_sec_session_ipsec_lp *sess,\n-\t\t\t struct rte_crypto_sym_xform *crypto_xform,\n-\t\t\t struct rte_crypto_sym_xform *auth_xform,\n-\t\t\t struct rte_crypto_sym_xform *cipher_xform)\n-{\n-\tif (crypto_xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\tsess->iv_offset = crypto_xform->aead.iv.offset;\n-\t\tsess->iv_length = crypto_xform->aead.iv.length;\n-\t\tsess->aad_length = crypto_xform->aead.aad_length;\n-\t\tsess->mac_len = crypto_xform->aead.digest_length;\n-\t} else {\n-\t\tsess->iv_offset = cipher_xform->cipher.iv.offset;\n-\t\tsess->iv_length = cipher_xform->cipher.iv.length;\n-\t\tsess->auth_iv_offset = auth_xform->auth.iv.offset;\n-\t\tsess->auth_iv_length = auth_xform->auth.iv.length;\n-\t\tsess->mac_len = auth_xform->auth.digest_length;\n-\t}\n-}\n-\n-static int\n-crypto_sec_ipsec_outb_session_create(struct rte_cryptodev *crypto_dev,\n-\t\t\t\t struct rte_security_ipsec_xform *ipsec,\n-\t\t\t\t struct rte_crypto_sym_xform *crypto_xform,\n-\t\t\t\t struct rte_security_session *sec_sess)\n-{\n-\tstruct rte_crypto_sym_xform *auth_xform, *cipher_xform;\n-\tstruct otx2_ipsec_po_ip_template *template = NULL;\n-\tconst uint8_t *cipher_key, *auth_key;\n-\tstruct otx2_sec_session_ipsec_lp *lp;\n-\tstruct otx2_ipsec_po_sa_ctl *ctl;\n-\tint cipher_key_len, auth_key_len;\n-\tstruct otx2_ipsec_po_out_sa *sa;\n-\tstruct otx2_sec_session *sess;\n-\tstruct otx2_cpt_inst_s inst;\n-\tstruct rte_ipv6_hdr *ip6;\n-\tstruct rte_ipv4_hdr *ip;\n-\tint ret, ctx_len;\n-\n-\tsess = get_sec_session_private_data(sec_sess);\n-\tsess->ipsec.dir = RTE_SECURITY_IPSEC_SA_DIR_EGRESS;\n-\tlp = &sess->ipsec.lp;\n-\n-\tsa = &lp->out_sa;\n-\tctl = &sa->ctl;\n-\tif (ctl->valid) {\n-\t\totx2_err(\"SA already registered\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tmemset(sa, 0, sizeof(struct otx2_ipsec_po_out_sa));\n-\n-\t/* Initialize lookaside ipsec private data */\n-\tlp->ip_id = 0;\n-\tlp->seq_lo = 1;\n-\tlp->seq_hi = 0;\n-\n-\tret = ipsec_po_sa_ctl_set(ipsec, crypto_xform, ctl);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = ipsec_lp_len_precalc(ipsec, crypto_xform, lp);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\t/* Start ip id from 1 */\n-\tlp->ip_id = 1;\n-\n-\tif (ctl->enc_type == OTX2_IPSEC_PO_SA_ENC_AES_GCM) {\n-\t\ttemplate = &sa->aes_gcm.template;\n-\t\tctx_len = offsetof(struct otx2_ipsec_po_out_sa,\n-\t\t\t\taes_gcm.template) + sizeof(\n-\t\t\t\tsa->aes_gcm.template.ip4);\n-\t\tctx_len = RTE_ALIGN_CEIL(ctx_len, 8);\n-\t\tlp->ctx_len = ctx_len >> 3;\n-\t} else if (ctl->auth_type ==\n-\t\t\tOTX2_IPSEC_PO_SA_AUTH_SHA1) {\n-\t\ttemplate = &sa->sha1.template;\n-\t\tctx_len = offsetof(struct otx2_ipsec_po_out_sa,\n-\t\t\t\tsha1.template) + sizeof(\n-\t\t\t\tsa->sha1.template.ip4);\n-\t\tctx_len = RTE_ALIGN_CEIL(ctx_len, 8);\n-\t\tlp->ctx_len = ctx_len >> 3;\n-\t} else if (ctl->auth_type ==\n-\t\t\tOTX2_IPSEC_PO_SA_AUTH_SHA2_256) {\n-\t\ttemplate = &sa->sha2.template;\n-\t\tctx_len = offsetof(struct otx2_ipsec_po_out_sa,\n-\t\t\t\tsha2.template) + sizeof(\n-\t\t\t\tsa->sha2.template.ip4);\n-\t\tctx_len = RTE_ALIGN_CEIL(ctx_len, 8);\n-\t\tlp->ctx_len = ctx_len >> 3;\n-\t} else {\n-\t\treturn -EINVAL;\n-\t}\n-\tip = &template->ip4.ipv4_hdr;\n-\tif (ipsec->options.udp_encap) {\n-\t\tip->next_proto_id = IPPROTO_UDP;\n-\t\ttemplate->ip4.udp_src = rte_be_to_cpu_16(4500);\n-\t\ttemplate->ip4.udp_dst = rte_be_to_cpu_16(4500);\n-\t} else {\n-\t\tip->next_proto_id = IPPROTO_ESP;\n-\t}\n-\n-\tif (ipsec->mode == RTE_SECURITY_IPSEC_SA_MODE_TUNNEL) {\n-\t\tif (ipsec->tunnel.type == RTE_SECURITY_IPSEC_TUNNEL_IPV4) {\n-\t\t\tip->version_ihl = RTE_IPV4_VHL_DEF;\n-\t\t\tip->time_to_live = ipsec->tunnel.ipv4.ttl;\n-\t\t\tip->type_of_service |= (ipsec->tunnel.ipv4.dscp << 2);\n-\t\t\tif (ipsec->tunnel.ipv4.df)\n-\t\t\t\tip->fragment_offset = BIT(14);\n-\t\t\tmemcpy(&ip->src_addr, &ipsec->tunnel.ipv4.src_ip,\n-\t\t\t\tsizeof(struct in_addr));\n-\t\t\tmemcpy(&ip->dst_addr, &ipsec->tunnel.ipv4.dst_ip,\n-\t\t\t\tsizeof(struct in_addr));\n-\t\t} else if (ipsec->tunnel.type ==\n-\t\t\t\tRTE_SECURITY_IPSEC_TUNNEL_IPV6) {\n-\n-\t\t\tif (ctl->enc_type == OTX2_IPSEC_PO_SA_ENC_AES_GCM) {\n-\t\t\t\ttemplate = &sa->aes_gcm.template;\n-\t\t\t\tctx_len = offsetof(struct otx2_ipsec_po_out_sa,\n-\t\t\t\t\t\taes_gcm.template) + sizeof(\n-\t\t\t\t\t\tsa->aes_gcm.template.ip6);\n-\t\t\t\tctx_len = RTE_ALIGN_CEIL(ctx_len, 8);\n-\t\t\t\tlp->ctx_len = ctx_len >> 3;\n-\t\t\t} else if (ctl->auth_type ==\n-\t\t\t\t\tOTX2_IPSEC_PO_SA_AUTH_SHA1) {\n-\t\t\t\ttemplate = &sa->sha1.template;\n-\t\t\t\tctx_len = offsetof(struct otx2_ipsec_po_out_sa,\n-\t\t\t\t\t\tsha1.template) + sizeof(\n-\t\t\t\t\t\tsa->sha1.template.ip6);\n-\t\t\t\tctx_len = RTE_ALIGN_CEIL(ctx_len, 8);\n-\t\t\t\tlp->ctx_len = ctx_len >> 3;\n-\t\t\t} else if (ctl->auth_type ==\n-\t\t\t\t\tOTX2_IPSEC_PO_SA_AUTH_SHA2_256) {\n-\t\t\t\ttemplate = &sa->sha2.template;\n-\t\t\t\tctx_len = offsetof(struct otx2_ipsec_po_out_sa,\n-\t\t\t\t\t\tsha2.template) + sizeof(\n-\t\t\t\t\t\tsa->sha2.template.ip6);\n-\t\t\t\tctx_len = RTE_ALIGN_CEIL(ctx_len, 8);\n-\t\t\t\tlp->ctx_len = ctx_len >> 3;\n-\t\t\t} else {\n-\t\t\t\treturn -EINVAL;\n-\t\t\t}\n-\n-\t\t\tip6 = &template->ip6.ipv6_hdr;\n-\t\t\tif (ipsec->options.udp_encap) {\n-\t\t\t\tip6->proto = IPPROTO_UDP;\n-\t\t\t\ttemplate->ip6.udp_src = rte_be_to_cpu_16(4500);\n-\t\t\t\ttemplate->ip6.udp_dst = rte_be_to_cpu_16(4500);\n-\t\t\t} else {\n-\t\t\t\tip6->proto = (ipsec->proto ==\n-\t\t\t\t\tRTE_SECURITY_IPSEC_SA_PROTO_ESP) ?\n-\t\t\t\t\tIPPROTO_ESP : IPPROTO_AH;\n-\t\t\t}\n-\t\t\tip6->vtc_flow = rte_cpu_to_be_32(0x60000000 |\n-\t\t\t\t((ipsec->tunnel.ipv6.dscp <<\n-\t\t\t\t\tRTE_IPV6_HDR_TC_SHIFT) &\n-\t\t\t\t\tRTE_IPV6_HDR_TC_MASK) |\n-\t\t\t\t((ipsec->tunnel.ipv6.flabel <<\n-\t\t\t\t\tRTE_IPV6_HDR_FL_SHIFT) &\n-\t\t\t\t\tRTE_IPV6_HDR_FL_MASK));\n-\t\t\tip6->hop_limits = ipsec->tunnel.ipv6.hlimit;\n-\t\t\tmemcpy(&ip6->src_addr, &ipsec->tunnel.ipv6.src_addr,\n-\t\t\t\tsizeof(struct in6_addr));\n-\t\t\tmemcpy(&ip6->dst_addr, &ipsec->tunnel.ipv6.dst_addr,\n-\t\t\t\tsizeof(struct in6_addr));\n-\t\t}\n-\t}\n-\n-\tcipher_xform = crypto_xform;\n-\tauth_xform = crypto_xform->next;\n-\n-\tcipher_key_len = 0;\n-\tauth_key_len = 0;\n-\n-\tif (crypto_xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\tif (crypto_xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)\n-\t\t\tmemcpy(sa->iv.gcm.nonce, &ipsec->salt, 4);\n-\t\tcipher_key = crypto_xform->aead.key.data;\n-\t\tcipher_key_len = crypto_xform->aead.key.length;\n-\t} else {\n-\t\tcipher_key = cipher_xform->cipher.key.data;\n-\t\tcipher_key_len = cipher_xform->cipher.key.length;\n-\t\tauth_key = auth_xform->auth.key.data;\n-\t\tauth_key_len = auth_xform->auth.key.length;\n-\n-\t\tif (auth_xform->auth.algo == RTE_CRYPTO_AUTH_SHA1_HMAC)\n-\t\t\tmemcpy(sa->sha1.hmac_key, auth_key, auth_key_len);\n-\t\telse if (auth_xform->auth.algo == RTE_CRYPTO_AUTH_SHA256_HMAC)\n-\t\t\tmemcpy(sa->sha2.hmac_key, auth_key, auth_key_len);\n-\t}\n-\n-\tif (cipher_key_len != 0)\n-\t\tmemcpy(sa->cipher_key, cipher_key, cipher_key_len);\n-\telse\n-\t\treturn -EINVAL;\n-\n-\tinst.u64[7] = 0;\n-\tinst.egrp = OTX2_CPT_EGRP_SE;\n-\tinst.cptr = rte_mempool_virt2iova(sa);\n-\n-\tlp->cpt_inst_w7 = inst.u64[7];\n-\tlp->ucmd_opcode = (lp->ctx_len << 8) |\n-\t\t\t\t(OTX2_IPSEC_PO_PROCESS_IPSEC_OUTB);\n-\n-\t/* Set per packet IV and IKEv2 bits */\n-\tlp->ucmd_param1 = BIT(11) | BIT(9);\n-\tlp->ucmd_param2 = 0;\n-\n-\tset_session_misc_attributes(lp, crypto_xform,\n-\t\t\t\t auth_xform, cipher_xform);\n-\n-\treturn otx2_cpt_enq_sa_write(lp, crypto_dev->data->queue_pairs[0],\n-\t\t\t\t OTX2_IPSEC_PO_WRITE_IPSEC_OUTB);\n-}\n-\n-static int\n-crypto_sec_ipsec_inb_session_create(struct rte_cryptodev *crypto_dev,\n-\t\t\t\t struct rte_security_ipsec_xform *ipsec,\n-\t\t\t\t struct rte_crypto_sym_xform *crypto_xform,\n-\t\t\t\t struct rte_security_session *sec_sess)\n-{\n-\tstruct rte_crypto_sym_xform *auth_xform, *cipher_xform;\n-\tconst uint8_t *cipher_key, *auth_key;\n-\tstruct otx2_sec_session_ipsec_lp *lp;\n-\tstruct otx2_ipsec_po_sa_ctl *ctl;\n-\tint cipher_key_len, auth_key_len;\n-\tstruct otx2_ipsec_po_in_sa *sa;\n-\tstruct otx2_sec_session *sess;\n-\tstruct otx2_cpt_inst_s inst;\n-\tint ret;\n-\n-\tsess = get_sec_session_private_data(sec_sess);\n-\tsess->ipsec.dir = RTE_SECURITY_IPSEC_SA_DIR_INGRESS;\n-\tlp = &sess->ipsec.lp;\n-\n-\tsa = &lp->in_sa;\n-\tctl = &sa->ctl;\n-\n-\tif (ctl->valid) {\n-\t\totx2_err(\"SA already registered\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tmemset(sa, 0, sizeof(struct otx2_ipsec_po_in_sa));\n-\tsa->replay_win_sz = ipsec->replay_win_sz;\n-\n-\tret = ipsec_po_sa_ctl_set(ipsec, crypto_xform, ctl);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tauth_xform = crypto_xform;\n-\tcipher_xform = crypto_xform->next;\n-\n-\tcipher_key_len = 0;\n-\tauth_key_len = 0;\n-\n-\tif (crypto_xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\tif (crypto_xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)\n-\t\t\tmemcpy(sa->iv.gcm.nonce, &ipsec->salt, 4);\n-\t\tcipher_key = crypto_xform->aead.key.data;\n-\t\tcipher_key_len = crypto_xform->aead.key.length;\n-\n-\t\tlp->ctx_len = offsetof(struct otx2_ipsec_po_in_sa,\n-\t\t\t\t\t aes_gcm.hmac_key[0]) >> 3;\n-\t\tRTE_ASSERT(lp->ctx_len == OTX2_IPSEC_PO_AES_GCM_INB_CTX_LEN);\n-\t} else {\n-\t\tcipher_key = cipher_xform->cipher.key.data;\n-\t\tcipher_key_len = cipher_xform->cipher.key.length;\n-\t\tauth_key = auth_xform->auth.key.data;\n-\t\tauth_key_len = auth_xform->auth.key.length;\n-\n-\t\tif (auth_xform->auth.algo == RTE_CRYPTO_AUTH_SHA1_HMAC) {\n-\t\t\tmemcpy(sa->aes_gcm.hmac_key, auth_key, auth_key_len);\n-\t\t\tlp->ctx_len = offsetof(struct otx2_ipsec_po_in_sa,\n-\t\t\t\t\t\t aes_gcm.selector) >> 3;\n-\t\t} else if (auth_xform->auth.algo ==\n-\t\t\t\tRTE_CRYPTO_AUTH_SHA256_HMAC) {\n-\t\t\tmemcpy(sa->sha2.hmac_key, auth_key, auth_key_len);\n-\t\t\tlp->ctx_len = offsetof(struct otx2_ipsec_po_in_sa,\n-\t\t\t\t\t\t sha2.selector) >> 3;\n-\t\t}\n-\t}\n-\n-\tif (cipher_key_len != 0)\n-\t\tmemcpy(sa->cipher_key, cipher_key, cipher_key_len);\n-\telse\n-\t\treturn -EINVAL;\n-\n-\tinst.u64[7] = 0;\n-\tinst.egrp = OTX2_CPT_EGRP_SE;\n-\tinst.cptr = rte_mempool_virt2iova(sa);\n-\n-\tlp->cpt_inst_w7 = inst.u64[7];\n-\tlp->ucmd_opcode = (lp->ctx_len << 8) |\n-\t\t\t\t(OTX2_IPSEC_PO_PROCESS_IPSEC_INB);\n-\tlp->ucmd_param1 = 0;\n-\n-\t/* Set IKEv2 bit */\n-\tlp->ucmd_param2 = BIT(12);\n-\n-\tset_session_misc_attributes(lp, crypto_xform,\n-\t\t\t\t auth_xform, cipher_xform);\n-\n-\tif (sa->replay_win_sz) {\n-\t\tif (sa->replay_win_sz > OTX2_IPSEC_MAX_REPLAY_WIN_SZ) {\n-\t\t\totx2_err(\"Replay window size is not supported\");\n-\t\t\treturn -ENOTSUP;\n-\t\t}\n-\t\tsa->replay = rte_zmalloc(NULL, sizeof(struct otx2_ipsec_replay),\n-\t\t\t\t0);\n-\t\tif (sa->replay == NULL)\n-\t\t\treturn -ENOMEM;\n-\n-\t\t/* Set window bottom to 1, base and top to size of window */\n-\t\tsa->replay->winb = 1;\n-\t\tsa->replay->wint = sa->replay_win_sz;\n-\t\tsa->replay->base = sa->replay_win_sz;\n-\t\tsa->esn_low = 0;\n-\t\tsa->esn_hi = 0;\n-\t}\n-\n-\treturn otx2_cpt_enq_sa_write(lp, crypto_dev->data->queue_pairs[0],\n-\t\t\t\t OTX2_IPSEC_PO_WRITE_IPSEC_INB);\n-}\n-\n-static int\n-crypto_sec_ipsec_session_create(struct rte_cryptodev *crypto_dev,\n-\t\t\t\tstruct rte_security_ipsec_xform *ipsec,\n-\t\t\t\tstruct rte_crypto_sym_xform *crypto_xform,\n-\t\t\t\tstruct rte_security_session *sess)\n-{\n-\tint ret;\n-\n-\tif (crypto_dev->data->queue_pairs[0] == NULL) {\n-\t\totx2_err(\"Setup cpt queue pair before creating sec session\");\n-\t\treturn -EPERM;\n-\t}\n-\n-\tret = ipsec_po_xform_verify(ipsec, crypto_xform);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tif (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS)\n-\t\treturn crypto_sec_ipsec_inb_session_create(crypto_dev, ipsec,\n-\t\t\t\t\t\t\t crypto_xform, sess);\n-\telse\n-\t\treturn crypto_sec_ipsec_outb_session_create(crypto_dev, ipsec,\n-\t\t\t\t\t\t\t crypto_xform, sess);\n-}\n-\n-static int\n-otx2_crypto_sec_session_create(void *device,\n-\t\t\t struct rte_security_session_conf *conf,\n-\t\t\t struct rte_security_session *sess,\n-\t\t\t struct rte_mempool *mempool)\n-{\n-\tstruct otx2_sec_session *priv;\n-\tint ret;\n-\n-\tif (conf->action_type != RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL)\n-\t\treturn -ENOTSUP;\n-\n-\tif (rte_security_dynfield_register() < 0)\n-\t\treturn -rte_errno;\n-\n-\tif (rte_mempool_get(mempool, (void **)&priv)) {\n-\t\totx2_err(\"Could not allocate security session private data\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tset_sec_session_private_data(sess, priv);\n-\n-\tpriv->userdata = conf->userdata;\n-\n-\tif (conf->protocol == RTE_SECURITY_PROTOCOL_IPSEC)\n-\t\tret = crypto_sec_ipsec_session_create(device, &conf->ipsec,\n-\t\t\t\t\t\t conf->crypto_xform,\n-\t\t\t\t\t\t sess);\n-\telse\n-\t\tret = -ENOTSUP;\n-\n-\tif (ret)\n-\t\tgoto mempool_put;\n-\n-\treturn 0;\n-\n-mempool_put:\n-\trte_mempool_put(mempool, priv);\n-\tset_sec_session_private_data(sess, NULL);\n-\treturn ret;\n-}\n-\n-static int\n-otx2_crypto_sec_session_destroy(void *device __rte_unused,\n-\t\t\t\tstruct rte_security_session *sess)\n-{\n-\tstruct otx2_sec_session *priv;\n-\tstruct rte_mempool *sess_mp;\n-\n-\tpriv = get_sec_session_private_data(sess);\n-\n-\tif (priv == NULL)\n-\t\treturn 0;\n-\n-\tsess_mp = rte_mempool_from_obj(priv);\n-\n-\tmemset(priv, 0, sizeof(*priv));\n-\n-\tset_sec_session_private_data(sess, NULL);\n-\trte_mempool_put(sess_mp, priv);\n-\n-\treturn 0;\n-}\n-\n-static unsigned int\n-otx2_crypto_sec_session_get_size(void *device __rte_unused)\n-{\n-\treturn sizeof(struct otx2_sec_session);\n-}\n-\n-static int\n-otx2_crypto_sec_set_pkt_mdata(void *device __rte_unused,\n-\t\t\t struct rte_security_session *session,\n-\t\t\t struct rte_mbuf *m, void *params __rte_unused)\n-{\n-\t/* Set security session as the pkt metadata */\n-\t*rte_security_dynfield(m) = (rte_security_dynfield_t)session;\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_crypto_sec_get_userdata(void *device __rte_unused, uint64_t md,\n-\t\t\t void **userdata)\n-{\n-\t/* Retrieve userdata */\n-\t*userdata = (void *)md;\n-\n-\treturn 0;\n-}\n-\n-static struct rte_security_ops otx2_crypto_sec_ops = {\n-\t.session_create\t\t= otx2_crypto_sec_session_create,\n-\t.session_destroy\t= otx2_crypto_sec_session_destroy,\n-\t.session_get_size\t= otx2_crypto_sec_session_get_size,\n-\t.set_pkt_metadata\t= otx2_crypto_sec_set_pkt_mdata,\n-\t.get_userdata\t\t= otx2_crypto_sec_get_userdata,\n-\t.capabilities_get\t= otx2_crypto_sec_capabilities_get\n-};\n-\n-int\n-otx2_crypto_sec_ctx_create(struct rte_cryptodev *cdev)\n-{\n-\tstruct rte_security_ctx *ctx;\n-\n-\tctx = rte_malloc(\"otx2_cpt_dev_sec_ctx\",\n-\t\t\t sizeof(struct rte_security_ctx), 0);\n-\n-\tif (ctx == NULL)\n-\t\treturn -ENOMEM;\n-\n-\t/* Populate ctx */\n-\tctx->device = cdev;\n-\tctx->ops = &otx2_crypto_sec_ops;\n-\tctx->sess_cnt = 0;\n-\n-\tcdev->security_ctx = ctx;\n-\n-\treturn 0;\n-}\n-\n-void\n-otx2_crypto_sec_ctx_destroy(struct rte_cryptodev *cdev)\n-{\n-\trte_free(cdev->security_ctx);\n-}\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_sec.h b/drivers/crypto/octeontx2/otx2_cryptodev_sec.h\ndeleted file mode 100644\nindex ff3329c9c1..0000000000\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_sec.h\n+++ /dev/null\n@@ -1,64 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_CRYPTODEV_SEC_H__\n-#define __OTX2_CRYPTODEV_SEC_H__\n-\n-#include <rte_cryptodev.h>\n-\n-#include \"otx2_ipsec_po.h\"\n-\n-struct otx2_sec_session_ipsec_lp {\n-\tRTE_STD_C11\n-\tunion {\n-\t\t/* Inbound SA */\n-\t\tstruct otx2_ipsec_po_in_sa in_sa;\n-\t\t/* Outbound SA */\n-\t\tstruct otx2_ipsec_po_out_sa out_sa;\n-\t};\n-\n-\tuint64_t cpt_inst_w7;\n-\tunion {\n-\t\tuint64_t ucmd_w0;\n-\t\tstruct {\n-\t\t\tuint16_t ucmd_dlen;\n-\t\t\tuint16_t ucmd_param2;\n-\t\t\tuint16_t ucmd_param1;\n-\t\t\tuint16_t ucmd_opcode;\n-\t\t};\n-\t};\n-\n-\tuint8_t partial_len;\n-\tuint8_t roundup_len;\n-\tuint8_t roundup_byte;\n-\tuint16_t ip_id;\n-\tunion {\n-\t\tuint64_t esn;\n-\t\tstruct {\n-\t\t\tuint32_t seq_lo;\n-\t\t\tuint32_t seq_hi;\n-\t\t};\n-\t};\n-\n-\t/** Context length in 8-byte words */\n-\tsize_t ctx_len;\n-\t/** Auth IV offset in bytes */\n-\tuint16_t auth_iv_offset;\n-\t/** IV offset in bytes */\n-\tuint16_t iv_offset;\n-\t/** AAD length */\n-\tuint16_t aad_length;\n-\t/** MAC len in bytes */\n-\tuint8_t mac_len;\n-\t/** IV length in bytes */\n-\tuint8_t iv_length;\n-\t/** Auth IV length in bytes */\n-\tuint8_t auth_iv_length;\n-};\n-\n-int otx2_crypto_sec_ctx_create(struct rte_cryptodev *crypto_dev);\n-\n-void otx2_crypto_sec_ctx_destroy(struct rte_cryptodev *crypto_dev);\n-\n-#endif /* __OTX2_CRYPTODEV_SEC_H__ */\ndiff --git a/drivers/crypto/octeontx2/otx2_ipsec_anti_replay.h b/drivers/crypto/octeontx2/otx2_ipsec_anti_replay.h\ndeleted file mode 100644\nindex 089a3d073a..0000000000\n--- a/drivers/crypto/octeontx2/otx2_ipsec_anti_replay.h\n+++ /dev/null\n@@ -1,227 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_IPSEC_ANTI_REPLAY_H__\n-#define __OTX2_IPSEC_ANTI_REPLAY_H__\n-\n-#include <rte_mbuf.h>\n-\n-#include \"otx2_ipsec_fp.h\"\n-\n-#define WORD_SHIFT\t6\n-#define WORD_SIZE\t(1 << WORD_SHIFT)\n-#define WORD_MASK\t(WORD_SIZE - 1)\n-\n-#define IPSEC_ANTI_REPLAY_FAILED\t(-1)\n-\n-static inline int\n-anti_replay_check(struct otx2_ipsec_replay *replay, uint64_t seq,\n-\t\t\tuint64_t winsz)\n-{\n-\tuint64_t *window = &replay->window[0];\n-\tuint64_t ex_winsz = winsz + WORD_SIZE;\n-\tuint64_t winwords = ex_winsz >> WORD_SHIFT;\n-\tuint64_t base = replay->base;\n-\tuint32_t winb = replay->winb;\n-\tuint32_t wint = replay->wint;\n-\tuint64_t seqword, shiftwords;\n-\tuint64_t bit_pos;\n-\tuint64_t shift;\n-\tuint64_t *wptr;\n-\tuint64_t tmp;\n-\n-\tif (winsz > 64)\n-\t\tgoto slow_shift;\n-\t/* Check if the seq is the biggest one yet */\n-\tif (likely(seq > base)) {\n-\t\tshift = seq - base;\n-\t\tif (shift < winsz) { /* In window */\n-\t\t\t/*\n-\t\t\t * If more than 64-bit anti-replay window,\n-\t\t\t * use slow shift routine\n-\t\t\t */\n-\t\t\twptr = window + (shift >> WORD_SHIFT);\n-\t\t\t*wptr <<= shift;\n-\t\t\t*wptr |= 1ull;\n-\t\t} else {\n-\t\t\t/* No special handling of window size > 64 */\n-\t\t\twptr = window + ((winsz - 1) >> WORD_SHIFT);\n-\t\t\t/*\n-\t\t\t * Zero out the whole window (especially for\n-\t\t\t * bigger than 64b window) till the last 64b word\n-\t\t\t * as the incoming sequence number minus\n-\t\t\t * base sequence is more than the window size.\n-\t\t\t */\n-\t\t\twhile (window != wptr)\n-\t\t\t\t*window++ = 0ull;\n-\t\t\t/*\n-\t\t\t * Set the last bit (of the window) to 1\n-\t\t\t * as that corresponds to the base sequence number.\n-\t\t\t * Now any incoming sequence number which is\n-\t\t\t * (base - window size - 1) will pass anti-replay check\n-\t\t\t */\n-\t\t\t*wptr = 1ull;\n-\t\t}\n-\t\t/*\n-\t\t * Set the base to incoming sequence number as\n-\t\t * that is the biggest sequence number seen yet\n-\t\t */\n-\t\treplay->base = seq;\n-\t\treturn 0;\n-\t}\n-\n-\tbit_pos = base - seq;\n-\n-\t/* If seq falls behind the window, return failure */\n-\tif (bit_pos >= winsz)\n-\t\treturn IPSEC_ANTI_REPLAY_FAILED;\n-\n-\t/* seq is within anti-replay window */\n-\twptr = window + ((winsz - bit_pos - 1) >> WORD_SHIFT);\n-\tbit_pos &= WORD_MASK;\n-\n-\t/* Check if this is a replayed packet */\n-\tif (*wptr & ((1ull) << bit_pos))\n-\t\treturn IPSEC_ANTI_REPLAY_FAILED;\n-\n-\t/* mark as seen */\n-\t*wptr |= ((1ull) << bit_pos);\n-\treturn 0;\n-\n-slow_shift:\n-\tif (likely(seq > base)) {\n-\t\tuint32_t i;\n-\n-\t\tshift = seq - base;\n-\t\tif (unlikely(shift >= winsz)) {\n-\t\t\t/*\n-\t\t\t * shift is bigger than the window,\n-\t\t\t * so just zero out everything\n-\t\t\t */\n-\t\t\tfor (i = 0; i < winwords; i++)\n-\t\t\t\twindow[i] = 0;\n-winupdate:\n-\t\t\t/* Find out the word */\n-\t\t\tseqword = ((seq - 1) % ex_winsz) >> WORD_SHIFT;\n-\n-\t\t\t/* Find out the bit in the word */\n-\t\t\tbit_pos = (seq - 1) & WORD_MASK;\n-\n-\t\t\t/*\n-\t\t\t * Set the bit corresponding to sequence number\n-\t\t\t * in window to mark it as received\n-\t\t\t */\n-\t\t\twindow[seqword] |= (1ull << (63 - bit_pos));\n-\n-\t\t\t/* wint and winb range from 1 to ex_winsz */\n-\t\t\treplay->wint = ((wint + shift - 1) % ex_winsz) + 1;\n-\t\t\treplay->winb = ((winb + shift - 1) % ex_winsz) + 1;\n-\n-\t\t\treplay->base = seq;\n-\t\t\treturn 0;\n-\t\t}\n-\n-\t\t/*\n-\t\t * New sequence number is bigger than the base but\n-\t\t * it's not bigger than base + window size\n-\t\t */\n-\n-\t\tshiftwords = ((wint + shift - 1) >> WORD_SHIFT) -\n-\t\t\t ((wint - 1) >> WORD_SHIFT);\n-\t\tif (unlikely(shiftwords)) {\n-\t\t\ttmp = (wint + WORD_SIZE - 1) / WORD_SIZE;\n-\t\t\tfor (i = 0; i < shiftwords; i++) {\n-\t\t\t\ttmp %= winwords;\n-\t\t\t\twindow[tmp++] = 0;\n-\t\t\t}\n-\t\t}\n-\n-\t\tgoto winupdate;\n-\t}\n-\n-\t/* Sequence number is before the window */\n-\tif (unlikely((seq + winsz) <= base))\n-\t\treturn IPSEC_ANTI_REPLAY_FAILED;\n-\n-\t/* Sequence number is within the window */\n-\n-\t/* Find out the word */\n-\tseqword = ((seq - 1) % ex_winsz) >> WORD_SHIFT;\n-\n-\t/* Find out the bit in the word */\n-\tbit_pos = (seq - 1) & WORD_MASK;\n-\n-\t/* Check if this is a replayed packet */\n-\tif (window[seqword] & (1ull << (63 - bit_pos)))\n-\t\treturn IPSEC_ANTI_REPLAY_FAILED;\n-\n-\t/*\n-\t * Set the bit corresponding to sequence number\n-\t * in window to mark it as received\n-\t */\n-\twindow[seqword] |= (1ull << (63 - bit_pos));\n-\n-\treturn 0;\n-}\n-\n-static inline int\n-cpt_ipsec_ip_antireplay_check(struct otx2_ipsec_fp_in_sa *sa, void *l3_ptr)\n-{\n-\tstruct otx2_ipsec_fp_res_hdr *hdr = l3_ptr;\n-\tuint64_t seq_in_sa;\n-\tuint32_t seqh = 0;\n-\tuint32_t seql;\n-\tuint64_t seq;\n-\tuint8_t esn;\n-\tint ret;\n-\n-\tesn = sa->ctl.esn_en;\n-\tseql = rte_be_to_cpu_32(hdr->seq_no_lo);\n-\n-\tif (!esn)\n-\t\tseq = (uint64_t)seql;\n-\telse {\n-\t\tseqh = rte_be_to_cpu_32(hdr->seq_no_hi);\n-\t\tseq = ((uint64_t)seqh << 32) | seql;\n-\t}\n-\n-\tif (unlikely(seq == 0))\n-\t\treturn IPSEC_ANTI_REPLAY_FAILED;\n-\n-\trte_spinlock_lock(&sa->replay->lock);\n-\tret = anti_replay_check(sa->replay, seq, sa->replay_win_sz);\n-\tif (esn && (ret == 0)) {\n-\t\tseq_in_sa = ((uint64_t)rte_be_to_cpu_32(sa->esn_hi) << 32) |\n-\t\t\t\trte_be_to_cpu_32(sa->esn_low);\n-\t\tif (seq > seq_in_sa) {\n-\t\t\tsa->esn_low = rte_cpu_to_be_32(seql);\n-\t\t\tsa->esn_hi = rte_cpu_to_be_32(seqh);\n-\t\t}\n-\t}\n-\trte_spinlock_unlock(&sa->replay->lock);\n-\n-\treturn ret;\n-}\n-\n-static inline uint32_t\n-anti_replay_get_seqh(uint32_t winsz, uint32_t seql,\n-\t\t\tuint32_t esn_hi, uint32_t esn_low)\n-{\n-\tuint32_t win_low = esn_low - winsz + 1;\n-\n-\tif (esn_low > winsz - 1) {\n-\t\t/* Window is in one sequence number subspace */\n-\t\tif (seql > win_low)\n-\t\t\treturn esn_hi;\n-\t\telse\n-\t\t\treturn esn_hi + 1;\n-\t} else {\n-\t\t/* Window is split across two sequence number subspaces */\n-\t\tif (seql > win_low)\n-\t\t\treturn esn_hi - 1;\n-\t\telse\n-\t\t\treturn esn_hi;\n-\t}\n-}\n-#endif /* __OTX2_IPSEC_ANTI_REPLAY_H__ */\ndiff --git a/drivers/crypto/octeontx2/otx2_ipsec_fp.h b/drivers/crypto/octeontx2/otx2_ipsec_fp.h\ndeleted file mode 100644\nindex 2461e7462b..0000000000\n--- a/drivers/crypto/octeontx2/otx2_ipsec_fp.h\n+++ /dev/null\n@@ -1,371 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_IPSEC_FP_H__\n-#define __OTX2_IPSEC_FP_H__\n-\n-#include <rte_crypto_sym.h>\n-#include <rte_security.h>\n-\n-/* Macros for anti replay and ESN */\n-#define OTX2_IPSEC_MAX_REPLAY_WIN_SZ\t1024\n-\n-struct otx2_ipsec_fp_res_hdr {\n-\tuint32_t spi;\n-\tuint32_t seq_no_lo;\n-\tuint32_t seq_no_hi;\n-\tuint32_t rsvd;\n-};\n-\n-enum {\n-\tOTX2_IPSEC_FP_SA_DIRECTION_INBOUND = 0,\n-\tOTX2_IPSEC_FP_SA_DIRECTION_OUTBOUND = 1,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_FP_SA_IP_VERSION_4 = 0,\n-\tOTX2_IPSEC_FP_SA_IP_VERSION_6 = 1,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_FP_SA_MODE_TRANSPORT = 0,\n-\tOTX2_IPSEC_FP_SA_MODE_TUNNEL = 1,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_FP_SA_PROTOCOL_AH = 0,\n-\tOTX2_IPSEC_FP_SA_PROTOCOL_ESP = 1,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_FP_SA_AES_KEY_LEN_128 = 1,\n-\tOTX2_IPSEC_FP_SA_AES_KEY_LEN_192 = 2,\n-\tOTX2_IPSEC_FP_SA_AES_KEY_LEN_256 = 3,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_FP_SA_ENC_NULL = 0,\n-\tOTX2_IPSEC_FP_SA_ENC_DES_CBC = 1,\n-\tOTX2_IPSEC_FP_SA_ENC_3DES_CBC = 2,\n-\tOTX2_IPSEC_FP_SA_ENC_AES_CBC = 3,\n-\tOTX2_IPSEC_FP_SA_ENC_AES_CTR = 4,\n-\tOTX2_IPSEC_FP_SA_ENC_AES_GCM = 5,\n-\tOTX2_IPSEC_FP_SA_ENC_AES_CCM = 6,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_FP_SA_AUTH_NULL = 0,\n-\tOTX2_IPSEC_FP_SA_AUTH_MD5 = 1,\n-\tOTX2_IPSEC_FP_SA_AUTH_SHA1 = 2,\n-\tOTX2_IPSEC_FP_SA_AUTH_SHA2_224 = 3,\n-\tOTX2_IPSEC_FP_SA_AUTH_SHA2_256 = 4,\n-\tOTX2_IPSEC_FP_SA_AUTH_SHA2_384 = 5,\n-\tOTX2_IPSEC_FP_SA_AUTH_SHA2_512 = 6,\n-\tOTX2_IPSEC_FP_SA_AUTH_AES_GMAC = 7,\n-\tOTX2_IPSEC_FP_SA_AUTH_AES_XCBC_128 = 8,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_FP_SA_FRAG_POST = 0,\n-\tOTX2_IPSEC_FP_SA_FRAG_PRE = 1,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_FP_SA_ENCAP_NONE = 0,\n-\tOTX2_IPSEC_FP_SA_ENCAP_UDP = 1,\n-};\n-\n-struct otx2_ipsec_fp_sa_ctl {\n-\trte_be32_t spi : 32;\n-\tuint64_t exp_proto_inter_frag : 8;\n-\tuint64_t rsvd_42_40 : 3;\n-\tuint64_t esn_en : 1;\n-\tuint64_t rsvd_45_44 : 2;\n-\tuint64_t encap_type : 2;\n-\tuint64_t enc_type : 3;\n-\tuint64_t rsvd_48 : 1;\n-\tuint64_t auth_type : 4;\n-\tuint64_t valid : 1;\n-\tuint64_t direction : 1;\n-\tuint64_t outer_ip_ver : 1;\n-\tuint64_t inner_ip_ver : 1;\n-\tuint64_t ipsec_mode : 1;\n-\tuint64_t ipsec_proto : 1;\n-\tuint64_t aes_key_len : 2;\n-};\n-\n-struct otx2_ipsec_fp_out_sa {\n-\t/* w0 */\n-\tstruct otx2_ipsec_fp_sa_ctl ctl;\n-\n-\t/* w1 */\n-\tuint8_t nonce[4];\n-\tuint16_t udp_src;\n-\tuint16_t udp_dst;\n-\n-\t/* w2 */\n-\tuint32_t ip_src;\n-\tuint32_t ip_dst;\n-\n-\t/* w3-w6 */\n-\tuint8_t cipher_key[32];\n-\n-\t/* w7-w12 */\n-\tuint8_t hmac_key[48];\n-};\n-\n-struct otx2_ipsec_replay {\n-\trte_spinlock_t lock;\n-\tuint32_t winb;\n-\tuint32_t wint;\n-\tuint64_t base; /**< base of the anti-replay window */\n-\tuint64_t window[17]; /**< anti-replay window */\n-};\n-\n-struct otx2_ipsec_fp_in_sa {\n-\t/* w0 */\n-\tstruct otx2_ipsec_fp_sa_ctl ctl;\n-\n-\t/* w1 */\n-\tuint8_t nonce[4]; /* Only for AES-GCM */\n-\tuint32_t unused;\n-\n-\t/* w2 */\n-\tuint32_t esn_hi;\n-\tuint32_t esn_low;\n-\n-\t/* w3-w6 */\n-\tuint8_t cipher_key[32];\n-\n-\t/* w7-w12 */\n-\tuint8_t hmac_key[48];\n-\n-\tRTE_STD_C11\n-\tunion {\n-\t\tvoid *userdata;\n-\t\tuint64_t udata64;\n-\t};\n-\tunion {\n-\t\tstruct otx2_ipsec_replay *replay;\n-\t\tuint64_t replay64;\n-\t};\n-\tuint32_t replay_win_sz;\n-\n-\tuint32_t reserved1;\n-};\n-\n-static inline int\n-ipsec_fp_xform_cipher_verify(struct rte_crypto_sym_xform *xform)\n-{\n-\tif (xform->cipher.algo == RTE_CRYPTO_CIPHER_AES_CBC) {\n-\t\tswitch (xform->cipher.key.length) {\n-\t\tcase 16:\n-\t\tcase 24:\n-\t\tcase 32:\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -ENOTSUP;\n-\t\t}\n-\t\treturn 0;\n-\t}\n-\n-\treturn -ENOTSUP;\n-}\n-\n-static inline int\n-ipsec_fp_xform_auth_verify(struct rte_crypto_sym_xform *xform)\n-{\n-\tuint16_t keylen = xform->auth.key.length;\n-\n-\tif (xform->auth.algo == RTE_CRYPTO_AUTH_SHA1_HMAC) {\n-\t\tif (keylen >= 20 && keylen <= 64)\n-\t\t\treturn 0;\n-\t}\n-\n-\treturn -ENOTSUP;\n-}\n-\n-static inline int\n-ipsec_fp_xform_aead_verify(struct rte_security_ipsec_xform *ipsec,\n-\t\t\t struct rte_crypto_sym_xform *xform)\n-{\n-\tif (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS &&\n-\t xform->aead.op != RTE_CRYPTO_AEAD_OP_ENCRYPT)\n-\t\treturn -EINVAL;\n-\n-\tif (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS &&\n-\t xform->aead.op != RTE_CRYPTO_AEAD_OP_DECRYPT)\n-\t\treturn -EINVAL;\n-\n-\tif (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM) {\n-\t\tswitch (xform->aead.key.length) {\n-\t\tcase 16:\n-\t\tcase 24:\n-\t\tcase 32:\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\treturn 0;\n-\t}\n-\n-\treturn -ENOTSUP;\n-}\n-\n-static inline int\n-ipsec_fp_xform_verify(struct rte_security_ipsec_xform *ipsec,\n-\t\t struct rte_crypto_sym_xform *xform)\n-{\n-\tstruct rte_crypto_sym_xform *auth_xform, *cipher_xform;\n-\tint ret;\n-\n-\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)\n-\t\treturn ipsec_fp_xform_aead_verify(ipsec, xform);\n-\n-\tif (xform->next == NULL)\n-\t\treturn -EINVAL;\n-\n-\tif (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS) {\n-\t\t/* Ingress */\n-\t\tif (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH ||\n-\t\t xform->next->type != RTE_CRYPTO_SYM_XFORM_CIPHER)\n-\t\t\treturn -EINVAL;\n-\t\tauth_xform = xform;\n-\t\tcipher_xform = xform->next;\n-\t} else {\n-\t\t/* Egress */\n-\t\tif (xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER ||\n-\t\t xform->next->type != RTE_CRYPTO_SYM_XFORM_AUTH)\n-\t\t\treturn -EINVAL;\n-\t\tcipher_xform = xform;\n-\t\tauth_xform = xform->next;\n-\t}\n-\n-\tret = ipsec_fp_xform_cipher_verify(cipher_xform);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = ipsec_fp_xform_auth_verify(auth_xform);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\treturn 0;\n-}\n-\n-static inline int\n-ipsec_fp_sa_ctl_set(struct rte_security_ipsec_xform *ipsec,\n-\t\t struct rte_crypto_sym_xform *xform,\n-\t\t struct otx2_ipsec_fp_sa_ctl *ctl)\n-{\n-\tstruct rte_crypto_sym_xform *cipher_xform, *auth_xform;\n-\tint aes_key_len;\n-\n-\tif (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS) {\n-\t\tctl->direction = OTX2_IPSEC_FP_SA_DIRECTION_OUTBOUND;\n-\t\tcipher_xform = xform;\n-\t\tauth_xform = xform->next;\n-\t} else if (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS) {\n-\t\tctl->direction = OTX2_IPSEC_FP_SA_DIRECTION_INBOUND;\n-\t\tauth_xform = xform;\n-\t\tcipher_xform = xform->next;\n-\t} else {\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (ipsec->mode == RTE_SECURITY_IPSEC_SA_MODE_TUNNEL) {\n-\t\tif (ipsec->tunnel.type == RTE_SECURITY_IPSEC_TUNNEL_IPV4)\n-\t\t\tctl->outer_ip_ver = OTX2_IPSEC_FP_SA_IP_VERSION_4;\n-\t\telse if (ipsec->tunnel.type == RTE_SECURITY_IPSEC_TUNNEL_IPV6)\n-\t\t\tctl->outer_ip_ver = OTX2_IPSEC_FP_SA_IP_VERSION_6;\n-\t\telse\n-\t\t\treturn -EINVAL;\n-\t}\n-\n-\tctl->inner_ip_ver = OTX2_IPSEC_FP_SA_IP_VERSION_4;\n-\n-\tif (ipsec->mode == RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT)\n-\t\tctl->ipsec_mode = OTX2_IPSEC_FP_SA_MODE_TRANSPORT;\n-\telse if (ipsec->mode == RTE_SECURITY_IPSEC_SA_MODE_TUNNEL)\n-\t\tctl->ipsec_mode = OTX2_IPSEC_FP_SA_MODE_TUNNEL;\n-\telse\n-\t\treturn -EINVAL;\n-\n-\tif (ipsec->proto == RTE_SECURITY_IPSEC_SA_PROTO_AH)\n-\t\tctl->ipsec_proto = OTX2_IPSEC_FP_SA_PROTOCOL_AH;\n-\telse if (ipsec->proto == RTE_SECURITY_IPSEC_SA_PROTO_ESP)\n-\t\tctl->ipsec_proto = OTX2_IPSEC_FP_SA_PROTOCOL_ESP;\n-\telse\n-\t\treturn -EINVAL;\n-\n-\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\tif (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM) {\n-\t\t\tctl->enc_type = OTX2_IPSEC_FP_SA_ENC_AES_GCM;\n-\t\t\taes_key_len = xform->aead.key.length;\n-\t\t} else {\n-\t\t\treturn -ENOTSUP;\n-\t\t}\n-\t} else if (cipher_xform->cipher.algo == RTE_CRYPTO_CIPHER_AES_CBC) {\n-\t\tctl->enc_type = OTX2_IPSEC_FP_SA_ENC_AES_CBC;\n-\t\taes_key_len = cipher_xform->cipher.key.length;\n-\t} else {\n-\t\treturn -ENOTSUP;\n-\t}\n-\n-\tswitch (aes_key_len) {\n-\tcase 16:\n-\t\tctl->aes_key_len = OTX2_IPSEC_FP_SA_AES_KEY_LEN_128;\n-\t\tbreak;\n-\tcase 24:\n-\t\tctl->aes_key_len = OTX2_IPSEC_FP_SA_AES_KEY_LEN_192;\n-\t\tbreak;\n-\tcase 32:\n-\t\tctl->aes_key_len = OTX2_IPSEC_FP_SA_AES_KEY_LEN_256;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (xform->type != RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\tswitch (auth_xform->auth.algo) {\n-\t\tcase RTE_CRYPTO_AUTH_NULL:\n-\t\t\tctl->auth_type = OTX2_IPSEC_FP_SA_AUTH_NULL;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_MD5_HMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_FP_SA_AUTH_MD5;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_SHA1_HMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_FP_SA_AUTH_SHA1;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_SHA224_HMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_FP_SA_AUTH_SHA2_224;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_SHA256_HMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_FP_SA_AUTH_SHA2_256;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_SHA384_HMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_FP_SA_AUTH_SHA2_384;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_SHA512_HMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_FP_SA_AUTH_SHA2_512;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_AES_GMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_FP_SA_AUTH_AES_GMAC;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_AES_XCBC_MAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_FP_SA_AUTH_AES_XCBC_128;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -ENOTSUP;\n-\t\t}\n-\t}\n-\n-\tif (ipsec->options.esn == 1)\n-\t\tctl->esn_en = 1;\n-\n-\tctl->spi = rte_cpu_to_be_32(ipsec->spi);\n-\n-\treturn 0;\n-}\n-\n-#endif /* __OTX2_IPSEC_FP_H__ */\ndiff --git a/drivers/crypto/octeontx2/otx2_ipsec_po.h b/drivers/crypto/octeontx2/otx2_ipsec_po.h\ndeleted file mode 100644\nindex 695f552644..0000000000\n--- a/drivers/crypto/octeontx2/otx2_ipsec_po.h\n+++ /dev/null\n@@ -1,447 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_IPSEC_PO_H__\n-#define __OTX2_IPSEC_PO_H__\n-\n-#include <rte_crypto_sym.h>\n-#include <rte_ip.h>\n-#include <rte_security.h>\n-\n-#define OTX2_IPSEC_PO_AES_GCM_INB_CTX_LEN 0x09\n-\n-#define OTX2_IPSEC_PO_WRITE_IPSEC_OUTB 0x20\n-#define OTX2_IPSEC_PO_WRITE_IPSEC_INB 0x21\n-#define OTX2_IPSEC_PO_PROCESS_IPSEC_OUTB 0x23\n-#define OTX2_IPSEC_PO_PROCESS_IPSEC_INB 0x24\n-\n-#define OTX2_IPSEC_PO_INB_RPTR_HDR 0x8\n-\n-enum otx2_ipsec_po_comp_e {\n-\tOTX2_IPSEC_PO_CC_SUCCESS = 0x00,\n-\tOTX2_IPSEC_PO_CC_AUTH_UNSUPPORTED = 0xB0,\n-\tOTX2_IPSEC_PO_CC_ENCRYPT_UNSUPPORTED = 0xB1,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_PO_SA_DIRECTION_INBOUND = 0,\n-\tOTX2_IPSEC_PO_SA_DIRECTION_OUTBOUND = 1,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_PO_SA_IP_VERSION_4 = 0,\n-\tOTX2_IPSEC_PO_SA_IP_VERSION_6 = 1,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_PO_SA_MODE_TRANSPORT = 0,\n-\tOTX2_IPSEC_PO_SA_MODE_TUNNEL = 1,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_PO_SA_PROTOCOL_AH = 0,\n-\tOTX2_IPSEC_PO_SA_PROTOCOL_ESP = 1,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_PO_SA_AES_KEY_LEN_128 = 1,\n-\tOTX2_IPSEC_PO_SA_AES_KEY_LEN_192 = 2,\n-\tOTX2_IPSEC_PO_SA_AES_KEY_LEN_256 = 3,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_PO_SA_ENC_NULL = 0,\n-\tOTX2_IPSEC_PO_SA_ENC_DES_CBC = 1,\n-\tOTX2_IPSEC_PO_SA_ENC_3DES_CBC = 2,\n-\tOTX2_IPSEC_PO_SA_ENC_AES_CBC = 3,\n-\tOTX2_IPSEC_PO_SA_ENC_AES_CTR = 4,\n-\tOTX2_IPSEC_PO_SA_ENC_AES_GCM = 5,\n-\tOTX2_IPSEC_PO_SA_ENC_AES_CCM = 6,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_PO_SA_AUTH_NULL = 0,\n-\tOTX2_IPSEC_PO_SA_AUTH_MD5 = 1,\n-\tOTX2_IPSEC_PO_SA_AUTH_SHA1 = 2,\n-\tOTX2_IPSEC_PO_SA_AUTH_SHA2_224 = 3,\n-\tOTX2_IPSEC_PO_SA_AUTH_SHA2_256 = 4,\n-\tOTX2_IPSEC_PO_SA_AUTH_SHA2_384 = 5,\n-\tOTX2_IPSEC_PO_SA_AUTH_SHA2_512 = 6,\n-\tOTX2_IPSEC_PO_SA_AUTH_AES_GMAC = 7,\n-\tOTX2_IPSEC_PO_SA_AUTH_AES_XCBC_128 = 8,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_PO_SA_FRAG_POST = 0,\n-\tOTX2_IPSEC_PO_SA_FRAG_PRE = 1,\n-};\n-\n-enum {\n-\tOTX2_IPSEC_PO_SA_ENCAP_NONE = 0,\n-\tOTX2_IPSEC_PO_SA_ENCAP_UDP = 1,\n-};\n-\n-struct otx2_ipsec_po_out_hdr {\n-\tuint32_t ip_id;\n-\tuint32_t seq;\n-\tuint8_t iv[16];\n-};\n-\n-union otx2_ipsec_po_bit_perfect_iv {\n-\tuint8_t aes_iv[16];\n-\tuint8_t des_iv[8];\n-\tstruct {\n-\t\tuint8_t nonce[4];\n-\t\tuint8_t iv[8];\n-\t\tuint8_t counter[4];\n-\t} gcm;\n-};\n-\n-struct otx2_ipsec_po_traffic_selector {\n-\trte_be16_t src_port[2];\n-\trte_be16_t dst_port[2];\n-\tRTE_STD_C11\n-\tunion {\n-\t\tstruct {\n-\t\t\trte_be32_t src_addr[2];\n-\t\t\trte_be32_t dst_addr[2];\n-\t\t} ipv4;\n-\t\tstruct {\n-\t\t\tuint8_t src_addr[32];\n-\t\t\tuint8_t dst_addr[32];\n-\t\t} ipv6;\n-\t};\n-};\n-\n-struct otx2_ipsec_po_sa_ctl {\n-\trte_be32_t spi : 32;\n-\tuint64_t exp_proto_inter_frag : 8;\n-\tuint64_t rsvd_42_40 : 3;\n-\tuint64_t esn_en : 1;\n-\tuint64_t rsvd_45_44 : 2;\n-\tuint64_t encap_type : 2;\n-\tuint64_t enc_type : 3;\n-\tuint64_t rsvd_48 : 1;\n-\tuint64_t auth_type : 4;\n-\tuint64_t valid : 1;\n-\tuint64_t direction : 1;\n-\tuint64_t outer_ip_ver : 1;\n-\tuint64_t inner_ip_ver : 1;\n-\tuint64_t ipsec_mode : 1;\n-\tuint64_t ipsec_proto : 1;\n-\tuint64_t aes_key_len : 2;\n-};\n-\n-struct otx2_ipsec_po_in_sa {\n-\t/* w0 */\n-\tstruct otx2_ipsec_po_sa_ctl ctl;\n-\n-\t/* w1-w4 */\n-\tuint8_t cipher_key[32];\n-\n-\t/* w5-w6 */\n-\tunion otx2_ipsec_po_bit_perfect_iv iv;\n-\n-\t/* w7 */\n-\tuint32_t esn_hi;\n-\tuint32_t esn_low;\n-\n-\t/* w8 */\n-\tuint8_t udp_encap[8];\n-\n-\t/* w9-w33 */\n-\tunion {\n-\t\tstruct {\n-\t\t\tuint8_t hmac_key[48];\n-\t\t\tstruct otx2_ipsec_po_traffic_selector selector;\n-\t\t} aes_gcm;\n-\t\tstruct {\n-\t\t\tuint8_t hmac_key[64];\n-\t\t\tuint8_t hmac_iv[64];\n-\t\t\tstruct otx2_ipsec_po_traffic_selector selector;\n-\t\t} sha2;\n-\t};\n-\tunion {\n-\t\tstruct otx2_ipsec_replay *replay;\n-\t\tuint64_t replay64;\n-\t};\n-\tuint32_t replay_win_sz;\n-};\n-\n-struct otx2_ipsec_po_ip_template {\n-\tRTE_STD_C11\n-\tunion {\n-\t\tstruct {\n-\t\t\tstruct rte_ipv4_hdr ipv4_hdr;\n-\t\t\tuint16_t udp_src;\n-\t\t\tuint16_t udp_dst;\n-\t\t} ip4;\n-\t\tstruct {\n-\t\t\tstruct rte_ipv6_hdr ipv6_hdr;\n-\t\t\tuint16_t udp_src;\n-\t\t\tuint16_t udp_dst;\n-\t\t} ip6;\n-\t};\n-};\n-\n-struct otx2_ipsec_po_out_sa {\n-\t/* w0 */\n-\tstruct otx2_ipsec_po_sa_ctl ctl;\n-\n-\t/* w1-w4 */\n-\tuint8_t cipher_key[32];\n-\n-\t/* w5-w6 */\n-\tunion otx2_ipsec_po_bit_perfect_iv iv;\n-\n-\t/* w7 */\n-\tuint32_t esn_hi;\n-\tuint32_t esn_low;\n-\n-\t/* w8-w55 */\n-\tunion {\n-\t\tstruct {\n-\t\t\tstruct otx2_ipsec_po_ip_template template;\n-\t\t} aes_gcm;\n-\t\tstruct {\n-\t\t\tuint8_t hmac_key[24];\n-\t\t\tuint8_t unused[24];\n-\t\t\tstruct otx2_ipsec_po_ip_template template;\n-\t\t} sha1;\n-\t\tstruct {\n-\t\t\tuint8_t hmac_key[64];\n-\t\t\tuint8_t hmac_iv[64];\n-\t\t\tstruct otx2_ipsec_po_ip_template template;\n-\t\t} sha2;\n-\t};\n-};\n-\n-static inline int\n-ipsec_po_xform_cipher_verify(struct rte_crypto_sym_xform *xform)\n-{\n-\tif (xform->cipher.algo == RTE_CRYPTO_CIPHER_AES_CBC) {\n-\t\tswitch (xform->cipher.key.length) {\n-\t\tcase 16:\n-\t\tcase 24:\n-\t\tcase 32:\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -ENOTSUP;\n-\t\t}\n-\t\treturn 0;\n-\t}\n-\n-\treturn -ENOTSUP;\n-}\n-\n-static inline int\n-ipsec_po_xform_auth_verify(struct rte_crypto_sym_xform *xform)\n-{\n-\tuint16_t keylen = xform->auth.key.length;\n-\n-\tif (xform->auth.algo == RTE_CRYPTO_AUTH_SHA1_HMAC) {\n-\t\tif (keylen >= 20 && keylen <= 64)\n-\t\t\treturn 0;\n-\t} else if (xform->auth.algo == RTE_CRYPTO_AUTH_SHA256_HMAC) {\n-\t\tif (keylen >= 32 && keylen <= 64)\n-\t\t\treturn 0;\n-\t}\n-\n-\treturn -ENOTSUP;\n-}\n-\n-static inline int\n-ipsec_po_xform_aead_verify(struct rte_security_ipsec_xform *ipsec,\n-\t\t\t struct rte_crypto_sym_xform *xform)\n-{\n-\tif (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS &&\n-\t xform->aead.op != RTE_CRYPTO_AEAD_OP_ENCRYPT)\n-\t\treturn -EINVAL;\n-\n-\tif (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS &&\n-\t xform->aead.op != RTE_CRYPTO_AEAD_OP_DECRYPT)\n-\t\treturn -EINVAL;\n-\n-\tif (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM) {\n-\t\tswitch (xform->aead.key.length) {\n-\t\tcase 16:\n-\t\tcase 24:\n-\t\tcase 32:\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\treturn 0;\n-\t}\n-\n-\treturn -ENOTSUP;\n-}\n-\n-static inline int\n-ipsec_po_xform_verify(struct rte_security_ipsec_xform *ipsec,\n-\t\t struct rte_crypto_sym_xform *xform)\n-{\n-\tstruct rte_crypto_sym_xform *auth_xform, *cipher_xform;\n-\tint ret;\n-\n-\tif (ipsec->life.bytes_hard_limit != 0 ||\n-\t ipsec->life.bytes_soft_limit != 0 ||\n-\t ipsec->life.packets_hard_limit != 0 ||\n-\t ipsec->life.packets_soft_limit != 0)\n-\t\treturn -ENOTSUP;\n-\n-\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)\n-\t\treturn ipsec_po_xform_aead_verify(ipsec, xform);\n-\n-\tif (xform->next == NULL)\n-\t\treturn -EINVAL;\n-\n-\tif (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS) {\n-\t\t/* Ingress */\n-\t\tif (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH ||\n-\t\t xform->next->type != RTE_CRYPTO_SYM_XFORM_CIPHER)\n-\t\t\treturn -EINVAL;\n-\t\tauth_xform = xform;\n-\t\tcipher_xform = xform->next;\n-\t} else {\n-\t\t/* Egress */\n-\t\tif (xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER ||\n-\t\t xform->next->type != RTE_CRYPTO_SYM_XFORM_AUTH)\n-\t\t\treturn -EINVAL;\n-\t\tcipher_xform = xform;\n-\t\tauth_xform = xform->next;\n-\t}\n-\n-\tret = ipsec_po_xform_cipher_verify(cipher_xform);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tret = ipsec_po_xform_auth_verify(auth_xform);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\treturn 0;\n-}\n-\n-static inline int\n-ipsec_po_sa_ctl_set(struct rte_security_ipsec_xform *ipsec,\n-\t\t struct rte_crypto_sym_xform *xform,\n-\t\t struct otx2_ipsec_po_sa_ctl *ctl)\n-{\n-\tstruct rte_crypto_sym_xform *cipher_xform, *auth_xform;\n-\tint aes_key_len;\n-\n-\tif (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS) {\n-\t\tctl->direction = OTX2_IPSEC_PO_SA_DIRECTION_OUTBOUND;\n-\t\tcipher_xform = xform;\n-\t\tauth_xform = xform->next;\n-\t} else if (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS) {\n-\t\tctl->direction = OTX2_IPSEC_PO_SA_DIRECTION_INBOUND;\n-\t\tauth_xform = xform;\n-\t\tcipher_xform = xform->next;\n-\t} else {\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (ipsec->mode == RTE_SECURITY_IPSEC_SA_MODE_TUNNEL) {\n-\t\tif (ipsec->tunnel.type == RTE_SECURITY_IPSEC_TUNNEL_IPV4)\n-\t\t\tctl->outer_ip_ver = OTX2_IPSEC_PO_SA_IP_VERSION_4;\n-\t\telse if (ipsec->tunnel.type == RTE_SECURITY_IPSEC_TUNNEL_IPV6)\n-\t\t\tctl->outer_ip_ver = OTX2_IPSEC_PO_SA_IP_VERSION_6;\n-\t\telse\n-\t\t\treturn -EINVAL;\n-\t}\n-\n-\tctl->inner_ip_ver = ctl->outer_ip_ver;\n-\n-\tif (ipsec->mode == RTE_SECURITY_IPSEC_SA_MODE_TRANSPORT)\n-\t\tctl->ipsec_mode = OTX2_IPSEC_PO_SA_MODE_TRANSPORT;\n-\telse if (ipsec->mode == RTE_SECURITY_IPSEC_SA_MODE_TUNNEL)\n-\t\tctl->ipsec_mode = OTX2_IPSEC_PO_SA_MODE_TUNNEL;\n-\telse\n-\t\treturn -EINVAL;\n-\n-\tif (ipsec->proto == RTE_SECURITY_IPSEC_SA_PROTO_AH)\n-\t\tctl->ipsec_proto = OTX2_IPSEC_PO_SA_PROTOCOL_AH;\n-\telse if (ipsec->proto == RTE_SECURITY_IPSEC_SA_PROTO_ESP)\n-\t\tctl->ipsec_proto = OTX2_IPSEC_PO_SA_PROTOCOL_ESP;\n-\telse\n-\t\treturn -EINVAL;\n-\n-\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\tif (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM) {\n-\t\t\tctl->enc_type = OTX2_IPSEC_PO_SA_ENC_AES_GCM;\n-\t\t\taes_key_len = xform->aead.key.length;\n-\t\t} else {\n-\t\t\treturn -ENOTSUP;\n-\t\t}\n-\t} else if (cipher_xform->cipher.algo == RTE_CRYPTO_CIPHER_AES_CBC) {\n-\t\tctl->enc_type = OTX2_IPSEC_PO_SA_ENC_AES_CBC;\n-\t\taes_key_len = cipher_xform->cipher.key.length;\n-\t} else {\n-\t\treturn -ENOTSUP;\n-\t}\n-\n-\n-\tswitch (aes_key_len) {\n-\tcase 16:\n-\t\tctl->aes_key_len = OTX2_IPSEC_PO_SA_AES_KEY_LEN_128;\n-\t\tbreak;\n-\tcase 24:\n-\t\tctl->aes_key_len = OTX2_IPSEC_PO_SA_AES_KEY_LEN_192;\n-\t\tbreak;\n-\tcase 32:\n-\t\tctl->aes_key_len = OTX2_IPSEC_PO_SA_AES_KEY_LEN_256;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (xform->type != RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\tswitch (auth_xform->auth.algo) {\n-\t\tcase RTE_CRYPTO_AUTH_NULL:\n-\t\t\tctl->auth_type = OTX2_IPSEC_PO_SA_AUTH_NULL;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_MD5_HMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_PO_SA_AUTH_MD5;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_SHA1_HMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_PO_SA_AUTH_SHA1;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_SHA224_HMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_PO_SA_AUTH_SHA2_224;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_SHA256_HMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_PO_SA_AUTH_SHA2_256;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_SHA384_HMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_PO_SA_AUTH_SHA2_384;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_SHA512_HMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_PO_SA_AUTH_SHA2_512;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_AES_GMAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_PO_SA_AUTH_AES_GMAC;\n-\t\t\tbreak;\n-\t\tcase RTE_CRYPTO_AUTH_AES_XCBC_MAC:\n-\t\t\tctl->auth_type = OTX2_IPSEC_PO_SA_AUTH_AES_XCBC_128;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -ENOTSUP;\n-\t\t}\n-\t}\n-\n-\tif (ipsec->options.esn)\n-\t\tctl->esn_en = 1;\n-\n-\tif (ipsec->options.udp_encap == 1)\n-\t\tctl->encap_type = OTX2_IPSEC_PO_SA_ENCAP_UDP;\n-\n-\tctl->spi = rte_cpu_to_be_32(ipsec->spi);\n-\tctl->valid = 1;\n-\n-\treturn 0;\n-}\n-\n-#endif /* __OTX2_IPSEC_PO_H__ */\ndiff --git a/drivers/crypto/octeontx2/otx2_ipsec_po_ops.h b/drivers/crypto/octeontx2/otx2_ipsec_po_ops.h\ndeleted file mode 100644\nindex c3abf02187..0000000000\n--- a/drivers/crypto/octeontx2/otx2_ipsec_po_ops.h\n+++ /dev/null\n@@ -1,167 +0,0 @@\n-\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_IPSEC_PO_OPS_H__\n-#define __OTX2_IPSEC_PO_OPS_H__\n-\n-#include <rte_crypto_sym.h>\n-#include <rte_security.h>\n-\n-#include \"otx2_cryptodev.h\"\n-#include \"otx2_security.h\"\n-\n-static __rte_always_inline int32_t\n-otx2_ipsec_po_out_rlen_get(struct otx2_sec_session_ipsec_lp *sess,\n-\t\t\t uint32_t plen)\n-{\n-\tuint32_t enc_payload_len;\n-\n-\tenc_payload_len = RTE_ALIGN_CEIL(plen + sess->roundup_len,\n-\t\t\tsess->roundup_byte);\n-\n-\treturn sess->partial_len + enc_payload_len;\n-}\n-\n-static __rte_always_inline struct cpt_request_info *\n-alloc_request_struct(char *maddr, void *cop, int mdata_len)\n-{\n-\tstruct cpt_request_info *req;\n-\tstruct cpt_meta_info *meta;\n-\tuint8_t *resp_addr;\n-\tuintptr_t *op;\n-\n-\tmeta = (void *)RTE_PTR_ALIGN((uint8_t *)maddr, 16);\n-\n-\top = (uintptr_t *)meta->deq_op_info;\n-\treq = &meta->cpt_req;\n-\tresp_addr = (uint8_t *)&meta->cpt_res;\n-\n-\treq->completion_addr = (uint64_t *)((uint8_t *)resp_addr);\n-\t*req->completion_addr = COMPLETION_CODE_INIT;\n-\treq->comp_baddr = rte_mem_virt2iova(resp_addr);\n-\treq->op = op;\n-\n-\top[0] = (uintptr_t)((uint64_t)meta | 1ull);\n-\top[1] = (uintptr_t)cop;\n-\top[2] = (uintptr_t)req;\n-\top[3] = mdata_len;\n-\n-\treturn req;\n-}\n-\n-static __rte_always_inline int\n-process_outb_sa(struct rte_crypto_op *cop,\n-\t struct otx2_sec_session_ipsec_lp *sess,\n-\t struct cpt_qp_meta_info *m_info, void **prep_req)\n-{\n-\tuint32_t dlen, rlen, extend_head, extend_tail;\n-\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n-\tstruct rte_mbuf *m_src = sym_op->m_src;\n-\tstruct cpt_request_info *req = NULL;\n-\tstruct otx2_ipsec_po_out_hdr *hdr;\n-\tstruct otx2_ipsec_po_out_sa *sa;\n-\tint hdr_len, mdata_len, ret = 0;\n-\tvq_cmd_word0_t word0;\n-\tchar *mdata, *data;\n-\n-\tsa = &sess->out_sa;\n-\thdr_len = sizeof(*hdr);\n-\n-\tdlen = rte_pktmbuf_pkt_len(m_src) + hdr_len;\n-\trlen = otx2_ipsec_po_out_rlen_get(sess, dlen - hdr_len);\n-\n-\textend_head = hdr_len + RTE_ETHER_HDR_LEN;\n-\textend_tail = rlen - dlen;\n-\tmdata_len = m_info->lb_mlen + 8;\n-\n-\tmdata = rte_pktmbuf_append(m_src, extend_tail + mdata_len);\n-\tif (unlikely(mdata == NULL)) {\n-\t\totx2_err(\"Not enough tail room\\n\");\n-\t\tret = -ENOMEM;\n-\t\tgoto exit;\n-\t}\n-\n-\tmdata += extend_tail; /* mdata follows encrypted data */\n-\treq = alloc_request_struct(mdata, (void *)cop, mdata_len);\n-\n-\tdata = rte_pktmbuf_prepend(m_src, extend_head);\n-\tif (unlikely(data == NULL)) {\n-\t\totx2_err(\"Not enough head room\\n\");\n-\t\tret = -ENOMEM;\n-\t\tgoto exit;\n-\t}\n-\n-\t/*\n-\t * Move the Ethernet header, to insert otx2_ipsec_po_out_hdr prior\n-\t * to the IP header\n-\t */\n-\tmemcpy(data, data + hdr_len, RTE_ETHER_HDR_LEN);\n-\n-\thdr = (struct otx2_ipsec_po_out_hdr *)rte_pktmbuf_adj(m_src,\n-\t\t\t\t\t\t\tRTE_ETHER_HDR_LEN);\n-\n-\tmemcpy(&hdr->iv[0], rte_crypto_op_ctod_offset(cop, uint8_t *,\n-\t\tsess->iv_offset), sess->iv_length);\n-\n-\t/* Prepare CPT instruction */\n-\tword0.u64 = sess->ucmd_w0;\n-\tword0.s.dlen = dlen;\n-\n-\treq->ist.ei0 = word0.u64;\n-\treq->ist.ei1 = rte_pktmbuf_iova(m_src);\n-\treq->ist.ei2 = req->ist.ei1;\n-\n-\tsa->esn_hi = sess->seq_hi;\n-\n-\thdr->seq = rte_cpu_to_be_32(sess->seq_lo);\n-\thdr->ip_id = rte_cpu_to_be_32(sess->ip_id);\n-\n-\tsess->ip_id++;\n-\tsess->esn++;\n-\n-exit:\n-\t*prep_req = req;\n-\n-\treturn ret;\n-}\n-\n-static __rte_always_inline int\n-process_inb_sa(struct rte_crypto_op *cop,\n-\t struct otx2_sec_session_ipsec_lp *sess,\n-\t struct cpt_qp_meta_info *m_info, void **prep_req)\n-{\n-\tstruct rte_crypto_sym_op *sym_op = cop->sym;\n-\tstruct rte_mbuf *m_src = sym_op->m_src;\n-\tstruct cpt_request_info *req = NULL;\n-\tint mdata_len, ret = 0;\n-\tvq_cmd_word0_t word0;\n-\tuint32_t dlen;\n-\tchar *mdata;\n-\n-\tdlen = rte_pktmbuf_pkt_len(m_src);\n-\tmdata_len = m_info->lb_mlen + 8;\n-\n-\tmdata = rte_pktmbuf_append(m_src, mdata_len);\n-\tif (unlikely(mdata == NULL)) {\n-\t\totx2_err(\"Not enough tail room\\n\");\n-\t\tret = -ENOMEM;\n-\t\tgoto exit;\n-\t}\n-\n-\treq = alloc_request_struct(mdata, (void *)cop, mdata_len);\n-\n-\t/* Prepare CPT instruction */\n-\tword0.u64 = sess->ucmd_w0;\n-\tword0.s.dlen = dlen;\n-\n-\treq->ist.ei0 = word0.u64;\n-\treq->ist.ei1 = rte_pktmbuf_iova(m_src);\n-\treq->ist.ei2 = req->ist.ei1;\n-\n-exit:\n-\t*prep_req = req;\n-\treturn ret;\n-}\n-#endif /* __OTX2_IPSEC_PO_OPS_H__ */\ndiff --git a/drivers/crypto/octeontx2/otx2_security.h b/drivers/crypto/octeontx2/otx2_security.h\ndeleted file mode 100644\nindex 29c8fc351b..0000000000\n--- a/drivers/crypto/octeontx2/otx2_security.h\n+++ /dev/null\n@@ -1,37 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_SECURITY_H__\n-#define __OTX2_SECURITY_H__\n-\n-#include <rte_security.h>\n-\n-#include \"otx2_cryptodev_sec.h\"\n-#include \"otx2_ethdev_sec.h\"\n-\n-#define OTX2_SEC_AH_HDR_LEN\t\t\t12\n-#define OTX2_SEC_AES_GCM_IV_LEN\t\t\t8\n-#define OTX2_SEC_AES_GCM_MAC_LEN\t\t16\n-#define OTX2_SEC_AES_CBC_IV_LEN\t\t\t16\n-#define OTX2_SEC_SHA1_HMAC_LEN\t\t\t12\n-#define OTX2_SEC_SHA2_HMAC_LEN\t\t\t16\n-\n-#define OTX2_SEC_AES_GCM_ROUNDUP_BYTE_LEN\t4\n-#define OTX2_SEC_AES_CBC_ROUNDUP_BYTE_LEN\t16\n-\n-struct otx2_sec_session_ipsec {\n-\tunion {\n-\t\tstruct otx2_sec_session_ipsec_ip ip;\n-\t\tstruct otx2_sec_session_ipsec_lp lp;\n-\t};\n-\tenum rte_security_ipsec_sa_direction dir;\n-};\n-\n-struct otx2_sec_session {\n-\tstruct otx2_sec_session_ipsec ipsec;\n-\tvoid *userdata;\n-\t/**< Userdata registered by the application */\n-} __rte_cache_aligned;\n-\n-#endif /* __OTX2_SECURITY_H__ */\ndiff --git a/drivers/crypto/octeontx2/version.map b/drivers/crypto/octeontx2/version.map\ndeleted file mode 100644\nindex d36663132a..0000000000\n--- a/drivers/crypto/octeontx2/version.map\n+++ /dev/null\n@@ -1,13 +0,0 @@\n-DPDK_22 {\n-\tlocal: *;\n-};\n-\n-INTERNAL {\n-\tglobal:\n-\n-\totx2_cryptodev_driver_id;\n-\totx2_cpt_af_reg_read;\n-\totx2_cpt_af_reg_write;\n-\n-\tlocal: *;\n-};\ndiff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c\nindex b68ce6c0a4..8db9775d7b 100644\n--- a/drivers/event/cnxk/cn9k_eventdev.c\n+++ b/drivers/event/cnxk/cn9k_eventdev.c\n@@ -1127,6 +1127,16 @@ cn9k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n }\n \n static const struct rte_pci_id cn9k_pci_sso_map[] = {\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),\n \t{\n \t\t.vendor_id = 0,\n \t},\ndiff --git a/drivers/event/meson.build b/drivers/event/meson.build\nindex 63d6b410b2..d6706b57f7 100644\n--- a/drivers/event/meson.build\n+++ b/drivers/event/meson.build\n@@ -11,7 +11,6 @@ drivers = [\n 'dpaa',\n 'dpaa2',\n 'dsw',\n- 'octeontx2',\n 'opdl',\n 'skeleton',\n 'sw',\ndiff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build\ndeleted file mode 100644\nindex ce360af5f8..0000000000\n--- a/drivers/event/octeontx2/meson.build\n+++ /dev/null\n@@ -1,26 +0,0 @@\n-# SPDX-License-Identifier: BSD-3-Clause\n-# Copyright(C) 2019 Marvell International Ltd.\n-#\n-\n-if not is_linux or not dpdk_conf.get('RTE_ARCH_64')\n- build = false\n- reason = 'only supported on 64-bit Linux'\n- subdir_done()\n-endif\n-\n-sources = files(\n- 'otx2_worker.c',\n- 'otx2_worker_dual.c',\n- 'otx2_evdev.c',\n- 'otx2_evdev_adptr.c',\n- 'otx2_evdev_crypto_adptr.c',\n- 'otx2_evdev_irq.c',\n- 'otx2_evdev_selftest.c',\n- 'otx2_tim_evdev.c',\n- 'otx2_tim_worker.c',\n-)\n-\n-deps += ['bus_pci', 'common_octeontx2', 'crypto_octeontx2', 'mempool_octeontx2', 'net_octeontx2']\n-\n-includes += include_directories('../../crypto/octeontx2')\n-includes += include_directories('../../common/cpt')\ndiff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\ndeleted file mode 100644\nindex ccf28b678b..0000000000\n--- a/drivers/event/octeontx2/otx2_evdev.c\n+++ /dev/null\n@@ -1,1900 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <inttypes.h>\n-\n-#include <rte_bus_pci.h>\n-#include <rte_common.h>\n-#include <rte_eal.h>\n-#include <eventdev_pmd_pci.h>\n-#include <rte_kvargs.h>\n-#include <rte_mbuf_pool_ops.h>\n-#include <rte_pci.h>\n-\n-#include \"otx2_evdev.h\"\n-#include \"otx2_evdev_crypto_adptr_tx.h\"\n-#include \"otx2_evdev_stats.h\"\n-#include \"otx2_irq.h\"\n-#include \"otx2_tim_evdev.h\"\n-\n-static inline int\n-sso_get_msix_offsets(const struct rte_eventdev *event_dev)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuint8_t nb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct msix_offset_rsp *msix_rsp;\n-\tint i, rc;\n-\n-\t/* Get SSO and SSOW MSIX vector offsets */\n-\totx2_mbox_alloc_msg_msix_offset(mbox);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);\n-\n-\tfor (i = 0; i < nb_ports; i++)\n-\t\tdev->ssow_msixoff[i] = msix_rsp->ssow_msixoff[i];\n-\n-\tfor (i = 0; i < dev->nb_event_queues; i++)\n-\t\tdev->sso_msixoff[i] = msix_rsp->sso_msixoff[i];\n-\n-\treturn rc;\n-}\n-\n-void\n-sso_fastpath_fns_set(struct rte_eventdev *event_dev)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\t/* Single WS modes */\n-\tconst event_dequeue_t ssogws_deq[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_burst_t ssogws_deq_burst[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_burst_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_t ssogws_deq_timeout[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_timeout_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_burst_t\n-\t\tssogws_deq_timeout_burst[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\totx2_ssogws_deq_timeout_burst_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_t ssogws_deq_seg[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_deq_seg_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_burst_t\n-\t\tssogws_deq_seg_burst[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\totx2_ssogws_deq_seg_burst_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_t ssogws_deq_seg_timeout[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\totx2_ssogws_deq_seg_timeout_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_burst_t\n-\t\tssogws_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\t\totx2_ssogws_deq_seg_timeout_burst_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\n-\t/* Dual WS modes */\n-\tconst event_dequeue_t ssogws_dual_deq[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_burst_t\n-\t\tssogws_dual_deq_burst[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\totx2_ssogws_dual_deq_burst_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_t ssogws_dual_deq_timeout[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\totx2_ssogws_dual_deq_timeout_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_burst_t\n-\t\tssogws_dual_deq_timeout_burst[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\t\\\n-\t\t\totx2_ssogws_dual_deq_timeout_burst_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_t ssogws_dual_deq_seg[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] = otx2_ssogws_dual_deq_seg_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_burst_t\n-\t\tssogws_dual_deq_seg_burst[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\totx2_ssogws_dual_deq_seg_burst_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_t\n-\t\tssogws_dual_deq_seg_timeout[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\totx2_ssogws_dual_deq_seg_timeout_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\tconst event_dequeue_burst_t\n-\t\tssogws_dual_deq_seg_timeout_burst[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\totx2_ssogws_dual_deq_seg_timeout_burst_ ##name,\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\t};\n-\n-\t/* Tx modes */\n-\tconst event_tx_adapter_enqueue_t\n-\t\tssogws_tx_adptr_enq[2][2][2][2][2][2][2] = {\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\totx2_ssogws_tx_adptr_enq_ ## name,\n-\t\t\tSSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef T\n-\t\t};\n-\n-\tconst event_tx_adapter_enqueue_t\n-\t\tssogws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\totx2_ssogws_tx_adptr_enq_seg_ ## name,\n-\t\t\tSSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef T\n-\t\t};\n-\n-\tconst event_tx_adapter_enqueue_t\n-\t\tssogws_dual_tx_adptr_enq[2][2][2][2][2][2][2] = {\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\totx2_ssogws_dual_tx_adptr_enq_ ## name,\n-\t\t\tSSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef T\n-\t\t};\n-\n-\tconst event_tx_adapter_enqueue_t\n-\t\tssogws_dual_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-\t\t[f6][f5][f4][f3][f2][f1][f0] =\t\t\t\t\\\n-\t\t\totx2_ssogws_dual_tx_adptr_enq_seg_ ## name,\n-\t\t\tSSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef T\n-\t\t};\n-\n-\tevent_dev->enqueue\t\t\t= otx2_ssogws_enq;\n-\tevent_dev->enqueue_burst\t\t= otx2_ssogws_enq_burst;\n-\tevent_dev->enqueue_new_burst\t\t= otx2_ssogws_enq_new_burst;\n-\tevent_dev->enqueue_forward_burst\t= otx2_ssogws_enq_fwd_burst;\n-\tif (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {\n-\t\tevent_dev->dequeue\t\t= ssogws_deq_seg\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n-\t\tevent_dev->dequeue_burst\t= ssogws_deq_seg_burst\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n-\t\tif (dev->is_timeout_deq) {\n-\t\t\tevent_dev->dequeue\t= ssogws_deq_seg_timeout\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n-\t\t\tevent_dev->dequeue_burst\t=\n-\t\t\t\tssogws_deq_seg_timeout_burst\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n-\t\t}\n-\t} else {\n-\t\tevent_dev->dequeue\t\t\t= ssogws_deq\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n-\t\tevent_dev->dequeue_burst\t\t= ssogws_deq_burst\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n-\t\tif (dev->is_timeout_deq) {\n-\t\t\tevent_dev->dequeue\t\t= ssogws_deq_timeout\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n-\t\t\tevent_dev->dequeue_burst\t=\n-\t\t\t\tssogws_deq_timeout_burst\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n-\t\t}\n-\t}\n-\n-\tif (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {\n-\t\t/* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */\n-\t\tevent_dev->txa_enqueue = ssogws_tx_adptr_enq_seg\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n-\t} else {\n-\t\tevent_dev->txa_enqueue = ssogws_tx_adptr_enq\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)]\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)]\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)]\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n-\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n-\t}\n-\tevent_dev->ca_enqueue = otx2_ssogws_ca_enq;\n-\n-\tif (dev->dual_ws) {\n-\t\tevent_dev->enqueue\t\t= otx2_ssogws_dual_enq;\n-\t\tevent_dev->enqueue_burst\t= otx2_ssogws_dual_enq_burst;\n-\t\tevent_dev->enqueue_new_burst\t=\n-\t\t\t\t\totx2_ssogws_dual_enq_new_burst;\n-\t\tevent_dev->enqueue_forward_burst =\n-\t\t\t\t\totx2_ssogws_dual_enq_fwd_burst;\n-\n-\t\tif (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {\n-\t\t\tevent_dev->dequeue\t= ssogws_dual_deq_seg\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n-\t\t\tevent_dev->dequeue_burst = ssogws_dual_deq_seg_burst\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n-\t\t\tif (dev->is_timeout_deq) {\n-\t\t\t\tevent_dev->dequeue\t=\n-\t\t\t\t\tssogws_dual_deq_seg_timeout\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\t\tNIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\t\tNIX_RX_OFFLOAD_RSS_F)];\n-\t\t\t\tevent_dev->dequeue_burst =\n-\t\t\t\t\tssogws_dual_deq_seg_timeout_burst\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\t\tNIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\t\tNIX_RX_OFFLOAD_RSS_F)];\n-\t\t\t}\n-\t\t} else {\n-\t\t\tevent_dev->dequeue\t\t= ssogws_dual_deq\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n-\t\t\tevent_dev->dequeue_burst\t= ssogws_dual_deq_burst\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t\t[!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)];\n-\t\t\tif (dev->is_timeout_deq) {\n-\t\t\t\tevent_dev->dequeue\t=\n-\t\t\t\t\tssogws_dual_deq_timeout\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\t\tNIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\t\tNIX_RX_OFFLOAD_RSS_F)];\n-\t\t\t\tevent_dev->dequeue_burst =\n-\t\t\t\t\tssogws_dual_deq_timeout_burst\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\tNIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\t\tNIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t\t\t\t[!!(dev->rx_offloads &\n-\t\t\t\t\t\t\tNIX_RX_OFFLOAD_RSS_F)];\n-\t\t\t}\n-\t\t}\n-\n-\t\tif (dev->tx_offloads & NIX_TX_MULTI_SEG_F) {\n-\t\t/* [SEC] [TSMP] [MBUF_NOFF] [VLAN] [OL3_L4_CSUM] [L3_L4_CSUM] */\n-\t\t\tevent_dev->txa_enqueue = ssogws_dual_tx_adptr_enq_seg\n-\t\t\t\t[!!(dev->tx_offloads &\n-\t\t\t\t\t\tNIX_TX_OFFLOAD_SECURITY_F)]\n-\t\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]\n-\t\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]\n-\t\t\t\t[!!(dev->tx_offloads &\n-\t\t\t\t\t\tNIX_TX_OFFLOAD_MBUF_NOFF_F)]\n-\t\t\t\t[!!(dev->tx_offloads &\n-\t\t\t\t\t\tNIX_TX_OFFLOAD_VLAN_QINQ_F)]\n-\t\t\t\t[!!(dev->tx_offloads &\n-\t\t\t\t\t\tNIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n-\t\t\t\t[!!(dev->tx_offloads &\n-\t\t\t\t\t\tNIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n-\t\t} else {\n-\t\t\tevent_dev->txa_enqueue = ssogws_dual_tx_adptr_enq\n-\t\t\t\t[!!(dev->tx_offloads &\n-\t\t\t\t\t\tNIX_TX_OFFLOAD_SECURITY_F)]\n-\t\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)]\n-\t\t\t\t[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)]\n-\t\t\t\t[!!(dev->tx_offloads &\n-\t\t\t\t\t\tNIX_TX_OFFLOAD_MBUF_NOFF_F)]\n-\t\t\t\t[!!(dev->tx_offloads &\n-\t\t\t\t\t\tNIX_TX_OFFLOAD_VLAN_QINQ_F)]\n-\t\t\t\t[!!(dev->tx_offloads &\n-\t\t\t\t\t\tNIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n-\t\t\t\t[!!(dev->tx_offloads &\n-\t\t\t\t\t\tNIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n-\t\t}\n-\t\tevent_dev->ca_enqueue = otx2_ssogws_dual_ca_enq;\n-\t}\n-\n-\tevent_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;\n-\trte_mb();\n-}\n-\n-static void\n-otx2_sso_info_get(struct rte_eventdev *event_dev,\n-\t\t struct rte_event_dev_info *dev_info)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\n-\tdev_info->driver_name = RTE_STR(EVENTDEV_NAME_OCTEONTX2_PMD);\n-\tdev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns;\n-\tdev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns;\n-\tdev_info->max_event_queues = dev->max_event_queues;\n-\tdev_info->max_event_queue_flows = (1ULL << 20);\n-\tdev_info->max_event_queue_priority_levels = 8;\n-\tdev_info->max_event_priority_levels = 1;\n-\tdev_info->max_event_ports = dev->max_event_ports;\n-\tdev_info->max_event_port_dequeue_depth = 1;\n-\tdev_info->max_event_port_enqueue_depth = 1;\n-\tdev_info->max_num_events = dev->max_num_events;\n-\tdev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS |\n-\t\t\t\t\tRTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED |\n-\t\t\t\t\tRTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES |\n-\t\t\t\t\tRTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK |\n-\t\t\t\t\tRTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT |\n-\t\t\t\t\tRTE_EVENT_DEV_CAP_NONSEQ_MODE |\n-\t\t\t\t\tRTE_EVENT_DEV_CAP_CARRY_FLOW_ID |\n-\t\t\t\t\tRTE_EVENT_DEV_CAP_MAINTENANCE_FREE;\n-}\n-\n-static void\n-sso_port_link_modify(struct otx2_ssogws *ws, uint8_t queue, uint8_t enable)\n-{\n-\tuintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);\n-\tuint64_t val;\n-\n-\tval = queue;\n-\tval |= 0ULL << 12; /* SET 0 */\n-\tval |= 0x8000800080000000; /* Dont modify rest of the masks */\n-\tval |= (uint64_t)enable << 14; /* Enable/Disable Membership. */\n-\n-\totx2_write64(val, base + SSOW_LF_GWS_GRPMSK_CHG);\n-}\n-\n-static int\n-otx2_sso_port_link(struct rte_eventdev *event_dev, void *port,\n-\t\t const uint8_t queues[], const uint8_t priorities[],\n-\t\t uint16_t nb_links)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuint8_t port_id = 0;\n-\tuint16_t link;\n-\n-\tRTE_SET_USED(priorities);\n-\tfor (link = 0; link < nb_links; link++) {\n-\t\tif (dev->dual_ws) {\n-\t\t\tstruct otx2_ssogws_dual *ws = port;\n-\n-\t\t\tport_id = ws->port;\n-\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n-\t\t\t\t\t&ws->ws_state[0], queues[link], true);\n-\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n-\t\t\t\t\t&ws->ws_state[1], queues[link], true);\n-\t\t} else {\n-\t\t\tstruct otx2_ssogws *ws = port;\n-\n-\t\t\tport_id = ws->port;\n-\t\t\tsso_port_link_modify(ws, queues[link], true);\n-\t\t}\n-\t}\n-\tsso_func_trace(\"Port=%d nb_links=%d\", port_id, nb_links);\n-\n-\treturn (int)nb_links;\n-}\n-\n-static int\n-otx2_sso_port_unlink(struct rte_eventdev *event_dev, void *port,\n-\t\t uint8_t queues[], uint16_t nb_unlinks)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuint8_t port_id = 0;\n-\tuint16_t unlink;\n-\n-\tfor (unlink = 0; unlink < nb_unlinks; unlink++) {\n-\t\tif (dev->dual_ws) {\n-\t\t\tstruct otx2_ssogws_dual *ws = port;\n-\n-\t\t\tport_id = ws->port;\n-\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n-\t\t\t\t\t&ws->ws_state[0], queues[unlink],\n-\t\t\t\t\tfalse);\n-\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n-\t\t\t\t\t&ws->ws_state[1], queues[unlink],\n-\t\t\t\t\tfalse);\n-\t\t} else {\n-\t\t\tstruct otx2_ssogws *ws = port;\n-\n-\t\t\tport_id = ws->port;\n-\t\t\tsso_port_link_modify(ws, queues[unlink], false);\n-\t\t}\n-\t}\n-\tsso_func_trace(\"Port=%d nb_unlinks=%d\", port_id, nb_unlinks);\n-\n-\treturn (int)nb_unlinks;\n-}\n-\n-static int\n-sso_hw_lf_cfg(struct otx2_mbox *mbox, enum otx2_sso_lf_type type,\n-\t uint16_t nb_lf, uint8_t attach)\n-{\n-\tif (attach) {\n-\t\tstruct rsrc_attach_req *req;\n-\n-\t\treq = otx2_mbox_alloc_msg_attach_resources(mbox);\n-\t\tswitch (type) {\n-\t\tcase SSO_LF_GGRP:\n-\t\t\treq->sso = nb_lf;\n-\t\t\tbreak;\n-\t\tcase SSO_LF_GWS:\n-\t\t\treq->ssow = nb_lf;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\treq->modify = true;\n-\t\tif (otx2_mbox_process(mbox) < 0)\n-\t\t\treturn -EIO;\n-\t} else {\n-\t\tstruct rsrc_detach_req *req;\n-\n-\t\treq = otx2_mbox_alloc_msg_detach_resources(mbox);\n-\t\tswitch (type) {\n-\t\tcase SSO_LF_GGRP:\n-\t\t\treq->sso = true;\n-\t\t\tbreak;\n-\t\tcase SSO_LF_GWS:\n-\t\t\treq->ssow = true;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\treq->partial = true;\n-\t\tif (otx2_mbox_process(mbox) < 0)\n-\t\t\treturn -EIO;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,\n-\t enum otx2_sso_lf_type type, uint16_t nb_lf, uint8_t alloc)\n-{\n-\tvoid *rsp;\n-\tint rc;\n-\n-\tif (alloc) {\n-\t\tswitch (type) {\n-\t\tcase SSO_LF_GGRP:\n-\t\t\t{\n-\t\t\tstruct sso_lf_alloc_req *req_ggrp;\n-\t\t\treq_ggrp = otx2_mbox_alloc_msg_sso_lf_alloc(mbox);\n-\t\t\treq_ggrp->hwgrps = nb_lf;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase SSO_LF_GWS:\n-\t\t\t{\n-\t\t\tstruct ssow_lf_alloc_req *req_hws;\n-\t\t\treq_hws = otx2_mbox_alloc_msg_ssow_lf_alloc(mbox);\n-\t\t\treq_hws->hws = nb_lf;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t} else {\n-\t\tswitch (type) {\n-\t\tcase SSO_LF_GGRP:\n-\t\t\t{\n-\t\t\tstruct sso_lf_free_req *req_ggrp;\n-\t\t\treq_ggrp = otx2_mbox_alloc_msg_sso_lf_free(mbox);\n-\t\t\treq_ggrp->hwgrps = nb_lf;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase SSO_LF_GWS:\n-\t\t\t{\n-\t\t\tstruct ssow_lf_free_req *req_hws;\n-\t\t\treq_hws = otx2_mbox_alloc_msg_ssow_lf_free(mbox);\n-\t\t\treq_hws->hws = nb_lf;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\trc = otx2_mbox_process_msg_tmo(mbox, (void **)&rsp, ~0);\n-\tif (rc < 0)\n-\t\treturn rc;\n-\n-\tif (alloc && type == SSO_LF_GGRP) {\n-\t\tstruct sso_lf_alloc_rsp *rsp_ggrp = rsp;\n-\n-\t\tdev->xaq_buf_size = rsp_ggrp->xaq_buf_size;\n-\t\tdev->xae_waes = rsp_ggrp->xaq_wq_entries;\n-\t\tdev->iue = rsp_ggrp->in_unit_entries;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static void\n-otx2_sso_port_release(void *port)\n-{\n-\tstruct otx2_ssogws_cookie *gws_cookie = ssogws_get_cookie(port);\n-\tstruct otx2_sso_evdev *dev;\n-\tint i;\n-\n-\tif (!gws_cookie->configured)\n-\t\tgoto free;\n-\n-\tdev = sso_pmd_priv(gws_cookie->event_dev);\n-\tif (dev->dual_ws) {\n-\t\tstruct otx2_ssogws_dual *ws = port;\n-\n-\t\tfor (i = 0; i < dev->nb_event_queues; i++) {\n-\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n-\t\t\t\t\t &ws->ws_state[0], i, false);\n-\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n-\t\t\t\t\t &ws->ws_state[1], i, false);\n-\t\t}\n-\t\tmemset(ws, 0, sizeof(*ws));\n-\t} else {\n-\t\tstruct otx2_ssogws *ws = port;\n-\n-\t\tfor (i = 0; i < dev->nb_event_queues; i++)\n-\t\t\tsso_port_link_modify(ws, i, false);\n-\t\tmemset(ws, 0, sizeof(*ws));\n-\t}\n-\n-\tmemset(gws_cookie, 0, sizeof(*gws_cookie));\n-\n-free:\n-\trte_free(gws_cookie);\n-}\n-\n-static void\n-otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)\n-{\n-\tRTE_SET_USED(event_dev);\n-\tRTE_SET_USED(queue_id);\n-}\n-\n-static void\n-sso_restore_links(const struct rte_eventdev *event_dev)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuint16_t *links_map;\n-\tint i, j;\n-\n-\tfor (i = 0; i < dev->nb_event_ports; i++) {\n-\t\tlinks_map = event_dev->data->links_map;\n-\t\t/* Point links_map to this port specific area */\n-\t\tlinks_map += (i * RTE_EVENT_MAX_QUEUES_PER_DEV);\n-\t\tif (dev->dual_ws) {\n-\t\t\tstruct otx2_ssogws_dual *ws;\n-\n-\t\t\tws = event_dev->data->ports[i];\n-\t\t\tfor (j = 0; j < dev->nb_event_queues; j++) {\n-\t\t\t\tif (links_map[j] == 0xdead)\n-\t\t\t\t\tcontinue;\n-\t\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n-\t\t\t\t\t\t&ws->ws_state[0], j, true);\n-\t\t\t\tsso_port_link_modify((struct otx2_ssogws *)\n-\t\t\t\t\t\t&ws->ws_state[1], j, true);\n-\t\t\t\tsso_func_trace(\"Restoring port %d queue %d \"\n-\t\t\t\t\t\t\"link\", i, j);\n-\t\t\t}\n-\t\t} else {\n-\t\t\tstruct otx2_ssogws *ws;\n-\n-\t\t\tws = event_dev->data->ports[i];\n-\t\t\tfor (j = 0; j < dev->nb_event_queues; j++) {\n-\t\t\t\tif (links_map[j] == 0xdead)\n-\t\t\t\t\tcontinue;\n-\t\t\t\tsso_port_link_modify(ws, j, true);\n-\t\t\t\tsso_func_trace(\"Restoring port %d queue %d \"\n-\t\t\t\t\t\t\"link\", i, j);\n-\t\t\t}\n-\t\t}\n-\t}\n-}\n-\n-static void\n-sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)\n-{\n-\tws->tag_op\t\t= base + SSOW_LF_GWS_TAG;\n-\tws->wqp_op\t\t= base + SSOW_LF_GWS_WQP;\n-\tws->getwrk_op\t\t= base + SSOW_LF_GWS_OP_GET_WORK;\n-\tws->swtag_flush_op\t= base + SSOW_LF_GWS_OP_SWTAG_FLUSH;\n-\tws->swtag_norm_op\t= base + SSOW_LF_GWS_OP_SWTAG_NORM;\n-\tws->swtag_desched_op\t= base + SSOW_LF_GWS_OP_SWTAG_DESCHED;\n-}\n-\n-static int\n-sso_configure_dual_ports(const struct rte_eventdev *event_dev)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tuint8_t vws = 0;\n-\tuint8_t nb_lf;\n-\tint i, rc;\n-\n-\totx2_sso_dbg(\"Configuring event ports %d\", dev->nb_event_ports);\n-\n-\tnb_lf = dev->nb_event_ports * 2;\n-\t/* Ask AF to attach required LFs. */\n-\trc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to attach SSO GWS LF\");\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tif (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {\n-\t\tsso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);\n-\t\totx2_err(\"Failed to init SSO GWS LF\");\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tfor (i = 0; i < dev->nb_event_ports; i++) {\n-\t\tstruct otx2_ssogws_cookie *gws_cookie;\n-\t\tstruct otx2_ssogws_dual *ws;\n-\t\tuintptr_t base;\n-\n-\t\tif (event_dev->data->ports[i] != NULL) {\n-\t\t\tws = event_dev->data->ports[i];\n-\t\t} else {\n-\t\t\t/* Allocate event port memory */\n-\t\t\tws = rte_zmalloc_socket(\"otx2_sso_ws\",\n-\t\t\t\t\tsizeof(struct otx2_ssogws_dual) +\n-\t\t\t\t\tRTE_CACHE_LINE_SIZE,\n-\t\t\t\t\tRTE_CACHE_LINE_SIZE,\n-\t\t\t\t\tevent_dev->data->socket_id);\n-\t\t\tif (ws == NULL) {\n-\t\t\t\totx2_err(\"Failed to alloc memory for port=%d\",\n-\t\t\t\t\t i);\n-\t\t\t\trc = -ENOMEM;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\n-\t\t\t/* First cache line is reserved for cookie */\n-\t\t\tws = (struct otx2_ssogws_dual *)\n-\t\t\t\t((uint8_t *)ws + RTE_CACHE_LINE_SIZE);\n-\t\t}\n-\n-\t\tws->port = i;\n-\t\tbase = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);\n-\t\tsso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[0], base);\n-\t\tws->base[0] = base;\n-\t\tvws++;\n-\n-\t\tbase = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | vws << 12);\n-\t\tsso_set_port_ops((struct otx2_ssogws *)&ws->ws_state[1], base);\n-\t\tws->base[1] = base;\n-\t\tvws++;\n-\n-\t\tgws_cookie = ssogws_get_cookie(ws);\n-\t\tgws_cookie->event_dev = event_dev;\n-\t\tgws_cookie->configured = 1;\n-\n-\t\tevent_dev->data->ports[i] = ws;\n-\t}\n-\n-\tif (rc < 0) {\n-\t\tsso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);\n-\t\tsso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static int\n-sso_configure_ports(const struct rte_eventdev *event_dev)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tuint8_t nb_lf;\n-\tint i, rc;\n-\n-\totx2_sso_dbg(\"Configuring event ports %d\", dev->nb_event_ports);\n-\n-\tnb_lf = dev->nb_event_ports;\n-\t/* Ask AF to attach required LFs. */\n-\trc = sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, true);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to attach SSO GWS LF\");\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tif (sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, true) < 0) {\n-\t\tsso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);\n-\t\totx2_err(\"Failed to init SSO GWS LF\");\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tfor (i = 0; i < nb_lf; i++) {\n-\t\tstruct otx2_ssogws_cookie *gws_cookie;\n-\t\tstruct otx2_ssogws *ws;\n-\t\tuintptr_t base;\n-\n-\t\tif (event_dev->data->ports[i] != NULL) {\n-\t\t\tws = event_dev->data->ports[i];\n-\t\t} else {\n-\t\t\t/* Allocate event port memory */\n-\t\t\tws = rte_zmalloc_socket(\"otx2_sso_ws\",\n-\t\t\t\t\t\tsizeof(struct otx2_ssogws) +\n-\t\t\t\t\t\tRTE_CACHE_LINE_SIZE,\n-\t\t\t\t\t\tRTE_CACHE_LINE_SIZE,\n-\t\t\t\t\t\tevent_dev->data->socket_id);\n-\t\t\tif (ws == NULL) {\n-\t\t\t\totx2_err(\"Failed to alloc memory for port=%d\",\n-\t\t\t\t\t i);\n-\t\t\t\trc = -ENOMEM;\n-\t\t\t\tbreak;\n-\t\t\t}\n-\n-\t\t\t/* First cache line is reserved for cookie */\n-\t\t\tws = (struct otx2_ssogws *)\n-\t\t\t\t((uint8_t *)ws + RTE_CACHE_LINE_SIZE);\n-\t\t}\n-\n-\t\tws->port = i;\n-\t\tbase = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);\n-\t\tsso_set_port_ops(ws, base);\n-\t\tws->base = base;\n-\n-\t\tgws_cookie = ssogws_get_cookie(ws);\n-\t\tgws_cookie->event_dev = event_dev;\n-\t\tgws_cookie->configured = 1;\n-\n-\t\tevent_dev->data->ports[i] = ws;\n-\t}\n-\n-\tif (rc < 0) {\n-\t\tsso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);\n-\t\tsso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static int\n-sso_configure_queues(const struct rte_eventdev *event_dev)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tuint8_t nb_lf;\n-\tint rc;\n-\n-\totx2_sso_dbg(\"Configuring event queues %d\", dev->nb_event_queues);\n-\n-\tnb_lf = dev->nb_event_queues;\n-\t/* Ask AF to attach required LFs. */\n-\trc = sso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, true);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to attach SSO GGRP LF\");\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tif (sso_lf_cfg(dev, mbox, SSO_LF_GGRP, nb_lf, true) < 0) {\n-\t\tsso_hw_lf_cfg(mbox, SSO_LF_GGRP, nb_lf, false);\n-\t\totx2_err(\"Failed to init SSO GGRP LF\");\n-\t\treturn -ENODEV;\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static int\n-sso_xaq_allocate(struct otx2_sso_evdev *dev)\n-{\n-\tconst struct rte_memzone *mz;\n-\tstruct npa_aura_s *aura;\n-\tstatic int reconfig_cnt;\n-\tchar pool_name[RTE_MEMZONE_NAMESIZE];\n-\tuint32_t xaq_cnt;\n-\tint rc;\n-\n-\tif (dev->xaq_pool)\n-\t\trte_mempool_free(dev->xaq_pool);\n-\n-\t/*\n-\t * Allocate memory for Add work backpressure.\n-\t */\n-\tmz = rte_memzone_lookup(OTX2_SSO_FC_NAME);\n-\tif (mz == NULL)\n-\t\tmz = rte_memzone_reserve_aligned(OTX2_SSO_FC_NAME,\n-\t\t\t\t\t\t OTX2_ALIGN +\n-\t\t\t\t\t\t sizeof(struct npa_aura_s),\n-\t\t\t\t\t\t rte_socket_id(),\n-\t\t\t\t\t\t RTE_MEMZONE_IOVA_CONTIG,\n-\t\t\t\t\t\t OTX2_ALIGN);\n-\tif (mz == NULL) {\n-\t\totx2_err(\"Failed to allocate mem for fcmem\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tdev->fc_iova = mz->iova;\n-\tdev->fc_mem = mz->addr;\n-\t*dev->fc_mem = 0;\n-\taura = (struct npa_aura_s *)((uintptr_t)dev->fc_mem + OTX2_ALIGN);\n-\tmemset(aura, 0, sizeof(struct npa_aura_s));\n-\n-\taura->fc_ena = 1;\n-\taura->fc_addr = dev->fc_iova;\n-\taura->fc_hyst_bits = 0; /* Store count on all updates */\n-\n-\t/* Taken from HRM 14.3.3(4) */\n-\txaq_cnt = dev->nb_event_queues * OTX2_SSO_XAQ_CACHE_CNT;\n-\tif (dev->xae_cnt)\n-\t\txaq_cnt += dev->xae_cnt / dev->xae_waes;\n-\telse if (dev->adptr_xae_cnt)\n-\t\txaq_cnt += (dev->adptr_xae_cnt / dev->xae_waes) +\n-\t\t\t(OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);\n-\telse\n-\t\txaq_cnt += (dev->iue / dev->xae_waes) +\n-\t\t\t(OTX2_SSO_XAQ_SLACK * dev->nb_event_queues);\n-\n-\totx2_sso_dbg(\"Configuring %d xaq buffers\", xaq_cnt);\n-\t/* Setup XAQ based on number of nb queues. */\n-\tsnprintf(pool_name, 30, \"otx2_xaq_buf_pool_%d\", reconfig_cnt);\n-\tdev->xaq_pool = (void *)rte_mempool_create_empty(pool_name,\n-\t\t\txaq_cnt, dev->xaq_buf_size, 0, 0,\n-\t\t\trte_socket_id(), 0);\n-\n-\tif (dev->xaq_pool == NULL) {\n-\t\totx2_err(\"Unable to create empty mempool.\");\n-\t\trte_memzone_free(mz);\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\trc = rte_mempool_set_ops_byname(dev->xaq_pool,\n-\t\t\t\t\trte_mbuf_platform_mempool_ops(), aura);\n-\tif (rc != 0) {\n-\t\totx2_err(\"Unable to set xaqpool ops.\");\n-\t\tgoto alloc_fail;\n-\t}\n-\n-\trc = rte_mempool_populate_default(dev->xaq_pool);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Unable to set populate xaqpool.\");\n-\t\tgoto alloc_fail;\n-\t}\n-\treconfig_cnt++;\n-\t/* When SW does addwork (enqueue) check if there is space in XAQ by\n-\t * comparing fc_addr above against the xaq_lmt calculated below.\n-\t * There should be a minimum headroom (OTX2_SSO_XAQ_SLACK / 2) for SSO\n-\t * to request XAQ to cache them even before enqueue is called.\n-\t */\n-\tdev->xaq_lmt = xaq_cnt - (OTX2_SSO_XAQ_SLACK / 2 *\n-\t\t\t\t dev->nb_event_queues);\n-\tdev->nb_xaq_cfg = xaq_cnt;\n-\n-\treturn 0;\n-alloc_fail:\n-\trte_mempool_free(dev->xaq_pool);\n-\trte_memzone_free(mz);\n-\treturn rc;\n-}\n-\n-static int\n-sso_ggrp_alloc_xaq(struct otx2_sso_evdev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct sso_hw_setconfig *req;\n-\n-\totx2_sso_dbg(\"Configuring XAQ for GGRPs\");\n-\treq = otx2_mbox_alloc_msg_sso_hw_setconfig(mbox);\n-\treq->npa_pf_func = otx2_npa_pf_func_get();\n-\treq->npa_aura_id = npa_lf_aura_handle_to_aura(dev->xaq_pool->pool_id);\n-\treq->hwgrps = dev->nb_event_queues;\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static int\n-sso_ggrp_free_xaq(struct otx2_sso_evdev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct sso_release_xaq *req;\n-\n-\totx2_sso_dbg(\"Freeing XAQ for GGRPs\");\n-\treq = otx2_mbox_alloc_msg_sso_hw_release_xaq_aura(mbox);\n-\treq->hwgrps = dev->nb_event_queues;\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static void\n-sso_lf_teardown(struct otx2_sso_evdev *dev,\n-\t\tenum otx2_sso_lf_type lf_type)\n-{\n-\tuint8_t nb_lf;\n-\n-\tswitch (lf_type) {\n-\tcase SSO_LF_GGRP:\n-\t\tnb_lf = dev->nb_event_queues;\n-\t\tbreak;\n-\tcase SSO_LF_GWS:\n-\t\tnb_lf = dev->nb_event_ports;\n-\t\tnb_lf *= dev->dual_ws ? 2 : 1;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn;\n-\t}\n-\n-\tsso_lf_cfg(dev, dev->mbox, lf_type, nb_lf, false);\n-\tsso_hw_lf_cfg(dev->mbox, lf_type, nb_lf, false);\n-}\n-\n-static int\n-otx2_sso_configure(const struct rte_eventdev *event_dev)\n-{\n-\tstruct rte_event_dev_config *conf = &event_dev->data->dev_conf;\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuint32_t deq_tmo_ns;\n-\tint rc;\n-\n-\tsso_func_trace();\n-\tdeq_tmo_ns = conf->dequeue_timeout_ns;\n-\n-\tif (deq_tmo_ns == 0)\n-\t\tdeq_tmo_ns = dev->min_dequeue_timeout_ns;\n-\n-\tif (deq_tmo_ns < dev->min_dequeue_timeout_ns ||\n-\t deq_tmo_ns > dev->max_dequeue_timeout_ns) {\n-\t\totx2_err(\"Unsupported dequeue timeout requested\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (conf->event_dev_cfg & RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT)\n-\t\tdev->is_timeout_deq = 1;\n-\n-\tdev->deq_tmo_ns = deq_tmo_ns;\n-\n-\tif (conf->nb_event_ports > dev->max_event_ports ||\n-\t conf->nb_event_queues > dev->max_event_queues) {\n-\t\totx2_err(\"Unsupported event queues/ports requested\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (conf->nb_event_port_dequeue_depth > 1) {\n-\t\totx2_err(\"Unsupported event port deq depth requested\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (conf->nb_event_port_enqueue_depth > 1) {\n-\t\totx2_err(\"Unsupported event port enq depth requested\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (dev->configured)\n-\t\tsso_unregister_irqs(event_dev);\n-\n-\tif (dev->nb_event_queues) {\n-\t\t/* Finit any previous queues. */\n-\t\tsso_lf_teardown(dev, SSO_LF_GGRP);\n-\t}\n-\tif (dev->nb_event_ports) {\n-\t\t/* Finit any previous ports. */\n-\t\tsso_lf_teardown(dev, SSO_LF_GWS);\n-\t}\n-\n-\tdev->nb_event_queues = conf->nb_event_queues;\n-\tdev->nb_event_ports = conf->nb_event_ports;\n-\n-\tif (dev->dual_ws)\n-\t\trc = sso_configure_dual_ports(event_dev);\n-\telse\n-\t\trc = sso_configure_ports(event_dev);\n-\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to configure event ports\");\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tif (sso_configure_queues(event_dev) < 0) {\n-\t\totx2_err(\"Failed to configure event queues\");\n-\t\trc = -ENODEV;\n-\t\tgoto teardown_hws;\n-\t}\n-\n-\tif (sso_xaq_allocate(dev) < 0) {\n-\t\trc = -ENOMEM;\n-\t\tgoto teardown_hwggrp;\n-\t}\n-\n-\t/* Restore any prior port-queue mapping. */\n-\tsso_restore_links(event_dev);\n-\trc = sso_ggrp_alloc_xaq(dev);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to alloc xaq to ggrp %d\", rc);\n-\t\tgoto teardown_hwggrp;\n-\t}\n-\n-\trc = sso_get_msix_offsets(event_dev);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to get msix offsets %d\", rc);\n-\t\tgoto teardown_hwggrp;\n-\t}\n-\n-\trc = sso_register_irqs(event_dev);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to register irq %d\", rc);\n-\t\tgoto teardown_hwggrp;\n-\t}\n-\n-\tdev->configured = 1;\n-\trte_mb();\n-\n-\treturn 0;\n-teardown_hwggrp:\n-\tsso_lf_teardown(dev, SSO_LF_GGRP);\n-teardown_hws:\n-\tsso_lf_teardown(dev, SSO_LF_GWS);\n-\tdev->nb_event_queues = 0;\n-\tdev->nb_event_ports = 0;\n-\tdev->configured = 0;\n-\treturn rc;\n-}\n-\n-static void\n-otx2_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,\n-\t\t\tstruct rte_event_queue_conf *queue_conf)\n-{\n-\tRTE_SET_USED(event_dev);\n-\tRTE_SET_USED(queue_id);\n-\n-\tqueue_conf->nb_atomic_flows = (1ULL << 20);\n-\tqueue_conf->nb_atomic_order_sequences = (1ULL << 20);\n-\tqueue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ALL_TYPES;\n-\tqueue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;\n-}\n-\n-static int\n-otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,\n-\t\t const struct rte_event_queue_conf *queue_conf)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct sso_grp_priority *req;\n-\tint rc;\n-\n-\tsso_func_trace(\"Queue=%d prio=%d\", queue_id, queue_conf->priority);\n-\n-\treq = otx2_mbox_alloc_msg_sso_grp_set_priority(dev->mbox);\n-\treq->grp = queue_id;\n-\treq->weight = 0xFF;\n-\treq->affinity = 0xFF;\n-\t/* Normalize <0-255> to <0-7> */\n-\treq->priority = queue_conf->priority / 32;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to set priority queue=%d\", queue_id);\n-\t\treturn rc;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static void\n-otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,\n-\t\t struct rte_event_port_conf *port_conf)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\n-\tRTE_SET_USED(port_id);\n-\tport_conf->new_event_threshold = dev->max_num_events;\n-\tport_conf->dequeue_depth = 1;\n-\tport_conf->enqueue_depth = 1;\n-}\n-\n-static int\n-otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,\n-\t\t const struct rte_event_port_conf *port_conf)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};\n-\tuint64_t val;\n-\tuint16_t q;\n-\n-\tsso_func_trace(\"Port=%d\", port_id);\n-\tRTE_SET_USED(port_conf);\n-\n-\tif (event_dev->data->ports[port_id] == NULL) {\n-\t\totx2_err(\"Invalid port Id %d\", port_id);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tfor (q = 0; q < dev->nb_event_queues; q++) {\n-\t\tgrps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);\n-\t\tif (grps_base[q] == 0) {\n-\t\t\totx2_err(\"Failed to get grp[%d] base addr\", q);\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\t/* Set get_work timeout for HWS */\n-\tval = NSEC2USEC(dev->deq_tmo_ns) - 1;\n-\n-\tif (dev->dual_ws) {\n-\t\tstruct otx2_ssogws_dual *ws = event_dev->data->ports[port_id];\n-\n-\t\trte_memcpy(ws->grps_base, grps_base,\n-\t\t\t sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);\n-\t\tws->fc_mem = dev->fc_mem;\n-\t\tws->xaq_lmt = dev->xaq_lmt;\n-\t\tws->tstamp = dev->tstamp;\n-\t\totx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(\n-\t\t\t ws->ws_state[0].getwrk_op) + SSOW_LF_GWS_NW_TIM);\n-\t\totx2_write64(val, OTX2_SSOW_GET_BASE_ADDR(\n-\t\t\t ws->ws_state[1].getwrk_op) + SSOW_LF_GWS_NW_TIM);\n-\t} else {\n-\t\tstruct otx2_ssogws *ws = event_dev->data->ports[port_id];\n-\t\tuintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);\n-\n-\t\trte_memcpy(ws->grps_base, grps_base,\n-\t\t\t sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);\n-\t\tws->fc_mem = dev->fc_mem;\n-\t\tws->xaq_lmt = dev->xaq_lmt;\n-\t\tws->tstamp = dev->tstamp;\n-\t\totx2_write64(val, base + SSOW_LF_GWS_NW_TIM);\n-\t}\n-\n-\totx2_sso_dbg(\"Port=%d ws=%p\", port_id, event_dev->data->ports[port_id]);\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,\n-\t\t uint64_t *tmo_ticks)\n-{\n-\tRTE_SET_USED(event_dev);\n-\t*tmo_ticks = NSEC2TICK(ns, rte_get_timer_hz());\n-\n-\treturn 0;\n-}\n-\n-static void\n-ssogws_dump(struct otx2_ssogws *ws, FILE *f)\n-{\n-\tuintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);\n-\n-\tfprintf(f, \"SSOW_LF_GWS Base addr 0x%\" PRIx64 \"\\n\", (uint64_t)base);\n-\tfprintf(f, \"SSOW_LF_GWS_LINKS 0x%\" PRIx64 \"\\n\",\n-\t\totx2_read64(base + SSOW_LF_GWS_LINKS));\n-\tfprintf(f, \"SSOW_LF_GWS_PENDWQP 0x%\" PRIx64 \"\\n\",\n-\t\totx2_read64(base + SSOW_LF_GWS_PENDWQP));\n-\tfprintf(f, \"SSOW_LF_GWS_PENDSTATE 0x%\" PRIx64 \"\\n\",\n-\t\totx2_read64(base + SSOW_LF_GWS_PENDSTATE));\n-\tfprintf(f, \"SSOW_LF_GWS_NW_TIM 0x%\" PRIx64 \"\\n\",\n-\t\totx2_read64(base + SSOW_LF_GWS_NW_TIM));\n-\tfprintf(f, \"SSOW_LF_GWS_TAG 0x%\" PRIx64 \"\\n\",\n-\t\totx2_read64(base + SSOW_LF_GWS_TAG));\n-\tfprintf(f, \"SSOW_LF_GWS_WQP 0x%\" PRIx64 \"\\n\",\n-\t\totx2_read64(base + SSOW_LF_GWS_TAG));\n-\tfprintf(f, \"SSOW_LF_GWS_SWTP 0x%\" PRIx64 \"\\n\",\n-\t\totx2_read64(base + SSOW_LF_GWS_SWTP));\n-\tfprintf(f, \"SSOW_LF_GWS_PENDTAG 0x%\" PRIx64 \"\\n\",\n-\t\totx2_read64(base + SSOW_LF_GWS_PENDTAG));\n-}\n-\n-static void\n-ssoggrp_dump(uintptr_t base, FILE *f)\n-{\n-\tfprintf(f, \"SSO_LF_GGRP Base addr 0x%\" PRIx64 \"\\n\", (uint64_t)base);\n-\tfprintf(f, \"SSO_LF_GGRP_QCTL 0x%\" PRIx64 \"\\n\",\n-\t\totx2_read64(base + SSO_LF_GGRP_QCTL));\n-\tfprintf(f, \"SSO_LF_GGRP_XAQ_CNT 0x%\" PRIx64 \"\\n\",\n-\t\totx2_read64(base + SSO_LF_GGRP_XAQ_CNT));\n-\tfprintf(f, \"SSO_LF_GGRP_INT_THR 0x%\" PRIx64 \"\\n\",\n-\t\totx2_read64(base + SSO_LF_GGRP_INT_THR));\n-\tfprintf(f, \"SSO_LF_GGRP_INT_CNT 0x%\" PRIX64 \"\\n\",\n-\t\totx2_read64(base + SSO_LF_GGRP_INT_CNT));\n-\tfprintf(f, \"SSO_LF_GGRP_AQ_CNT 0x%\" PRIX64 \"\\n\",\n-\t\totx2_read64(base + SSO_LF_GGRP_AQ_CNT));\n-\tfprintf(f, \"SSO_LF_GGRP_AQ_THR 0x%\" PRIX64 \"\\n\",\n-\t\totx2_read64(base + SSO_LF_GGRP_AQ_THR));\n-\tfprintf(f, \"SSO_LF_GGRP_MISC_CNT 0x%\" PRIx64 \"\\n\",\n-\t\totx2_read64(base + SSO_LF_GGRP_MISC_CNT));\n-}\n-\n-static void\n-otx2_sso_dump(struct rte_eventdev *event_dev, FILE *f)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuint8_t queue;\n-\tuint8_t port;\n-\n-\tfprintf(f, \"[%s] SSO running in [%s] mode\\n\", __func__, dev->dual_ws ?\n-\t\t\"dual_ws\" : \"single_ws\");\n-\t/* Dump SSOW registers */\n-\tfor (port = 0; port < dev->nb_event_ports; port++) {\n-\t\tif (dev->dual_ws) {\n-\t\t\tstruct otx2_ssogws_dual *ws =\n-\t\t\t\tevent_dev->data->ports[port];\n-\n-\t\t\tfprintf(f, \"[%s] SSO dual workslot[%d] vws[%d] dump\\n\",\n-\t\t\t\t__func__, port, 0);\n-\t\t\tssogws_dump((struct otx2_ssogws *)&ws->ws_state[0], f);\n-\t\t\tfprintf(f, \"[%s]SSO dual workslot[%d] vws[%d] dump\\n\",\n-\t\t\t\t__func__, port, 1);\n-\t\t\tssogws_dump((struct otx2_ssogws *)&ws->ws_state[1], f);\n-\t\t} else {\n-\t\t\tfprintf(f, \"[%s]SSO single workslot[%d] dump\\n\",\n-\t\t\t\t__func__, port);\n-\t\t\tssogws_dump(event_dev->data->ports[port], f);\n-\t\t}\n-\t}\n-\n-\t/* Dump SSO registers */\n-\tfor (queue = 0; queue < dev->nb_event_queues; queue++) {\n-\t\tfprintf(f, \"[%s]SSO group[%d] dump\\n\", __func__, queue);\n-\t\tif (dev->dual_ws) {\n-\t\t\tstruct otx2_ssogws_dual *ws = event_dev->data->ports[0];\n-\t\t\tssoggrp_dump(ws->grps_base[queue], f);\n-\t\t} else {\n-\t\t\tstruct otx2_ssogws *ws = event_dev->data->ports[0];\n-\t\t\tssoggrp_dump(ws->grps_base[queue], f);\n-\t\t}\n-\t}\n-}\n-\n-static void\n-otx2_handle_event(void *arg, struct rte_event event)\n-{\n-\tstruct rte_eventdev *event_dev = arg;\n-\n-\tif (event_dev->dev_ops->dev_stop_flush != NULL)\n-\t\tevent_dev->dev_ops->dev_stop_flush(event_dev->data->dev_id,\n-\t\t\t\tevent, event_dev->data->dev_stop_flush_arg);\n-}\n-\n-static void\n-sso_qos_cfg(struct rte_eventdev *event_dev)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tstruct sso_grp_qos_cfg *req;\n-\tuint16_t i;\n-\n-\tfor (i = 0; i < dev->qos_queue_cnt; i++) {\n-\t\tuint8_t xaq_prcnt = dev->qos_parse_data[i].xaq_prcnt;\n-\t\tuint8_t iaq_prcnt = dev->qos_parse_data[i].iaq_prcnt;\n-\t\tuint8_t taq_prcnt = dev->qos_parse_data[i].taq_prcnt;\n-\n-\t\tif (dev->qos_parse_data[i].queue >= dev->nb_event_queues)\n-\t\t\tcontinue;\n-\n-\t\treq = otx2_mbox_alloc_msg_sso_grp_qos_config(dev->mbox);\n-\t\treq->xaq_limit = (dev->nb_xaq_cfg *\n-\t\t\t\t (xaq_prcnt ? xaq_prcnt : 100)) / 100;\n-\t\treq->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK *\n-\t\t\t\t(iaq_prcnt ? iaq_prcnt : 100)) / 100;\n-\t\treq->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK *\n-\t\t\t\t(taq_prcnt ? taq_prcnt : 100)) / 100;\n-\t}\n-\n-\tif (dev->qos_queue_cnt)\n-\t\totx2_mbox_process(dev->mbox);\n-}\n-\n-static void\n-sso_cleanup(struct rte_eventdev *event_dev, uint8_t enable)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuint16_t i;\n-\n-\tfor (i = 0; i < dev->nb_event_ports; i++) {\n-\t\tif (dev->dual_ws) {\n-\t\t\tstruct otx2_ssogws_dual *ws;\n-\n-\t\t\tws = event_dev->data->ports[i];\n-\t\t\tssogws_reset((struct otx2_ssogws *)&ws->ws_state[0]);\n-\t\t\tssogws_reset((struct otx2_ssogws *)&ws->ws_state[1]);\n-\t\t\tws->swtag_req = 0;\n-\t\t\tws->vws = 0;\n-\t\t\tws->fc_mem = dev->fc_mem;\n-\t\t\tws->xaq_lmt = dev->xaq_lmt;\n-\t\t} else {\n-\t\t\tstruct otx2_ssogws *ws;\n-\n-\t\t\tws = event_dev->data->ports[i];\n-\t\t\tssogws_reset(ws);\n-\t\t\tws->swtag_req = 0;\n-\t\t\tws->fc_mem = dev->fc_mem;\n-\t\t\tws->xaq_lmt = dev->xaq_lmt;\n-\t\t}\n-\t}\n-\n-\trte_mb();\n-\tif (dev->dual_ws) {\n-\t\tstruct otx2_ssogws_dual *ws = event_dev->data->ports[0];\n-\t\tstruct otx2_ssogws temp_ws;\n-\n-\t\tmemcpy(&temp_ws, &ws->ws_state[0],\n-\t\t sizeof(struct otx2_ssogws_state));\n-\t\tfor (i = 0; i < dev->nb_event_queues; i++) {\n-\t\t\t/* Consume all the events through HWS0 */\n-\t\t\tssogws_flush_events(&temp_ws, i, ws->grps_base[i],\n-\t\t\t\t\t otx2_handle_event, event_dev);\n-\t\t\t/* Enable/Disable SSO GGRP */\n-\t\t\totx2_write64(enable, ws->grps_base[i] +\n-\t\t\t\t SSO_LF_GGRP_QCTL);\n-\t\t}\n-\t} else {\n-\t\tstruct otx2_ssogws *ws = event_dev->data->ports[0];\n-\n-\t\tfor (i = 0; i < dev->nb_event_queues; i++) {\n-\t\t\t/* Consume all the events through HWS0 */\n-\t\t\tssogws_flush_events(ws, i, ws->grps_base[i],\n-\t\t\t\t\t otx2_handle_event, event_dev);\n-\t\t\t/* Enable/Disable SSO GGRP */\n-\t\t\totx2_write64(enable, ws->grps_base[i] +\n-\t\t\t\t SSO_LF_GGRP_QCTL);\n-\t\t}\n-\t}\n-\n-\t/* reset SSO GWS cache */\n-\totx2_mbox_alloc_msg_sso_ws_cache_inv(dev->mbox);\n-\totx2_mbox_process(dev->mbox);\n-}\n-\n-int\n-sso_xae_reconfigure(struct rte_eventdev *event_dev)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tint rc = 0;\n-\n-\tif (event_dev->data->dev_started)\n-\t\tsso_cleanup(event_dev, 0);\n-\n-\trc = sso_ggrp_free_xaq(dev);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to free XAQ\\n\");\n-\t\treturn rc;\n-\t}\n-\n-\trte_mempool_free(dev->xaq_pool);\n-\tdev->xaq_pool = NULL;\n-\trc = sso_xaq_allocate(dev);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to alloc xaq pool %d\", rc);\n-\t\treturn rc;\n-\t}\n-\trc = sso_ggrp_alloc_xaq(dev);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to alloc xaq to ggrp %d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\trte_mb();\n-\tif (event_dev->data->dev_started)\n-\t\tsso_cleanup(event_dev, 1);\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_sso_start(struct rte_eventdev *event_dev)\n-{\n-\tsso_func_trace();\n-\tsso_qos_cfg(event_dev);\n-\tsso_cleanup(event_dev, 1);\n-\tsso_fastpath_fns_set(event_dev);\n-\n-\treturn 0;\n-}\n-\n-static void\n-otx2_sso_stop(struct rte_eventdev *event_dev)\n-{\n-\tsso_func_trace();\n-\tsso_cleanup(event_dev, 0);\n-\trte_mb();\n-}\n-\n-static int\n-otx2_sso_close(struct rte_eventdev *event_dev)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuint8_t all_queues[RTE_EVENT_MAX_QUEUES_PER_DEV];\n-\tuint16_t i;\n-\n-\tif (!dev->configured)\n-\t\treturn 0;\n-\n-\tsso_unregister_irqs(event_dev);\n-\n-\tfor (i = 0; i < dev->nb_event_queues; i++)\n-\t\tall_queues[i] = i;\n-\n-\tfor (i = 0; i < dev->nb_event_ports; i++)\n-\t\totx2_sso_port_unlink(event_dev, event_dev->data->ports[i],\n-\t\t\t\t all_queues, dev->nb_event_queues);\n-\n-\tsso_lf_teardown(dev, SSO_LF_GGRP);\n-\tsso_lf_teardown(dev, SSO_LF_GWS);\n-\tdev->nb_event_ports = 0;\n-\tdev->nb_event_queues = 0;\n-\trte_mempool_free(dev->xaq_pool);\n-\trte_memzone_free(rte_memzone_lookup(OTX2_SSO_FC_NAME));\n-\n-\treturn 0;\n-}\n-\n-/* Initialize and register event driver with DPDK Application */\n-static struct eventdev_ops otx2_sso_ops = {\n-\t.dev_infos_get = otx2_sso_info_get,\n-\t.dev_configure = otx2_sso_configure,\n-\t.queue_def_conf = otx2_sso_queue_def_conf,\n-\t.queue_setup = otx2_sso_queue_setup,\n-\t.queue_release = otx2_sso_queue_release,\n-\t.port_def_conf = otx2_sso_port_def_conf,\n-\t.port_setup = otx2_sso_port_setup,\n-\t.port_release = otx2_sso_port_release,\n-\t.port_link = otx2_sso_port_link,\n-\t.port_unlink = otx2_sso_port_unlink,\n-\t.timeout_ticks = otx2_sso_timeout_ticks,\n-\n-\t.eth_rx_adapter_caps_get = otx2_sso_rx_adapter_caps_get,\n-\t.eth_rx_adapter_queue_add = otx2_sso_rx_adapter_queue_add,\n-\t.eth_rx_adapter_queue_del = otx2_sso_rx_adapter_queue_del,\n-\t.eth_rx_adapter_start = otx2_sso_rx_adapter_start,\n-\t.eth_rx_adapter_stop = otx2_sso_rx_adapter_stop,\n-\n-\t.eth_tx_adapter_caps_get = otx2_sso_tx_adapter_caps_get,\n-\t.eth_tx_adapter_queue_add = otx2_sso_tx_adapter_queue_add,\n-\t.eth_tx_adapter_queue_del = otx2_sso_tx_adapter_queue_del,\n-\n-\t.timer_adapter_caps_get = otx2_tim_caps_get,\n-\n-\t.crypto_adapter_caps_get = otx2_ca_caps_get,\n-\t.crypto_adapter_queue_pair_add = otx2_ca_qp_add,\n-\t.crypto_adapter_queue_pair_del = otx2_ca_qp_del,\n-\n-\t.xstats_get = otx2_sso_xstats_get,\n-\t.xstats_reset = otx2_sso_xstats_reset,\n-\t.xstats_get_names = otx2_sso_xstats_get_names,\n-\n-\t.dump = otx2_sso_dump,\n-\t.dev_start = otx2_sso_start,\n-\t.dev_stop = otx2_sso_stop,\n-\t.dev_close = otx2_sso_close,\n-\t.dev_selftest = otx2_sso_selftest,\n-};\n-\n-#define OTX2_SSO_XAE_CNT\t\"xae_cnt\"\n-#define OTX2_SSO_SINGLE_WS\t\"single_ws\"\n-#define OTX2_SSO_GGRP_QOS\t\"qos\"\n-#define OTX2_SSO_FORCE_BP\t\"force_rx_bp\"\n-\n-static void\n-parse_queue_param(char *value, void *opaque)\n-{\n-\tstruct otx2_sso_qos queue_qos = {0};\n-\tuint8_t *val = (uint8_t *)&queue_qos;\n-\tstruct otx2_sso_evdev *dev = opaque;\n-\tchar *tok = strtok(value, \"-\");\n-\tstruct otx2_sso_qos *old_ptr;\n-\n-\tif (!strlen(value))\n-\t\treturn;\n-\n-\twhile (tok != NULL) {\n-\t\t*val = atoi(tok);\n-\t\ttok = strtok(NULL, \"-\");\n-\t\tval++;\n-\t}\n-\n-\tif (val != (&queue_qos.iaq_prcnt + 1)) {\n-\t\totx2_err(\"Invalid QoS parameter expected [Qx-XAQ-TAQ-IAQ]\");\n-\t\treturn;\n-\t}\n-\n-\tdev->qos_queue_cnt++;\n-\told_ptr = dev->qos_parse_data;\n-\tdev->qos_parse_data = rte_realloc(dev->qos_parse_data,\n-\t\t\t\t\t sizeof(struct otx2_sso_qos) *\n-\t\t\t\t\t dev->qos_queue_cnt, 0);\n-\tif (dev->qos_parse_data == NULL) {\n-\t\tdev->qos_parse_data = old_ptr;\n-\t\tdev->qos_queue_cnt--;\n-\t\treturn;\n-\t}\n-\tdev->qos_parse_data[dev->qos_queue_cnt - 1] = queue_qos;\n-}\n-\n-static void\n-parse_qos_list(const char *value, void *opaque)\n-{\n-\tchar *s = strdup(value);\n-\tchar *start = NULL;\n-\tchar *end = NULL;\n-\tchar *f = s;\n-\n-\twhile (*s) {\n-\t\tif (*s == '[')\n-\t\t\tstart = s;\n-\t\telse if (*s == ']')\n-\t\t\tend = s;\n-\n-\t\tif (start && start < end) {\n-\t\t\t*end = 0;\n-\t\t\tparse_queue_param(start + 1, opaque);\n-\t\t\ts = end;\n-\t\t\tstart = end;\n-\t\t}\n-\t\ts++;\n-\t}\n-\n-\tfree(f);\n-}\n-\n-static int\n-parse_sso_kvargs_dict(const char *key, const char *value, void *opaque)\n-{\n-\tRTE_SET_USED(key);\n-\n-\t/* Dict format [Qx-XAQ-TAQ-IAQ][Qz-XAQ-TAQ-IAQ] use '-' cause ','\n-\t * isn't allowed. Everything is expressed in percentages, 0 represents\n-\t * default.\n-\t */\n-\tparse_qos_list(value, opaque);\n-\n-\treturn 0;\n-}\n-\n-static void\n-sso_parse_devargs(struct otx2_sso_evdev *dev, struct rte_devargs *devargs)\n-{\n-\tstruct rte_kvargs *kvlist;\n-\tuint8_t single_ws = 0;\n-\n-\tif (devargs == NULL)\n-\t\treturn;\n-\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n-\tif (kvlist == NULL)\n-\t\treturn;\n-\n-\trte_kvargs_process(kvlist, OTX2_SSO_XAE_CNT, &parse_kvargs_value,\n-\t\t\t &dev->xae_cnt);\n-\trte_kvargs_process(kvlist, OTX2_SSO_SINGLE_WS, &parse_kvargs_flag,\n-\t\t\t &single_ws);\n-\trte_kvargs_process(kvlist, OTX2_SSO_GGRP_QOS, &parse_sso_kvargs_dict,\n-\t\t\t dev);\n-\trte_kvargs_process(kvlist, OTX2_SSO_FORCE_BP, &parse_kvargs_flag,\n-\t\t\t &dev->force_rx_bp);\n-\totx2_parse_common_devargs(kvlist);\n-\tdev->dual_ws = !single_ws;\n-\trte_kvargs_free(kvlist);\n-}\n-\n-static int\n-otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n-{\n-\treturn rte_event_pmd_pci_probe(pci_drv, pci_dev,\n-\t\t\t\t sizeof(struct otx2_sso_evdev),\n-\t\t\t\t otx2_sso_init);\n-}\n-\n-static int\n-otx2_sso_remove(struct rte_pci_device *pci_dev)\n-{\n-\treturn rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);\n-}\n-\n-static const struct rte_pci_id pci_sso_map[] = {\n-\t{\n-\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n-\t\t\t PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)\n-\t},\n-\t{\n-\t\t.vendor_id = 0,\n-\t},\n-};\n-\n-static struct rte_pci_driver pci_sso = {\n-\t.id_table = pci_sso_map,\n-\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,\n-\t.probe = otx2_sso_probe,\n-\t.remove = otx2_sso_remove,\n-};\n-\n-int\n-otx2_sso_init(struct rte_eventdev *event_dev)\n-{\n-\tstruct free_rsrcs_rsp *rsrc_cnt;\n-\tstruct rte_pci_device *pci_dev;\n-\tstruct otx2_sso_evdev *dev;\n-\tint rc;\n-\n-\tevent_dev->dev_ops = &otx2_sso_ops;\n-\t/* For secondary processes, the primary has done all the work */\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n-\t\tsso_fastpath_fns_set(event_dev);\n-\t\treturn 0;\n-\t}\n-\n-\tdev = sso_pmd_priv(event_dev);\n-\n-\tpci_dev = container_of(event_dev->dev, struct rte_pci_device, device);\n-\n-\t/* Initialize the base otx2_dev object */\n-\trc = otx2_dev_init(pci_dev, dev);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to initialize otx2_dev rc=%d\", rc);\n-\t\tgoto error;\n-\t}\n-\n-\t/* Get SSO and SSOW MSIX rsrc cnt */\n-\totx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);\n-\trc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Unable to get free rsrc count\");\n-\t\tgoto otx2_dev_uninit;\n-\t}\n-\totx2_sso_dbg(\"SSO %d SSOW %d NPA %d provisioned\", rsrc_cnt->sso,\n-\t\t rsrc_cnt->ssow, rsrc_cnt->npa);\n-\n-\tdev->max_event_ports = RTE_MIN(rsrc_cnt->ssow, OTX2_SSO_MAX_VHWS);\n-\tdev->max_event_queues = RTE_MIN(rsrc_cnt->sso, OTX2_SSO_MAX_VHGRP);\n-\t/* Grab the NPA LF if required */\n-\trc = otx2_npa_lf_init(pci_dev, dev);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Unable to init NPA lf. It might not be provisioned\");\n-\t\tgoto otx2_dev_uninit;\n-\t}\n-\n-\tdev->drv_inited = true;\n-\tdev->is_timeout_deq = 0;\n-\tdev->min_dequeue_timeout_ns = USEC2NSEC(1);\n-\tdev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF);\n-\tdev->max_num_events = -1;\n-\tdev->nb_event_queues = 0;\n-\tdev->nb_event_ports = 0;\n-\n-\tif (!dev->max_event_ports || !dev->max_event_queues) {\n-\t\totx2_err(\"Not enough eventdev resource queues=%d ports=%d\",\n-\t\t\t dev->max_event_queues, dev->max_event_ports);\n-\t\trc = -ENODEV;\n-\t\tgoto otx2_npa_lf_uninit;\n-\t}\n-\n-\tdev->dual_ws = 1;\n-\tsso_parse_devargs(dev, pci_dev->device.devargs);\n-\tif (dev->dual_ws) {\n-\t\totx2_sso_dbg(\"Using dual workslot mode\");\n-\t\tdev->max_event_ports = dev->max_event_ports / 2;\n-\t} else {\n-\t\totx2_sso_dbg(\"Using single workslot mode\");\n-\t}\n-\n-\totx2_sso_pf_func_set(dev->pf_func);\n-\totx2_sso_dbg(\"Initializing %s max_queues=%d max_ports=%d\",\n-\t\t event_dev->data->name, dev->max_event_queues,\n-\t\t dev->max_event_ports);\n-\n-\totx2_tim_init(pci_dev, (struct otx2_dev *)dev);\n-\n-\treturn 0;\n-\n-otx2_npa_lf_uninit:\n-\totx2_npa_lf_fini();\n-otx2_dev_uninit:\n-\totx2_dev_fini(pci_dev, dev);\n-error:\n-\treturn rc;\n-}\n-\n-int\n-otx2_sso_fini(struct rte_eventdev *event_dev)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tstruct rte_pci_device *pci_dev;\n-\n-\t/* For secondary processes, nothing to be done */\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn 0;\n-\n-\tpci_dev = container_of(event_dev->dev, struct rte_pci_device, device);\n-\n-\tif (!dev->drv_inited)\n-\t\tgoto dev_fini;\n-\n-\tdev->drv_inited = false;\n-\totx2_npa_lf_fini();\n-\n-dev_fini:\n-\tif (otx2_npa_lf_active(dev)) {\n-\t\totx2_info(\"Common resource in use by other devices\");\n-\t\treturn -EAGAIN;\n-\t}\n-\n-\totx2_tim_fini();\n-\totx2_dev_fini(pci_dev, dev);\n-\n-\treturn 0;\n-}\n-\n-RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);\n-RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);\n-RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, \"vfio-pci\");\n-RTE_PMD_REGISTER_PARAM_STRING(event_octeontx2, OTX2_SSO_XAE_CNT \"=<int>\"\n-\t\t\t OTX2_SSO_SINGLE_WS \"=1\"\n-\t\t\t OTX2_SSO_GGRP_QOS \"=<string>\"\n-\t\t\t OTX2_SSO_FORCE_BP \"=1\"\n-\t\t\t OTX2_NPA_LOCK_MASK \"=<1-65535>\");\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\ndeleted file mode 100644\nindex a5d34b7df7..0000000000\n--- a/drivers/event/octeontx2/otx2_evdev.h\n+++ /dev/null\n@@ -1,430 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_EVDEV_H__\n-#define __OTX2_EVDEV_H__\n-\n-#include <rte_eventdev.h>\n-#include <eventdev_pmd.h>\n-#include <rte_event_eth_rx_adapter.h>\n-#include <rte_event_eth_tx_adapter.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_dev.h\"\n-#include \"otx2_ethdev.h\"\n-#include \"otx2_mempool.h\"\n-#include \"otx2_tim_evdev.h\"\n-\n-#define EVENTDEV_NAME_OCTEONTX2_PMD event_octeontx2\n-\n-#define sso_func_trace otx2_sso_dbg\n-\n-#define OTX2_SSO_MAX_VHGRP RTE_EVENT_MAX_QUEUES_PER_DEV\n-#define OTX2_SSO_MAX_VHWS (UINT8_MAX)\n-#define OTX2_SSO_FC_NAME \"otx2_evdev_xaq_fc\"\n-#define OTX2_SSO_SQB_LIMIT (0x180)\n-#define OTX2_SSO_XAQ_SLACK (8)\n-#define OTX2_SSO_XAQ_CACHE_CNT (0x7)\n-#define OTX2_SSO_WQE_SG_PTR (9)\n-\n-/* SSO LF register offsets (BAR2) */\n-#define SSO_LF_GGRP_OP_ADD_WORK0 (0x0ull)\n-#define SSO_LF_GGRP_OP_ADD_WORK1 (0x8ull)\n-\n-#define SSO_LF_GGRP_QCTL (0x20ull)\n-#define SSO_LF_GGRP_EXE_DIS (0x80ull)\n-#define SSO_LF_GGRP_INT (0x100ull)\n-#define SSO_LF_GGRP_INT_W1S (0x108ull)\n-#define SSO_LF_GGRP_INT_ENA_W1S (0x110ull)\n-#define SSO_LF_GGRP_INT_ENA_W1C (0x118ull)\n-#define SSO_LF_GGRP_INT_THR (0x140ull)\n-#define SSO_LF_GGRP_INT_CNT (0x180ull)\n-#define SSO_LF_GGRP_XAQ_CNT (0x1b0ull)\n-#define SSO_LF_GGRP_AQ_CNT (0x1c0ull)\n-#define SSO_LF_GGRP_AQ_THR (0x1e0ull)\n-#define SSO_LF_GGRP_MISC_CNT (0x200ull)\n-\n-/* SSOW LF register offsets (BAR2) */\n-#define SSOW_LF_GWS_LINKS (0x10ull)\n-#define SSOW_LF_GWS_PENDWQP (0x40ull)\n-#define SSOW_LF_GWS_PENDSTATE (0x50ull)\n-#define SSOW_LF_GWS_NW_TIM (0x70ull)\n-#define SSOW_LF_GWS_GRPMSK_CHG (0x80ull)\n-#define SSOW_LF_GWS_INT (0x100ull)\n-#define SSOW_LF_GWS_INT_W1S (0x108ull)\n-#define SSOW_LF_GWS_INT_ENA_W1S (0x110ull)\n-#define SSOW_LF_GWS_INT_ENA_W1C (0x118ull)\n-#define SSOW_LF_GWS_TAG (0x200ull)\n-#define SSOW_LF_GWS_WQP (0x210ull)\n-#define SSOW_LF_GWS_SWTP (0x220ull)\n-#define SSOW_LF_GWS_PENDTAG (0x230ull)\n-#define SSOW_LF_GWS_OP_ALLOC_WE (0x400ull)\n-#define SSOW_LF_GWS_OP_GET_WORK (0x600ull)\n-#define SSOW_LF_GWS_OP_SWTAG_FLUSH (0x800ull)\n-#define SSOW_LF_GWS_OP_SWTAG_UNTAG (0x810ull)\n-#define SSOW_LF_GWS_OP_SWTP_CLR (0x820ull)\n-#define SSOW_LF_GWS_OP_UPD_WQP_GRP0 (0x830ull)\n-#define SSOW_LF_GWS_OP_UPD_WQP_GRP1 (0x838ull)\n-#define SSOW_LF_GWS_OP_DESCHED (0x880ull)\n-#define SSOW_LF_GWS_OP_DESCHED_NOSCH (0x8c0ull)\n-#define SSOW_LF_GWS_OP_SWTAG_DESCHED (0x980ull)\n-#define SSOW_LF_GWS_OP_SWTAG_NOSCHED (0x9c0ull)\n-#define SSOW_LF_GWS_OP_CLR_NSCHED0 (0xa00ull)\n-#define SSOW_LF_GWS_OP_CLR_NSCHED1 (0xa08ull)\n-#define SSOW_LF_GWS_OP_SWTP_SET (0xc00ull)\n-#define SSOW_LF_GWS_OP_SWTAG_NORM (0xc10ull)\n-#define SSOW_LF_GWS_OP_SWTAG_FULL0 (0xc20ull)\n-#define SSOW_LF_GWS_OP_SWTAG_FULL1 (0xc28ull)\n-#define SSOW_LF_GWS_OP_GWC_INVAL (0xe00ull)\n-\n-#define OTX2_SSOW_GET_BASE_ADDR(_GW) ((_GW) - SSOW_LF_GWS_OP_GET_WORK)\n-#define OTX2_SSOW_TT_FROM_TAG(x)\t (((x) >> 32) & SSO_TT_EMPTY)\n-#define OTX2_SSOW_GRP_FROM_TAG(x)\t (((x) >> 36) & 0x3ff)\n-\n-#define NSEC2USEC(__ns)\t\t\t((__ns) / 1E3)\n-#define USEC2NSEC(__us) ((__us) * 1E3)\n-#define NSEC2TICK(__ns, __freq)\t\t(((__ns) * (__freq)) / 1E9)\n-#define TICK2NSEC(__tck, __freq)\t(((__tck) * 1E9) / (__freq))\n-\n-enum otx2_sso_lf_type {\n-\tSSO_LF_GGRP,\n-\tSSO_LF_GWS\n-};\n-\n-union otx2_sso_event {\n-\tuint64_t get_work0;\n-\tstruct {\n-\t\tuint32_t flow_id:20;\n-\t\tuint32_t sub_event_type:8;\n-\t\tuint32_t event_type:4;\n-\t\tuint8_t op:2;\n-\t\tuint8_t rsvd:4;\n-\t\tuint8_t sched_type:2;\n-\t\tuint8_t queue_id;\n-\t\tuint8_t priority;\n-\t\tuint8_t impl_opaque;\n-\t};\n-} __rte_aligned(64);\n-\n-enum {\n-\tSSO_SYNC_ORDERED,\n-\tSSO_SYNC_ATOMIC,\n-\tSSO_SYNC_UNTAGGED,\n-\tSSO_SYNC_EMPTY\n-};\n-\n-struct otx2_sso_qos {\n-\tuint8_t queue;\n-\tuint8_t xaq_prcnt;\n-\tuint8_t taq_prcnt;\n-\tuint8_t iaq_prcnt;\n-};\n-\n-struct otx2_sso_evdev {\n-\tOTX2_DEV; /* Base class */\n-\tuint8_t max_event_queues;\n-\tuint8_t max_event_ports;\n-\tuint8_t is_timeout_deq;\n-\tuint8_t nb_event_queues;\n-\tuint8_t nb_event_ports;\n-\tuint8_t configured;\n-\tuint32_t deq_tmo_ns;\n-\tuint32_t min_dequeue_timeout_ns;\n-\tuint32_t max_dequeue_timeout_ns;\n-\tint32_t max_num_events;\n-\tuint64_t *fc_mem;\n-\tuint64_t xaq_lmt;\n-\tuint64_t nb_xaq_cfg;\n-\trte_iova_t fc_iova;\n-\tstruct rte_mempool *xaq_pool;\n-\tuint64_t rx_offloads;\n-\tuint64_t tx_offloads;\n-\tuint64_t adptr_xae_cnt;\n-\tuint16_t rx_adptr_pool_cnt;\n-\tuint64_t *rx_adptr_pools;\n-\tuint16_t max_port_id;\n-\tuint16_t tim_adptr_ring_cnt;\n-\tuint16_t *timer_adptr_rings;\n-\tuint64_t *timer_adptr_sz;\n-\t/* Dev args */\n-\tuint8_t dual_ws;\n-\tuint32_t xae_cnt;\n-\tuint8_t qos_queue_cnt;\n-\tuint8_t force_rx_bp;\n-\tstruct otx2_sso_qos *qos_parse_data;\n-\t/* HW const */\n-\tuint32_t xae_waes;\n-\tuint32_t xaq_buf_size;\n-\tuint32_t iue;\n-\t/* MSIX offsets */\n-\tuint16_t sso_msixoff[OTX2_SSO_MAX_VHGRP];\n-\tuint16_t ssow_msixoff[OTX2_SSO_MAX_VHWS];\n-\t/* PTP timestamp */\n-\tstruct otx2_timesync_info *tstamp;\n-} __rte_cache_aligned;\n-\n-#define OTX2_SSOGWS_OPS \\\n-\t/* WS ops */ \\\n-\tuintptr_t getwrk_op; \\\n-\tuintptr_t tag_op; \\\n-\tuintptr_t wqp_op; \\\n-\tuintptr_t swtag_flush_op; \\\n-\tuintptr_t swtag_norm_op; \\\n-\tuintptr_t swtag_desched_op;\n-\n-/* Event port aka GWS */\n-struct otx2_ssogws {\n-\t/* Get Work Fastpath data */\n-\tOTX2_SSOGWS_OPS;\n-\t/* PTP timestamp */\n-\tstruct otx2_timesync_info *tstamp;\n-\tvoid *lookup_mem;\n-\tuint8_t swtag_req;\n-\tuint8_t port;\n-\t/* Add Work Fastpath data */\n-\tuint64_t xaq_lmt __rte_cache_aligned;\n-\tuint64_t *fc_mem;\n-\tuintptr_t grps_base[OTX2_SSO_MAX_VHGRP];\n-\t/* Tx Fastpath data */\n-\tuint64_t base __rte_cache_aligned;\n-\tuint8_t tx_adptr_data[];\n-} __rte_cache_aligned;\n-\n-struct otx2_ssogws_state {\n-\tOTX2_SSOGWS_OPS;\n-};\n-\n-struct otx2_ssogws_dual {\n-\t/* Get Work Fastpath data */\n-\tstruct otx2_ssogws_state ws_state[2]; /* Ping and Pong */\n-\t/* PTP timestamp */\n-\tstruct otx2_timesync_info *tstamp;\n-\tvoid *lookup_mem;\n-\tuint8_t swtag_req;\n-\tuint8_t vws; /* Ping pong bit */\n-\tuint8_t port;\n-\t/* Add Work Fastpath data */\n-\tuint64_t xaq_lmt __rte_cache_aligned;\n-\tuint64_t *fc_mem;\n-\tuintptr_t grps_base[OTX2_SSO_MAX_VHGRP];\n-\t/* Tx Fastpath data */\n-\tuint64_t base[2] __rte_cache_aligned;\n-\tuint8_t tx_adptr_data[];\n-} __rte_cache_aligned;\n-\n-static inline struct otx2_sso_evdev *\n-sso_pmd_priv(const struct rte_eventdev *event_dev)\n-{\n-\treturn event_dev->data->dev_private;\n-}\n-\n-struct otx2_ssogws_cookie {\n-\tconst struct rte_eventdev *event_dev;\n-\tbool configured;\n-};\n-\n-static inline struct otx2_ssogws_cookie *\n-ssogws_get_cookie(void *ws)\n-{\n-\treturn (struct otx2_ssogws_cookie *)\n-\t\t((uint8_t *)ws - RTE_CACHE_LINE_SIZE);\n-}\n-\n-static const union mbuf_initializer mbuf_init = {\n-\t.fields = {\n-\t\t.data_off = RTE_PKTMBUF_HEADROOM,\n-\t\t.refcnt = 1,\n-\t\t.nb_segs = 1,\n-\t\t.port = 0\n-\t}\n-};\n-\n-static __rte_always_inline void\n-otx2_wqe_to_mbuf(uint64_t get_work1, const uint64_t mbuf, uint8_t port_id,\n-\t\t const uint32_t tag, const uint32_t flags,\n-\t\t const void * const lookup_mem)\n-{\n-\tstruct nix_wqe_hdr_s *wqe = (struct nix_wqe_hdr_s *)get_work1;\n-\tuint64_t val = mbuf_init.value | (uint64_t)port_id << 48;\n-\n-\tif (flags & NIX_RX_OFFLOAD_TSTAMP_F)\n-\t\tval |= NIX_TIMESYNC_RX_OFFSET;\n-\n-\totx2_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,\n-\t\t\t (struct rte_mbuf *)mbuf, lookup_mem,\n-\t\t\t val, flags);\n-\n-}\n-\n-static inline int\n-parse_kvargs_flag(const char *key, const char *value, void *opaque)\n-{\n-\tRTE_SET_USED(key);\n-\n-\t*(uint8_t *)opaque = !!atoi(value);\n-\treturn 0;\n-}\n-\n-static inline int\n-parse_kvargs_value(const char *key, const char *value, void *opaque)\n-{\n-\tRTE_SET_USED(key);\n-\n-\t*(uint32_t *)opaque = (uint32_t)atoi(value);\n-\treturn 0;\n-}\n-\n-#define SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\tNIX_RX_FASTPATH_MODES\n-#define SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\tNIX_TX_FASTPATH_MODES\n-\n-/* Single WS API's */\n-uint16_t otx2_ssogws_enq(void *port, const struct rte_event *ev);\n-uint16_t otx2_ssogws_enq_burst(void *port, const struct rte_event ev[],\n-\t\t\t uint16_t nb_events);\n-uint16_t otx2_ssogws_enq_new_burst(void *port, const struct rte_event ev[],\n-\t\t\t\t uint16_t nb_events);\n-uint16_t otx2_ssogws_enq_fwd_burst(void *port, const struct rte_event ev[],\n-\t\t\t\t uint16_t nb_events);\n-\n-/* Dual WS API's */\n-uint16_t otx2_ssogws_dual_enq(void *port, const struct rte_event *ev);\n-uint16_t otx2_ssogws_dual_enq_burst(void *port, const struct rte_event ev[],\n-\t\t\t\t uint16_t nb_events);\n-uint16_t otx2_ssogws_dual_enq_new_burst(void *port, const struct rte_event ev[],\n-\t\t\t\t\tuint16_t nb_events);\n-uint16_t otx2_ssogws_dual_enq_fwd_burst(void *port, const struct rte_event ev[],\n-\t\t\t\t\tuint16_t nb_events);\n-\n-/* Auto generated API's */\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t \\\n-uint16_t otx2_ssogws_deq_ ##name(void *port, struct rte_event *ev,\t \\\n-\t\t\t\t uint64_t timeout_ticks);\t\t \\\n-uint16_t otx2_ssogws_deq_burst_ ##name(void *port, struct rte_event ev[], \\\n-\t\t\t\t uint16_t nb_events,\t\t \\\n-\t\t\t\t uint64_t timeout_ticks);\t\t \\\n-uint16_t otx2_ssogws_deq_timeout_ ##name(void *port,\t\t\t \\\n-\t\t\t\t\t struct rte_event *ev,\t\t \\\n-\t\t\t\t\t uint64_t timeout_ticks);\t \\\n-uint16_t otx2_ssogws_deq_timeout_burst_ ##name(void *port,\t\t \\\n-\t\t\t\t\t struct rte_event ev[],\t \\\n-\t\t\t\t\t uint16_t nb_events,\t \\\n-\t\t\t\t\t uint64_t timeout_ticks);\t \\\n-uint16_t otx2_ssogws_deq_seg_ ##name(void *port, struct rte_event *ev,\t \\\n-\t\t\t\t uint64_t timeout_ticks);\t\t \\\n-uint16_t otx2_ssogws_deq_seg_burst_ ##name(void *port,\t\t\t \\\n-\t\t\t\t\t struct rte_event ev[],\t \\\n-\t\t\t\t\t uint16_t nb_events,\t\t \\\n-\t\t\t\t\t uint64_t timeout_ticks);\t \\\n-uint16_t otx2_ssogws_deq_seg_timeout_ ##name(void *port,\t\t \\\n-\t\t\t\t\t struct rte_event *ev,\t \\\n-\t\t\t\t\t uint64_t timeout_ticks);\t \\\n-uint16_t otx2_ssogws_deq_seg_timeout_burst_ ##name(void *port,\t\t \\\n-\t\t\t\t\t\t struct rte_event ev[], \\\n-\t\t\t\t\t\t uint16_t nb_events,\t \\\n-\t\t\t\t\t\t uint64_t timeout_ticks); \\\n-\t\t\t\t\t\t\t\t\t \\\n-uint16_t otx2_ssogws_dual_deq_ ##name(void *port, struct rte_event *ev,\t \\\n-\t\t\t\t uint64_t timeout_ticks);\t\t \\\n-uint16_t otx2_ssogws_dual_deq_burst_ ##name(void *port,\t\t\t \\\n-\t\t\t\t\t struct rte_event ev[],\t \\\n-\t\t\t\t\t uint16_t nb_events,\t\t \\\n-\t\t\t\t\t uint64_t timeout_ticks);\t \\\n-uint16_t otx2_ssogws_dual_deq_timeout_ ##name(void *port,\t\t \\\n-\t\t\t\t\t struct rte_event *ev,\t \\\n-\t\t\t\t\t uint64_t timeout_ticks);\t \\\n-uint16_t otx2_ssogws_dual_deq_timeout_burst_ ##name(void *port,\t\t \\\n-\t\t\t\t\t\t struct rte_event ev[], \\\n-\t\t\t\t\t\t uint16_t nb_events,\t \\\n-\t\t\t\t\t\t uint64_t timeout_ticks); \\\n-uint16_t otx2_ssogws_dual_deq_seg_ ##name(void *port, struct rte_event *ev, \\\n-\t\t\t\t\t uint64_t timeout_ticks);\t \\\n-uint16_t otx2_ssogws_dual_deq_seg_burst_ ##name(void *port,\t\t \\\n-\t\t\t\t\t\tstruct rte_event ev[],\t \\\n-\t\t\t\t\t\tuint16_t nb_events,\t \\\n-\t\t\t\t\t\tuint64_t timeout_ticks); \\\n-uint16_t otx2_ssogws_dual_deq_seg_timeout_ ##name(void *port,\t\t \\\n-\t\t\t\t\t\t struct rte_event *ev,\t \\\n-\t\t\t\t\t\t uint64_t timeout_ticks); \\\n-uint16_t otx2_ssogws_dual_deq_seg_timeout_burst_ ##name(void *port,\t \\\n-\t\t\t\t\t\t\tstruct rte_event ev[], \\\n-\t\t\t\t\t\t\tuint16_t nb_events, \\\n-\t\t\t\t\t\t uint64_t timeout_ticks);\\\n-\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t \\\n-uint16_t otx2_ssogws_tx_adptr_enq_ ## name(void *port, struct rte_event ev[],\\\n-\t\t\t\t\t uint16_t nb_events);\t\t \\\n-uint16_t otx2_ssogws_tx_adptr_enq_seg_ ## name(void *port,\t\t \\\n-\t\t\t\t\t struct rte_event ev[],\t \\\n-\t\t\t\t\t uint16_t nb_events);\t \\\n-uint16_t otx2_ssogws_dual_tx_adptr_enq_ ## name(void *port,\t\t \\\n-\t\t\t\t\t\tstruct rte_event ev[],\t \\\n-\t\t\t\t\t\tuint16_t nb_events);\t \\\n-uint16_t otx2_ssogws_dual_tx_adptr_enq_seg_ ## name(void *port,\t\t \\\n-\t\t\t\t\t\t struct rte_event ev[], \\\n-\t\t\t\t\t\t uint16_t nb_events); \\\n-\n-SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef T\n-\n-void sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data,\n-\t\t uint32_t event_type);\n-int sso_xae_reconfigure(struct rte_eventdev *event_dev);\n-void sso_fastpath_fns_set(struct rte_eventdev *event_dev);\n-\n-int otx2_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,\n-\t\t\t\t const struct rte_eth_dev *eth_dev,\n-\t\t\t\t uint32_t *caps);\n-int otx2_sso_rx_adapter_queue_add(const struct rte_eventdev *event_dev,\n-\t\t\t\t const struct rte_eth_dev *eth_dev,\n-\t\t\t\t int32_t rx_queue_id,\n-\t\tconst struct rte_event_eth_rx_adapter_queue_conf *queue_conf);\n-int otx2_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,\n-\t\t\t\t const struct rte_eth_dev *eth_dev,\n-\t\t\t\t int32_t rx_queue_id);\n-int otx2_sso_rx_adapter_start(const struct rte_eventdev *event_dev,\n-\t\t\t const struct rte_eth_dev *eth_dev);\n-int otx2_sso_rx_adapter_stop(const struct rte_eventdev *event_dev,\n-\t\t\t const struct rte_eth_dev *eth_dev);\n-int otx2_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,\n-\t\t\t\t const struct rte_eth_dev *eth_dev,\n-\t\t\t\t uint32_t *caps);\n-int otx2_sso_tx_adapter_queue_add(uint8_t id,\n-\t\t\t\t const struct rte_eventdev *event_dev,\n-\t\t\t\t const struct rte_eth_dev *eth_dev,\n-\t\t\t\t int32_t tx_queue_id);\n-\n-int otx2_sso_tx_adapter_queue_del(uint8_t id,\n-\t\t\t\t const struct rte_eventdev *event_dev,\n-\t\t\t\t const struct rte_eth_dev *eth_dev,\n-\t\t\t\t int32_t tx_queue_id);\n-\n-/* Event crypto adapter API's */\n-int otx2_ca_caps_get(const struct rte_eventdev *dev,\n-\t\t const struct rte_cryptodev *cdev, uint32_t *caps);\n-\n-int otx2_ca_qp_add(const struct rte_eventdev *dev,\n-\t\t const struct rte_cryptodev *cdev, int32_t queue_pair_id,\n-\t\t const struct rte_event *event);\n-\n-int otx2_ca_qp_del(const struct rte_eventdev *dev,\n-\t\t const struct rte_cryptodev *cdev, int32_t queue_pair_id);\n-\n-/* Clean up API's */\n-typedef void (*otx2_handle_event_t)(void *arg, struct rte_event ev);\n-void ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id,\n-\t\t\t uintptr_t base, otx2_handle_event_t fn, void *arg);\n-void ssogws_reset(struct otx2_ssogws *ws);\n-/* Selftest */\n-int otx2_sso_selftest(void);\n-/* Init and Fini API's */\n-int otx2_sso_init(struct rte_eventdev *event_dev);\n-int otx2_sso_fini(struct rte_eventdev *event_dev);\n-/* IRQ handlers */\n-int sso_register_irqs(const struct rte_eventdev *event_dev);\n-void sso_unregister_irqs(const struct rte_eventdev *event_dev);\n-\n-#endif /* __OTX2_EVDEV_H__ */\ndiff --git a/drivers/event/octeontx2/otx2_evdev_adptr.c b/drivers/event/octeontx2/otx2_evdev_adptr.c\ndeleted file mode 100644\nindex a91f784b1e..0000000000\n--- a/drivers/event/octeontx2/otx2_evdev_adptr.c\n+++ /dev/null\n@@ -1,656 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019-2021 Marvell.\n- */\n-\n-#include \"otx2_evdev.h\"\n-\n-#define NIX_RQ_AURA_THRESH(x) (((x)*95) / 100)\n-\n-int\n-otx2_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,\n-\t\t\t const struct rte_eth_dev *eth_dev, uint32_t *caps)\n-{\n-\tint rc;\n-\n-\tRTE_SET_USED(event_dev);\n-\trc = strncmp(eth_dev->device->driver->name, \"net_octeontx2\", 13);\n-\tif (rc)\n-\t\t*caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;\n-\telse\n-\t\t*caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |\n-\t\t\tRTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ;\n-\n-\treturn 0;\n-}\n-\n-static inline int\n-sso_rxq_enable(struct otx2_eth_dev *dev, uint16_t qid, uint8_t tt, uint8_t ggrp,\n-\t uint16_t eth_port_id)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_aq_enq_req *aq;\n-\tint rc;\n-\n-\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\taq->qidx = qid;\n-\taq->ctype = NIX_AQ_CTYPE_CQ;\n-\taq->op = NIX_AQ_INSTOP_WRITE;\n-\n-\taq->cq.ena = 0;\n-\taq->cq.caching = 0;\n-\n-\totx2_mbox_memset(&aq->cq_mask, 0, sizeof(struct nix_cq_ctx_s));\n-\taq->cq_mask.ena = ~(aq->cq_mask.ena);\n-\taq->cq_mask.caching = ~(aq->cq_mask.caching);\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to disable cq context\");\n-\t\tgoto fail;\n-\t}\n-\n-\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\taq->qidx = qid;\n-\taq->ctype = NIX_AQ_CTYPE_RQ;\n-\taq->op = NIX_AQ_INSTOP_WRITE;\n-\n-\taq->rq.sso_ena = 1;\n-\taq->rq.sso_tt = tt;\n-\taq->rq.sso_grp = ggrp;\n-\taq->rq.ena_wqwd = 1;\n-\t/* Mbuf Header generation :\n-\t * > FIRST_SKIP is a super set of WQE_SKIP, dont modify first skip as\n-\t * it already has data related to mbuf size, headroom, private area.\n-\t * > Using WQE_SKIP we can directly assign\n-\t *\t\tmbuf = wqe - sizeof(struct mbuf);\n-\t * so that mbuf header will not have unpredicted values while headroom\n-\t * and private data starts at the beginning of wqe_data.\n-\t */\n-\taq->rq.wqe_skip = 1;\n-\taq->rq.wqe_caching = 1;\n-\taq->rq.spb_ena = 0;\n-\taq->rq.flow_tagw = 20; /* 20-bits */\n-\n-\t/* Flow Tag calculation :\n-\t *\n-\t * rq_tag <31:24> = good/bad_tag<8:0>;\n-\t * rq_tag <23:0> = [ltag]\n-\t *\n-\t * flow_tag_mask<31:0> = (1 << flow_tagw) - 1; <31:20>\n-\t * tag<31:0> = (~flow_tag_mask & rq_tag) | (flow_tag_mask & flow_tag);\n-\t *\n-\t * Setup :\n-\t * ltag<23:0> = (eth_port_id & 0xF) << 20;\n-\t * good/bad_tag<8:0> =\n-\t *\t((eth_port_id >> 4) & 0xF) | (RTE_EVENT_TYPE_ETHDEV << 4);\n-\t *\n-\t * TAG<31:0> on getwork = <31:28>(RTE_EVENT_TYPE_ETHDEV) |\n-\t *\t\t\t\t<27:20> (eth_port_id) | <20:0> [TAG]\n-\t */\n-\n-\taq->rq.ltag = (eth_port_id & 0xF) << 20;\n-\taq->rq.good_utag = ((eth_port_id >> 4) & 0xF) |\n-\t\t\t\t(RTE_EVENT_TYPE_ETHDEV << 4);\n-\taq->rq.bad_utag = aq->rq.good_utag;\n-\n-\taq->rq.ena = 0;\t\t /* Don't enable RQ yet */\n-\taq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */\n-\taq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */\n-\n-\totx2_mbox_memset(&aq->rq_mask, 0, sizeof(struct nix_rq_ctx_s));\n-\t/* mask the bits to write. */\n-\taq->rq_mask.sso_ena = ~(aq->rq_mask.sso_ena);\n-\taq->rq_mask.sso_tt = ~(aq->rq_mask.sso_tt);\n-\taq->rq_mask.sso_grp = ~(aq->rq_mask.sso_grp);\n-\taq->rq_mask.ena_wqwd = ~(aq->rq_mask.ena_wqwd);\n-\taq->rq_mask.wqe_skip = ~(aq->rq_mask.wqe_skip);\n-\taq->rq_mask.wqe_caching = ~(aq->rq_mask.wqe_caching);\n-\taq->rq_mask.spb_ena = ~(aq->rq_mask.spb_ena);\n-\taq->rq_mask.flow_tagw = ~(aq->rq_mask.flow_tagw);\n-\taq->rq_mask.ltag = ~(aq->rq_mask.ltag);\n-\taq->rq_mask.good_utag = ~(aq->rq_mask.good_utag);\n-\taq->rq_mask.bad_utag = ~(aq->rq_mask.bad_utag);\n-\taq->rq_mask.ena = ~(aq->rq_mask.ena);\n-\taq->rq_mask.pb_caching = ~(aq->rq_mask.pb_caching);\n-\taq->rq_mask.xqe_imm_size = ~(aq->rq_mask.xqe_imm_size);\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to init rx adapter context\");\n-\t\tgoto fail;\n-\t}\n-\n-\treturn 0;\n-fail:\n-\treturn rc;\n-}\n-\n-static inline int\n-sso_rxq_disable(struct otx2_eth_dev *dev, uint16_t qid)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_aq_enq_req *aq;\n-\tint rc;\n-\n-\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\taq->qidx = qid;\n-\taq->ctype = NIX_AQ_CTYPE_CQ;\n-\taq->op = NIX_AQ_INSTOP_WRITE;\n-\n-\taq->cq.ena = 1;\n-\taq->cq.caching = 1;\n-\n-\totx2_mbox_memset(&aq->cq_mask, 0, sizeof(struct nix_cq_ctx_s));\n-\taq->cq_mask.ena = ~(aq->cq_mask.ena);\n-\taq->cq_mask.caching = ~(aq->cq_mask.caching);\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to enable cq context\");\n-\t\tgoto fail;\n-\t}\n-\n-\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\taq->qidx = qid;\n-\taq->ctype = NIX_AQ_CTYPE_RQ;\n-\taq->op = NIX_AQ_INSTOP_WRITE;\n-\n-\taq->rq.sso_ena = 0;\n-\taq->rq.sso_tt = SSO_TT_UNTAGGED;\n-\taq->rq.sso_grp = 0;\n-\taq->rq.ena_wqwd = 0;\n-\taq->rq.wqe_caching = 0;\n-\taq->rq.wqe_skip = 0;\n-\taq->rq.spb_ena = 0;\n-\taq->rq.flow_tagw = 0x20;\n-\taq->rq.ltag = 0;\n-\taq->rq.good_utag = 0;\n-\taq->rq.bad_utag = 0;\n-\taq->rq.ena = 1;\n-\taq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */\n-\taq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */\n-\n-\totx2_mbox_memset(&aq->rq_mask, 0, sizeof(struct nix_rq_ctx_s));\n-\t/* mask the bits to write. */\n-\taq->rq_mask.sso_ena = ~(aq->rq_mask.sso_ena);\n-\taq->rq_mask.sso_tt = ~(aq->rq_mask.sso_tt);\n-\taq->rq_mask.sso_grp = ~(aq->rq_mask.sso_grp);\n-\taq->rq_mask.ena_wqwd = ~(aq->rq_mask.ena_wqwd);\n-\taq->rq_mask.wqe_caching = ~(aq->rq_mask.wqe_caching);\n-\taq->rq_mask.wqe_skip = ~(aq->rq_mask.wqe_skip);\n-\taq->rq_mask.spb_ena = ~(aq->rq_mask.spb_ena);\n-\taq->rq_mask.flow_tagw = ~(aq->rq_mask.flow_tagw);\n-\taq->rq_mask.ltag = ~(aq->rq_mask.ltag);\n-\taq->rq_mask.good_utag = ~(aq->rq_mask.good_utag);\n-\taq->rq_mask.bad_utag = ~(aq->rq_mask.bad_utag);\n-\taq->rq_mask.ena = ~(aq->rq_mask.ena);\n-\taq->rq_mask.pb_caching = ~(aq->rq_mask.pb_caching);\n-\taq->rq_mask.xqe_imm_size = ~(aq->rq_mask.xqe_imm_size);\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to clear rx adapter context\");\n-\t\tgoto fail;\n-\t}\n-\n-\treturn 0;\n-fail:\n-\treturn rc;\n-}\n-\n-void\n-sso_updt_xae_cnt(struct otx2_sso_evdev *dev, void *data, uint32_t event_type)\n-{\n-\tint i;\n-\n-\tswitch (event_type) {\n-\tcase RTE_EVENT_TYPE_ETHDEV:\n-\t{\n-\t\tstruct otx2_eth_rxq *rxq = data;\n-\t\tuint64_t *old_ptr;\n-\n-\t\tfor (i = 0; i < dev->rx_adptr_pool_cnt; i++) {\n-\t\t\tif ((uint64_t)rxq->pool == dev->rx_adptr_pools[i])\n-\t\t\t\treturn;\n-\t\t}\n-\n-\t\tdev->rx_adptr_pool_cnt++;\n-\t\told_ptr = dev->rx_adptr_pools;\n-\t\tdev->rx_adptr_pools = rte_realloc(dev->rx_adptr_pools,\n-\t\t\t\t\t\t sizeof(uint64_t) *\n-\t\t\t\t\t\t dev->rx_adptr_pool_cnt, 0);\n-\t\tif (dev->rx_adptr_pools == NULL) {\n-\t\t\tdev->adptr_xae_cnt += rxq->pool->size;\n-\t\t\tdev->rx_adptr_pools = old_ptr;\n-\t\t\tdev->rx_adptr_pool_cnt--;\n-\t\t\treturn;\n-\t\t}\n-\t\tdev->rx_adptr_pools[dev->rx_adptr_pool_cnt - 1] =\n-\t\t\t(uint64_t)rxq->pool;\n-\n-\t\tdev->adptr_xae_cnt += rxq->pool->size;\n-\t\tbreak;\n-\t}\n-\tcase RTE_EVENT_TYPE_TIMER:\n-\t{\n-\t\tstruct otx2_tim_ring *timr = data;\n-\t\tuint16_t *old_ring_ptr;\n-\t\tuint64_t *old_sz_ptr;\n-\n-\t\tfor (i = 0; i < dev->tim_adptr_ring_cnt; i++) {\n-\t\t\tif (timr->ring_id != dev->timer_adptr_rings[i])\n-\t\t\t\tcontinue;\n-\t\t\tif (timr->nb_timers == dev->timer_adptr_sz[i])\n-\t\t\t\treturn;\n-\t\t\tdev->adptr_xae_cnt -= dev->timer_adptr_sz[i];\n-\t\t\tdev->adptr_xae_cnt += timr->nb_timers;\n-\t\t\tdev->timer_adptr_sz[i] = timr->nb_timers;\n-\n-\t\t\treturn;\n-\t\t}\n-\n-\t\tdev->tim_adptr_ring_cnt++;\n-\t\told_ring_ptr = dev->timer_adptr_rings;\n-\t\told_sz_ptr = dev->timer_adptr_sz;\n-\n-\t\tdev->timer_adptr_rings = rte_realloc(dev->timer_adptr_rings,\n-\t\t\t\t\t\t sizeof(uint16_t) *\n-\t\t\t\t\t\t dev->tim_adptr_ring_cnt,\n-\t\t\t\t\t\t 0);\n-\t\tif (dev->timer_adptr_rings == NULL) {\n-\t\t\tdev->adptr_xae_cnt += timr->nb_timers;\n-\t\t\tdev->timer_adptr_rings = old_ring_ptr;\n-\t\t\tdev->tim_adptr_ring_cnt--;\n-\t\t\treturn;\n-\t\t}\n-\n-\t\tdev->timer_adptr_sz = rte_realloc(dev->timer_adptr_sz,\n-\t\t\t\t\t\t sizeof(uint64_t) *\n-\t\t\t\t\t\t dev->tim_adptr_ring_cnt,\n-\t\t\t\t\t\t 0);\n-\n-\t\tif (dev->timer_adptr_sz == NULL) {\n-\t\t\tdev->adptr_xae_cnt += timr->nb_timers;\n-\t\t\tdev->timer_adptr_sz = old_sz_ptr;\n-\t\t\tdev->tim_adptr_ring_cnt--;\n-\t\t\treturn;\n-\t\t}\n-\n-\t\tdev->timer_adptr_rings[dev->tim_adptr_ring_cnt - 1] =\n-\t\t\ttimr->ring_id;\n-\t\tdev->timer_adptr_sz[dev->tim_adptr_ring_cnt - 1] =\n-\t\t\ttimr->nb_timers;\n-\n-\t\tdev->adptr_xae_cnt += timr->nb_timers;\n-\t\tbreak;\n-\t}\n-\tdefault:\n-\t\tbreak;\n-\t}\n-}\n-\n-static inline void\n-sso_updt_lookup_mem(const struct rte_eventdev *event_dev, void *lookup_mem)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tint i;\n-\n-\tfor (i = 0; i < dev->nb_event_ports; i++) {\n-\t\tif (dev->dual_ws) {\n-\t\t\tstruct otx2_ssogws_dual *ws = event_dev->data->ports[i];\n-\n-\t\t\tws->lookup_mem = lookup_mem;\n-\t\t} else {\n-\t\t\tstruct otx2_ssogws *ws = event_dev->data->ports[i];\n-\n-\t\t\tws->lookup_mem = lookup_mem;\n-\t\t}\n-\t}\n-}\n-\n-static inline void\n-sso_cfg_nix_mp_bpid(struct otx2_sso_evdev *dev,\n-\t\t struct otx2_eth_dev *otx2_eth_dev, struct otx2_eth_rxq *rxq,\n-\t\t uint8_t ena)\n-{\n-\tstruct otx2_fc_info *fc = &otx2_eth_dev->fc_info;\n-\tstruct npa_aq_enq_req *req;\n-\tstruct npa_aq_enq_rsp *rsp;\n-\tstruct otx2_npa_lf *lf;\n-\tstruct otx2_mbox *mbox;\n-\tuint32_t limit;\n-\tint rc;\n-\n-\tif (otx2_dev_is_sdp(otx2_eth_dev))\n-\t\treturn;\n-\n-\tlf = otx2_npa_lf_obj_get();\n-\tif (!lf)\n-\t\treturn;\n-\tmbox = lf->mbox;\n-\n-\treq = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\tif (req == NULL)\n-\t\treturn;\n-\n-\treq->aura_id = npa_lf_aura_handle_to_aura(rxq->pool->pool_id);\n-\treq->ctype = NPA_AQ_CTYPE_AURA;\n-\treq->op = NPA_AQ_INSTOP_READ;\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn;\n-\n-\tlimit = rsp->aura.limit;\n-\t/* BP is already enabled. */\n-\tif (rsp->aura.bp_ena) {\n-\t\t/* If BP ids don't match disable BP. */\n-\t\tif ((rsp->aura.nix0_bpid != fc->bpid[0]) && !dev->force_rx_bp) {\n-\t\t\treq = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\t\t\tif (req == NULL)\n-\t\t\t\treturn;\n-\n-\t\t\treq->aura_id =\n-\t\t\t\tnpa_lf_aura_handle_to_aura(rxq->pool->pool_id);\n-\t\t\treq->ctype = NPA_AQ_CTYPE_AURA;\n-\t\t\treq->op = NPA_AQ_INSTOP_WRITE;\n-\n-\t\t\treq->aura.bp_ena = 0;\n-\t\t\treq->aura_mask.bp_ena = ~(req->aura_mask.bp_ena);\n-\n-\t\t\totx2_mbox_process(mbox);\n-\t\t}\n-\t\treturn;\n-\t}\n-\n-\t/* BP was previously enabled but now disabled skip. */\n-\tif (rsp->aura.bp)\n-\t\treturn;\n-\n-\treq = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\tif (req == NULL)\n-\t\treturn;\n-\n-\treq->aura_id = npa_lf_aura_handle_to_aura(rxq->pool->pool_id);\n-\treq->ctype = NPA_AQ_CTYPE_AURA;\n-\treq->op = NPA_AQ_INSTOP_WRITE;\n-\n-\tif (ena) {\n-\t\treq->aura.nix0_bpid = fc->bpid[0];\n-\t\treq->aura_mask.nix0_bpid = ~(req->aura_mask.nix0_bpid);\n-\t\treq->aura.bp = NIX_RQ_AURA_THRESH(\n-\t\t\tlimit > 128 ? 256 : limit); /* 95% of size*/\n-\t\treq->aura_mask.bp = ~(req->aura_mask.bp);\n-\t}\n-\n-\treq->aura.bp_ena = !!ena;\n-\treq->aura_mask.bp_ena = ~(req->aura_mask.bp_ena);\n-\n-\totx2_mbox_process(mbox);\n-}\n-\n-int\n-otx2_sso_rx_adapter_queue_add(const struct rte_eventdev *event_dev,\n-\t\t\t const struct rte_eth_dev *eth_dev,\n-\t\t\t int32_t rx_queue_id,\n-\t\tconst struct rte_event_eth_rx_adapter_queue_conf *queue_conf)\n-{\n-\tstruct otx2_eth_dev *otx2_eth_dev = eth_dev->data->dev_private;\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuint16_t port = eth_dev->data->port_id;\n-\tstruct otx2_eth_rxq *rxq;\n-\tint i, rc;\n-\n-\trc = strncmp(eth_dev->device->driver->name, \"net_octeontx2\", 13);\n-\tif (rc)\n-\t\treturn -EINVAL;\n-\n-\tif (rx_queue_id < 0) {\n-\t\tfor (i = 0 ; i < eth_dev->data->nb_rx_queues; i++) {\n-\t\t\trxq = eth_dev->data->rx_queues[i];\n-\t\t\tsso_updt_xae_cnt(dev, rxq, RTE_EVENT_TYPE_ETHDEV);\n-\t\t\tsso_cfg_nix_mp_bpid(dev, otx2_eth_dev, rxq, true);\n-\t\t\trc = sso_xae_reconfigure(\n-\t\t\t\t(struct rte_eventdev *)(uintptr_t)event_dev);\n-\t\t\trc |= sso_rxq_enable(otx2_eth_dev, i,\n-\t\t\t\t\t queue_conf->ev.sched_type,\n-\t\t\t\t\t queue_conf->ev.queue_id, port);\n-\t\t}\n-\t\trxq = eth_dev->data->rx_queues[0];\n-\t\tsso_updt_lookup_mem(event_dev, rxq->lookup_mem);\n-\t} else {\n-\t\trxq = eth_dev->data->rx_queues[rx_queue_id];\n-\t\tsso_updt_xae_cnt(dev, rxq, RTE_EVENT_TYPE_ETHDEV);\n-\t\tsso_cfg_nix_mp_bpid(dev, otx2_eth_dev, rxq, true);\n-\t\trc = sso_xae_reconfigure((struct rte_eventdev *)\n-\t\t\t\t\t (uintptr_t)event_dev);\n-\t\trc |= sso_rxq_enable(otx2_eth_dev, (uint16_t)rx_queue_id,\n-\t\t\t\t queue_conf->ev.sched_type,\n-\t\t\t\t queue_conf->ev.queue_id, port);\n-\t\tsso_updt_lookup_mem(event_dev, rxq->lookup_mem);\n-\t}\n-\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to configure Rx adapter port=%d, q=%d\", port,\n-\t\t\t queue_conf->ev.queue_id);\n-\t\treturn rc;\n-\t}\n-\n-\tdev->rx_offloads |= otx2_eth_dev->rx_offload_flags;\n-\tdev->tstamp = &otx2_eth_dev->tstamp;\n-\tsso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,\n-\t\t\t const struct rte_eth_dev *eth_dev,\n-\t\t\t int32_t rx_queue_id)\n-{\n-\tstruct otx2_eth_dev *otx2_eth_dev = eth_dev->data->dev_private;\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tint i, rc;\n-\n-\trc = strncmp(eth_dev->device->driver->name, \"net_octeontx2\", 13);\n-\tif (rc)\n-\t\treturn -EINVAL;\n-\n-\tif (rx_queue_id < 0) {\n-\t\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n-\t\t\trc = sso_rxq_disable(otx2_eth_dev, i);\n-\t\t\tsso_cfg_nix_mp_bpid(dev, otx2_eth_dev,\n-\t\t\t\t\t eth_dev->data->rx_queues[i], false);\n-\t\t}\n-\t} else {\n-\t\trc = sso_rxq_disable(otx2_eth_dev, (uint16_t)rx_queue_id);\n-\t\tsso_cfg_nix_mp_bpid(dev, otx2_eth_dev,\n-\t\t\t\t eth_dev->data->rx_queues[rx_queue_id],\n-\t\t\t\t false);\n-\t}\n-\n-\tif (rc < 0)\n-\t\totx2_err(\"Failed to clear Rx adapter config port=%d, q=%d\",\n-\t\t\t eth_dev->data->port_id, rx_queue_id);\n-\n-\treturn rc;\n-}\n-\n-int\n-otx2_sso_rx_adapter_start(const struct rte_eventdev *event_dev,\n-\t\t\t const struct rte_eth_dev *eth_dev)\n-{\n-\tRTE_SET_USED(event_dev);\n-\tRTE_SET_USED(eth_dev);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_sso_rx_adapter_stop(const struct rte_eventdev *event_dev,\n-\t\t\t const struct rte_eth_dev *eth_dev)\n-{\n-\tRTE_SET_USED(event_dev);\n-\tRTE_SET_USED(eth_dev);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,\n-\t\t\t const struct rte_eth_dev *eth_dev, uint32_t *caps)\n-{\n-\tint ret;\n-\n-\tRTE_SET_USED(dev);\n-\tret = strncmp(eth_dev->device->driver->name, \"net_octeontx2,\", 13);\n-\tif (ret)\n-\t\t*caps = 0;\n-\telse\n-\t\t*caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT;\n-\n-\treturn 0;\n-}\n-\n-static int\n-sso_sqb_aura_limit_edit(struct rte_mempool *mp, uint16_t nb_sqb_bufs)\n-{\n-\tstruct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;\n-\tstruct npa_aq_enq_req *aura_req;\n-\n-\taura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n-\taura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);\n-\taura_req->ctype = NPA_AQ_CTYPE_AURA;\n-\taura_req->op = NPA_AQ_INSTOP_WRITE;\n-\n-\taura_req->aura.limit = nb_sqb_bufs;\n-\taura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);\n-\n-\treturn otx2_mbox_process(npa_lf->mbox);\n-}\n-\n-static int\n-sso_add_tx_queue_data(const struct rte_eventdev *event_dev,\n-\t\t uint16_t eth_port_id, uint16_t tx_queue_id,\n-\t\t struct otx2_eth_txq *txq)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tint i;\n-\n-\tfor (i = 0; i < event_dev->data->nb_ports; i++) {\n-\t\tdev->max_port_id = RTE_MAX(dev->max_port_id, eth_port_id);\n-\t\tif (dev->dual_ws) {\n-\t\t\tstruct otx2_ssogws_dual *old_dws;\n-\t\t\tstruct otx2_ssogws_dual *dws;\n-\n-\t\t\told_dws = event_dev->data->ports[i];\n-\t\t\tdws = rte_realloc_socket(ssogws_get_cookie(old_dws),\n-\t\t\t\t\t\t sizeof(struct otx2_ssogws_dual)\n-\t\t\t\t\t\t + RTE_CACHE_LINE_SIZE +\n-\t\t\t\t\t\t (sizeof(uint64_t) *\n-\t\t\t\t\t\t (dev->max_port_id + 1) *\n-\t\t\t\t\t\t RTE_MAX_QUEUES_PER_PORT),\n-\t\t\t\t\t\t RTE_CACHE_LINE_SIZE,\n-\t\t\t\t\t\t event_dev->data->socket_id);\n-\t\t\tif (dws == NULL)\n-\t\t\t\treturn -ENOMEM;\n-\n-\t\t\t/* First cache line is reserved for cookie */\n-\t\t\tdws = (struct otx2_ssogws_dual *)\n-\t\t\t\t((uint8_t *)dws + RTE_CACHE_LINE_SIZE);\n-\n-\t\t\t((uint64_t (*)[RTE_MAX_QUEUES_PER_PORT]\n-\t\t\t )&dws->tx_adptr_data)[eth_port_id][tx_queue_id] =\n-\t\t\t\t(uint64_t)txq;\n-\t\t\tevent_dev->data->ports[i] = dws;\n-\t\t} else {\n-\t\t\tstruct otx2_ssogws *old_ws;\n-\t\t\tstruct otx2_ssogws *ws;\n-\n-\t\t\told_ws = event_dev->data->ports[i];\n-\t\t\tws = rte_realloc_socket(ssogws_get_cookie(old_ws),\n-\t\t\t\t\t\tsizeof(struct otx2_ssogws) +\n-\t\t\t\t\t\tRTE_CACHE_LINE_SIZE +\n-\t\t\t\t\t\t(sizeof(uint64_t) *\n-\t\t\t\t\t\t (dev->max_port_id + 1) *\n-\t\t\t\t\t\t RTE_MAX_QUEUES_PER_PORT),\n-\t\t\t\t\t\tRTE_CACHE_LINE_SIZE,\n-\t\t\t\t\t\tevent_dev->data->socket_id);\n-\t\t\tif (ws == NULL)\n-\t\t\t\treturn -ENOMEM;\n-\n-\t\t\t/* First cache line is reserved for cookie */\n-\t\t\tws = (struct otx2_ssogws *)\n-\t\t\t\t((uint8_t *)ws + RTE_CACHE_LINE_SIZE);\n-\n-\t\t\t((uint64_t (*)[RTE_MAX_QUEUES_PER_PORT]\n-\t\t\t )&ws->tx_adptr_data)[eth_port_id][tx_queue_id] =\n-\t\t\t\t(uint64_t)txq;\n-\t\t\tevent_dev->data->ports[i] = ws;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,\n-\t\t\t const struct rte_eth_dev *eth_dev,\n-\t\t\t int32_t tx_queue_id)\n-{\n-\tstruct otx2_eth_dev *otx2_eth_dev = eth_dev->data->dev_private;\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tstruct otx2_eth_txq *txq;\n-\tint i, ret;\n-\n-\tRTE_SET_USED(id);\n-\tif (tx_queue_id < 0) {\n-\t\tfor (i = 0 ; i < eth_dev->data->nb_tx_queues; i++) {\n-\t\t\ttxq = eth_dev->data->tx_queues[i];\n-\t\t\tsso_sqb_aura_limit_edit(txq->sqb_pool,\n-\t\t\t\t\tOTX2_SSO_SQB_LIMIT);\n-\t\t\tret = sso_add_tx_queue_data(event_dev,\n-\t\t\t\t\t\t eth_dev->data->port_id, i,\n-\t\t\t\t\t\t txq);\n-\t\t\tif (ret < 0)\n-\t\t\t\treturn ret;\n-\t\t}\n-\t} else {\n-\t\ttxq = eth_dev->data->tx_queues[tx_queue_id];\n-\t\tsso_sqb_aura_limit_edit(txq->sqb_pool, OTX2_SSO_SQB_LIMIT);\n-\t\tret = sso_add_tx_queue_data(event_dev, eth_dev->data->port_id,\n-\t\t\t\t\t tx_queue_id, txq);\n-\t\tif (ret < 0)\n-\t\t\treturn ret;\n-\t}\n-\n-\tdev->tx_offloads |= otx2_eth_dev->tx_offload_flags;\n-\tsso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,\n-\t\t\t const struct rte_eth_dev *eth_dev,\n-\t\t\t int32_t tx_queue_id)\n-{\n-\tstruct otx2_eth_txq *txq;\n-\tint i;\n-\n-\tRTE_SET_USED(id);\n-\tRTE_SET_USED(eth_dev);\n-\tRTE_SET_USED(event_dev);\n-\tif (tx_queue_id < 0) {\n-\t\tfor (i = 0 ; i < eth_dev->data->nb_tx_queues; i++) {\n-\t\t\ttxq = eth_dev->data->tx_queues[i];\n-\t\t\tsso_sqb_aura_limit_edit(txq->sqb_pool,\n-\t\t\t\t\t\ttxq->nb_sqb_bufs);\n-\t\t}\n-\t} else {\n-\t\ttxq = eth_dev->data->tx_queues[tx_queue_id];\n-\t\tsso_sqb_aura_limit_edit(txq->sqb_pool, txq->nb_sqb_bufs);\n-\t}\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c b/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\ndeleted file mode 100644\nindex d59d6c53f6..0000000000\n--- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr.c\n+++ /dev/null\n@@ -1,132 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020-2021 Marvell.\n- */\n-\n-#include <cryptodev_pmd.h>\n-#include <rte_eventdev.h>\n-\n-#include \"otx2_cryptodev.h\"\n-#include \"otx2_cryptodev_hw_access.h\"\n-#include \"otx2_cryptodev_qp.h\"\n-#include \"otx2_cryptodev_mbox.h\"\n-#include \"otx2_evdev.h\"\n-\n-int\n-otx2_ca_caps_get(const struct rte_eventdev *dev,\n-\t\tconst struct rte_cryptodev *cdev, uint32_t *caps)\n-{\n-\tRTE_SET_USED(dev);\n-\tRTE_SET_USED(cdev);\n-\n-\t*caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND |\n-\t\tRTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW |\n-\t\tRTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD;\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_ca_qp_sso_link(const struct rte_cryptodev *cdev, struct otx2_cpt_qp *qp,\n-\t\t uint16_t sso_pf_func)\n-{\n-\tunion otx2_cpt_af_lf_ctl2 af_lf_ctl2;\n-\tint ret;\n-\n-\tret = otx2_cpt_af_reg_read(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n-\t\t\t\t qp->blkaddr, &af_lf_ctl2.u);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\taf_lf_ctl2.s.sso_pf_func = sso_pf_func;\n-\tret = otx2_cpt_af_reg_write(cdev, OTX2_CPT_AF_LF_CTL2(qp->id),\n-\t\t\t\t qp->blkaddr, af_lf_ctl2.u);\n-\treturn ret;\n-}\n-\n-static void\n-otx2_ca_qp_init(struct otx2_cpt_qp *qp, const struct rte_event *event)\n-{\n-\tif (event) {\n-\t\tqp->qp_ev_bind = 1;\n-\t\trte_memcpy(&qp->ev, event, sizeof(struct rte_event));\n-\t} else {\n-\t\tqp->qp_ev_bind = 0;\n-\t}\n-\tqp->ca_enable = 1;\n-}\n-\n-int\n-otx2_ca_qp_add(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,\n-\t\tint32_t queue_pair_id, const struct rte_event *event)\n-{\n-\tstruct otx2_sso_evdev *sso_evdev = sso_pmd_priv(dev);\n-\tstruct otx2_cpt_vf *vf = cdev->data->dev_private;\n-\tuint16_t sso_pf_func = otx2_sso_pf_func_get();\n-\tstruct otx2_cpt_qp *qp;\n-\tuint8_t qp_id;\n-\tint ret;\n-\n-\tif (queue_pair_id == -1) {\n-\t\tfor (qp_id = 0; qp_id < vf->nb_queues; qp_id++) {\n-\t\t\tqp = cdev->data->queue_pairs[qp_id];\n-\t\t\tret = otx2_ca_qp_sso_link(cdev, qp, sso_pf_func);\n-\t\t\tif (ret) {\n-\t\t\t\tuint8_t qp_tmp;\n-\t\t\t\tfor (qp_tmp = 0; qp_tmp < qp_id; qp_tmp++)\n-\t\t\t\t\totx2_ca_qp_del(dev, cdev, qp_tmp);\n-\t\t\t\treturn ret;\n-\t\t\t}\n-\t\t\totx2_ca_qp_init(qp, event);\n-\t\t}\n-\t} else {\n-\t\tqp = cdev->data->queue_pairs[queue_pair_id];\n-\t\tret = otx2_ca_qp_sso_link(cdev, qp, sso_pf_func);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t\totx2_ca_qp_init(qp, event);\n-\t}\n-\n-\tsso_evdev->rx_offloads |= NIX_RX_OFFLOAD_SECURITY_F;\n-\tsso_fastpath_fns_set((struct rte_eventdev *)(uintptr_t)dev);\n-\n-\t/* Update crypto adapter xae count */\n-\tif (queue_pair_id == -1)\n-\t\tsso_evdev->adptr_xae_cnt +=\n-\t\t\tvf->nb_queues * OTX2_CPT_DEFAULT_CMD_QLEN;\n-\telse\n-\t\tsso_evdev->adptr_xae_cnt += OTX2_CPT_DEFAULT_CMD_QLEN;\n-\tsso_xae_reconfigure((struct rte_eventdev *)(uintptr_t)dev);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_ca_qp_del(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev,\n-\t\tint32_t queue_pair_id)\n-{\n-\tstruct otx2_cpt_vf *vf = cdev->data->dev_private;\n-\tstruct otx2_cpt_qp *qp;\n-\tuint8_t qp_id;\n-\tint ret;\n-\n-\tRTE_SET_USED(dev);\n-\n-\tret = 0;\n-\tif (queue_pair_id == -1) {\n-\t\tfor (qp_id = 0; qp_id < vf->nb_queues; qp_id++) {\n-\t\t\tqp = cdev->data->queue_pairs[qp_id];\n-\t\t\tret = otx2_ca_qp_sso_link(cdev, qp, 0);\n-\t\t\tif (ret)\n-\t\t\t\treturn ret;\n-\t\t\tqp->ca_enable = 0;\n-\t\t}\n-\t} else {\n-\t\tqp = cdev->data->queue_pairs[queue_pair_id];\n-\t\tret = otx2_ca_qp_sso_link(cdev, qp, 0);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t\tqp->ca_enable = 0;\n-\t}\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr_rx.h b/drivers/event/octeontx2/otx2_evdev_crypto_adptr_rx.h\ndeleted file mode 100644\nindex b33cb7e139..0000000000\n--- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr_rx.h\n+++ /dev/null\n@@ -1,77 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_EVDEV_CRYPTO_ADPTR_RX_H_\n-#define _OTX2_EVDEV_CRYPTO_ADPTR_RX_H_\n-\n-#include <rte_cryptodev.h>\n-#include <cryptodev_pmd.h>\n-#include <rte_eventdev.h>\n-\n-#include \"cpt_pmd_logs.h\"\n-#include \"cpt_ucode.h\"\n-\n-#include \"otx2_cryptodev.h\"\n-#include \"otx2_cryptodev_hw_access.h\"\n-#include \"otx2_cryptodev_ops_helper.h\"\n-#include \"otx2_cryptodev_qp.h\"\n-\n-static inline void\n-otx2_ca_deq_post_process(const struct otx2_cpt_qp *qp,\n-\t\t\t struct rte_crypto_op *cop, uintptr_t *rsp,\n-\t\t\t uint8_t cc)\n-{\n-\tif (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {\n-\t\tif (likely(cc == NO_ERR)) {\n-\t\t\t/* Verify authentication data if required */\n-\t\t\tif (unlikely(rsp[2]))\n-\t\t\t\tcompl_auth_verify(cop, (uint8_t *)rsp[2],\n-\t\t\t\t\t\t rsp[3]);\n-\t\t\telse\n-\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n-\t\t} else {\n-\t\t\tif (cc == ERR_GC_ICV_MISCOMPARE)\n-\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n-\t\t\telse\n-\t\t\t\tcop->status = RTE_CRYPTO_OP_STATUS_ERROR;\n-\t\t}\n-\n-\t\tif (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {\n-\t\t\tsym_session_clear(otx2_cryptodev_driver_id,\n-\t\t\t\t\t cop->sym->session);\n-\t\t\tmemset(cop->sym->session, 0,\n-\t\t\trte_cryptodev_sym_get_existing_header_session_size(\n-\t\t\t\tcop->sym->session));\n-\t\t\trte_mempool_put(qp->sess_mp, cop->sym->session);\n-\t\t\tcop->sym->session = NULL;\n-\t\t}\n-\t}\n-\n-}\n-\n-static inline uint64_t\n-otx2_handle_crypto_event(uint64_t get_work1)\n-{\n-\tstruct cpt_request_info *req;\n-\tconst struct otx2_cpt_qp *qp;\n-\tstruct rte_crypto_op *cop;\n-\tuintptr_t *rsp;\n-\tvoid *metabuf;\n-\tuint8_t cc;\n-\n-\treq = (struct cpt_request_info *)(get_work1);\n-\tcc = otx2_cpt_compcode_get(req);\n-\tqp = req->qp;\n-\n-\trsp = req->op;\n-\tmetabuf = (void *)rsp[0];\n-\tcop = (void *)rsp[1];\n-\n-\totx2_ca_deq_post_process(qp, cop, rsp, cc);\n-\n-\trte_mempool_put(qp->meta_info.pool, metabuf);\n-\n-\treturn (uint64_t)(cop);\n-}\n-#endif /* _OTX2_EVDEV_CRYPTO_ADPTR_RX_H_ */\ndiff --git a/drivers/event/octeontx2/otx2_evdev_crypto_adptr_tx.h b/drivers/event/octeontx2/otx2_evdev_crypto_adptr_tx.h\ndeleted file mode 100644\nindex 1fc56f903b..0000000000\n--- a/drivers/event/octeontx2/otx2_evdev_crypto_adptr_tx.h\n+++ /dev/null\n@@ -1,83 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2021 Marvell International Ltd.\n- */\n-\n-#ifndef _OTX2_EVDEV_CRYPTO_ADPTR_TX_H_\n-#define _OTX2_EVDEV_CRYPTO_ADPTR_TX_H_\n-\n-#include <rte_cryptodev.h>\n-#include <cryptodev_pmd.h>\n-#include <rte_event_crypto_adapter.h>\n-#include <rte_eventdev.h>\n-\n-#include <otx2_cryptodev_qp.h>\n-#include <otx2_worker.h>\n-\n-static inline uint16_t\n-otx2_ca_enq(uintptr_t tag_op, const struct rte_event *ev)\n-{\n-\tunion rte_event_crypto_metadata *m_data;\n-\tstruct rte_crypto_op *crypto_op;\n-\tstruct rte_cryptodev *cdev;\n-\tstruct otx2_cpt_qp *qp;\n-\tuint8_t cdev_id;\n-\tuint16_t qp_id;\n-\n-\tcrypto_op = ev->event_ptr;\n-\tif (crypto_op == NULL)\n-\t\treturn 0;\n-\n-\tif (crypto_op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {\n-\t\tm_data = rte_cryptodev_sym_session_get_user_data(\n-\t\t\t\t\t\tcrypto_op->sym->session);\n-\t\tif (m_data == NULL)\n-\t\t\tgoto free_op;\n-\n-\t\tcdev_id = m_data->request_info.cdev_id;\n-\t\tqp_id = m_data->request_info.queue_pair_id;\n-\t} else if (crypto_op->sess_type == RTE_CRYPTO_OP_SESSIONLESS &&\n-\t\t crypto_op->private_data_offset) {\n-\t\tm_data = (union rte_event_crypto_metadata *)\n-\t\t\t ((uint8_t *)crypto_op +\n-\t\t\t crypto_op->private_data_offset);\n-\t\tcdev_id = m_data->request_info.cdev_id;\n-\t\tqp_id = m_data->request_info.queue_pair_id;\n-\t} else {\n-\t\tgoto free_op;\n-\t}\n-\n-\tcdev = &rte_cryptodevs[cdev_id];\n-\tqp = cdev->data->queue_pairs[qp_id];\n-\n-\tif (!ev->sched_type)\n-\t\totx2_ssogws_head_wait(tag_op);\n-\tif (qp->ca_enable)\n-\t\treturn cdev->enqueue_burst(qp, &crypto_op, 1);\n-\n-free_op:\n-\trte_pktmbuf_free(crypto_op->sym->m_src);\n-\trte_crypto_op_free(crypto_op);\n-\trte_errno = EINVAL;\n-\treturn 0;\n-}\n-\n-static uint16_t __rte_hot\n-otx2_ssogws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)\n-{\n-\tstruct otx2_ssogws *ws = port;\n-\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn otx2_ca_enq(ws->tag_op, ev);\n-}\n-\n-static uint16_t __rte_hot\n-otx2_ssogws_dual_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)\n-{\n-\tstruct otx2_ssogws_dual *ws = port;\n-\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn otx2_ca_enq(ws->ws_state[!ws->vws].tag_op, ev);\n-}\n-#endif /* _OTX2_EVDEV_CRYPTO_ADPTR_TX_H_ */\ndiff --git a/drivers/event/octeontx2/otx2_evdev_irq.c b/drivers/event/octeontx2/otx2_evdev_irq.c\ndeleted file mode 100644\nindex 9b7ad27b04..0000000000\n--- a/drivers/event/octeontx2/otx2_evdev_irq.c\n+++ /dev/null\n@@ -1,272 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_evdev.h\"\n-#include \"otx2_tim_evdev.h\"\n-\n-static void\n-sso_lf_irq(void *param)\n-{\n-\tuintptr_t base = (uintptr_t)param;\n-\tuint64_t intr;\n-\tuint8_t ggrp;\n-\n-\tggrp = (base >> 12) & 0xFF;\n-\n-\tintr = otx2_read64(base + SSO_LF_GGRP_INT);\n-\tif (intr == 0)\n-\t\treturn;\n-\n-\totx2_err(\"GGRP %d GGRP_INT=0x%\" PRIx64 \"\", ggrp, intr);\n-\n-\t/* Clear interrupt */\n-\totx2_write64(intr, base + SSO_LF_GGRP_INT);\n-}\n-\n-static int\n-sso_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t ggrp_msixoff,\n-\t\t uintptr_t base)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tint rc, vec;\n-\n-\tvec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;\n-\n-\t/* Clear err interrupt */\n-\totx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C);\n-\t/* Set used interrupt vectors */\n-\trc = otx2_register_irq(handle, sso_lf_irq, (void *)base, vec);\n-\t/* Enable hw interrupt */\n-\totx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1S);\n-\n-\treturn rc;\n-}\n-\n-static void\n-ssow_lf_irq(void *param)\n-{\n-\tuintptr_t base = (uintptr_t)param;\n-\tuint8_t gws = (base >> 12) & 0xFF;\n-\tuint64_t intr;\n-\n-\tintr = otx2_read64(base + SSOW_LF_GWS_INT);\n-\tif (intr == 0)\n-\t\treturn;\n-\n-\totx2_err(\"GWS %d GWS_INT=0x%\" PRIx64 \"\", gws, intr);\n-\n-\t/* Clear interrupt */\n-\totx2_write64(intr, base + SSOW_LF_GWS_INT);\n-}\n-\n-static int\n-ssow_lf_register_irq(const struct rte_eventdev *event_dev, uint16_t gws_msixoff,\n-\t\t uintptr_t base)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tint rc, vec;\n-\n-\tvec = gws_msixoff + SSOW_LF_INT_VEC_IOP;\n-\n-\t/* Clear err interrupt */\n-\totx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C);\n-\t/* Set used interrupt vectors */\n-\trc = otx2_register_irq(handle, ssow_lf_irq, (void *)base, vec);\n-\t/* Enable hw interrupt */\n-\totx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1S);\n-\n-\treturn rc;\n-}\n-\n-static void\n-sso_lf_unregister_irq(const struct rte_eventdev *event_dev,\n-\t\t uint16_t ggrp_msixoff, uintptr_t base)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tint vec;\n-\n-\tvec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;\n-\n-\t/* Clear err interrupt */\n-\totx2_write64(~0ull, base + SSO_LF_GGRP_INT_ENA_W1C);\n-\totx2_unregister_irq(handle, sso_lf_irq, (void *)base, vec);\n-}\n-\n-static void\n-ssow_lf_unregister_irq(const struct rte_eventdev *event_dev,\n-\t\t uint16_t gws_msixoff, uintptr_t base)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(event_dev->dev);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tint vec;\n-\n-\tvec = gws_msixoff + SSOW_LF_INT_VEC_IOP;\n-\n-\t/* Clear err interrupt */\n-\totx2_write64(~0ull, base + SSOW_LF_GWS_INT_ENA_W1C);\n-\totx2_unregister_irq(handle, ssow_lf_irq, (void *)base, vec);\n-}\n-\n-int\n-sso_register_irqs(const struct rte_eventdev *event_dev)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tint i, rc = -EINVAL;\n-\tuint8_t nb_ports;\n-\n-\tnb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);\n-\n-\tfor (i = 0; i < dev->nb_event_queues; i++) {\n-\t\tif (dev->sso_msixoff[i] == MSIX_VECTOR_INVALID) {\n-\t\t\totx2_err(\"Invalid SSOLF MSIX offset[%d] vector: 0x%x\",\n-\t\t\t\t i, dev->sso_msixoff[i]);\n-\t\t\tgoto fail;\n-\t\t}\n-\t}\n-\n-\tfor (i = 0; i < nb_ports; i++) {\n-\t\tif (dev->ssow_msixoff[i] == MSIX_VECTOR_INVALID) {\n-\t\t\totx2_err(\"Invalid SSOWLF MSIX offset[%d] vector: 0x%x\",\n-\t\t\t\t i, dev->ssow_msixoff[i]);\n-\t\t\tgoto fail;\n-\t\t}\n-\t}\n-\n-\tfor (i = 0; i < dev->nb_event_queues; i++) {\n-\t\tuintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 |\n-\t\t\t\t\t i << 12);\n-\t\trc = sso_lf_register_irq(event_dev, dev->sso_msixoff[i], base);\n-\t}\n-\n-\tfor (i = 0; i < nb_ports; i++) {\n-\t\tuintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 |\n-\t\t\t\t\t i << 12);\n-\t\trc = ssow_lf_register_irq(event_dev, dev->ssow_msixoff[i],\n-\t\t\t\t\t base);\n-\t}\n-\n-fail:\n-\treturn rc;\n-}\n-\n-void\n-sso_unregister_irqs(const struct rte_eventdev *event_dev)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuint8_t nb_ports;\n-\tint i;\n-\n-\tnb_ports = dev->nb_event_ports * (dev->dual_ws ? 2 : 1);\n-\n-\tfor (i = 0; i < dev->nb_event_queues; i++) {\n-\t\tuintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 |\n-\t\t\t\t\t i << 12);\n-\t\tsso_lf_unregister_irq(event_dev, dev->sso_msixoff[i], base);\n-\t}\n-\n-\tfor (i = 0; i < nb_ports; i++) {\n-\t\tuintptr_t base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 |\n-\t\t\t\t\t i << 12);\n-\t\tssow_lf_unregister_irq(event_dev, dev->ssow_msixoff[i], base);\n-\t}\n-}\n-\n-static void\n-tim_lf_irq(void *param)\n-{\n-\tuintptr_t base = (uintptr_t)param;\n-\tuint64_t intr;\n-\tuint8_t ring;\n-\n-\tring = (base >> 12) & 0xFF;\n-\n-\tintr = otx2_read64(base + TIM_LF_NRSPERR_INT);\n-\totx2_err(\"TIM RING %d TIM_LF_NRSPERR_INT=0x%\" PRIx64 \"\", ring, intr);\n-\tintr = otx2_read64(base + TIM_LF_RAS_INT);\n-\totx2_err(\"TIM RING %d TIM_LF_RAS_INT=0x%\" PRIx64 \"\", ring, intr);\n-\n-\t/* Clear interrupt */\n-\totx2_write64(intr, base + TIM_LF_NRSPERR_INT);\n-\totx2_write64(intr, base + TIM_LF_RAS_INT);\n-}\n-\n-static int\n-tim_lf_register_irq(struct rte_pci_device *pci_dev, uint16_t tim_msixoff,\n-\t\t uintptr_t base)\n-{\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tint rc, vec;\n-\n-\tvec = tim_msixoff + TIM_LF_INT_VEC_NRSPERR_INT;\n-\n-\t/* Clear err interrupt */\n-\totx2_write64(~0ull, base + TIM_LF_NRSPERR_INT);\n-\t/* Set used interrupt vectors */\n-\trc = otx2_register_irq(handle, tim_lf_irq, (void *)base, vec);\n-\t/* Enable hw interrupt */\n-\totx2_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1S);\n-\n-\tvec = tim_msixoff + TIM_LF_INT_VEC_RAS_INT;\n-\n-\t/* Clear err interrupt */\n-\totx2_write64(~0ull, base + TIM_LF_RAS_INT);\n-\t/* Set used interrupt vectors */\n-\trc = otx2_register_irq(handle, tim_lf_irq, (void *)base, vec);\n-\t/* Enable hw interrupt */\n-\totx2_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1S);\n-\n-\treturn rc;\n-}\n-\n-static void\n-tim_lf_unregister_irq(struct rte_pci_device *pci_dev, uint16_t tim_msixoff,\n-\t\t uintptr_t base)\n-{\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tint vec;\n-\n-\tvec = tim_msixoff + TIM_LF_INT_VEC_NRSPERR_INT;\n-\n-\t/* Clear err interrupt */\n-\totx2_write64(~0ull, base + TIM_LF_NRSPERR_INT_ENA_W1C);\n-\totx2_unregister_irq(handle, tim_lf_irq, (void *)base, vec);\n-\n-\tvec = tim_msixoff + TIM_LF_INT_VEC_RAS_INT;\n-\n-\t/* Clear err interrupt */\n-\totx2_write64(~0ull, base + TIM_LF_RAS_INT_ENA_W1C);\n-\totx2_unregister_irq(handle, tim_lf_irq, (void *)base, vec);\n-}\n-\n-int\n-tim_register_irq(uint16_t ring_id)\n-{\n-\tstruct otx2_tim_evdev *dev = tim_priv_get();\n-\tint rc = -EINVAL;\n-\tuintptr_t base;\n-\n-\tif (dev->tim_msixoff[ring_id] == MSIX_VECTOR_INVALID) {\n-\t\totx2_err(\"Invalid TIMLF MSIX offset[%d] vector: 0x%x\",\n-\t\t\t ring_id, dev->tim_msixoff[ring_id]);\n-\t\tgoto fail;\n-\t}\n-\n-\tbase = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);\n-\trc = tim_lf_register_irq(dev->pci_dev, dev->tim_msixoff[ring_id], base);\n-fail:\n-\treturn rc;\n-}\n-\n-void\n-tim_unregister_irq(uint16_t ring_id)\n-{\n-\tstruct otx2_tim_evdev *dev = tim_priv_get();\n-\tuintptr_t base;\n-\n-\tbase = dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);\n-\ttim_lf_unregister_irq(dev->pci_dev, dev->tim_msixoff[ring_id], base);\n-}\ndiff --git a/drivers/event/octeontx2/otx2_evdev_selftest.c b/drivers/event/octeontx2/otx2_evdev_selftest.c\ndeleted file mode 100644\nindex 48bfaf893d..0000000000\n--- a/drivers/event/octeontx2/otx2_evdev_selftest.c\n+++ /dev/null\n@@ -1,1517 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_atomic.h>\n-#include <rte_common.h>\n-#include <rte_cycles.h>\n-#include <rte_debug.h>\n-#include <rte_eal.h>\n-#include <rte_ethdev.h>\n-#include <rte_eventdev.h>\n-#include <rte_hexdump.h>\n-#include <rte_launch.h>\n-#include <rte_lcore.h>\n-#include <rte_mbuf.h>\n-#include <rte_malloc.h>\n-#include <rte_memcpy.h>\n-#include <rte_per_lcore.h>\n-#include <rte_random.h>\n-#include <rte_test.h>\n-\n-#include \"otx2_evdev.h\"\n-\n-#define NUM_PACKETS (1024)\n-#define MAX_EVENTS (1024)\n-\n-#define OCTEONTX2_TEST_RUN(setup, teardown, test) \\\n-\tocteontx_test_run(setup, teardown, test, #test)\n-\n-static int total;\n-static int passed;\n-static int failed;\n-static int unsupported;\n-\n-static int evdev;\n-static struct rte_mempool *eventdev_test_mempool;\n-\n-struct event_attr {\n-\tuint32_t flow_id;\n-\tuint8_t event_type;\n-\tuint8_t sub_event_type;\n-\tuint8_t sched_type;\n-\tuint8_t queue;\n-\tuint8_t port;\n-};\n-\n-static uint32_t seqn_list_index;\n-static int seqn_list[NUM_PACKETS];\n-\n-static inline void\n-seqn_list_init(void)\n-{\n-\tRTE_BUILD_BUG_ON(NUM_PACKETS < MAX_EVENTS);\n-\tmemset(seqn_list, 0, sizeof(seqn_list));\n-\tseqn_list_index = 0;\n-}\n-\n-static inline int\n-seqn_list_update(int val)\n-{\n-\tif (seqn_list_index >= NUM_PACKETS)\n-\t\treturn -1;\n-\n-\tseqn_list[seqn_list_index++] = val;\n-\trte_smp_wmb();\n-\treturn 0;\n-}\n-\n-static inline int\n-seqn_list_check(int limit)\n-{\n-\tint i;\n-\n-\tfor (i = 0; i < limit; i++) {\n-\t\tif (seqn_list[i] != i) {\n-\t\t\totx2_err(\"Seqn mismatch %d %d\", seqn_list[i], i);\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\treturn 0;\n-}\n-\n-struct test_core_param {\n-\trte_atomic32_t *total_events;\n-\tuint64_t dequeue_tmo_ticks;\n-\tuint8_t port;\n-\tuint8_t sched_type;\n-};\n-\n-static int\n-testsuite_setup(void)\n-{\n-\tconst char *eventdev_name = \"event_octeontx2\";\n-\n-\tevdev = rte_event_dev_get_dev_id(eventdev_name);\n-\tif (evdev < 0) {\n-\t\totx2_err(\"%d: Eventdev %s not found\", __LINE__, eventdev_name);\n-\t\treturn -1;\n-\t}\n-\treturn 0;\n-}\n-\n-static void\n-testsuite_teardown(void)\n-{\n-\trte_event_dev_close(evdev);\n-}\n-\n-static inline void\n-devconf_set_default_sane_values(struct rte_event_dev_config *dev_conf,\n-\t\t\t\tstruct rte_event_dev_info *info)\n-{\n-\tmemset(dev_conf, 0, sizeof(struct rte_event_dev_config));\n-\tdev_conf->dequeue_timeout_ns = info->min_dequeue_timeout_ns;\n-\tdev_conf->nb_event_ports = info->max_event_ports;\n-\tdev_conf->nb_event_queues = info->max_event_queues;\n-\tdev_conf->nb_event_queue_flows = info->max_event_queue_flows;\n-\tdev_conf->nb_event_port_dequeue_depth =\n-\t\t\tinfo->max_event_port_dequeue_depth;\n-\tdev_conf->nb_event_port_enqueue_depth =\n-\t\t\tinfo->max_event_port_enqueue_depth;\n-\tdev_conf->nb_event_port_enqueue_depth =\n-\t\t\tinfo->max_event_port_enqueue_depth;\n-\tdev_conf->nb_events_limit =\n-\t\t\tinfo->max_num_events;\n-}\n-\n-enum {\n-\tTEST_EVENTDEV_SETUP_DEFAULT,\n-\tTEST_EVENTDEV_SETUP_PRIORITY,\n-\tTEST_EVENTDEV_SETUP_DEQUEUE_TIMEOUT,\n-};\n-\n-static inline int\n-_eventdev_setup(int mode)\n-{\n-\tconst char *pool_name = \"evdev_octeontx_test_pool\";\n-\tstruct rte_event_dev_config dev_conf;\n-\tstruct rte_event_dev_info info;\n-\tint i, ret;\n-\n-\t/* Create and destrory pool for each test case to make it standalone */\n-\teventdev_test_mempool = rte_pktmbuf_pool_create(pool_name, MAX_EVENTS,\n-\t\t\t\t\t\t\t0, 0, 512,\n-\t\t\t\t\t\t\trte_socket_id());\n-\tif (!eventdev_test_mempool) {\n-\t\totx2_err(\"ERROR creating mempool\");\n-\t\treturn -1;\n-\t}\n-\n-\tret = rte_event_dev_info_get(evdev, &info);\n-\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to get event dev info\");\n-\n-\tdevconf_set_default_sane_values(&dev_conf, &info);\n-\tif (mode == TEST_EVENTDEV_SETUP_DEQUEUE_TIMEOUT)\n-\t\tdev_conf.event_dev_cfg |= RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT;\n-\n-\tret = rte_event_dev_configure(evdev, &dev_conf);\n-\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to configure eventdev\");\n-\n-\tuint32_t queue_count;\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_QUEUE_COUNT, &queue_count),\n-\t\t\t\t\"Queue count get failed\");\n-\n-\tif (mode == TEST_EVENTDEV_SETUP_PRIORITY) {\n-\t\tif (queue_count > 8)\n-\t\t\tqueue_count = 8;\n-\n-\t\t/* Configure event queues(0 to n) with\n-\t\t * RTE_EVENT_DEV_PRIORITY_HIGHEST to\n-\t\t * RTE_EVENT_DEV_PRIORITY_LOWEST\n-\t\t */\n-\t\tuint8_t step = (RTE_EVENT_DEV_PRIORITY_LOWEST + 1) /\n-\t\t\t\tqueue_count;\n-\t\tfor (i = 0; i < (int)queue_count; i++) {\n-\t\t\tstruct rte_event_queue_conf queue_conf;\n-\n-\t\t\tret = rte_event_queue_default_conf_get(evdev, i,\n-\t\t\t\t\t\t\t &queue_conf);\n-\t\t\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to get def_conf%d\",\n-\t\t\t\t\t\ti);\n-\t\t\tqueue_conf.priority = i * step;\n-\t\t\tret = rte_event_queue_setup(evdev, i, &queue_conf);\n-\t\t\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to setup queue=%d\",\n-\t\t\t\t\t\ti);\n-\t\t}\n-\n-\t} else {\n-\t\t/* Configure event queues with default priority */\n-\t\tfor (i = 0; i < (int)queue_count; i++) {\n-\t\t\tret = rte_event_queue_setup(evdev, i, NULL);\n-\t\t\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to setup queue=%d\",\n-\t\t\t\t\t\ti);\n-\t\t}\n-\t}\n-\t/* Configure event ports */\n-\tuint32_t port_count;\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_PORT_COUNT, &port_count),\n-\t\t\t\t\"Port count get failed\");\n-\tfor (i = 0; i < (int)port_count; i++) {\n-\t\tret = rte_event_port_setup(evdev, i, NULL);\n-\t\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to setup port=%d\", i);\n-\t\tret = rte_event_port_link(evdev, i, NULL, NULL, 0);\n-\t\tRTE_TEST_ASSERT(ret >= 0, \"Failed to link all queues port=%d\",\n-\t\t\t\ti);\n-\t}\n-\n-\tret = rte_event_dev_start(evdev);\n-\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to start device\");\n-\n-\treturn 0;\n-}\n-\n-static inline int\n-eventdev_setup(void)\n-{\n-\treturn _eventdev_setup(TEST_EVENTDEV_SETUP_DEFAULT);\n-}\n-\n-static inline int\n-eventdev_setup_priority(void)\n-{\n-\treturn _eventdev_setup(TEST_EVENTDEV_SETUP_PRIORITY);\n-}\n-\n-static inline int\n-eventdev_setup_dequeue_timeout(void)\n-{\n-\treturn _eventdev_setup(TEST_EVENTDEV_SETUP_DEQUEUE_TIMEOUT);\n-}\n-\n-static inline void\n-eventdev_teardown(void)\n-{\n-\trte_event_dev_stop(evdev);\n-\trte_mempool_free(eventdev_test_mempool);\n-}\n-\n-static inline void\n-update_event_and_validation_attr(struct rte_mbuf *m, struct rte_event *ev,\n-\t\t\t\t uint32_t flow_id, uint8_t event_type,\n-\t\t\t\t uint8_t sub_event_type, uint8_t sched_type,\n-\t\t\t\t uint8_t queue, uint8_t port)\n-{\n-\tstruct event_attr *attr;\n-\n-\t/* Store the event attributes in mbuf for future reference */\n-\tattr = rte_pktmbuf_mtod(m, struct event_attr *);\n-\tattr->flow_id = flow_id;\n-\tattr->event_type = event_type;\n-\tattr->sub_event_type = sub_event_type;\n-\tattr->sched_type = sched_type;\n-\tattr->queue = queue;\n-\tattr->port = port;\n-\n-\tev->flow_id = flow_id;\n-\tev->sub_event_type = sub_event_type;\n-\tev->event_type = event_type;\n-\t/* Inject the new event */\n-\tev->op = RTE_EVENT_OP_NEW;\n-\tev->sched_type = sched_type;\n-\tev->queue_id = queue;\n-\tev->mbuf = m;\n-}\n-\n-static inline int\n-inject_events(uint32_t flow_id, uint8_t event_type, uint8_t sub_event_type,\n-\t uint8_t sched_type, uint8_t queue, uint8_t port,\n-\t unsigned int events)\n-{\n-\tstruct rte_mbuf *m;\n-\tunsigned int i;\n-\n-\tfor (i = 0; i < events; i++) {\n-\t\tstruct rte_event ev = {.event = 0, .u64 = 0};\n-\n-\t\tm = rte_pktmbuf_alloc(eventdev_test_mempool);\n-\t\tRTE_TEST_ASSERT_NOT_NULL(m, \"mempool alloc failed\");\n-\n-\t\t*rte_event_pmd_selftest_seqn(m) = i;\n-\t\tupdate_event_and_validation_attr(m, &ev, flow_id, event_type,\n-\t\t\t\t\t\t sub_event_type, sched_type,\n-\t\t\t\t\t\t queue, port);\n-\t\trte_event_enqueue_burst(evdev, port, &ev, 1);\n-\t}\n-\treturn 0;\n-}\n-\n-static inline int\n-check_excess_events(uint8_t port)\n-{\n-\tuint16_t valid_event;\n-\tstruct rte_event ev;\n-\tint i;\n-\n-\t/* Check for excess events, try for a few times and exit */\n-\tfor (i = 0; i < 32; i++) {\n-\t\tvalid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0);\n-\n-\t\tRTE_TEST_ASSERT_SUCCESS(valid_event,\n-\t\t\t\t\t\"Unexpected valid event=%d\",\n-\t\t\t\t\t*rte_event_pmd_selftest_seqn(ev.mbuf));\n-\t}\n-\treturn 0;\n-}\n-\n-static inline int\n-generate_random_events(const unsigned int total_events)\n-{\n-\tstruct rte_event_dev_info info;\n-\tuint32_t queue_count;\n-\tunsigned int i;\n-\tint ret;\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_QUEUE_COUNT, &queue_count),\n-\t\t\t\t\"Queue count get failed\");\n-\n-\tret = rte_event_dev_info_get(evdev, &info);\n-\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to get event dev info\");\n-\tfor (i = 0; i < total_events; i++) {\n-\t\tret = inject_events(\n-\t\t\trte_rand() % info.max_event_queue_flows /*flow_id */,\n-\t\t\tRTE_EVENT_TYPE_CPU /* event_type */,\n-\t\t\trte_rand() % 256 /* sub_event_type */,\n-\t\t\trte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1),\n-\t\t\trte_rand() % queue_count /* queue */,\n-\t\t\t0 /* port */,\n-\t\t\t1 /* events */);\n-\t\tif (ret)\n-\t\t\treturn -1;\n-\t}\n-\treturn ret;\n-}\n-\n-\n-static inline int\n-validate_event(struct rte_event *ev)\n-{\n-\tstruct event_attr *attr;\n-\n-\tattr = rte_pktmbuf_mtod(ev->mbuf, struct event_attr *);\n-\tRTE_TEST_ASSERT_EQUAL(attr->flow_id, ev->flow_id,\n-\t\t\t \"flow_id mismatch enq=%d deq =%d\",\n-\t\t\t attr->flow_id, ev->flow_id);\n-\tRTE_TEST_ASSERT_EQUAL(attr->event_type, ev->event_type,\n-\t\t\t \"event_type mismatch enq=%d deq =%d\",\n-\t\t\t attr->event_type, ev->event_type);\n-\tRTE_TEST_ASSERT_EQUAL(attr->sub_event_type, ev->sub_event_type,\n-\t\t\t \"sub_event_type mismatch enq=%d deq =%d\",\n-\t\t\t attr->sub_event_type, ev->sub_event_type);\n-\tRTE_TEST_ASSERT_EQUAL(attr->sched_type, ev->sched_type,\n-\t\t\t \"sched_type mismatch enq=%d deq =%d\",\n-\t\t\t attr->sched_type, ev->sched_type);\n-\tRTE_TEST_ASSERT_EQUAL(attr->queue, ev->queue_id,\n-\t\t\t \"queue mismatch enq=%d deq =%d\",\n-\t\t\t attr->queue, ev->queue_id);\n-\treturn 0;\n-}\n-\n-typedef int (*validate_event_cb)(uint32_t index, uint8_t port,\n-\t\t\t\t struct rte_event *ev);\n-\n-static inline int\n-consume_events(uint8_t port, const uint32_t total_events, validate_event_cb fn)\n-{\n-\tuint32_t events = 0, forward_progress_cnt = 0, index = 0;\n-\tuint16_t valid_event;\n-\tstruct rte_event ev;\n-\tint ret;\n-\n-\twhile (1) {\n-\t\tif (++forward_progress_cnt > UINT16_MAX) {\n-\t\t\totx2_err(\"Detected deadlock\");\n-\t\t\treturn -1;\n-\t\t}\n-\n-\t\tvalid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0);\n-\t\tif (!valid_event)\n-\t\t\tcontinue;\n-\n-\t\tforward_progress_cnt = 0;\n-\t\tret = validate_event(&ev);\n-\t\tif (ret)\n-\t\t\treturn -1;\n-\n-\t\tif (fn != NULL) {\n-\t\t\tret = fn(index, port, &ev);\n-\t\t\tRTE_TEST_ASSERT_SUCCESS(ret,\n-\t\t\t\t\"Failed to validate test specific event\");\n-\t\t}\n-\n-\t\t++index;\n-\n-\t\trte_pktmbuf_free(ev.mbuf);\n-\t\tif (++events >= total_events)\n-\t\t\tbreak;\n-\t}\n-\n-\treturn check_excess_events(port);\n-}\n-\n-static int\n-validate_simple_enqdeq(uint32_t index, uint8_t port, struct rte_event *ev)\n-{\n-\tRTE_SET_USED(port);\n-\tRTE_TEST_ASSERT_EQUAL(index, *rte_event_pmd_selftest_seqn(ev->mbuf),\n-\t\t\"index=%d != seqn=%d\",\n-\t\tindex, *rte_event_pmd_selftest_seqn(ev->mbuf));\n-\treturn 0;\n-}\n-\n-static inline int\n-test_simple_enqdeq(uint8_t sched_type)\n-{\n-\tint ret;\n-\n-\tret = inject_events(0 /*flow_id */,\n-\t\t\t RTE_EVENT_TYPE_CPU /* event_type */,\n-\t\t\t 0 /* sub_event_type */,\n-\t\t\t sched_type,\n-\t\t\t 0 /* queue */,\n-\t\t\t 0 /* port */,\n-\t\t\t MAX_EVENTS);\n-\tif (ret)\n-\t\treturn -1;\n-\n-\treturn consume_events(0 /* port */, MAX_EVENTS,\tvalidate_simple_enqdeq);\n-}\n-\n-static int\n-test_simple_enqdeq_ordered(void)\n-{\n-\treturn test_simple_enqdeq(RTE_SCHED_TYPE_ORDERED);\n-}\n-\n-static int\n-test_simple_enqdeq_atomic(void)\n-{\n-\treturn test_simple_enqdeq(RTE_SCHED_TYPE_ATOMIC);\n-}\n-\n-static int\n-test_simple_enqdeq_parallel(void)\n-{\n-\treturn test_simple_enqdeq(RTE_SCHED_TYPE_PARALLEL);\n-}\n-\n-/*\n- * Generate a prescribed number of events and spread them across available\n- * queues. On dequeue, using single event port(port 0) verify the enqueued\n- * event attributes\n- */\n-static int\n-test_multi_queue_enq_single_port_deq(void)\n-{\n-\tint ret;\n-\n-\tret = generate_random_events(MAX_EVENTS);\n-\tif (ret)\n-\t\treturn -1;\n-\n-\treturn consume_events(0 /* port */, MAX_EVENTS, NULL);\n-}\n-\n-/*\n- * Inject 0..MAX_EVENTS events over 0..queue_count with modulus\n- * operation\n- *\n- * For example, Inject 32 events over 0..7 queues\n- * enqueue events 0, 8, 16, 24 in queue 0\n- * enqueue events 1, 9, 17, 25 in queue 1\n- * ..\n- * ..\n- * enqueue events 7, 15, 23, 31 in queue 7\n- *\n- * On dequeue, Validate the events comes in 0,8,16,24,1,9,17,25..,7,15,23,31\n- * order from queue0(highest priority) to queue7(lowest_priority)\n- */\n-static int\n-validate_queue_priority(uint32_t index, uint8_t port, struct rte_event *ev)\n-{\n-\tuint32_t queue_count;\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_QUEUE_COUNT, &queue_count),\n-\t\t\t\t\"Queue count get failed\");\n-\tif (queue_count > 8)\n-\t\tqueue_count = 8;\n-\tuint32_t range = MAX_EVENTS / queue_count;\n-\tuint32_t expected_val = (index % range) * queue_count;\n-\n-\texpected_val += ev->queue_id;\n-\tRTE_SET_USED(port);\n-\tRTE_TEST_ASSERT_EQUAL(\n-\t\t*rte_event_pmd_selftest_seqn(ev->mbuf), expected_val,\n-\t\t\"seqn=%d index=%d expected=%d range=%d nb_queues=%d max_event=%d\",\n-\t\t*rte_event_pmd_selftest_seqn(ev->mbuf), index, expected_val,\n-\t\trange, queue_count, MAX_EVENTS);\n-\treturn 0;\n-}\n-\n-static int\n-test_multi_queue_priority(void)\n-{\n-\tint i, max_evts_roundoff;\n-\t/* See validate_queue_priority() comments for priority validate logic */\n-\tuint32_t queue_count;\n-\tstruct rte_mbuf *m;\n-\tuint8_t queue;\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_QUEUE_COUNT, &queue_count),\n-\t\t\t\t\"Queue count get failed\");\n-\tif (queue_count > 8)\n-\t\tqueue_count = 8;\n-\tmax_evts_roundoff = MAX_EVENTS / queue_count;\n-\tmax_evts_roundoff *= queue_count;\n-\n-\tfor (i = 0; i < max_evts_roundoff; i++) {\n-\t\tstruct rte_event ev = {.event = 0, .u64 = 0};\n-\n-\t\tm = rte_pktmbuf_alloc(eventdev_test_mempool);\n-\t\tRTE_TEST_ASSERT_NOT_NULL(m, \"mempool alloc failed\");\n-\n-\t\t*rte_event_pmd_selftest_seqn(m) = i;\n-\t\tqueue = i % queue_count;\n-\t\tupdate_event_and_validation_attr(m, &ev, 0, RTE_EVENT_TYPE_CPU,\n-\t\t\t\t\t\t 0, RTE_SCHED_TYPE_PARALLEL,\n-\t\t\t\t\t\t queue, 0);\n-\t\trte_event_enqueue_burst(evdev, 0, &ev, 1);\n-\t}\n-\n-\treturn consume_events(0, max_evts_roundoff, validate_queue_priority);\n-}\n-\n-static int\n-worker_multi_port_fn(void *arg)\n-{\n-\tstruct test_core_param *param = arg;\n-\trte_atomic32_t *total_events = param->total_events;\n-\tuint8_t port = param->port;\n-\tuint16_t valid_event;\n-\tstruct rte_event ev;\n-\tint ret;\n-\n-\twhile (rte_atomic32_read(total_events) > 0) {\n-\t\tvalid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0);\n-\t\tif (!valid_event)\n-\t\t\tcontinue;\n-\n-\t\tret = validate_event(&ev);\n-\t\tRTE_TEST_ASSERT_SUCCESS(ret, \"Failed to validate event\");\n-\t\trte_pktmbuf_free(ev.mbuf);\n-\t\trte_atomic32_sub(total_events, 1);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static inline int\n-wait_workers_to_join(const rte_atomic32_t *count)\n-{\n-\tuint64_t cycles, print_cycles;\n-\n-\tcycles = rte_get_timer_cycles();\n-\tprint_cycles = cycles;\n-\twhile (rte_atomic32_read(count)) {\n-\t\tuint64_t new_cycles = rte_get_timer_cycles();\n-\n-\t\tif (new_cycles - print_cycles > rte_get_timer_hz()) {\n-\t\t\totx2_err(\"Events %d\", rte_atomic32_read(count));\n-\t\t\tprint_cycles = new_cycles;\n-\t\t}\n-\t\tif (new_cycles - cycles > rte_get_timer_hz() * 10000000000) {\n-\t\t\totx2_err(\"No schedules for seconds, deadlock (%d)\",\n-\t\t\t\t rte_atomic32_read(count));\n-\t\t\trte_event_dev_dump(evdev, stdout);\n-\t\t\tcycles = new_cycles;\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\trte_eal_mp_wait_lcore();\n-\n-\treturn 0;\n-}\n-\n-static inline int\n-launch_workers_and_wait(int (*main_thread)(void *),\n-\t\t\tint (*worker_thread)(void *), uint32_t total_events,\n-\t\t\tuint8_t nb_workers, uint8_t sched_type)\n-{\n-\trte_atomic32_t atomic_total_events;\n-\tstruct test_core_param *param;\n-\tuint64_t dequeue_tmo_ticks;\n-\tuint8_t port = 0;\n-\tint w_lcore;\n-\tint ret;\n-\n-\tif (!nb_workers)\n-\t\treturn 0;\n-\n-\trte_atomic32_set(&atomic_total_events, total_events);\n-\tseqn_list_init();\n-\n-\tparam = malloc(sizeof(struct test_core_param) * nb_workers);\n-\tif (!param)\n-\t\treturn -1;\n-\n-\tret = rte_event_dequeue_timeout_ticks(evdev,\n-\t\t\t\t\t rte_rand() % 10000000/* 10ms */,\n-\t\t\t\t\t &dequeue_tmo_ticks);\n-\tif (ret) {\n-\t\tfree(param);\n-\t\treturn -1;\n-\t}\n-\n-\tparam[0].total_events = &atomic_total_events;\n-\tparam[0].sched_type = sched_type;\n-\tparam[0].port = 0;\n-\tparam[0].dequeue_tmo_ticks = dequeue_tmo_ticks;\n-\trte_wmb();\n-\n-\tw_lcore = rte_get_next_lcore(\n-\t\t\t/* start core */ -1,\n-\t\t\t/* skip main */ 1,\n-\t\t\t/* wrap */ 0);\n-\trte_eal_remote_launch(main_thread, ¶m[0], w_lcore);\n-\n-\tfor (port = 1; port < nb_workers; port++) {\n-\t\tparam[port].total_events = &atomic_total_events;\n-\t\tparam[port].sched_type = sched_type;\n-\t\tparam[port].port = port;\n-\t\tparam[port].dequeue_tmo_ticks = dequeue_tmo_ticks;\n-\t\trte_smp_wmb();\n-\t\tw_lcore = rte_get_next_lcore(w_lcore, 1, 0);\n-\t\trte_eal_remote_launch(worker_thread, ¶m[port], w_lcore);\n-\t}\n-\n-\trte_smp_wmb();\n-\tret = wait_workers_to_join(&atomic_total_events);\n-\tfree(param);\n-\n-\treturn ret;\n-}\n-\n-/*\n- * Generate a prescribed number of events and spread them across available\n- * queues. Dequeue the events through multiple ports and verify the enqueued\n- * event attributes\n- */\n-static int\n-test_multi_queue_enq_multi_port_deq(void)\n-{\n-\tconst unsigned int total_events = MAX_EVENTS;\n-\tuint32_t nr_ports;\n-\tint ret;\n-\n-\tret = generate_random_events(total_events);\n-\tif (ret)\n-\t\treturn -1;\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_PORT_COUNT, &nr_ports),\n-\t\t\t\t\"Port count get failed\");\n-\tnr_ports = RTE_MIN(nr_ports, rte_lcore_count() - 1);\n-\n-\tif (!nr_ports) {\n-\t\totx2_err(\"Not enough ports=%d or workers=%d\", nr_ports,\n-\t\t\t rte_lcore_count() - 1);\n-\t\treturn 0;\n-\t}\n-\n-\treturn launch_workers_and_wait(worker_multi_port_fn,\n-\t\t\t\t worker_multi_port_fn, total_events,\n-\t\t\t\t nr_ports, 0xff /* invalid */);\n-}\n-\n-static\n-void flush(uint8_t dev_id, struct rte_event event, void *arg)\n-{\n-\tunsigned int *count = arg;\n-\n-\tRTE_SET_USED(dev_id);\n-\tif (event.event_type == RTE_EVENT_TYPE_CPU)\n-\t\t*count = *count + 1;\n-}\n-\n-static int\n-test_dev_stop_flush(void)\n-{\n-\tunsigned int total_events = MAX_EVENTS, count = 0;\n-\tint ret;\n-\n-\tret = generate_random_events(total_events);\n-\tif (ret)\n-\t\treturn -1;\n-\n-\tret = rte_event_dev_stop_flush_callback_register(evdev, flush, &count);\n-\tif (ret)\n-\t\treturn -2;\n-\trte_event_dev_stop(evdev);\n-\tret = rte_event_dev_stop_flush_callback_register(evdev, NULL, NULL);\n-\tif (ret)\n-\t\treturn -3;\n-\tRTE_TEST_ASSERT_EQUAL(total_events, count,\n-\t\t\t \"count mismatch total_events=%d count=%d\",\n-\t\t\t total_events, count);\n-\n-\treturn 0;\n-}\n-\n-static int\n-validate_queue_to_port_single_link(uint32_t index, uint8_t port,\n-\t\t\t\t struct rte_event *ev)\n-{\n-\tRTE_SET_USED(index);\n-\tRTE_TEST_ASSERT_EQUAL(port, ev->queue_id,\n-\t\t\t \"queue mismatch enq=%d deq =%d\",\n-\t\t\t port, ev->queue_id);\n-\n-\treturn 0;\n-}\n-\n-/*\n- * Link queue x to port x and check correctness of link by checking\n- * queue_id == x on dequeue on the specific port x\n- */\n-static int\n-test_queue_to_port_single_link(void)\n-{\n-\tint i, nr_links, ret;\n-\tuint32_t queue_count;\n-\tuint32_t port_count;\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_PORT_COUNT, &port_count),\n-\t\t\t\t\"Port count get failed\");\n-\n-\t/* Unlink all connections that created in eventdev_setup */\n-\tfor (i = 0; i < (int)port_count; i++) {\n-\t\tret = rte_event_port_unlink(evdev, i, NULL, 0);\n-\t\tRTE_TEST_ASSERT(ret >= 0,\n-\t\t\t\t\"Failed to unlink all queues port=%d\", i);\n-\t}\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_QUEUE_COUNT, &queue_count),\n-\t\t\t\t\"Queue count get failed\");\n-\n-\tnr_links = RTE_MIN(port_count, queue_count);\n-\tconst unsigned int total_events = MAX_EVENTS / nr_links;\n-\n-\t/* Link queue x to port x and inject events to queue x through port x */\n-\tfor (i = 0; i < nr_links; i++) {\n-\t\tuint8_t queue = (uint8_t)i;\n-\n-\t\tret = rte_event_port_link(evdev, i, &queue, NULL, 1);\n-\t\tRTE_TEST_ASSERT(ret == 1, \"Failed to link queue to port %d\", i);\n-\n-\t\tret = inject_events(0x100 /*flow_id */,\n-\t\t\t\t RTE_EVENT_TYPE_CPU /* event_type */,\n-\t\t\t\t rte_rand() % 256 /* sub_event_type */,\n-\t\t\t\t rte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1),\n-\t\t\t\t queue /* queue */, i /* port */,\n-\t\t\t\t total_events /* events */);\n-\t\tif (ret)\n-\t\t\treturn -1;\n-\t}\n-\n-\t/* Verify the events generated from correct queue */\n-\tfor (i = 0; i < nr_links; i++) {\n-\t\tret = consume_events(i /* port */, total_events,\n-\t\t\t\t validate_queue_to_port_single_link);\n-\t\tif (ret)\n-\t\t\treturn -1;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-validate_queue_to_port_multi_link(uint32_t index, uint8_t port,\n-\t\t\t\t struct rte_event *ev)\n-{\n-\tRTE_SET_USED(index);\n-\tRTE_TEST_ASSERT_EQUAL(port, (ev->queue_id & 0x1),\n-\t\t\t \"queue mismatch enq=%d deq =%d\",\n-\t\t\t port, ev->queue_id);\n-\n-\treturn 0;\n-}\n-\n-/*\n- * Link all even number of queues to port 0 and all odd number of queues to\n- * port 1 and verify the link connection on dequeue\n- */\n-static int\n-test_queue_to_port_multi_link(void)\n-{\n-\tint ret, port0_events = 0, port1_events = 0;\n-\tuint32_t nr_queues = 0;\n-\tuint32_t nr_ports = 0;\n-\tuint8_t queue, port;\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_QUEUE_COUNT, &nr_queues),\n-\t\t\t\t\"Queue count get failed\");\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_QUEUE_COUNT, &nr_queues),\n-\t\t\t\t\"Queue count get failed\");\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_PORT_COUNT, &nr_ports),\n-\t\t\t\t\"Port count get failed\");\n-\n-\tif (nr_ports < 2) {\n-\t\totx2_err(\"Not enough ports to test ports=%d\", nr_ports);\n-\t\treturn 0;\n-\t}\n-\n-\t/* Unlink all connections that created in eventdev_setup */\n-\tfor (port = 0; port < nr_ports; port++) {\n-\t\tret = rte_event_port_unlink(evdev, port, NULL, 0);\n-\t\tRTE_TEST_ASSERT(ret >= 0, \"Failed to unlink all queues port=%d\",\n-\t\t\t\tport);\n-\t}\n-\n-\tconst unsigned int total_events = MAX_EVENTS / nr_queues;\n-\n-\t/* Link all even number of queues to port0 and odd numbers to port 1*/\n-\tfor (queue = 0; queue < nr_queues; queue++) {\n-\t\tport = queue & 0x1;\n-\t\tret = rte_event_port_link(evdev, port, &queue, NULL, 1);\n-\t\tRTE_TEST_ASSERT(ret == 1, \"Failed to link queue=%d to port=%d\",\n-\t\t\t\tqueue, port);\n-\n-\t\tret = inject_events(0x100 /*flow_id */,\n-\t\t\t\t RTE_EVENT_TYPE_CPU /* event_type */,\n-\t\t\t\t rte_rand() % 256 /* sub_event_type */,\n-\t\t\t\t rte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1),\n-\t\t\t\t queue /* queue */, port /* port */,\n-\t\t\t\t total_events /* events */);\n-\t\tif (ret)\n-\t\t\treturn -1;\n-\n-\t\tif (port == 0)\n-\t\t\tport0_events += total_events;\n-\t\telse\n-\t\t\tport1_events += total_events;\n-\t}\n-\n-\tret = consume_events(0 /* port */, port0_events,\n-\t\t\t validate_queue_to_port_multi_link);\n-\tif (ret)\n-\t\treturn -1;\n-\tret = consume_events(1 /* port */, port1_events,\n-\t\t\t validate_queue_to_port_multi_link);\n-\tif (ret)\n-\t\treturn -1;\n-\n-\treturn 0;\n-}\n-\n-static int\n-worker_flow_based_pipeline(void *arg)\n-{\n-\tstruct test_core_param *param = arg;\n-\tuint64_t dequeue_tmo_ticks = param->dequeue_tmo_ticks;\n-\trte_atomic32_t *total_events = param->total_events;\n-\tuint8_t new_sched_type = param->sched_type;\n-\tuint8_t port = param->port;\n-\tuint16_t valid_event;\n-\tstruct rte_event ev;\n-\n-\twhile (rte_atomic32_read(total_events) > 0) {\n-\t\tvalid_event = rte_event_dequeue_burst(evdev, port, &ev, 1,\n-\t\t\t\t\t\t dequeue_tmo_ticks);\n-\t\tif (!valid_event)\n-\t\t\tcontinue;\n-\n-\t\t/* Events from stage 0 */\n-\t\tif (ev.sub_event_type == 0) {\n-\t\t\t/* Move to atomic flow to maintain the ordering */\n-\t\t\tev.flow_id = 0x2;\n-\t\t\tev.event_type = RTE_EVENT_TYPE_CPU;\n-\t\t\tev.sub_event_type = 1; /* stage 1 */\n-\t\t\tev.sched_type = new_sched_type;\n-\t\t\tev.op = RTE_EVENT_OP_FORWARD;\n-\t\t\trte_event_enqueue_burst(evdev, port, &ev, 1);\n-\t\t} else if (ev.sub_event_type == 1) { /* Events from stage 1*/\n-\t\t\tuint32_t seqn = *rte_event_pmd_selftest_seqn(ev.mbuf);\n-\n-\t\t\tif (seqn_list_update(seqn) == 0) {\n-\t\t\t\trte_pktmbuf_free(ev.mbuf);\n-\t\t\t\trte_atomic32_sub(total_events, 1);\n-\t\t\t} else {\n-\t\t\t\totx2_err(\"Failed to update seqn_list\");\n-\t\t\t\treturn -1;\n-\t\t\t}\n-\t\t} else {\n-\t\t\totx2_err(\"Invalid ev.sub_event_type = %d\",\n-\t\t\t\t ev.sub_event_type);\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\treturn 0;\n-}\n-\n-static int\n-test_multiport_flow_sched_type_test(uint8_t in_sched_type,\n-\t\t\t\t uint8_t out_sched_type)\n-{\n-\tconst unsigned int total_events = MAX_EVENTS;\n-\tuint32_t nr_ports;\n-\tint ret;\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_PORT_COUNT, &nr_ports),\n-\t\t\t\t\"Port count get failed\");\n-\tnr_ports = RTE_MIN(nr_ports, rte_lcore_count() - 1);\n-\n-\tif (!nr_ports) {\n-\t\totx2_err(\"Not enough ports=%d or workers=%d\", nr_ports,\n-\t\t\t rte_lcore_count() - 1);\n-\t\treturn 0;\n-\t}\n-\n-\t/* Injects events with a 0 sequence number to total_events */\n-\tret = inject_events(0x1 /*flow_id */,\n-\t\t\t RTE_EVENT_TYPE_CPU /* event_type */,\n-\t\t\t 0 /* sub_event_type (stage 0) */,\n-\t\t\t in_sched_type,\n-\t\t\t 0 /* queue */,\n-\t\t\t 0 /* port */,\n-\t\t\t total_events /* events */);\n-\tif (ret)\n-\t\treturn -1;\n-\n-\trte_mb();\n-\tret = launch_workers_and_wait(worker_flow_based_pipeline,\n-\t\t\t\t worker_flow_based_pipeline, total_events,\n-\t\t\t\t nr_ports, out_sched_type);\n-\tif (ret)\n-\t\treturn -1;\n-\n-\tif (in_sched_type != RTE_SCHED_TYPE_PARALLEL &&\n-\t out_sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\t\t/* Check the events order maintained or not */\n-\t\treturn seqn_list_check(total_events);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-/* Multi port ordered to atomic transaction */\n-static int\n-test_multi_port_flow_ordered_to_atomic(void)\n-{\n-\t/* Ingress event order test */\n-\treturn test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_ORDERED,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_ATOMIC);\n-}\n-\n-static int\n-test_multi_port_flow_ordered_to_ordered(void)\n-{\n-\treturn test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_ORDERED,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_ORDERED);\n-}\n-\n-static int\n-test_multi_port_flow_ordered_to_parallel(void)\n-{\n-\treturn test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_ORDERED,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_PARALLEL);\n-}\n-\n-static int\n-test_multi_port_flow_atomic_to_atomic(void)\n-{\n-\t/* Ingress event order test */\n-\treturn test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_ATOMIC,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_ATOMIC);\n-}\n-\n-static int\n-test_multi_port_flow_atomic_to_ordered(void)\n-{\n-\treturn test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_ATOMIC,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_ORDERED);\n-}\n-\n-static int\n-test_multi_port_flow_atomic_to_parallel(void)\n-{\n-\treturn test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_ATOMIC,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_PARALLEL);\n-}\n-\n-static int\n-test_multi_port_flow_parallel_to_atomic(void)\n-{\n-\treturn test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_PARALLEL,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_ATOMIC);\n-}\n-\n-static int\n-test_multi_port_flow_parallel_to_ordered(void)\n-{\n-\treturn test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_PARALLEL,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_ORDERED);\n-}\n-\n-static int\n-test_multi_port_flow_parallel_to_parallel(void)\n-{\n-\treturn test_multiport_flow_sched_type_test(RTE_SCHED_TYPE_PARALLEL,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_PARALLEL);\n-}\n-\n-static int\n-worker_group_based_pipeline(void *arg)\n-{\n-\tstruct test_core_param *param = arg;\n-\tuint64_t dequeue_tmo_ticks = param->dequeue_tmo_ticks;\n-\trte_atomic32_t *total_events = param->total_events;\n-\tuint8_t new_sched_type = param->sched_type;\n-\tuint8_t port = param->port;\n-\tuint16_t valid_event;\n-\tstruct rte_event ev;\n-\n-\twhile (rte_atomic32_read(total_events) > 0) {\n-\t\tvalid_event = rte_event_dequeue_burst(evdev, port, &ev, 1,\n-\t\t\t\t\t\t dequeue_tmo_ticks);\n-\t\tif (!valid_event)\n-\t\t\tcontinue;\n-\n-\t\t/* Events from stage 0(group 0) */\n-\t\tif (ev.queue_id == 0) {\n-\t\t\t/* Move to atomic flow to maintain the ordering */\n-\t\t\tev.flow_id = 0x2;\n-\t\t\tev.event_type = RTE_EVENT_TYPE_CPU;\n-\t\t\tev.sched_type = new_sched_type;\n-\t\t\tev.queue_id = 1; /* Stage 1*/\n-\t\t\tev.op = RTE_EVENT_OP_FORWARD;\n-\t\t\trte_event_enqueue_burst(evdev, port, &ev, 1);\n-\t\t} else if (ev.queue_id == 1) { /* Events from stage 1(group 1)*/\n-\t\t\tuint32_t seqn = *rte_event_pmd_selftest_seqn(ev.mbuf);\n-\n-\t\t\tif (seqn_list_update(seqn) == 0) {\n-\t\t\t\trte_pktmbuf_free(ev.mbuf);\n-\t\t\t\trte_atomic32_sub(total_events, 1);\n-\t\t\t} else {\n-\t\t\t\totx2_err(\"Failed to update seqn_list\");\n-\t\t\t\treturn -1;\n-\t\t\t}\n-\t\t} else {\n-\t\t\totx2_err(\"Invalid ev.queue_id = %d\", ev.queue_id);\n-\t\t\treturn -1;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-test_multiport_queue_sched_type_test(uint8_t in_sched_type,\n-\t\t\t\t uint8_t out_sched_type)\n-{\n-\tconst unsigned int total_events = MAX_EVENTS;\n-\tuint32_t queue_count;\n-\tuint32_t nr_ports;\n-\tint ret;\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_PORT_COUNT, &nr_ports),\n-\t\t\t\t\"Port count get failed\");\n-\n-\tnr_ports = RTE_MIN(nr_ports, rte_lcore_count() - 1);\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_QUEUE_COUNT, &queue_count),\n-\t\t\t\t\"Queue count get failed\");\n-\tif (queue_count < 2 || !nr_ports) {\n-\t\totx2_err(\"Not enough queues=%d ports=%d or workers=%d\",\n-\t\t\t queue_count, nr_ports,\n-\t\t\t rte_lcore_count() - 1);\n-\t\treturn 0;\n-\t}\n-\n-\t/* Injects events with a 0 sequence number to total_events */\n-\tret = inject_events(0x1 /*flow_id */,\n-\t\t\t RTE_EVENT_TYPE_CPU /* event_type */,\n-\t\t\t 0 /* sub_event_type (stage 0) */,\n-\t\t\t in_sched_type,\n-\t\t\t 0 /* queue */,\n-\t\t\t 0 /* port */,\n-\t\t\t total_events /* events */);\n-\tif (ret)\n-\t\treturn -1;\n-\n-\tret = launch_workers_and_wait(worker_group_based_pipeline,\n-\t\t\t\t worker_group_based_pipeline, total_events,\n-\t\t\t\t nr_ports, out_sched_type);\n-\tif (ret)\n-\t\treturn -1;\n-\n-\tif (in_sched_type != RTE_SCHED_TYPE_PARALLEL &&\n-\t out_sched_type == RTE_SCHED_TYPE_ATOMIC) {\n-\t\t/* Check the events order maintained or not */\n-\t\treturn seqn_list_check(total_events);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-test_multi_port_queue_ordered_to_atomic(void)\n-{\n-\t/* Ingress event order test */\n-\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ORDERED,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_ATOMIC);\n-}\n-\n-static int\n-test_multi_port_queue_ordered_to_ordered(void)\n-{\n-\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ORDERED,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_ORDERED);\n-}\n-\n-static int\n-test_multi_port_queue_ordered_to_parallel(void)\n-{\n-\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ORDERED,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_PARALLEL);\n-}\n-\n-static int\n-test_multi_port_queue_atomic_to_atomic(void)\n-{\n-\t/* Ingress event order test */\n-\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ATOMIC,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_ATOMIC);\n-}\n-\n-static int\n-test_multi_port_queue_atomic_to_ordered(void)\n-{\n-\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ATOMIC,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_ORDERED);\n-}\n-\n-static int\n-test_multi_port_queue_atomic_to_parallel(void)\n-{\n-\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_ATOMIC,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_PARALLEL);\n-}\n-\n-static int\n-test_multi_port_queue_parallel_to_atomic(void)\n-{\n-\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_PARALLEL,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_ATOMIC);\n-}\n-\n-static int\n-test_multi_port_queue_parallel_to_ordered(void)\n-{\n-\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_PARALLEL,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_ORDERED);\n-}\n-\n-static int\n-test_multi_port_queue_parallel_to_parallel(void)\n-{\n-\treturn test_multiport_queue_sched_type_test(RTE_SCHED_TYPE_PARALLEL,\n-\t\t\t\t\t\t RTE_SCHED_TYPE_PARALLEL);\n-}\n-\n-static int\n-worker_flow_based_pipeline_max_stages_rand_sched_type(void *arg)\n-{\n-\tstruct test_core_param *param = arg;\n-\trte_atomic32_t *total_events = param->total_events;\n-\tuint8_t port = param->port;\n-\tuint16_t valid_event;\n-\tstruct rte_event ev;\n-\n-\twhile (rte_atomic32_read(total_events) > 0) {\n-\t\tvalid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0);\n-\t\tif (!valid_event)\n-\t\t\tcontinue;\n-\n-\t\tif (ev.sub_event_type == 255) { /* last stage */\n-\t\t\trte_pktmbuf_free(ev.mbuf);\n-\t\t\trte_atomic32_sub(total_events, 1);\n-\t\t} else {\n-\t\t\tev.event_type = RTE_EVENT_TYPE_CPU;\n-\t\t\tev.sub_event_type++;\n-\t\t\tev.sched_type =\n-\t\t\t\trte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1);\n-\t\t\tev.op = RTE_EVENT_OP_FORWARD;\n-\t\t\trte_event_enqueue_burst(evdev, port, &ev, 1);\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-launch_multi_port_max_stages_random_sched_type(int (*fn)(void *))\n-{\n-\tuint32_t nr_ports;\n-\tint ret;\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_PORT_COUNT, &nr_ports),\n-\t\t\t\t\"Port count get failed\");\n-\tnr_ports = RTE_MIN(nr_ports, rte_lcore_count() - 1);\n-\n-\tif (!nr_ports) {\n-\t\totx2_err(\"Not enough ports=%d or workers=%d\",\n-\t\t\t nr_ports, rte_lcore_count() - 1);\n-\t\treturn 0;\n-\t}\n-\n-\t/* Injects events with a 0 sequence number to total_events */\n-\tret = inject_events(0x1 /*flow_id */,\n-\t\t\t RTE_EVENT_TYPE_CPU /* event_type */,\n-\t\t\t 0 /* sub_event_type (stage 0) */,\n-\t\t\t rte_rand() %\n-\t\t\t\t(RTE_SCHED_TYPE_PARALLEL + 1) /* sched_type */,\n-\t\t\t 0 /* queue */,\n-\t\t\t 0 /* port */,\n-\t\t\t MAX_EVENTS /* events */);\n-\tif (ret)\n-\t\treturn -1;\n-\n-\treturn launch_workers_and_wait(fn, fn, MAX_EVENTS, nr_ports,\n-\t\t\t\t 0xff /* invalid */);\n-}\n-\n-/* Flow based pipeline with maximum stages with random sched type */\n-static int\n-test_multi_port_flow_max_stages_random_sched_type(void)\n-{\n-\treturn launch_multi_port_max_stages_random_sched_type(\n-\t\tworker_flow_based_pipeline_max_stages_rand_sched_type);\n-}\n-\n-static int\n-worker_queue_based_pipeline_max_stages_rand_sched_type(void *arg)\n-{\n-\tstruct test_core_param *param = arg;\n-\tuint8_t port = param->port;\n-\tuint32_t queue_count;\n-\tuint16_t valid_event;\n-\tstruct rte_event ev;\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_QUEUE_COUNT, &queue_count),\n-\t\t\t\t\"Queue count get failed\");\n-\tuint8_t nr_queues = queue_count;\n-\trte_atomic32_t *total_events = param->total_events;\n-\n-\twhile (rte_atomic32_read(total_events) > 0) {\n-\t\tvalid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0);\n-\t\tif (!valid_event)\n-\t\t\tcontinue;\n-\n-\t\tif (ev.queue_id == nr_queues - 1) { /* last stage */\n-\t\t\trte_pktmbuf_free(ev.mbuf);\n-\t\t\trte_atomic32_sub(total_events, 1);\n-\t\t} else {\n-\t\t\tev.event_type = RTE_EVENT_TYPE_CPU;\n-\t\t\tev.queue_id++;\n-\t\t\tev.sched_type =\n-\t\t\t\trte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1);\n-\t\t\tev.op = RTE_EVENT_OP_FORWARD;\n-\t\t\trte_event_enqueue_burst(evdev, port, &ev, 1);\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-/* Queue based pipeline with maximum stages with random sched type */\n-static int\n-test_multi_port_queue_max_stages_random_sched_type(void)\n-{\n-\treturn launch_multi_port_max_stages_random_sched_type(\n-\t\tworker_queue_based_pipeline_max_stages_rand_sched_type);\n-}\n-\n-static int\n-worker_mixed_pipeline_max_stages_rand_sched_type(void *arg)\n-{\n-\tstruct test_core_param *param = arg;\n-\tuint8_t port = param->port;\n-\tuint32_t queue_count;\n-\tuint16_t valid_event;\n-\tstruct rte_event ev;\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_QUEUE_COUNT, &queue_count),\n-\t\t\t\t\"Queue count get failed\");\n-\tuint8_t nr_queues = queue_count;\n-\trte_atomic32_t *total_events = param->total_events;\n-\n-\twhile (rte_atomic32_read(total_events) > 0) {\n-\t\tvalid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0);\n-\t\tif (!valid_event)\n-\t\t\tcontinue;\n-\n-\t\tif (ev.queue_id == nr_queues - 1) { /* Last stage */\n-\t\t\trte_pktmbuf_free(ev.mbuf);\n-\t\t\trte_atomic32_sub(total_events, 1);\n-\t\t} else {\n-\t\t\tev.event_type = RTE_EVENT_TYPE_CPU;\n-\t\t\tev.queue_id++;\n-\t\t\tev.sub_event_type = rte_rand() % 256;\n-\t\t\tev.sched_type =\n-\t\t\t\trte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1);\n-\t\t\tev.op = RTE_EVENT_OP_FORWARD;\n-\t\t\trte_event_enqueue_burst(evdev, port, &ev, 1);\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-/* Queue and flow based pipeline with maximum stages with random sched type */\n-static int\n-test_multi_port_mixed_max_stages_random_sched_type(void)\n-{\n-\treturn launch_multi_port_max_stages_random_sched_type(\n-\t\tworker_mixed_pipeline_max_stages_rand_sched_type);\n-}\n-\n-static int\n-worker_ordered_flow_producer(void *arg)\n-{\n-\tstruct test_core_param *param = arg;\n-\tuint8_t port = param->port;\n-\tstruct rte_mbuf *m;\n-\tint counter = 0;\n-\n-\twhile (counter < NUM_PACKETS) {\n-\t\tm = rte_pktmbuf_alloc(eventdev_test_mempool);\n-\t\tif (m == NULL)\n-\t\t\tcontinue;\n-\n-\t\t*rte_event_pmd_selftest_seqn(m) = counter++;\n-\n-\t\tstruct rte_event ev = {.event = 0, .u64 = 0};\n-\n-\t\tev.flow_id = 0x1; /* Generate a fat flow */\n-\t\tev.sub_event_type = 0;\n-\t\t/* Inject the new event */\n-\t\tev.op = RTE_EVENT_OP_NEW;\n-\t\tev.event_type = RTE_EVENT_TYPE_CPU;\n-\t\tev.sched_type = RTE_SCHED_TYPE_ORDERED;\n-\t\tev.queue_id = 0;\n-\t\tev.mbuf = m;\n-\t\trte_event_enqueue_burst(evdev, port, &ev, 1);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static inline int\n-test_producer_consumer_ingress_order_test(int (*fn)(void *))\n-{\n-\tuint32_t nr_ports;\n-\n-\tRTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev,\n-\t\t\t\tRTE_EVENT_DEV_ATTR_PORT_COUNT, &nr_ports),\n-\t\t\t\t\"Port count get failed\");\n-\tnr_ports = RTE_MIN(nr_ports, rte_lcore_count() - 1);\n-\n-\tif (rte_lcore_count() < 3 || nr_ports < 2) {\n-\t\totx2_err(\"### Not enough cores for test.\");\n-\t\treturn 0;\n-\t}\n-\n-\tlaunch_workers_and_wait(worker_ordered_flow_producer, fn,\n-\t\t\t\tNUM_PACKETS, nr_ports, RTE_SCHED_TYPE_ATOMIC);\n-\t/* Check the events order maintained or not */\n-\treturn seqn_list_check(NUM_PACKETS);\n-}\n-\n-/* Flow based producer consumer ingress order test */\n-static int\n-test_flow_producer_consumer_ingress_order_test(void)\n-{\n-\treturn test_producer_consumer_ingress_order_test(\n-\t\t\t\tworker_flow_based_pipeline);\n-}\n-\n-/* Queue based producer consumer ingress order test */\n-static int\n-test_queue_producer_consumer_ingress_order_test(void)\n-{\n-\treturn test_producer_consumer_ingress_order_test(\n-\t\t\t\tworker_group_based_pipeline);\n-}\n-\n-static void octeontx_test_run(int (*setup)(void), void (*tdown)(void),\n-\t\t\t int (*test)(void), const char *name)\n-{\n-\tif (setup() < 0) {\n-\t\tprintf(\"Error setting up test %s\", name);\n-\t\tunsupported++;\n-\t} else {\n-\t\tif (test() < 0) {\n-\t\t\tfailed++;\n-\t\t\tprintf(\"+ TestCase [%2d] : %s failed\\n\", total, name);\n-\t\t} else {\n-\t\t\tpassed++;\n-\t\t\tprintf(\"+ TestCase [%2d] : %s succeeded\\n\", total,\n-\t\t\t name);\n-\t\t}\n-\t}\n-\n-\ttotal++;\n-\ttdown();\n-}\n-\n-int\n-otx2_sso_selftest(void)\n-{\n-\ttestsuite_setup();\n-\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_simple_enqdeq_ordered);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_simple_enqdeq_atomic);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_simple_enqdeq_parallel);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_queue_enq_single_port_deq);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_dev_stop_flush);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_queue_enq_multi_port_deq);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_queue_to_port_single_link);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_queue_to_port_multi_link);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_flow_ordered_to_atomic);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_flow_ordered_to_ordered);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_flow_ordered_to_parallel);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_flow_atomic_to_atomic);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_flow_atomic_to_ordered);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_flow_atomic_to_parallel);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_flow_parallel_to_atomic);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_flow_parallel_to_ordered);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_flow_parallel_to_parallel);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_queue_ordered_to_atomic);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_queue_ordered_to_ordered);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_queue_ordered_to_parallel);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_queue_atomic_to_atomic);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_queue_atomic_to_ordered);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_queue_atomic_to_parallel);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_queue_parallel_to_atomic);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_queue_parallel_to_ordered);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_queue_parallel_to_parallel);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_flow_max_stages_random_sched_type);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_queue_max_stages_random_sched_type);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_multi_port_mixed_max_stages_random_sched_type);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_flow_producer_consumer_ingress_order_test);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup, eventdev_teardown,\n-\t\t\t test_queue_producer_consumer_ingress_order_test);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup_priority, eventdev_teardown,\n-\t\t\t test_multi_queue_priority);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup_dequeue_timeout, eventdev_teardown,\n-\t\t\t test_multi_port_flow_ordered_to_atomic);\n-\tOCTEONTX2_TEST_RUN(eventdev_setup_dequeue_timeout, eventdev_teardown,\n-\t\t\t test_multi_port_queue_ordered_to_atomic);\n-\tprintf(\"Total tests : %d\\n\", total);\n-\tprintf(\"Passed : %d\\n\", passed);\n-\tprintf(\"Failed : %d\\n\", failed);\n-\tprintf(\"Not supported : %d\\n\", unsupported);\n-\n-\ttestsuite_teardown();\n-\n-\tif (failed)\n-\t\treturn -1;\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/event/octeontx2/otx2_evdev_stats.h b/drivers/event/octeontx2/otx2_evdev_stats.h\ndeleted file mode 100644\nindex 74fcec8a07..0000000000\n--- a/drivers/event/octeontx2/otx2_evdev_stats.h\n+++ /dev/null\n@@ -1,286 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_EVDEV_STATS_H__\n-#define __OTX2_EVDEV_STATS_H__\n-\n-#include \"otx2_evdev.h\"\n-\n-struct otx2_sso_xstats_name {\n-\tconst char name[RTE_EVENT_DEV_XSTATS_NAME_SIZE];\n-\tconst size_t offset;\n-\tconst uint64_t mask;\n-\tconst uint8_t shift;\n-\tuint64_t reset_snap[OTX2_SSO_MAX_VHGRP];\n-};\n-\n-static struct otx2_sso_xstats_name sso_hws_xstats[] = {\n-\t{\"last_grp_serviced\",\toffsetof(struct sso_hws_stats, arbitration),\n-\t\t\t\t0x3FF, 0, {0} },\n-\t{\"affinity_arbitration_credits\",\n-\t\t\t\toffsetof(struct sso_hws_stats, arbitration),\n-\t\t\t\t0xF, 16, {0} },\n-};\n-\n-static struct otx2_sso_xstats_name sso_grp_xstats[] = {\n-\t{\"wrk_sched\",\t\toffsetof(struct sso_grp_stats, ws_pc), ~0x0, 0,\n-\t\t\t\t{0} },\n-\t{\"xaq_dram\",\t\toffsetof(struct sso_grp_stats, ext_pc), ~0x0,\n-\t\t\t\t0, {0} },\n-\t{\"add_wrk\",\t\toffsetof(struct sso_grp_stats, wa_pc), ~0x0, 0,\n-\t\t\t\t{0} },\n-\t{\"tag_switch_req\",\toffsetof(struct sso_grp_stats, ts_pc), ~0x0, 0,\n-\t\t\t\t{0} },\n-\t{\"desched_req\",\t\toffsetof(struct sso_grp_stats, ds_pc), ~0x0, 0,\n-\t\t\t\t{0} },\n-\t{\"desched_wrk\",\t\toffsetof(struct sso_grp_stats, dq_pc), ~0x0, 0,\n-\t\t\t\t{0} },\n-\t{\"xaq_cached\",\t\toffsetof(struct sso_grp_stats, aw_status), 0x3,\n-\t\t\t\t0, {0} },\n-\t{\"work_inflight\",\toffsetof(struct sso_grp_stats, aw_status), 0x3F,\n-\t\t\t\t16, {0} },\n-\t{\"inuse_pages\",\t\toffsetof(struct sso_grp_stats, page_cnt),\n-\t\t\t\t0xFFFFFFFF, 0, {0} },\n-};\n-\n-#define OTX2_SSO_NUM_HWS_XSTATS RTE_DIM(sso_hws_xstats)\n-#define OTX2_SSO_NUM_GRP_XSTATS RTE_DIM(sso_grp_xstats)\n-\n-#define OTX2_SSO_NUM_XSTATS (OTX2_SSO_NUM_HWS_XSTATS + OTX2_SSO_NUM_GRP_XSTATS)\n-\n-static int\n-otx2_sso_xstats_get(const struct rte_eventdev *event_dev,\n-\t\t enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id,\n-\t\t const unsigned int ids[], uint64_t values[], unsigned int n)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tstruct otx2_sso_xstats_name *xstats;\n-\tstruct otx2_sso_xstats_name *xstat;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tuint32_t xstats_mode_count = 0;\n-\tuint32_t start_offset = 0;\n-\tunsigned int i;\n-\tuint64_t value;\n-\tvoid *req_rsp;\n-\tint rc;\n-\n-\tswitch (mode) {\n-\tcase RTE_EVENT_DEV_XSTATS_DEVICE:\n-\t\treturn 0;\n-\tcase RTE_EVENT_DEV_XSTATS_PORT:\n-\t\tif (queue_port_id >= (signed int)dev->nb_event_ports)\n-\t\t\tgoto invalid_value;\n-\n-\t\txstats_mode_count = OTX2_SSO_NUM_HWS_XSTATS;\n-\t\txstats = sso_hws_xstats;\n-\n-\t\treq_rsp = otx2_mbox_alloc_msg_sso_hws_get_stats(mbox);\n-\t\t\t((struct sso_info_req *)req_rsp)->hws = dev->dual_ws ?\n-\t\t\t\t\t2 * queue_port_id : queue_port_id;\n-\t\trc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);\n-\t\tif (rc < 0)\n-\t\t\tgoto invalid_value;\n-\n-\t\tif (dev->dual_ws) {\n-\t\t\tfor (i = 0; i < n && i < xstats_mode_count; i++) {\n-\t\t\t\txstat = &xstats[ids[i] - start_offset];\n-\t\t\t\tvalues[i] = *(uint64_t *)\n-\t\t\t\t\t((char *)req_rsp + xstat->offset);\n-\t\t\t\tvalues[i] = (values[i] >> xstat->shift) &\n-\t\t\t\t\txstat->mask;\n-\t\t\t}\n-\n-\t\t\treq_rsp = otx2_mbox_alloc_msg_sso_hws_get_stats(mbox);\n-\t\t\t((struct sso_info_req *)req_rsp)->hws =\n-\t\t\t\t\t(2 * queue_port_id) + 1;\n-\t\t\trc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);\n-\t\t\tif (rc < 0)\n-\t\t\t\tgoto invalid_value;\n-\t\t}\n-\n-\t\tbreak;\n-\tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n-\t\tif (queue_port_id >= (signed int)dev->nb_event_queues)\n-\t\t\tgoto invalid_value;\n-\n-\t\txstats_mode_count = OTX2_SSO_NUM_GRP_XSTATS;\n-\t\tstart_offset = OTX2_SSO_NUM_HWS_XSTATS;\n-\t\txstats = sso_grp_xstats;\n-\n-\t\treq_rsp = otx2_mbox_alloc_msg_sso_grp_get_stats(mbox);\n-\t\t\t((struct sso_info_req *)req_rsp)->grp = queue_port_id;\n-\t\trc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);\n-\t\tif (rc < 0)\n-\t\t\tgoto invalid_value;\n-\n-\t\tbreak;\n-\tdefault:\n-\t\totx2_err(\"Invalid mode received\");\n-\t\tgoto invalid_value;\n-\t};\n-\n-\tfor (i = 0; i < n && i < xstats_mode_count; i++) {\n-\t\txstat = &xstats[ids[i] - start_offset];\n-\t\tvalue = *(uint64_t *)((char *)req_rsp + xstat->offset);\n-\t\tvalue = (value >> xstat->shift) & xstat->mask;\n-\n-\t\tif ((mode == RTE_EVENT_DEV_XSTATS_PORT) && dev->dual_ws)\n-\t\t\tvalues[i] += value;\n-\t\telse\n-\t\t\tvalues[i] = value;\n-\n-\t\tvalues[i] -= xstat->reset_snap[queue_port_id];\n-\t}\n-\n-\treturn i;\n-invalid_value:\n-\treturn -EINVAL;\n-}\n-\n-static int\n-otx2_sso_xstats_reset(struct rte_eventdev *event_dev,\n-\t\t enum rte_event_dev_xstats_mode mode,\n-\t\t int16_t queue_port_id, const uint32_t ids[], uint32_t n)\n-{\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tstruct otx2_sso_xstats_name *xstats;\n-\tstruct otx2_sso_xstats_name *xstat;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tuint32_t xstats_mode_count = 0;\n-\tuint32_t start_offset = 0;\n-\tunsigned int i;\n-\tuint64_t value;\n-\tvoid *req_rsp;\n-\tint rc;\n-\n-\tswitch (mode) {\n-\tcase RTE_EVENT_DEV_XSTATS_DEVICE:\n-\t\treturn 0;\n-\tcase RTE_EVENT_DEV_XSTATS_PORT:\n-\t\tif (queue_port_id >= (signed int)dev->nb_event_ports)\n-\t\t\tgoto invalid_value;\n-\n-\t\txstats_mode_count = OTX2_SSO_NUM_HWS_XSTATS;\n-\t\txstats = sso_hws_xstats;\n-\n-\t\treq_rsp = otx2_mbox_alloc_msg_sso_hws_get_stats(mbox);\n-\t\t((struct sso_info_req *)req_rsp)->hws = dev->dual_ws ?\n-\t\t\t2 * queue_port_id : queue_port_id;\n-\t\trc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);\n-\t\tif (rc < 0)\n-\t\t\tgoto invalid_value;\n-\n-\t\tif (dev->dual_ws) {\n-\t\t\tfor (i = 0; i < n && i < xstats_mode_count; i++) {\n-\t\t\t\txstat = &xstats[ids[i] - start_offset];\n-\t\t\t\txstat->reset_snap[queue_port_id] = *(uint64_t *)\n-\t\t\t\t\t((char *)req_rsp + xstat->offset);\n-\t\t\t\txstat->reset_snap[queue_port_id] =\n-\t\t\t\t\t(xstat->reset_snap[queue_port_id] >>\n-\t\t\t\t\t\txstat->shift) & xstat->mask;\n-\t\t\t}\n-\n-\t\t\treq_rsp = otx2_mbox_alloc_msg_sso_hws_get_stats(mbox);\n-\t\t\t((struct sso_info_req *)req_rsp)->hws =\n-\t\t\t\t\t(2 * queue_port_id) + 1;\n-\t\t\trc = otx2_mbox_process_msg(mbox, (void **)&req_rsp);\n-\t\t\tif (rc < 0)\n-\t\t\t\tgoto invalid_value;\n-\t\t}\n-\n-\t\tbreak;\n-\tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n-\t\tif (queue_port_id >= (signed int)dev->nb_event_queues)\n-\t\t\tgoto invalid_value;\n-\n-\t\txstats_mode_count = OTX2_SSO_NUM_GRP_XSTATS;\n-\t\tstart_offset = OTX2_SSO_NUM_HWS_XSTATS;\n-\t\txstats = sso_grp_xstats;\n-\n-\t\treq_rsp = otx2_mbox_alloc_msg_sso_grp_get_stats(mbox);\n-\t\t\t((struct sso_info_req *)req_rsp)->grp = queue_port_id;\n-\t\trc = otx2_mbox_process_msg(mbox, (void *)&req_rsp);\n-\t\tif (rc < 0)\n-\t\t\tgoto invalid_value;\n-\n-\t\tbreak;\n-\tdefault:\n-\t\totx2_err(\"Invalid mode received\");\n-\t\tgoto invalid_value;\n-\t};\n-\n-\tfor (i = 0; i < n && i < xstats_mode_count; i++) {\n-\t\txstat = &xstats[ids[i] - start_offset];\n-\t\tvalue = *(uint64_t *)((char *)req_rsp + xstat->offset);\n-\t\tvalue = (value >> xstat->shift) & xstat->mask;\n-\n-\t\tif ((mode == RTE_EVENT_DEV_XSTATS_PORT) && dev->dual_ws)\n-\t\t\txstat->reset_snap[queue_port_id] += value;\n-\t\telse\n-\t\t\txstat->reset_snap[queue_port_id] = value;\n-\t}\n-\treturn i;\n-invalid_value:\n-\treturn -EINVAL;\n-}\n-\n-static int\n-otx2_sso_xstats_get_names(const struct rte_eventdev *event_dev,\n-\t\t\t enum rte_event_dev_xstats_mode mode,\n-\t\t\t uint8_t queue_port_id,\n-\t\t\t struct rte_event_dev_xstats_name *xstats_names,\n-\t\t\t unsigned int *ids, unsigned int size)\n-{\n-\tstruct rte_event_dev_xstats_name xstats_names_copy[OTX2_SSO_NUM_XSTATS];\n-\tstruct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);\n-\tuint32_t xstats_mode_count = 0;\n-\tuint32_t start_offset = 0;\n-\tunsigned int xidx = 0;\n-\tunsigned int i;\n-\n-\tfor (i = 0; i < OTX2_SSO_NUM_HWS_XSTATS; i++) {\n-\t\tsnprintf(xstats_names_copy[i].name,\n-\t\t\t sizeof(xstats_names_copy[i].name), \"%s\",\n-\t\t\t sso_hws_xstats[i].name);\n-\t}\n-\n-\tfor (; i < OTX2_SSO_NUM_XSTATS; i++) {\n-\t\tsnprintf(xstats_names_copy[i].name,\n-\t\t\t sizeof(xstats_names_copy[i].name), \"%s\",\n-\t\t\t sso_grp_xstats[i - OTX2_SSO_NUM_HWS_XSTATS].name);\n-\t}\n-\n-\tswitch (mode) {\n-\tcase RTE_EVENT_DEV_XSTATS_DEVICE:\n-\t\tbreak;\n-\tcase RTE_EVENT_DEV_XSTATS_PORT:\n-\t\tif (queue_port_id >= (signed int)dev->nb_event_ports)\n-\t\t\tbreak;\n-\t\txstats_mode_count = OTX2_SSO_NUM_HWS_XSTATS;\n-\t\tbreak;\n-\tcase RTE_EVENT_DEV_XSTATS_QUEUE:\n-\t\tif (queue_port_id >= (signed int)dev->nb_event_queues)\n-\t\t\tbreak;\n-\t\txstats_mode_count = OTX2_SSO_NUM_GRP_XSTATS;\n-\t\tstart_offset = OTX2_SSO_NUM_HWS_XSTATS;\n-\t\tbreak;\n-\tdefault:\n-\t\totx2_err(\"Invalid mode received\");\n-\t\treturn -EINVAL;\n-\t};\n-\n-\tif (xstats_mode_count > size || !ids || !xstats_names)\n-\t\treturn xstats_mode_count;\n-\n-\tfor (i = 0; i < xstats_mode_count; i++) {\n-\t\txidx = i + start_offset;\n-\t\tstrncpy(xstats_names[i].name, xstats_names_copy[xidx].name,\n-\t\t\tsizeof(xstats_names[i].name));\n-\t\tids[i] = xidx;\n-\t}\n-\n-\treturn i;\n-}\n-\n-#endif\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\ndeleted file mode 100644\nindex 6da8b14b78..0000000000\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ /dev/null\n@@ -1,735 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_kvargs.h>\n-#include <rte_malloc.h>\n-#include <rte_mbuf_pool_ops.h>\n-\n-#include \"otx2_evdev.h\"\n-#include \"otx2_tim_evdev.h\"\n-\n-static struct event_timer_adapter_ops otx2_tim_ops;\n-\n-static inline int\n-tim_get_msix_offsets(void)\n-{\n-\tstruct otx2_tim_evdev *dev = tim_priv_get();\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct msix_offset_rsp *msix_rsp;\n-\tint i, rc;\n-\n-\t/* Get TIM MSIX vector offsets */\n-\totx2_mbox_alloc_msg_msix_offset(mbox);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);\n-\n-\tfor (i = 0; i < dev->nb_rings; i++)\n-\t\tdev->tim_msixoff[i] = msix_rsp->timlf_msixoff[i];\n-\n-\treturn rc;\n-}\n-\n-static void\n-tim_set_fp_ops(struct otx2_tim_ring *tim_ring)\n-{\n-\tuint8_t prod_flag = !tim_ring->prod_type_sp;\n-\n-\t/* [DFB/FB] [SP][MP]*/\n-\tconst rte_event_timer_arm_burst_t arm_burst[2][2][2] = {\n-#define FP(_name, _f3, _f2, _f1, flags) \\\n-\t[_f3][_f2][_f1] = otx2_tim_arm_burst_##_name,\n-\t\tTIM_ARM_FASTPATH_MODES\n-#undef FP\n-\t};\n-\n-\tconst rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2][2] = {\n-#define FP(_name, _f2, _f1, flags) \\\n-\t[_f2][_f1] = otx2_tim_arm_tmo_tick_burst_##_name,\n-\t\tTIM_ARM_TMO_FASTPATH_MODES\n-#undef FP\n-\t};\n-\n-\totx2_tim_ops.arm_burst =\n-\t\tarm_burst[tim_ring->enable_stats][tim_ring->ena_dfb][prod_flag];\n-\totx2_tim_ops.arm_tmo_tick_burst =\n-\t\tarm_tmo_burst[tim_ring->enable_stats][tim_ring->ena_dfb];\n-\totx2_tim_ops.cancel_burst = otx2_tim_timer_cancel_burst;\n-}\n-\n-static void\n-otx2_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,\n-\t\t struct rte_event_timer_adapter_info *adptr_info)\n-{\n-\tstruct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;\n-\n-\tadptr_info->max_tmo_ns = tim_ring->max_tout;\n-\tadptr_info->min_resolution_ns = tim_ring->ena_periodic ?\n-\t\ttim_ring->max_tout : tim_ring->tck_nsec;\n-\trte_memcpy(&adptr_info->conf, &adptr->data->conf,\n-\t\t sizeof(struct rte_event_timer_adapter_conf));\n-}\n-\n-static int\n-tim_chnk_pool_create(struct otx2_tim_ring *tim_ring,\n-\t\t struct rte_event_timer_adapter_conf *rcfg)\n-{\n-\tunsigned int cache_sz = (tim_ring->nb_chunks / 1.5);\n-\tunsigned int mp_flags = 0;\n-\tchar pool_name[25];\n-\tint rc;\n-\n-\tcache_sz /= rte_lcore_count();\n-\t/* Create chunk pool. */\n-\tif (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {\n-\t\tmp_flags = RTE_MEMPOOL_F_SP_PUT | RTE_MEMPOOL_F_SC_GET;\n-\t\totx2_tim_dbg(\"Using single producer mode\");\n-\t\ttim_ring->prod_type_sp = true;\n-\t}\n-\n-\tsnprintf(pool_name, sizeof(pool_name), \"otx2_tim_chunk_pool%d\",\n-\t\t tim_ring->ring_id);\n-\n-\tif (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)\n-\t\tcache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;\n-\n-\tcache_sz = cache_sz != 0 ? cache_sz : 2;\n-\ttim_ring->nb_chunks += (cache_sz * rte_lcore_count());\n-\tif (!tim_ring->disable_npa) {\n-\t\ttim_ring->chunk_pool = rte_mempool_create_empty(pool_name,\n-\t\t\t\ttim_ring->nb_chunks, tim_ring->chunk_sz,\n-\t\t\t\tcache_sz, 0, rte_socket_id(), mp_flags);\n-\n-\t\tif (tim_ring->chunk_pool == NULL) {\n-\t\t\totx2_err(\"Unable to create chunkpool.\");\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\n-\t\trc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,\n-\t\t\t\t\t\trte_mbuf_platform_mempool_ops(),\n-\t\t\t\t\t\tNULL);\n-\t\tif (rc < 0) {\n-\t\t\totx2_err(\"Unable to set chunkpool ops\");\n-\t\t\tgoto free;\n-\t\t}\n-\n-\t\trc = rte_mempool_populate_default(tim_ring->chunk_pool);\n-\t\tif (rc < 0) {\n-\t\t\totx2_err(\"Unable to set populate chunkpool.\");\n-\t\t\tgoto free;\n-\t\t}\n-\t\ttim_ring->aura = npa_lf_aura_handle_to_aura(\n-\t\t\t\ttim_ring->chunk_pool->pool_id);\n-\t\ttim_ring->ena_dfb = tim_ring->ena_periodic ? 1 : 0;\n-\t} else {\n-\t\ttim_ring->chunk_pool = rte_mempool_create(pool_name,\n-\t\t\t\ttim_ring->nb_chunks, tim_ring->chunk_sz,\n-\t\t\t\tcache_sz, 0, NULL, NULL, NULL, NULL,\n-\t\t\t\trte_socket_id(),\n-\t\t\t\tmp_flags);\n-\t\tif (tim_ring->chunk_pool == NULL) {\n-\t\t\totx2_err(\"Unable to create chunkpool.\");\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t\ttim_ring->ena_dfb = 1;\n-\t}\n-\n-\treturn 0;\n-\n-free:\n-\trte_mempool_free(tim_ring->chunk_pool);\n-\treturn rc;\n-}\n-\n-static void\n-tim_err_desc(int rc)\n-{\n-\tswitch (rc) {\n-\tcase TIM_AF_NO_RINGS_LEFT:\n-\t\totx2_err(\"Unable to allocat new TIM ring.\");\n-\t\tbreak;\n-\tcase TIM_AF_INVALID_NPA_PF_FUNC:\n-\t\totx2_err(\"Invalid NPA pf func.\");\n-\t\tbreak;\n-\tcase TIM_AF_INVALID_SSO_PF_FUNC:\n-\t\totx2_err(\"Invalid SSO pf func.\");\n-\t\tbreak;\n-\tcase TIM_AF_RING_STILL_RUNNING:\n-\t\totx2_tim_dbg(\"Ring busy.\");\n-\t\tbreak;\n-\tcase TIM_AF_LF_INVALID:\n-\t\totx2_err(\"Invalid Ring id.\");\n-\t\tbreak;\n-\tcase TIM_AF_CSIZE_NOT_ALIGNED:\n-\t\totx2_err(\"Chunk size specified needs to be multiple of 16.\");\n-\t\tbreak;\n-\tcase TIM_AF_CSIZE_TOO_SMALL:\n-\t\totx2_err(\"Chunk size too small.\");\n-\t\tbreak;\n-\tcase TIM_AF_CSIZE_TOO_BIG:\n-\t\totx2_err(\"Chunk size too big.\");\n-\t\tbreak;\n-\tcase TIM_AF_INTERVAL_TOO_SMALL:\n-\t\totx2_err(\"Bucket traversal interval too small.\");\n-\t\tbreak;\n-\tcase TIM_AF_INVALID_BIG_ENDIAN_VALUE:\n-\t\totx2_err(\"Invalid Big endian value.\");\n-\t\tbreak;\n-\tcase TIM_AF_INVALID_CLOCK_SOURCE:\n-\t\totx2_err(\"Invalid Clock source specified.\");\n-\t\tbreak;\n-\tcase TIM_AF_GPIO_CLK_SRC_NOT_ENABLED:\n-\t\totx2_err(\"GPIO clock source not enabled.\");\n-\t\tbreak;\n-\tcase TIM_AF_INVALID_BSIZE:\n-\t\totx2_err(\"Invalid bucket size.\");\n-\t\tbreak;\n-\tcase TIM_AF_INVALID_ENABLE_PERIODIC:\n-\t\totx2_err(\"Invalid bucket size.\");\n-\t\tbreak;\n-\tcase TIM_AF_INVALID_ENABLE_DONTFREE:\n-\t\totx2_err(\"Invalid Don't free value.\");\n-\t\tbreak;\n-\tcase TIM_AF_ENA_DONTFRE_NSET_PERIODIC:\n-\t\totx2_err(\"Don't free bit not set when periodic is enabled.\");\n-\t\tbreak;\n-\tcase TIM_AF_RING_ALREADY_DISABLED:\n-\t\totx2_err(\"Ring already stopped\");\n-\t\tbreak;\n-\tdefault:\n-\t\totx2_err(\"Unknown Error.\");\n-\t}\n-}\n-\n-static int\n-otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)\n-{\n-\tstruct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;\n-\tstruct otx2_tim_evdev *dev = tim_priv_get();\n-\tstruct otx2_tim_ring *tim_ring;\n-\tstruct tim_config_req *cfg_req;\n-\tstruct tim_ring_req *free_req;\n-\tstruct tim_lf_alloc_req *req;\n-\tstruct tim_lf_alloc_rsp *rsp;\n-\tuint8_t is_periodic;\n-\tint i, rc;\n-\n-\tif (dev == NULL)\n-\t\treturn -ENODEV;\n-\n-\tif (adptr->data->id >= dev->nb_rings)\n-\t\treturn -ENODEV;\n-\n-\treq = otx2_mbox_alloc_msg_tim_lf_alloc(dev->mbox);\n-\treq->npa_pf_func = otx2_npa_pf_func_get();\n-\treq->sso_pf_func = otx2_sso_pf_func_get();\n-\treq->ring = adptr->data->id;\n-\n-\trc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);\n-\tif (rc < 0) {\n-\t\ttim_err_desc(rc);\n-\t\treturn -ENODEV;\n-\t}\n-\n-\tif (NSEC2TICK(RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10),\n-\t\t rsp->tenns_clk) < OTX2_TIM_MIN_TMO_TKS) {\n-\t\tif (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)\n-\t\t\trcfg->timer_tick_ns = TICK2NSEC(OTX2_TIM_MIN_TMO_TKS,\n-\t\t\t\t\trsp->tenns_clk);\n-\t\telse {\n-\t\t\trc = -ERANGE;\n-\t\t\tgoto rng_mem_err;\n-\t\t}\n-\t}\n-\n-\tis_periodic = 0;\n-\tif (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_PERIODIC) {\n-\t\tif (rcfg->max_tmo_ns &&\n-\t\t rcfg->max_tmo_ns != rcfg->timer_tick_ns) {\n-\t\t\trc = -ERANGE;\n-\t\t\tgoto rng_mem_err;\n-\t\t}\n-\n-\t\t/* Use 2 buckets to avoid contention */\n-\t\trcfg->max_tmo_ns = rcfg->timer_tick_ns;\n-\t\trcfg->timer_tick_ns /= 2;\n-\t\tis_periodic = 1;\n-\t}\n-\n-\ttim_ring = rte_zmalloc(\"otx2_tim_prv\", sizeof(struct otx2_tim_ring), 0);\n-\tif (tim_ring == NULL) {\n-\t\trc = -ENOMEM;\n-\t\tgoto rng_mem_err;\n-\t}\n-\n-\tadptr->data->adapter_priv = tim_ring;\n-\n-\ttim_ring->tenns_clk_freq = rsp->tenns_clk;\n-\ttim_ring->clk_src = (int)rcfg->clk_src;\n-\ttim_ring->ring_id = adptr->data->id;\n-\ttim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);\n-\ttim_ring->max_tout = is_periodic ?\n-\t\trcfg->timer_tick_ns * 2 : rcfg->max_tmo_ns;\n-\ttim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);\n-\ttim_ring->chunk_sz = dev->chunk_sz;\n-\ttim_ring->nb_timers = rcfg->nb_timers;\n-\ttim_ring->disable_npa = dev->disable_npa;\n-\ttim_ring->ena_periodic = is_periodic;\n-\ttim_ring->enable_stats = dev->enable_stats;\n-\n-\tfor (i = 0; i < dev->ring_ctl_cnt ; i++) {\n-\t\tstruct otx2_tim_ctl *ring_ctl = &dev->ring_ctl_data[i];\n-\n-\t\tif (ring_ctl->ring == tim_ring->ring_id) {\n-\t\t\ttim_ring->chunk_sz = ring_ctl->chunk_slots ?\n-\t\t\t\t((uint32_t)(ring_ctl->chunk_slots + 1) *\n-\t\t\t\t OTX2_TIM_CHUNK_ALIGNMENT) : tim_ring->chunk_sz;\n-\t\t\ttim_ring->enable_stats = ring_ctl->enable_stats;\n-\t\t\ttim_ring->disable_npa = ring_ctl->disable_npa;\n-\t\t}\n-\t}\n-\n-\tif (tim_ring->disable_npa) {\n-\t\ttim_ring->nb_chunks =\n-\t\t\ttim_ring->nb_timers /\n-\t\t\tOTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);\n-\t\ttim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts;\n-\t} else {\n-\t\ttim_ring->nb_chunks = tim_ring->nb_timers;\n-\t}\n-\ttim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);\n-\ttim_ring->bkt = rte_zmalloc(\"otx2_tim_bucket\", (tim_ring->nb_bkts) *\n-\t\t\t\t sizeof(struct otx2_tim_bkt),\n-\t\t\t\t RTE_CACHE_LINE_SIZE);\n-\tif (tim_ring->bkt == NULL)\n-\t\tgoto bkt_mem_err;\n-\n-\trc = tim_chnk_pool_create(tim_ring, rcfg);\n-\tif (rc < 0)\n-\t\tgoto chnk_mem_err;\n-\n-\tcfg_req = otx2_mbox_alloc_msg_tim_config_ring(dev->mbox);\n-\n-\tcfg_req->ring = tim_ring->ring_id;\n-\tcfg_req->bigendian = false;\n-\tcfg_req->clocksource = tim_ring->clk_src;\n-\tcfg_req->enableperiodic = tim_ring->ena_periodic;\n-\tcfg_req->enabledontfreebuffer = tim_ring->ena_dfb;\n-\tcfg_req->bucketsize = tim_ring->nb_bkts;\n-\tcfg_req->chunksize = tim_ring->chunk_sz;\n-\tcfg_req->interval = NSEC2TICK(tim_ring->tck_nsec,\n-\t\t\t\t tim_ring->tenns_clk_freq);\n-\n-\trc = otx2_mbox_process(dev->mbox);\n-\tif (rc < 0) {\n-\t\ttim_err_desc(rc);\n-\t\tgoto chnk_mem_err;\n-\t}\n-\n-\ttim_ring->base = dev->bar2 +\n-\t\t(RVU_BLOCK_ADDR_TIM << 20 | tim_ring->ring_id << 12);\n-\n-\trc = tim_register_irq(tim_ring->ring_id);\n-\tif (rc < 0)\n-\t\tgoto chnk_mem_err;\n-\n-\totx2_write64((uint64_t)tim_ring->bkt,\n-\t\t tim_ring->base + TIM_LF_RING_BASE);\n-\totx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);\n-\n-\t/* Set fastpath ops. */\n-\ttim_set_fp_ops(tim_ring);\n-\n-\t/* Update SSO xae count. */\n-\tsso_updt_xae_cnt(sso_pmd_priv(dev->event_dev), (void *)tim_ring,\n-\t\t\t RTE_EVENT_TYPE_TIMER);\n-\tsso_xae_reconfigure(dev->event_dev);\n-\n-\totx2_tim_dbg(\"Total memory used %\"PRIu64\"MB\\n\",\n-\t\t\t(uint64_t)(((tim_ring->nb_chunks * tim_ring->chunk_sz)\n-\t\t\t+ (tim_ring->nb_bkts * sizeof(struct otx2_tim_bkt))) /\n-\t\t\tBIT_ULL(20)));\n-\n-\treturn rc;\n-\n-chnk_mem_err:\n-\trte_free(tim_ring->bkt);\n-bkt_mem_err:\n-\trte_free(tim_ring);\n-rng_mem_err:\n-\tfree_req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);\n-\tfree_req->ring = adptr->data->id;\n-\totx2_mbox_process(dev->mbox);\n-\treturn rc;\n-}\n-\n-static void\n-otx2_tim_calibrate_start_tsc(struct otx2_tim_ring *tim_ring)\n-{\n-#define OTX2_TIM_CALIB_ITER\t1E6\n-\tuint32_t real_bkt, bucket;\n-\tint icount, ecount = 0;\n-\tuint64_t bkt_cyc;\n-\n-\tfor (icount = 0; icount < OTX2_TIM_CALIB_ITER; icount++) {\n-\t\treal_bkt = otx2_read64(tim_ring->base + TIM_LF_RING_REL) >> 44;\n-\t\tbkt_cyc = tim_cntvct();\n-\t\tbucket = (bkt_cyc - tim_ring->ring_start_cyc) /\n-\t\t\t\t\t\t\ttim_ring->tck_int;\n-\t\tbucket = bucket % (tim_ring->nb_bkts);\n-\t\ttim_ring->ring_start_cyc = bkt_cyc - (real_bkt *\n-\t\t\t\t\t\t\ttim_ring->tck_int);\n-\t\tif (bucket != real_bkt)\n-\t\t\tecount++;\n-\t}\n-\ttim_ring->last_updt_cyc = bkt_cyc;\n-\totx2_tim_dbg(\"Bucket mispredict %3.2f distance %d\\n\",\n-\t\t 100 - (((double)(icount - ecount) / (double)icount) * 100),\n-\t\t bucket - real_bkt);\n-}\n-\n-static int\n-otx2_tim_ring_start(const struct rte_event_timer_adapter *adptr)\n-{\n-\tstruct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;\n-\tstruct otx2_tim_evdev *dev = tim_priv_get();\n-\tstruct tim_enable_rsp *rsp;\n-\tstruct tim_ring_req *req;\n-\tint rc;\n-\n-\tif (dev == NULL)\n-\t\treturn -ENODEV;\n-\n-\treq = otx2_mbox_alloc_msg_tim_enable_ring(dev->mbox);\n-\treq->ring = tim_ring->ring_id;\n-\n-\trc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);\n-\tif (rc < 0) {\n-\t\ttim_err_desc(rc);\n-\t\tgoto fail;\n-\t}\n-\ttim_ring->ring_start_cyc = rsp->timestarted;\n-\ttim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, tim_cntfrq());\n-\ttim_ring->tot_int = tim_ring->tck_int * tim_ring->nb_bkts;\n-\ttim_ring->fast_div = rte_reciprocal_value_u64(tim_ring->tck_int);\n-\ttim_ring->fast_bkt = rte_reciprocal_value_u64(tim_ring->nb_bkts);\n-\n-\totx2_tim_calibrate_start_tsc(tim_ring);\n-\n-fail:\n-\treturn rc;\n-}\n-\n-static int\n-otx2_tim_ring_stop(const struct rte_event_timer_adapter *adptr)\n-{\n-\tstruct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;\n-\tstruct otx2_tim_evdev *dev = tim_priv_get();\n-\tstruct tim_ring_req *req;\n-\tint rc;\n-\n-\tif (dev == NULL)\n-\t\treturn -ENODEV;\n-\n-\treq = otx2_mbox_alloc_msg_tim_disable_ring(dev->mbox);\n-\treq->ring = tim_ring->ring_id;\n-\n-\trc = otx2_mbox_process(dev->mbox);\n-\tif (rc < 0) {\n-\t\ttim_err_desc(rc);\n-\t\trc = -EBUSY;\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static int\n-otx2_tim_ring_free(struct rte_event_timer_adapter *adptr)\n-{\n-\tstruct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;\n-\tstruct otx2_tim_evdev *dev = tim_priv_get();\n-\tstruct tim_ring_req *req;\n-\tint rc;\n-\n-\tif (dev == NULL)\n-\t\treturn -ENODEV;\n-\n-\ttim_unregister_irq(tim_ring->ring_id);\n-\n-\treq = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);\n-\treq->ring = tim_ring->ring_id;\n-\n-\trc = otx2_mbox_process(dev->mbox);\n-\tif (rc < 0) {\n-\t\ttim_err_desc(rc);\n-\t\treturn -EBUSY;\n-\t}\n-\n-\trte_free(tim_ring->bkt);\n-\trte_mempool_free(tim_ring->chunk_pool);\n-\trte_free(adptr->data->adapter_priv);\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_tim_stats_get(const struct rte_event_timer_adapter *adapter,\n-\t\t struct rte_event_timer_adapter_stats *stats)\n-{\n-\tstruct otx2_tim_ring *tim_ring = adapter->data->adapter_priv;\n-\tuint64_t bkt_cyc = tim_cntvct() - tim_ring->ring_start_cyc;\n-\n-\tstats->evtim_exp_count = __atomic_load_n(&tim_ring->arm_cnt,\n-\t\t\t\t\t\t __ATOMIC_RELAXED);\n-\tstats->ev_enq_count = stats->evtim_exp_count;\n-\tstats->adapter_tick_count = rte_reciprocal_divide_u64(bkt_cyc,\n-\t\t\t\t&tim_ring->fast_div);\n-\treturn 0;\n-}\n-\n-static int\n-otx2_tim_stats_reset(const struct rte_event_timer_adapter *adapter)\n-{\n-\tstruct otx2_tim_ring *tim_ring = adapter->data->adapter_priv;\n-\n-\t__atomic_store_n(&tim_ring->arm_cnt, 0, __ATOMIC_RELAXED);\n-\treturn 0;\n-}\n-\n-int\n-otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n-\t\t uint32_t *caps, const struct event_timer_adapter_ops **ops)\n-{\n-\tstruct otx2_tim_evdev *dev = tim_priv_get();\n-\n-\tRTE_SET_USED(flags);\n-\n-\tif (dev == NULL)\n-\t\treturn -ENODEV;\n-\n-\totx2_tim_ops.init = otx2_tim_ring_create;\n-\totx2_tim_ops.uninit = otx2_tim_ring_free;\n-\totx2_tim_ops.start = otx2_tim_ring_start;\n-\totx2_tim_ops.stop = otx2_tim_ring_stop;\n-\totx2_tim_ops.get_info\t= otx2_tim_ring_info_get;\n-\n-\tif (dev->enable_stats) {\n-\t\totx2_tim_ops.stats_get = otx2_tim_stats_get;\n-\t\totx2_tim_ops.stats_reset = otx2_tim_stats_reset;\n-\t}\n-\n-\t/* Store evdev pointer for later use. */\n-\tdev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;\n-\t*caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT |\n-\t\tRTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC;\n-\t*ops = &otx2_tim_ops;\n-\n-\treturn 0;\n-}\n-\n-#define OTX2_TIM_DISABLE_NPA\t\"tim_disable_npa\"\n-#define OTX2_TIM_CHNK_SLOTS\t\"tim_chnk_slots\"\n-#define OTX2_TIM_STATS_ENA\t\"tim_stats_ena\"\n-#define OTX2_TIM_RINGS_LMT\t\"tim_rings_lmt\"\n-#define OTX2_TIM_RING_CTL\t\"tim_ring_ctl\"\n-\n-static void\n-tim_parse_ring_param(char *value, void *opaque)\n-{\n-\tstruct otx2_tim_evdev *dev = opaque;\n-\tstruct otx2_tim_ctl ring_ctl = {0};\n-\tchar *tok = strtok(value, \"-\");\n-\tstruct otx2_tim_ctl *old_ptr;\n-\tuint16_t *val;\n-\n-\tval = (uint16_t *)&ring_ctl;\n-\n-\tif (!strlen(value))\n-\t\treturn;\n-\n-\twhile (tok != NULL) {\n-\t\t*val = atoi(tok);\n-\t\ttok = strtok(NULL, \"-\");\n-\t\tval++;\n-\t}\n-\n-\tif (val != (&ring_ctl.enable_stats + 1)) {\n-\t\totx2_err(\n-\t\t\"Invalid ring param expected [ring-chunk_sz-disable_npa-enable_stats]\");\n-\t\treturn;\n-\t}\n-\n-\tdev->ring_ctl_cnt++;\n-\told_ptr = dev->ring_ctl_data;\n-\tdev->ring_ctl_data = rte_realloc(dev->ring_ctl_data,\n-\t\t\t\t\t sizeof(struct otx2_tim_ctl) *\n-\t\t\t\t\t dev->ring_ctl_cnt, 0);\n-\tif (dev->ring_ctl_data == NULL) {\n-\t\tdev->ring_ctl_data = old_ptr;\n-\t\tdev->ring_ctl_cnt--;\n-\t\treturn;\n-\t}\n-\n-\tdev->ring_ctl_data[dev->ring_ctl_cnt - 1] = ring_ctl;\n-}\n-\n-static void\n-tim_parse_ring_ctl_list(const char *value, void *opaque)\n-{\n-\tchar *s = strdup(value);\n-\tchar *start = NULL;\n-\tchar *end = NULL;\n-\tchar *f = s;\n-\n-\twhile (*s) {\n-\t\tif (*s == '[')\n-\t\t\tstart = s;\n-\t\telse if (*s == ']')\n-\t\t\tend = s;\n-\n-\t\tif (start && start < end) {\n-\t\t\t*end = 0;\n-\t\t\ttim_parse_ring_param(start + 1, opaque);\n-\t\t\tstart = end;\n-\t\t\ts = end;\n-\t\t}\n-\t\ts++;\n-\t}\n-\n-\tfree(f);\n-}\n-\n-static int\n-tim_parse_kvargs_dict(const char *key, const char *value, void *opaque)\n-{\n-\tRTE_SET_USED(key);\n-\n-\t/* Dict format [ring-chunk_sz-disable_npa-enable_stats] use '-' as ','\n-\t * isn't allowed. 0 represents default.\n-\t */\n-\ttim_parse_ring_ctl_list(value, opaque);\n-\n-\treturn 0;\n-}\n-\n-static void\n-tim_parse_devargs(struct rte_devargs *devargs, struct otx2_tim_evdev *dev)\n-{\n-\tstruct rte_kvargs *kvlist;\n-\n-\tif (devargs == NULL)\n-\t\treturn;\n-\n-\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n-\tif (kvlist == NULL)\n-\t\treturn;\n-\n-\trte_kvargs_process(kvlist, OTX2_TIM_DISABLE_NPA,\n-\t\t\t &parse_kvargs_flag, &dev->disable_npa);\n-\trte_kvargs_process(kvlist, OTX2_TIM_CHNK_SLOTS,\n-\t\t\t &parse_kvargs_value, &dev->chunk_slots);\n-\trte_kvargs_process(kvlist, OTX2_TIM_STATS_ENA, &parse_kvargs_flag,\n-\t\t\t &dev->enable_stats);\n-\trte_kvargs_process(kvlist, OTX2_TIM_RINGS_LMT, &parse_kvargs_value,\n-\t\t\t &dev->min_ring_cnt);\n-\trte_kvargs_process(kvlist, OTX2_TIM_RING_CTL,\n-\t\t\t &tim_parse_kvargs_dict, &dev);\n-\n-\trte_kvargs_free(kvlist);\n-}\n-\n-void\n-otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev)\n-{\n-\tstruct rsrc_attach_req *atch_req;\n-\tstruct rsrc_detach_req *dtch_req;\n-\tstruct free_rsrcs_rsp *rsrc_cnt;\n-\tconst struct rte_memzone *mz;\n-\tstruct otx2_tim_evdev *dev;\n-\tint rc;\n-\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn;\n-\n-\tmz = rte_memzone_reserve(RTE_STR(OTX2_TIM_EVDEV_NAME),\n-\t\t\t\t sizeof(struct otx2_tim_evdev),\n-\t\t\t\t rte_socket_id(), 0);\n-\tif (mz == NULL) {\n-\t\totx2_tim_dbg(\"Unable to allocate memory for TIM Event device\");\n-\t\treturn;\n-\t}\n-\n-\tdev = mz->addr;\n-\tdev->pci_dev = pci_dev;\n-\tdev->mbox = cmn_dev->mbox;\n-\tdev->bar2 = cmn_dev->bar2;\n-\n-\ttim_parse_devargs(pci_dev->device.devargs, dev);\n-\n-\totx2_mbox_alloc_msg_free_rsrc_cnt(dev->mbox);\n-\trc = otx2_mbox_process_msg(dev->mbox, (void *)&rsrc_cnt);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Unable to get free rsrc count.\");\n-\t\tgoto mz_free;\n-\t}\n-\n-\tdev->nb_rings = dev->min_ring_cnt ?\n-\t\tRTE_MIN(dev->min_ring_cnt, rsrc_cnt->tim) : rsrc_cnt->tim;\n-\n-\tif (!dev->nb_rings) {\n-\t\totx2_tim_dbg(\"No TIM Logical functions provisioned.\");\n-\t\tgoto mz_free;\n-\t}\n-\n-\tatch_req = otx2_mbox_alloc_msg_attach_resources(dev->mbox);\n-\tatch_req->modify = true;\n-\tatch_req->timlfs = dev->nb_rings;\n-\n-\trc = otx2_mbox_process(dev->mbox);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Unable to attach TIM rings.\");\n-\t\tgoto mz_free;\n-\t}\n-\n-\trc = tim_get_msix_offsets();\n-\tif (rc < 0) {\n-\t\totx2_err(\"Unable to get MSIX offsets for TIM.\");\n-\t\tgoto detach;\n-\t}\n-\n-\tif (dev->chunk_slots &&\n-\t dev->chunk_slots <= OTX2_TIM_MAX_CHUNK_SLOTS &&\n-\t dev->chunk_slots >= OTX2_TIM_MIN_CHUNK_SLOTS) {\n-\t\tdev->chunk_sz = (dev->chunk_slots + 1) *\n-\t\t\tOTX2_TIM_CHUNK_ALIGNMENT;\n-\t} else {\n-\t\tdev->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ;\n-\t}\n-\n-\treturn;\n-\n-detach:\n-\tdtch_req = otx2_mbox_alloc_msg_detach_resources(dev->mbox);\n-\tdtch_req->partial = true;\n-\tdtch_req->timlfs = true;\n-\n-\totx2_mbox_process(dev->mbox);\n-mz_free:\n-\trte_memzone_free(mz);\n-}\n-\n-void\n-otx2_tim_fini(void)\n-{\n-\tstruct otx2_tim_evdev *dev = tim_priv_get();\n-\tstruct rsrc_detach_req *dtch_req;\n-\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn;\n-\n-\tdtch_req = otx2_mbox_alloc_msg_detach_resources(dev->mbox);\n-\tdtch_req->partial = true;\n-\tdtch_req->timlfs = true;\n-\n-\totx2_mbox_process(dev->mbox);\n-\trte_memzone_free(rte_memzone_lookup(RTE_STR(OTX2_TIM_EVDEV_NAME)));\n-}\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\ndeleted file mode 100644\nindex dac642e0e1..0000000000\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ /dev/null\n@@ -1,256 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_TIM_EVDEV_H__\n-#define __OTX2_TIM_EVDEV_H__\n-\n-#include <event_timer_adapter_pmd.h>\n-#include <rte_event_timer_adapter.h>\n-#include <rte_reciprocal.h>\n-\n-#include \"otx2_dev.h\"\n-\n-#define OTX2_TIM_EVDEV_NAME otx2_tim_eventdev\n-\n-#define otx2_tim_func_trace otx2_tim_dbg\n-\n-#define TIM_LF_RING_AURA\t\t(0x0)\n-#define TIM_LF_RING_BASE\t\t(0x130)\n-#define TIM_LF_NRSPERR_INT\t\t(0x200)\n-#define TIM_LF_NRSPERR_INT_W1S\t\t(0x208)\n-#define TIM_LF_NRSPERR_INT_ENA_W1S\t(0x210)\n-#define TIM_LF_NRSPERR_INT_ENA_W1C\t(0x218)\n-#define TIM_LF_RAS_INT\t\t\t(0x300)\n-#define TIM_LF_RAS_INT_W1S\t\t(0x308)\n-#define TIM_LF_RAS_INT_ENA_W1S\t\t(0x310)\n-#define TIM_LF_RAS_INT_ENA_W1C\t\t(0x318)\n-#define TIM_LF_RING_REL\t\t\t(0x400)\n-\n-#define TIM_BUCKET_W1_S_CHUNK_REMAINDER\t(48)\n-#define TIM_BUCKET_W1_M_CHUNK_REMAINDER\t((1ULL << (64 - \\\n-\t\t\t\t\t TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1)\n-#define TIM_BUCKET_W1_S_LOCK\t\t(40)\n-#define TIM_BUCKET_W1_M_LOCK\t\t((1ULL <<\t\\\n-\t\t\t\t\t (TIM_BUCKET_W1_S_CHUNK_REMAINDER - \\\n-\t\t\t\t\t TIM_BUCKET_W1_S_LOCK)) - 1)\n-#define TIM_BUCKET_W1_S_RSVD\t\t(35)\n-#define TIM_BUCKET_W1_S_BSK\t\t(34)\n-#define TIM_BUCKET_W1_M_BSK\t\t((1ULL <<\t\\\n-\t\t\t\t\t (TIM_BUCKET_W1_S_RSVD -\t \\\n-\t\t\t\t\t TIM_BUCKET_W1_S_BSK)) - 1)\n-#define TIM_BUCKET_W1_S_HBT\t\t(33)\n-#define TIM_BUCKET_W1_M_HBT\t\t((1ULL <<\t\\\n-\t\t\t\t\t (TIM_BUCKET_W1_S_BSK -\t\t \\\n-\t\t\t\t\t TIM_BUCKET_W1_S_HBT)) - 1)\n-#define TIM_BUCKET_W1_S_SBT\t\t(32)\n-#define TIM_BUCKET_W1_M_SBT\t\t((1ULL <<\t\\\n-\t\t\t\t\t (TIM_BUCKET_W1_S_HBT -\t\t \\\n-\t\t\t\t\t TIM_BUCKET_W1_S_SBT)) - 1)\n-#define TIM_BUCKET_W1_S_NUM_ENTRIES\t(0)\n-#define TIM_BUCKET_W1_M_NUM_ENTRIES\t((1ULL <<\t\\\n-\t\t\t\t\t (TIM_BUCKET_W1_S_SBT -\t\t \\\n-\t\t\t\t\t TIM_BUCKET_W1_S_NUM_ENTRIES)) - 1)\n-\n-#define TIM_BUCKET_SEMA\t\t\t(TIM_BUCKET_CHUNK_REMAIN)\n-\n-#define TIM_BUCKET_CHUNK_REMAIN \\\n-\t(TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER)\n-\n-#define TIM_BUCKET_LOCK \\\n-\t(TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK)\n-\n-#define TIM_BUCKET_SEMA_WLOCK \\\n-\t(TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK))\n-\n-#define OTX2_MAX_TIM_RINGS\t\t(256)\n-#define OTX2_TIM_MAX_BUCKETS\t\t(0xFFFFF)\n-#define OTX2_TIM_RING_DEF_CHUNK_SZ\t(4096)\n-#define OTX2_TIM_CHUNK_ALIGNMENT\t(16)\n-#define OTX2_TIM_MAX_BURST\t\t(RTE_CACHE_LINE_SIZE / \\\n-\t\t\t\t\t\tOTX2_TIM_CHUNK_ALIGNMENT)\n-#define OTX2_TIM_NB_CHUNK_SLOTS(sz)\t(((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1)\n-#define OTX2_TIM_MIN_CHUNK_SLOTS\t(0x8)\n-#define OTX2_TIM_MAX_CHUNK_SLOTS\t(0x1FFE)\n-#define OTX2_TIM_MIN_TMO_TKS\t\t(256)\n-\n-#define OTX2_TIM_SP 0x1\n-#define OTX2_TIM_MP 0x2\n-#define OTX2_TIM_ENA_FB 0x10\n-#define OTX2_TIM_ENA_DFB 0x20\n-#define OTX2_TIM_ENA_STATS 0x40\n-\n-enum otx2_tim_clk_src {\n-\tOTX2_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,\n-\tOTX2_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,\n-\tOTX2_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,\n-\tOTX2_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,\n-};\n-\n-struct otx2_tim_bkt {\n-\tuint64_t first_chunk;\n-\tunion {\n-\t\tuint64_t w1;\n-\t\tstruct {\n-\t\t\tuint32_t nb_entry;\n-\t\t\tuint8_t sbt:1;\n-\t\t\tuint8_t hbt:1;\n-\t\t\tuint8_t bsk:1;\n-\t\t\tuint8_t rsvd:5;\n-\t\t\tuint8_t lock;\n-\t\t\tint16_t chunk_remainder;\n-\t\t};\n-\t};\n-\tuint64_t current_chunk;\n-\tuint64_t pad;\n-} __rte_packed __rte_aligned(32);\n-\n-struct otx2_tim_ent {\n-\tuint64_t w0;\n-\tuint64_t wqe;\n-} __rte_packed;\n-\n-struct otx2_tim_ctl {\n-\tuint16_t ring;\n-\tuint16_t chunk_slots;\n-\tuint16_t disable_npa;\n-\tuint16_t enable_stats;\n-};\n-\n-struct otx2_tim_evdev {\n-\tstruct rte_pci_device *pci_dev;\n-\tstruct rte_eventdev *event_dev;\n-\tstruct otx2_mbox *mbox;\n-\tuint16_t nb_rings;\n-\tuint32_t chunk_sz;\n-\tuintptr_t bar2;\n-\t/* Dev args */\n-\tuint8_t disable_npa;\n-\tuint16_t chunk_slots;\n-\tuint16_t min_ring_cnt;\n-\tuint8_t enable_stats;\n-\tuint16_t ring_ctl_cnt;\n-\tstruct otx2_tim_ctl *ring_ctl_data;\n-\t/* HW const */\n-\t/* MSIX offsets */\n-\tuint16_t tim_msixoff[OTX2_MAX_TIM_RINGS];\n-};\n-\n-struct otx2_tim_ring {\n-\tuintptr_t base;\n-\tuint16_t nb_chunk_slots;\n-\tuint32_t nb_bkts;\n-\tuint64_t last_updt_cyc;\n-\tuint64_t ring_start_cyc;\n-\tuint64_t tck_int;\n-\tuint64_t tot_int;\n-\tstruct otx2_tim_bkt *bkt;\n-\tstruct rte_mempool *chunk_pool;\n-\tstruct rte_reciprocal_u64 fast_div;\n-\tstruct rte_reciprocal_u64 fast_bkt;\n-\tuint64_t arm_cnt;\n-\tuint8_t prod_type_sp;\n-\tuint8_t enable_stats;\n-\tuint8_t disable_npa;\n-\tuint8_t ena_dfb;\n-\tuint8_t ena_periodic;\n-\tuint16_t ring_id;\n-\tuint32_t aura;\n-\tuint64_t nb_timers;\n-\tuint64_t tck_nsec;\n-\tuint64_t max_tout;\n-\tuint64_t nb_chunks;\n-\tuint64_t chunk_sz;\n-\tuint64_t tenns_clk_freq;\n-\tenum otx2_tim_clk_src clk_src;\n-} __rte_cache_aligned;\n-\n-static inline struct otx2_tim_evdev *\n-tim_priv_get(void)\n-{\n-\tconst struct rte_memzone *mz;\n-\n-\tmz = rte_memzone_lookup(RTE_STR(OTX2_TIM_EVDEV_NAME));\n-\tif (mz == NULL)\n-\t\treturn NULL;\n-\n-\treturn mz->addr;\n-}\n-\n-#ifdef RTE_ARCH_ARM64\n-static inline uint64_t\n-tim_cntvct(void)\n-{\n-\treturn __rte_arm64_cntvct();\n-}\n-\n-static inline uint64_t\n-tim_cntfrq(void)\n-{\n-\treturn __rte_arm64_cntfrq();\n-}\n-#else\n-static inline uint64_t\n-tim_cntvct(void)\n-{\n-\treturn 0;\n-}\n-\n-static inline uint64_t\n-tim_cntfrq(void)\n-{\n-\treturn 0;\n-}\n-#endif\n-\n-#define TIM_ARM_FASTPATH_MODES \\\n-\tFP(sp, 0, 0, 0, OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \\\n-\tFP(mp, 0, 0, 1, OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \\\n-\tFP(fb_sp, 0, 1, 0, OTX2_TIM_ENA_FB | OTX2_TIM_SP) \\\n-\tFP(fb_mp, 0, 1, 1, OTX2_TIM_ENA_FB | OTX2_TIM_MP) \\\n-\tFP(stats_mod_sp, 1, 0, 0, \\\n-\t OTX2_TIM_ENA_STATS | OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \\\n-\tFP(stats_mod_mp, 1, 0, 1, \\\n-\t OTX2_TIM_ENA_STATS | OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \\\n-\tFP(stats_mod_fb_sp, 1, 1, 0, \\\n-\t OTX2_TIM_ENA_STATS | OTX2_TIM_ENA_FB | OTX2_TIM_SP) \\\n-\tFP(stats_mod_fb_mp, 1, 1, 1, \\\n-\t OTX2_TIM_ENA_STATS | OTX2_TIM_ENA_FB | OTX2_TIM_MP)\n-\n-#define TIM_ARM_TMO_FASTPATH_MODES \\\n-\tFP(dfb, 0, 0, OTX2_TIM_ENA_DFB) \\\n-\tFP(fb, 0, 1, OTX2_TIM_ENA_FB) \\\n-\tFP(stats_dfb, 1, 0, OTX2_TIM_ENA_STATS | OTX2_TIM_ENA_DFB) \\\n-\tFP(stats_fb, 1, 1, OTX2_TIM_ENA_STATS | OTX2_TIM_ENA_FB)\n-\n-#define FP(_name, _f3, _f2, _f1, flags) \\\n-\tuint16_t otx2_tim_arm_burst_##_name( \\\n-\t\tconst struct rte_event_timer_adapter *adptr, \\\n-\t\tstruct rte_event_timer **tim, const uint16_t nb_timers);\n-TIM_ARM_FASTPATH_MODES\n-#undef FP\n-\n-#define FP(_name, _f2, _f1, flags) \\\n-\tuint16_t otx2_tim_arm_tmo_tick_burst_##_name( \\\n-\t\tconst struct rte_event_timer_adapter *adptr, \\\n-\t\tstruct rte_event_timer **tim, const uint64_t timeout_tick, \\\n-\t\tconst uint16_t nb_timers);\n-TIM_ARM_TMO_FASTPATH_MODES\n-#undef FP\n-\n-uint16_t otx2_tim_timer_cancel_burst(\n-\t\tconst struct rte_event_timer_adapter *adptr,\n-\t\tstruct rte_event_timer **tim, const uint16_t nb_timers);\n-\n-int otx2_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,\n-\t\t uint32_t *caps,\n-\t\t const struct event_timer_adapter_ops **ops);\n-\n-void otx2_tim_init(struct rte_pci_device *pci_dev, struct otx2_dev *cmn_dev);\n-void otx2_tim_fini(void);\n-\n-/* TIM IRQ */\n-int tim_register_irq(uint16_t ring_id);\n-void tim_unregister_irq(uint16_t ring_id);\n-\n-#endif /* __OTX2_TIM_EVDEV_H__ */\ndiff --git a/drivers/event/octeontx2/otx2_tim_worker.c b/drivers/event/octeontx2/otx2_tim_worker.c\ndeleted file mode 100644\nindex 9ee07958fd..0000000000\n--- a/drivers/event/octeontx2/otx2_tim_worker.c\n+++ /dev/null\n@@ -1,192 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_tim_evdev.h\"\n-#include \"otx2_tim_worker.h\"\n-\n-static inline int\n-tim_arm_checks(const struct otx2_tim_ring * const tim_ring,\n-\t struct rte_event_timer * const tim)\n-{\n-\tif (unlikely(tim->state)) {\n-\t\ttim->state = RTE_EVENT_TIMER_ERROR;\n-\t\trte_errno = EALREADY;\n-\t\tgoto fail;\n-\t}\n-\n-\tif (unlikely(!tim->timeout_ticks ||\n-\t\t tim->timeout_ticks >= tim_ring->nb_bkts)) {\n-\t\ttim->state = tim->timeout_ticks ? RTE_EVENT_TIMER_ERROR_TOOLATE\n-\t\t\t: RTE_EVENT_TIMER_ERROR_TOOEARLY;\n-\t\trte_errno = EINVAL;\n-\t\tgoto fail;\n-\t}\n-\n-\treturn 0;\n-\n-fail:\n-\treturn -EINVAL;\n-}\n-\n-static inline void\n-tim_format_event(const struct rte_event_timer * const tim,\n-\t\t struct otx2_tim_ent * const entry)\n-{\n-\tentry->w0 = (tim->ev.event & 0xFFC000000000) >> 6 |\n-\t\t(tim->ev.event & 0xFFFFFFFFF);\n-\tentry->wqe = tim->ev.u64;\n-}\n-\n-static inline void\n-tim_sync_start_cyc(struct otx2_tim_ring *tim_ring)\n-{\n-\tuint64_t cur_cyc = tim_cntvct();\n-\tuint32_t real_bkt;\n-\n-\tif (cur_cyc - tim_ring->last_updt_cyc > tim_ring->tot_int) {\n-\t\treal_bkt = otx2_read64(tim_ring->base + TIM_LF_RING_REL) >> 44;\n-\t\tcur_cyc = tim_cntvct();\n-\n-\t\ttim_ring->ring_start_cyc = cur_cyc -\n-\t\t\t\t\t\t(real_bkt * tim_ring->tck_int);\n-\t\ttim_ring->last_updt_cyc = cur_cyc;\n-\t}\n-\n-}\n-\n-static __rte_always_inline uint16_t\n-tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr,\n-\t\t struct rte_event_timer **tim,\n-\t\t const uint16_t nb_timers,\n-\t\t const uint8_t flags)\n-{\n-\tstruct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;\n-\tstruct otx2_tim_ent entry;\n-\tuint16_t index;\n-\tint ret;\n-\n-\ttim_sync_start_cyc(tim_ring);\n-\tfor (index = 0; index < nb_timers; index++) {\n-\t\tif (tim_arm_checks(tim_ring, tim[index]))\n-\t\t\tbreak;\n-\n-\t\ttim_format_event(tim[index], &entry);\n-\t\tif (flags & OTX2_TIM_SP)\n-\t\t\tret = tim_add_entry_sp(tim_ring,\n-\t\t\t\t\t tim[index]->timeout_ticks,\n-\t\t\t\t\t tim[index], &entry, flags);\n-\t\tif (flags & OTX2_TIM_MP)\n-\t\t\tret = tim_add_entry_mp(tim_ring,\n-\t\t\t\t\t tim[index]->timeout_ticks,\n-\t\t\t\t\t tim[index], &entry, flags);\n-\n-\t\tif (unlikely(ret)) {\n-\t\t\trte_errno = -ret;\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tif (flags & OTX2_TIM_ENA_STATS)\n-\t\t__atomic_fetch_add(&tim_ring->arm_cnt, index, __ATOMIC_RELAXED);\n-\n-\treturn index;\n-}\n-\n-static __rte_always_inline uint16_t\n-tim_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr,\n-\t\t struct rte_event_timer **tim,\n-\t\t const uint64_t timeout_tick,\n-\t\t const uint16_t nb_timers, const uint8_t flags)\n-{\n-\tstruct otx2_tim_ent entry[OTX2_TIM_MAX_BURST] __rte_cache_aligned;\n-\tstruct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;\n-\tuint16_t set_timers = 0;\n-\tuint16_t arr_idx = 0;\n-\tuint16_t idx;\n-\tint ret;\n-\n-\tif (unlikely(!timeout_tick || timeout_tick >= tim_ring->nb_bkts)) {\n-\t\tconst enum rte_event_timer_state state = timeout_tick ?\n-\t\t\tRTE_EVENT_TIMER_ERROR_TOOLATE :\n-\t\t\tRTE_EVENT_TIMER_ERROR_TOOEARLY;\n-\t\tfor (idx = 0; idx < nb_timers; idx++)\n-\t\t\ttim[idx]->state = state;\n-\n-\t\trte_errno = EINVAL;\n-\t\treturn 0;\n-\t}\n-\n-\ttim_sync_start_cyc(tim_ring);\n-\twhile (arr_idx < nb_timers) {\n-\t\tfor (idx = 0; idx < OTX2_TIM_MAX_BURST && (arr_idx < nb_timers);\n-\t\t idx++, arr_idx++) {\n-\t\t\ttim_format_event(tim[arr_idx], &entry[idx]);\n-\t\t}\n-\t\tret = tim_add_entry_brst(tim_ring, timeout_tick,\n-\t\t\t\t\t &tim[set_timers], entry, idx, flags);\n-\t\tset_timers += ret;\n-\t\tif (ret != idx)\n-\t\t\tbreak;\n-\t}\n-\tif (flags & OTX2_TIM_ENA_STATS)\n-\t\t__atomic_fetch_add(&tim_ring->arm_cnt, set_timers,\n-\t\t\t\t __ATOMIC_RELAXED);\n-\n-\treturn set_timers;\n-}\n-\n-#define FP(_name, _f3, _f2, _f1, _flags)\t\t\t\t\\\n-uint16_t __rte_noinline\t\t\t\t\t\t\t \\\n-otx2_tim_arm_burst_ ## _name(const struct rte_event_timer_adapter *adptr, \\\n-\t\t\t struct rte_event_timer **tim,\t\t \\\n-\t\t\t const uint16_t nb_timers)\t\t\t \\\n-{\t\t\t\t\t\t\t\t\t \\\n-\treturn tim_timer_arm_burst(adptr, tim, nb_timers, _flags);\t \\\n-}\n-TIM_ARM_FASTPATH_MODES\n-#undef FP\n-\n-#define FP(_name, _f2, _f1, _flags)\t\t\t\t\\\n-uint16_t __rte_noinline\t\t\t\t\t\t\t\\\n-otx2_tim_arm_tmo_tick_burst_ ## _name(\t\t\t\t\t\\\n-\t\t\tconst struct rte_event_timer_adapter *adptr,\t\\\n-\t\t\t\t struct rte_event_timer **tim,\t\\\n-\t\t\t\t const uint64_t timeout_tick,\t\\\n-\t\t\t\t const uint16_t nb_timers)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\treturn tim_timer_arm_tmo_brst(adptr, tim, timeout_tick,\t\t\\\n-\t\t\tnb_timers, _flags);\t\t\t\t\\\n-}\n-TIM_ARM_TMO_FASTPATH_MODES\n-#undef FP\n-\n-uint16_t\n-otx2_tim_timer_cancel_burst(const struct rte_event_timer_adapter *adptr,\n-\t\t\t struct rte_event_timer **tim,\n-\t\t\t const uint16_t nb_timers)\n-{\n-\tuint16_t index;\n-\tint ret;\n-\n-\tRTE_SET_USED(adptr);\n-\trte_atomic_thread_fence(__ATOMIC_ACQUIRE);\n-\tfor (index = 0; index < nb_timers; index++) {\n-\t\tif (tim[index]->state == RTE_EVENT_TIMER_CANCELED) {\n-\t\t\trte_errno = EALREADY;\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\tif (tim[index]->state != RTE_EVENT_TIMER_ARMED) {\n-\t\t\trte_errno = EINVAL;\n-\t\t\tbreak;\n-\t\t}\n-\t\tret = tim_rm_entry(tim[index]);\n-\t\tif (ret) {\n-\t\t\trte_errno = -ret;\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\treturn index;\n-}\ndiff --git a/drivers/event/octeontx2/otx2_tim_worker.h b/drivers/event/octeontx2/otx2_tim_worker.h\ndeleted file mode 100644\nindex efe88a8692..0000000000\n--- a/drivers/event/octeontx2/otx2_tim_worker.h\n+++ /dev/null\n@@ -1,598 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_TIM_WORKER_H__\n-#define __OTX2_TIM_WORKER_H__\n-\n-#include \"otx2_tim_evdev.h\"\n-\n-static inline uint8_t\n-tim_bkt_fetch_lock(uint64_t w1)\n-{\n-\treturn (w1 >> TIM_BUCKET_W1_S_LOCK) &\n-\t\tTIM_BUCKET_W1_M_LOCK;\n-}\n-\n-static inline int16_t\n-tim_bkt_fetch_rem(uint64_t w1)\n-{\n-\treturn (w1 >> TIM_BUCKET_W1_S_CHUNK_REMAINDER) &\n-\t\tTIM_BUCKET_W1_M_CHUNK_REMAINDER;\n-}\n-\n-static inline int16_t\n-tim_bkt_get_rem(struct otx2_tim_bkt *bktp)\n-{\n-\treturn __atomic_load_n(&bktp->chunk_remainder, __ATOMIC_ACQUIRE);\n-}\n-\n-static inline void\n-tim_bkt_set_rem(struct otx2_tim_bkt *bktp, uint16_t v)\n-{\n-\t__atomic_store_n(&bktp->chunk_remainder, v, __ATOMIC_RELAXED);\n-}\n-\n-static inline void\n-tim_bkt_sub_rem(struct otx2_tim_bkt *bktp, uint16_t v)\n-{\n-\t__atomic_fetch_sub(&bktp->chunk_remainder, v, __ATOMIC_RELAXED);\n-}\n-\n-static inline uint8_t\n-tim_bkt_get_hbt(uint64_t w1)\n-{\n-\treturn (w1 >> TIM_BUCKET_W1_S_HBT) & TIM_BUCKET_W1_M_HBT;\n-}\n-\n-static inline uint8_t\n-tim_bkt_get_bsk(uint64_t w1)\n-{\n-\treturn (w1 >> TIM_BUCKET_W1_S_BSK) & TIM_BUCKET_W1_M_BSK;\n-}\n-\n-static inline uint64_t\n-tim_bkt_clr_bsk(struct otx2_tim_bkt *bktp)\n-{\n-\t/* Clear everything except lock. */\n-\tconst uint64_t v = TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK;\n-\n-\treturn __atomic_fetch_and(&bktp->w1, v, __ATOMIC_ACQ_REL);\n-}\n-\n-static inline uint64_t\n-tim_bkt_fetch_sema_lock(struct otx2_tim_bkt *bktp)\n-{\n-\treturn __atomic_fetch_add(&bktp->w1, TIM_BUCKET_SEMA_WLOCK,\n-\t\t\t__ATOMIC_ACQUIRE);\n-}\n-\n-static inline uint64_t\n-tim_bkt_fetch_sema(struct otx2_tim_bkt *bktp)\n-{\n-\treturn __atomic_fetch_add(&bktp->w1, TIM_BUCKET_SEMA, __ATOMIC_RELAXED);\n-}\n-\n-static inline uint64_t\n-tim_bkt_inc_lock(struct otx2_tim_bkt *bktp)\n-{\n-\tconst uint64_t v = 1ull << TIM_BUCKET_W1_S_LOCK;\n-\n-\treturn __atomic_fetch_add(&bktp->w1, v, __ATOMIC_ACQUIRE);\n-}\n-\n-static inline void\n-tim_bkt_dec_lock(struct otx2_tim_bkt *bktp)\n-{\n-\t__atomic_fetch_sub(&bktp->lock, 1, __ATOMIC_RELEASE);\n-}\n-\n-static inline void\n-tim_bkt_dec_lock_relaxed(struct otx2_tim_bkt *bktp)\n-{\n-\t__atomic_fetch_sub(&bktp->lock, 1, __ATOMIC_RELAXED);\n-}\n-\n-static inline uint32_t\n-tim_bkt_get_nent(uint64_t w1)\n-{\n-\treturn (w1 >> TIM_BUCKET_W1_S_NUM_ENTRIES) &\n-\t\tTIM_BUCKET_W1_M_NUM_ENTRIES;\n-}\n-\n-static inline void\n-tim_bkt_inc_nent(struct otx2_tim_bkt *bktp)\n-{\n-\t__atomic_add_fetch(&bktp->nb_entry, 1, __ATOMIC_RELAXED);\n-}\n-\n-static inline void\n-tim_bkt_add_nent(struct otx2_tim_bkt *bktp, uint32_t v)\n-{\n-\t__atomic_add_fetch(&bktp->nb_entry, v, __ATOMIC_RELAXED);\n-}\n-\n-static inline uint64_t\n-tim_bkt_clr_nent(struct otx2_tim_bkt *bktp)\n-{\n-\tconst uint64_t v = ~(TIM_BUCKET_W1_M_NUM_ENTRIES <<\n-\t\t\tTIM_BUCKET_W1_S_NUM_ENTRIES);\n-\n-\treturn __atomic_and_fetch(&bktp->w1, v, __ATOMIC_ACQ_REL);\n-}\n-\n-static inline uint64_t\n-tim_bkt_fast_mod(uint64_t n, uint64_t d, struct rte_reciprocal_u64 R)\n-{\n-\treturn (n - (d * rte_reciprocal_divide_u64(n, &R)));\n-}\n-\n-static __rte_always_inline void\n-tim_get_target_bucket(struct otx2_tim_ring *const tim_ring,\n-\t\t const uint32_t rel_bkt, struct otx2_tim_bkt **bkt,\n-\t\t struct otx2_tim_bkt **mirr_bkt)\n-{\n-\tconst uint64_t bkt_cyc = tim_cntvct() - tim_ring->ring_start_cyc;\n-\tuint64_t bucket =\n-\t\trte_reciprocal_divide_u64(bkt_cyc, &tim_ring->fast_div) +\n-\t\trel_bkt;\n-\tuint64_t mirr_bucket = 0;\n-\n-\tbucket =\n-\t\ttim_bkt_fast_mod(bucket, tim_ring->nb_bkts, tim_ring->fast_bkt);\n-\tmirr_bucket = tim_bkt_fast_mod(bucket + (tim_ring->nb_bkts >> 1),\n-\t\t\t\t tim_ring->nb_bkts, tim_ring->fast_bkt);\n-\t*bkt = &tim_ring->bkt[bucket];\n-\t*mirr_bkt = &tim_ring->bkt[mirr_bucket];\n-}\n-\n-static struct otx2_tim_ent *\n-tim_clr_bkt(struct otx2_tim_ring * const tim_ring,\n-\t struct otx2_tim_bkt * const bkt)\n-{\n-#define TIM_MAX_OUTSTANDING_OBJ\t\t64\n-\tvoid *pend_chunks[TIM_MAX_OUTSTANDING_OBJ];\n-\tstruct otx2_tim_ent *chunk;\n-\tstruct otx2_tim_ent *pnext;\n-\tuint8_t objs = 0;\n-\n-\n-\tchunk = ((struct otx2_tim_ent *)(uintptr_t)bkt->first_chunk);\n-\tchunk = (struct otx2_tim_ent *)(uintptr_t)(chunk +\n-\t\t\ttim_ring->nb_chunk_slots)->w0;\n-\twhile (chunk) {\n-\t\tpnext = (struct otx2_tim_ent *)(uintptr_t)\n-\t\t\t((chunk + tim_ring->nb_chunk_slots)->w0);\n-\t\tif (objs == TIM_MAX_OUTSTANDING_OBJ) {\n-\t\t\trte_mempool_put_bulk(tim_ring->chunk_pool, pend_chunks,\n-\t\t\t\t\t objs);\n-\t\t\tobjs = 0;\n-\t\t}\n-\t\tpend_chunks[objs++] = chunk;\n-\t\tchunk = pnext;\n-\t}\n-\n-\tif (objs)\n-\t\trte_mempool_put_bulk(tim_ring->chunk_pool, pend_chunks,\n-\t\t\t\tobjs);\n-\n-\treturn (struct otx2_tim_ent *)(uintptr_t)bkt->first_chunk;\n-}\n-\n-static struct otx2_tim_ent *\n-tim_refill_chunk(struct otx2_tim_bkt * const bkt,\n-\t\t struct otx2_tim_bkt * const mirr_bkt,\n-\t\t struct otx2_tim_ring * const tim_ring)\n-{\n-\tstruct otx2_tim_ent *chunk;\n-\n-\tif (bkt->nb_entry || !bkt->first_chunk) {\n-\t\tif (unlikely(rte_mempool_get(tim_ring->chunk_pool,\n-\t\t\t\t\t (void **)&chunk)))\n-\t\t\treturn NULL;\n-\t\tif (bkt->nb_entry) {\n-\t\t\t*(uint64_t *)(((struct otx2_tim_ent *)\n-\t\t\t\t\t\tmirr_bkt->current_chunk) +\n-\t\t\t\t\ttim_ring->nb_chunk_slots) =\n-\t\t\t\t(uintptr_t)chunk;\n-\t\t} else {\n-\t\t\tbkt->first_chunk = (uintptr_t)chunk;\n-\t\t}\n-\t} else {\n-\t\tchunk = tim_clr_bkt(tim_ring, bkt);\n-\t\tbkt->first_chunk = (uintptr_t)chunk;\n-\t}\n-\t*(uint64_t *)(chunk + tim_ring->nb_chunk_slots) = 0;\n-\n-\treturn chunk;\n-}\n-\n-static struct otx2_tim_ent *\n-tim_insert_chunk(struct otx2_tim_bkt * const bkt,\n-\t\t struct otx2_tim_bkt * const mirr_bkt,\n-\t\t struct otx2_tim_ring * const tim_ring)\n-{\n-\tstruct otx2_tim_ent *chunk;\n-\n-\tif (unlikely(rte_mempool_get(tim_ring->chunk_pool, (void **)&chunk)))\n-\t\treturn NULL;\n-\n-\t*(uint64_t *)(chunk + tim_ring->nb_chunk_slots) = 0;\n-\tif (bkt->nb_entry) {\n-\t\t*(uint64_t *)(((struct otx2_tim_ent *)(uintptr_t)\n-\t\t\t\t\tmirr_bkt->current_chunk) +\n-\t\t\t\ttim_ring->nb_chunk_slots) = (uintptr_t)chunk;\n-\t} else {\n-\t\tbkt->first_chunk = (uintptr_t)chunk;\n-\t}\n-\treturn chunk;\n-}\n-\n-static __rte_always_inline int\n-tim_add_entry_sp(struct otx2_tim_ring * const tim_ring,\n-\t\t const uint32_t rel_bkt,\n-\t\t struct rte_event_timer * const tim,\n-\t\t const struct otx2_tim_ent * const pent,\n-\t\t const uint8_t flags)\n-{\n-\tstruct otx2_tim_bkt *mirr_bkt;\n-\tstruct otx2_tim_ent *chunk;\n-\tstruct otx2_tim_bkt *bkt;\n-\tuint64_t lock_sema;\n-\tint16_t rem;\n-\n-__retry:\n-\ttim_get_target_bucket(tim_ring, rel_bkt, &bkt, &mirr_bkt);\n-\n-\t/* Get Bucket sema*/\n-\tlock_sema = tim_bkt_fetch_sema_lock(bkt);\n-\n-\t/* Bucket related checks. */\n-\tif (unlikely(tim_bkt_get_hbt(lock_sema))) {\n-\t\tif (tim_bkt_get_nent(lock_sema) != 0) {\n-\t\t\tuint64_t hbt_state;\n-#ifdef RTE_ARCH_ARM64\n-\t\t\tasm volatile(\"\t\tldxr %[hbt], [%[w1]]\t\\n\"\n-\t\t\t\t \"\t\ttbz %[hbt], 33, dne%=\t\\n\"\n-\t\t\t\t \"\t\tsevl\t\t\t\\n\"\n-\t\t\t\t \"rty%=:\twfe\t\t\t\\n\"\n-\t\t\t\t \"\t\tldxr %[hbt], [%[w1]]\t\\n\"\n-\t\t\t\t \"\t\ttbnz %[hbt], 33, rty%=\t\\n\"\n-\t\t\t\t \"dne%=:\t\t\t\t\\n\"\n-\t\t\t\t : [hbt] \"=&r\"(hbt_state)\n-\t\t\t\t : [w1] \"r\"((&bkt->w1))\n-\t\t\t\t : \"memory\");\n-#else\n-\t\t\tdo {\n-\t\t\t\thbt_state = __atomic_load_n(&bkt->w1,\n-\t\t\t\t\t\t\t __ATOMIC_RELAXED);\n-\t\t\t} while (hbt_state & BIT_ULL(33));\n-#endif\n-\n-\t\t\tif (!(hbt_state & BIT_ULL(34))) {\n-\t\t\t\ttim_bkt_dec_lock(bkt);\n-\t\t\t\tgoto __retry;\n-\t\t\t}\n-\t\t}\n-\t}\n-\t/* Insert the work. */\n-\trem = tim_bkt_fetch_rem(lock_sema);\n-\n-\tif (!rem) {\n-\t\tif (flags & OTX2_TIM_ENA_FB)\n-\t\t\tchunk = tim_refill_chunk(bkt, mirr_bkt, tim_ring);\n-\t\tif (flags & OTX2_TIM_ENA_DFB)\n-\t\t\tchunk = tim_insert_chunk(bkt, mirr_bkt, tim_ring);\n-\n-\t\tif (unlikely(chunk == NULL)) {\n-\t\t\tbkt->chunk_remainder = 0;\n-\t\t\ttim->impl_opaque[0] = 0;\n-\t\t\ttim->impl_opaque[1] = 0;\n-\t\t\ttim->state = RTE_EVENT_TIMER_ERROR;\n-\t\t\ttim_bkt_dec_lock(bkt);\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t\tmirr_bkt->current_chunk = (uintptr_t)chunk;\n-\t\tbkt->chunk_remainder = tim_ring->nb_chunk_slots - 1;\n-\t} else {\n-\t\tchunk = (struct otx2_tim_ent *)mirr_bkt->current_chunk;\n-\t\tchunk += tim_ring->nb_chunk_slots - rem;\n-\t}\n-\n-\t/* Copy work entry. */\n-\t*chunk = *pent;\n-\n-\ttim->impl_opaque[0] = (uintptr_t)chunk;\n-\ttim->impl_opaque[1] = (uintptr_t)bkt;\n-\t__atomic_store_n(&tim->state, RTE_EVENT_TIMER_ARMED, __ATOMIC_RELEASE);\n-\ttim_bkt_inc_nent(bkt);\n-\ttim_bkt_dec_lock_relaxed(bkt);\n-\n-\treturn 0;\n-}\n-\n-static __rte_always_inline int\n-tim_add_entry_mp(struct otx2_tim_ring * const tim_ring,\n-\t\t const uint32_t rel_bkt,\n-\t\t struct rte_event_timer * const tim,\n-\t\t const struct otx2_tim_ent * const pent,\n-\t\t const uint8_t flags)\n-{\n-\tstruct otx2_tim_bkt *mirr_bkt;\n-\tstruct otx2_tim_ent *chunk;\n-\tstruct otx2_tim_bkt *bkt;\n-\tuint64_t lock_sema;\n-\tint16_t rem;\n-\n-__retry:\n-\ttim_get_target_bucket(tim_ring, rel_bkt, &bkt, &mirr_bkt);\n-\t/* Get Bucket sema*/\n-\tlock_sema = tim_bkt_fetch_sema_lock(bkt);\n-\n-\t/* Bucket related checks. */\n-\tif (unlikely(tim_bkt_get_hbt(lock_sema))) {\n-\t\tif (tim_bkt_get_nent(lock_sema) != 0) {\n-\t\t\tuint64_t hbt_state;\n-#ifdef RTE_ARCH_ARM64\n-\t\t\tasm volatile(\"\t\tldxr %[hbt], [%[w1]]\t\\n\"\n-\t\t\t\t \"\t\ttbz %[hbt], 33, dne%=\t\\n\"\n-\t\t\t\t \"\t\tsevl\t\t\t\\n\"\n-\t\t\t\t \"rty%=:\twfe\t\t\t\\n\"\n-\t\t\t\t \"\t\tldxr %[hbt], [%[w1]]\t\\n\"\n-\t\t\t\t \"\t\ttbnz %[hbt], 33, rty%=\t\\n\"\n-\t\t\t\t \"dne%=:\t\t\t\t\\n\"\n-\t\t\t\t : [hbt] \"=&r\"(hbt_state)\n-\t\t\t\t : [w1] \"r\"((&bkt->w1))\n-\t\t\t\t : \"memory\");\n-#else\n-\t\t\tdo {\n-\t\t\t\thbt_state = __atomic_load_n(&bkt->w1,\n-\t\t\t\t\t\t\t __ATOMIC_RELAXED);\n-\t\t\t} while (hbt_state & BIT_ULL(33));\n-#endif\n-\n-\t\t\tif (!(hbt_state & BIT_ULL(34))) {\n-\t\t\t\ttim_bkt_dec_lock(bkt);\n-\t\t\t\tgoto __retry;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\trem = tim_bkt_fetch_rem(lock_sema);\n-\tif (rem < 0) {\n-\t\ttim_bkt_dec_lock(bkt);\n-#ifdef RTE_ARCH_ARM64\n-\t\tuint64_t w1;\n-\t\tasm volatile(\"\t\tldxr %[w1], [%[crem]]\t\\n\"\n-\t\t\t \"\t\ttbz %[w1], 63, dne%=\t\t\\n\"\n-\t\t\t \"\t\tsevl\t\t\t\t\\n\"\n-\t\t\t \"rty%=:\twfe\t\t\t\t\\n\"\n-\t\t\t \"\t\tldxr %[w1], [%[crem]]\t\\n\"\n-\t\t\t \"\t\ttbnz %[w1], 63, rty%=\t\t\\n\"\n-\t\t\t \"dne%=:\t\t\t\t\t\\n\"\n-\t\t\t : [w1] \"=&r\"(w1)\n-\t\t\t : [crem] \"r\"(&bkt->w1)\n-\t\t\t : \"memory\");\n-#else\n-\t\twhile (__atomic_load_n((int64_t *)&bkt->w1, __ATOMIC_RELAXED) <\n-\t\t 0)\n-\t\t\t;\n-#endif\n-\t\tgoto __retry;\n-\t} else if (!rem) {\n-\t\t/* Only one thread can be here*/\n-\t\tif (flags & OTX2_TIM_ENA_FB)\n-\t\t\tchunk = tim_refill_chunk(bkt, mirr_bkt, tim_ring);\n-\t\tif (flags & OTX2_TIM_ENA_DFB)\n-\t\t\tchunk = tim_insert_chunk(bkt, mirr_bkt, tim_ring);\n-\n-\t\tif (unlikely(chunk == NULL)) {\n-\t\t\ttim->impl_opaque[0] = 0;\n-\t\t\ttim->impl_opaque[1] = 0;\n-\t\t\ttim->state = RTE_EVENT_TIMER_ERROR;\n-\t\t\ttim_bkt_set_rem(bkt, 0);\n-\t\t\ttim_bkt_dec_lock(bkt);\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t\t*chunk = *pent;\n-\t\tif (tim_bkt_fetch_lock(lock_sema)) {\n-\t\t\tdo {\n-\t\t\t\tlock_sema = __atomic_load_n(&bkt->w1,\n-\t\t\t\t\t\t\t __ATOMIC_RELAXED);\n-\t\t\t} while (tim_bkt_fetch_lock(lock_sema) - 1);\n-\t\t\trte_atomic_thread_fence(__ATOMIC_ACQUIRE);\n-\t\t}\n-\t\tmirr_bkt->current_chunk = (uintptr_t)chunk;\n-\t\t__atomic_store_n(&bkt->chunk_remainder,\n-\t\t\t\ttim_ring->nb_chunk_slots - 1, __ATOMIC_RELEASE);\n-\t} else {\n-\t\tchunk = (struct otx2_tim_ent *)mirr_bkt->current_chunk;\n-\t\tchunk += tim_ring->nb_chunk_slots - rem;\n-\t\t*chunk = *pent;\n-\t}\n-\n-\ttim->impl_opaque[0] = (uintptr_t)chunk;\n-\ttim->impl_opaque[1] = (uintptr_t)bkt;\n-\t__atomic_store_n(&tim->state, RTE_EVENT_TIMER_ARMED, __ATOMIC_RELEASE);\n-\ttim_bkt_inc_nent(bkt);\n-\ttim_bkt_dec_lock_relaxed(bkt);\n-\n-\treturn 0;\n-}\n-\n-static inline uint16_t\n-tim_cpy_wrk(uint16_t index, uint16_t cpy_lmt,\n-\t struct otx2_tim_ent *chunk,\n-\t struct rte_event_timer ** const tim,\n-\t const struct otx2_tim_ent * const ents,\n-\t const struct otx2_tim_bkt * const bkt)\n-{\n-\tfor (; index < cpy_lmt; index++) {\n-\t\t*chunk = *(ents + index);\n-\t\ttim[index]->impl_opaque[0] = (uintptr_t)chunk++;\n-\t\ttim[index]->impl_opaque[1] = (uintptr_t)bkt;\n-\t\ttim[index]->state = RTE_EVENT_TIMER_ARMED;\n-\t}\n-\n-\treturn index;\n-}\n-\n-/* Burst mode functions */\n-static inline int\n-tim_add_entry_brst(struct otx2_tim_ring * const tim_ring,\n-\t\t const uint16_t rel_bkt,\n-\t\t struct rte_event_timer ** const tim,\n-\t\t const struct otx2_tim_ent *ents,\n-\t\t const uint16_t nb_timers, const uint8_t flags)\n-{\n-\tstruct otx2_tim_ent *chunk = NULL;\n-\tstruct otx2_tim_bkt *mirr_bkt;\n-\tstruct otx2_tim_bkt *bkt;\n-\tuint16_t chunk_remainder;\n-\tuint16_t index = 0;\n-\tuint64_t lock_sema;\n-\tint16_t rem, crem;\n-\tuint8_t lock_cnt;\n-\n-__retry:\n-\ttim_get_target_bucket(tim_ring, rel_bkt, &bkt, &mirr_bkt);\n-\n-\t/* Only one thread beyond this. */\n-\tlock_sema = tim_bkt_inc_lock(bkt);\n-\tlock_cnt = (uint8_t)\n-\t\t((lock_sema >> TIM_BUCKET_W1_S_LOCK) & TIM_BUCKET_W1_M_LOCK);\n-\n-\tif (lock_cnt) {\n-\t\ttim_bkt_dec_lock(bkt);\n-#ifdef RTE_ARCH_ARM64\n-\t\tasm volatile(\"\t\tldxrb %w[lock_cnt], [%[lock]]\t\\n\"\n-\t\t\t \"\t\ttst %w[lock_cnt], 255\t\t\\n\"\n-\t\t\t \"\t\tbeq dne%=\t\t\t\\n\"\n-\t\t\t \"\t\tsevl\t\t\t\t\\n\"\n-\t\t\t \"rty%=:\twfe\t\t\t\t\\n\"\n-\t\t\t \"\t\tldxrb %w[lock_cnt], [%[lock]]\t\\n\"\n-\t\t\t \"\t\ttst %w[lock_cnt], 255\t\t\\n\"\n-\t\t\t \"\t\tbne rty%=\t\t\t\\n\"\n-\t\t\t \"dne%=:\t\t\t\t\t\\n\"\n-\t\t\t : [lock_cnt] \"=&r\"(lock_cnt)\n-\t\t\t : [lock] \"r\"(&bkt->lock)\n-\t\t\t : \"memory\");\n-#else\n-\t\twhile (__atomic_load_n(&bkt->lock, __ATOMIC_RELAXED))\n-\t\t\t;\n-#endif\n-\t\tgoto __retry;\n-\t}\n-\n-\t/* Bucket related checks. */\n-\tif (unlikely(tim_bkt_get_hbt(lock_sema))) {\n-\t\tif (tim_bkt_get_nent(lock_sema) != 0) {\n-\t\t\tuint64_t hbt_state;\n-#ifdef RTE_ARCH_ARM64\n-\t\t\tasm volatile(\"\t\tldxr %[hbt], [%[w1]]\t\\n\"\n-\t\t\t\t \"\t\ttbz %[hbt], 33, dne%=\t\\n\"\n-\t\t\t\t \"\t\tsevl\t\t\t\\n\"\n-\t\t\t\t \"rty%=:\twfe\t\t\t\\n\"\n-\t\t\t\t \"\t\tldxr %[hbt], [%[w1]]\t\\n\"\n-\t\t\t\t \"\t\ttbnz %[hbt], 33, rty%=\t\\n\"\n-\t\t\t\t \"dne%=:\t\t\t\t\\n\"\n-\t\t\t\t : [hbt] \"=&r\"(hbt_state)\n-\t\t\t\t : [w1] \"r\"((&bkt->w1))\n-\t\t\t\t : \"memory\");\n-#else\n-\t\t\tdo {\n-\t\t\t\thbt_state = __atomic_load_n(&bkt->w1,\n-\t\t\t\t\t\t\t __ATOMIC_RELAXED);\n-\t\t\t} while (hbt_state & BIT_ULL(33));\n-#endif\n-\n-\t\t\tif (!(hbt_state & BIT_ULL(34))) {\n-\t\t\t\ttim_bkt_dec_lock(bkt);\n-\t\t\t\tgoto __retry;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\tchunk_remainder = tim_bkt_fetch_rem(lock_sema);\n-\trem = chunk_remainder - nb_timers;\n-\tif (rem < 0) {\n-\t\tcrem = tim_ring->nb_chunk_slots - chunk_remainder;\n-\t\tif (chunk_remainder && crem) {\n-\t\t\tchunk = ((struct otx2_tim_ent *)\n-\t\t\t\t\tmirr_bkt->current_chunk) + crem;\n-\n-\t\t\tindex = tim_cpy_wrk(index, chunk_remainder, chunk, tim,\n-\t\t\t\t\t ents, bkt);\n-\t\t\ttim_bkt_sub_rem(bkt, chunk_remainder);\n-\t\t\ttim_bkt_add_nent(bkt, chunk_remainder);\n-\t\t}\n-\n-\t\tif (flags & OTX2_TIM_ENA_FB)\n-\t\t\tchunk = tim_refill_chunk(bkt, mirr_bkt, tim_ring);\n-\t\tif (flags & OTX2_TIM_ENA_DFB)\n-\t\t\tchunk = tim_insert_chunk(bkt, mirr_bkt, tim_ring);\n-\n-\t\tif (unlikely(chunk == NULL)) {\n-\t\t\ttim_bkt_dec_lock(bkt);\n-\t\t\trte_errno = ENOMEM;\n-\t\t\ttim[index]->state = RTE_EVENT_TIMER_ERROR;\n-\t\t\treturn crem;\n-\t\t}\n-\t\t*(uint64_t *)(chunk + tim_ring->nb_chunk_slots) = 0;\n-\t\tmirr_bkt->current_chunk = (uintptr_t)chunk;\n-\t\ttim_cpy_wrk(index, nb_timers, chunk, tim, ents, bkt);\n-\n-\t\trem = nb_timers - chunk_remainder;\n-\t\ttim_bkt_set_rem(bkt, tim_ring->nb_chunk_slots - rem);\n-\t\ttim_bkt_add_nent(bkt, rem);\n-\t} else {\n-\t\tchunk = (struct otx2_tim_ent *)mirr_bkt->current_chunk;\n-\t\tchunk += (tim_ring->nb_chunk_slots - chunk_remainder);\n-\n-\t\ttim_cpy_wrk(index, nb_timers, chunk, tim, ents, bkt);\n-\t\ttim_bkt_sub_rem(bkt, nb_timers);\n-\t\ttim_bkt_add_nent(bkt, nb_timers);\n-\t}\n-\n-\ttim_bkt_dec_lock(bkt);\n-\n-\treturn nb_timers;\n-}\n-\n-static int\n-tim_rm_entry(struct rte_event_timer *tim)\n-{\n-\tstruct otx2_tim_ent *entry;\n-\tstruct otx2_tim_bkt *bkt;\n-\tuint64_t lock_sema;\n-\n-\tif (tim->impl_opaque[1] == 0 || tim->impl_opaque[0] == 0)\n-\t\treturn -ENOENT;\n-\n-\tentry = (struct otx2_tim_ent *)(uintptr_t)tim->impl_opaque[0];\n-\tif (entry->wqe != tim->ev.u64) {\n-\t\ttim->impl_opaque[0] = 0;\n-\t\ttim->impl_opaque[1] = 0;\n-\t\treturn -ENOENT;\n-\t}\n-\n-\tbkt = (struct otx2_tim_bkt *)(uintptr_t)tim->impl_opaque[1];\n-\tlock_sema = tim_bkt_inc_lock(bkt);\n-\tif (tim_bkt_get_hbt(lock_sema) || !tim_bkt_get_nent(lock_sema)) {\n-\t\ttim->impl_opaque[0] = 0;\n-\t\ttim->impl_opaque[1] = 0;\n-\t\ttim_bkt_dec_lock(bkt);\n-\t\treturn -ENOENT;\n-\t}\n-\n-\tentry->w0 = 0;\n-\tentry->wqe = 0;\n-\ttim->state = RTE_EVENT_TIMER_CANCELED;\n-\ttim->impl_opaque[0] = 0;\n-\ttim->impl_opaque[1] = 0;\n-\ttim_bkt_dec_lock(bkt);\n-\n-\treturn 0;\n-}\n-\n-#endif /* __OTX2_TIM_WORKER_H__ */\ndiff --git a/drivers/event/octeontx2/otx2_worker.c b/drivers/event/octeontx2/otx2_worker.c\ndeleted file mode 100644\nindex 95139d27a3..0000000000\n--- a/drivers/event/octeontx2/otx2_worker.c\n+++ /dev/null\n@@ -1,372 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_worker.h\"\n-\n-static __rte_noinline uint8_t\n-otx2_ssogws_new_event(struct otx2_ssogws *ws, const struct rte_event *ev)\n-{\n-\tconst uint32_t tag = (uint32_t)ev->event;\n-\tconst uint8_t new_tt = ev->sched_type;\n-\tconst uint64_t event_ptr = ev->u64;\n-\tconst uint16_t grp = ev->queue_id;\n-\n-\tif (ws->xaq_lmt <= *ws->fc_mem)\n-\t\treturn 0;\n-\n-\totx2_ssogws_add_work(ws, event_ptr, tag, new_tt, grp);\n-\n-\treturn 1;\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_fwd_swtag(struct otx2_ssogws *ws, const struct rte_event *ev)\n-{\n-\tconst uint32_t tag = (uint32_t)ev->event;\n-\tconst uint8_t new_tt = ev->sched_type;\n-\tconst uint8_t cur_tt = OTX2_SSOW_TT_FROM_TAG(otx2_read64(ws->tag_op));\n-\n-\t/* 96XX model\n-\t * cur_tt/new_tt SSO_SYNC_ORDERED SSO_SYNC_ATOMIC SSO_SYNC_UNTAGGED\n-\t *\n-\t * SSO_SYNC_ORDERED norm norm untag\n-\t * SSO_SYNC_ATOMIC norm norm\t\t untag\n-\t * SSO_SYNC_UNTAGGED norm norm NOOP\n-\t */\n-\n-\tif (new_tt == SSO_SYNC_UNTAGGED) {\n-\t\tif (cur_tt != SSO_SYNC_UNTAGGED)\n-\t\t\totx2_ssogws_swtag_untag(ws);\n-\t} else {\n-\t\totx2_ssogws_swtag_norm(ws, tag, new_tt);\n-\t}\n-\n-\tws->swtag_req = 1;\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_fwd_group(struct otx2_ssogws *ws, const struct rte_event *ev,\n-\t\t const uint16_t grp)\n-{\n-\tconst uint32_t tag = (uint32_t)ev->event;\n-\tconst uint8_t new_tt = ev->sched_type;\n-\n-\totx2_write64(ev->u64, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) +\n-\t\t SSOW_LF_GWS_OP_UPD_WQP_GRP1);\n-\trte_smp_wmb();\n-\totx2_ssogws_swtag_desched(ws, tag, new_tt, grp);\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_forward_event(struct otx2_ssogws *ws, const struct rte_event *ev)\n-{\n-\tconst uint8_t grp = ev->queue_id;\n-\n-\t/* Group hasn't changed, Use SWTAG to forward the event */\n-\tif (OTX2_SSOW_GRP_FROM_TAG(otx2_read64(ws->tag_op)) == grp)\n-\t\totx2_ssogws_fwd_swtag(ws, ev);\n-\telse\n-\t/*\n-\t * Group has been changed for group based work pipelining,\n-\t * Use deschedule/add_work operation to transfer the event to\n-\t * new group/core\n-\t */\n-\t\totx2_ssogws_fwd_group(ws, ev, grp);\n-}\n-\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_deq_ ##name(void *port, struct rte_event *ev,\t\t\\\n-\t\t\tuint64_t timeout_ticks)\t\t\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tstruct otx2_ssogws *ws = port;\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(timeout_ticks);\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tif (ws->swtag_req) {\t\t\t\t\t\t\\\n-\t\tws->swtag_req = 0;\t\t\t\t\t\\\n-\t\totx2_ssogws_swtag_wait(ws);\t\t\t\t\\\n-\t\treturn 1;\t\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn otx2_ssogws_get_work(ws, ev, flags, ws->lookup_mem);\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_deq_burst_ ##name(void *port, struct rte_event ev[],\t\\\n-\t\t\t uint16_t nb_events,\t\t\t\\\n-\t\t\t uint64_t timeout_ticks)\t\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn otx2_ssogws_deq_ ##name(port, ev, timeout_ticks);\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_deq_timeout_ ##name(void *port, struct rte_event *ev,\t\\\n-\t\t\t\tuint64_t timeout_ticks)\t\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tstruct otx2_ssogws *ws = port;\t\t\t\t\t\\\n-\tuint16_t ret = 1;\t\t\t\t\t\t\\\n-\tuint64_t iter;\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tif (ws->swtag_req) {\t\t\t\t\t\t\\\n-\t\tws->swtag_req = 0;\t\t\t\t\t\\\n-\t\totx2_ssogws_swtag_wait(ws);\t\t\t\t\\\n-\t\treturn ret;\t\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tret = otx2_ssogws_get_work(ws, ev, flags, ws->lookup_mem);\t\\\n-\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++)\t\\\n-\t\tret = otx2_ssogws_get_work(ws, ev, flags,\t\t\\\n-\t\t\t\t\t ws->lookup_mem);\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn ret;\t\t\t\t\t\t\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_deq_timeout_burst_ ##name(void *port, struct rte_event ev[],\\\n-\t\t\t\t uint16_t nb_events,\t\t\\\n-\t\t\t\t uint64_t timeout_ticks)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn otx2_ssogws_deq_timeout_ ##name(port, ev, timeout_ticks);\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_deq_seg_ ##name(void *port, struct rte_event *ev,\t\t\\\n-\t\t\t uint64_t timeout_ticks)\t\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tstruct otx2_ssogws *ws = port;\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(timeout_ticks);\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tif (ws->swtag_req) {\t\t\t\t\t\t\\\n-\t\tws->swtag_req = 0;\t\t\t\t\t\\\n-\t\totx2_ssogws_swtag_wait(ws);\t\t\t\t\\\n-\t\treturn 1;\t\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn otx2_ssogws_get_work(ws, ev, flags | NIX_RX_MULTI_SEG_F,\t\\\n-\t\t\t\t ws->lookup_mem);\t\t\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_deq_seg_burst_ ##name(void *port, struct rte_event ev[],\t\\\n-\t\t\t\t uint16_t nb_events,\t\t\t\\\n-\t\t\t\t uint64_t timeout_ticks)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn otx2_ssogws_deq_seg_ ##name(port, ev, timeout_ticks);\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_deq_seg_timeout_ ##name(void *port, struct rte_event *ev,\t\\\n-\t\t\t\t uint64_t timeout_ticks)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tstruct otx2_ssogws *ws = port;\t\t\t\t\t\\\n-\tuint16_t ret = 1;\t\t\t\t\t\t\\\n-\tuint64_t iter;\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tif (ws->swtag_req) {\t\t\t\t\t\t\\\n-\t\tws->swtag_req = 0;\t\t\t\t\t\\\n-\t\totx2_ssogws_swtag_wait(ws);\t\t\t\t\\\n-\t\treturn ret;\t\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tret = otx2_ssogws_get_work(ws, ev, flags | NIX_RX_MULTI_SEG_F,\t\\\n-\t\t\t\t ws->lookup_mem);\t\t\t\\\n-\tfor (iter = 1; iter < timeout_ticks && (ret == 0); iter++)\t\\\n-\t\tret = otx2_ssogws_get_work(ws, ev,\t\t\t\\\n-\t\t\t\t\t flags | NIX_RX_MULTI_SEG_F,\t\\\n-\t\t\t\t\t ws->lookup_mem);\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn ret;\t\t\t\t\t\t\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_deq_seg_timeout_burst_ ##name(void *port,\t\t\t\\\n-\t\t\t\t\t struct rte_event ev[],\t\\\n-\t\t\t\t\t uint16_t nb_events,\t\t\\\n-\t\t\t\t\t uint64_t timeout_ticks)\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn otx2_ssogws_deq_seg_timeout_ ##name(port, ev,\t\t\\\n-\t\t\t\t\t\t timeout_ticks);\t\\\n-}\n-\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\n-uint16_t __rte_hot\n-otx2_ssogws_enq(void *port, const struct rte_event *ev)\n-{\n-\tstruct otx2_ssogws *ws = port;\n-\n-\tswitch (ev->op) {\n-\tcase RTE_EVENT_OP_NEW:\n-\t\trte_smp_mb();\n-\t\treturn otx2_ssogws_new_event(ws, ev);\n-\tcase RTE_EVENT_OP_FORWARD:\n-\t\totx2_ssogws_forward_event(ws, ev);\n-\t\tbreak;\n-\tcase RTE_EVENT_OP_RELEASE:\n-\t\totx2_ssogws_swtag_flush(ws->tag_op, ws->swtag_flush_op);\n-\t\tbreak;\n-\tdefault:\n-\t\treturn 0;\n-\t}\n-\n-\treturn 1;\n-}\n-\n-uint16_t __rte_hot\n-otx2_ssogws_enq_burst(void *port, const struct rte_event ev[],\n-\t\t uint16_t nb_events)\n-{\n-\tRTE_SET_USED(nb_events);\n-\treturn otx2_ssogws_enq(port, ev);\n-}\n-\n-uint16_t __rte_hot\n-otx2_ssogws_enq_new_burst(void *port, const struct rte_event ev[],\n-\t\t\t uint16_t nb_events)\n-{\n-\tstruct otx2_ssogws *ws = port;\n-\tuint16_t i, rc = 1;\n-\n-\trte_smp_mb();\n-\tif (ws->xaq_lmt <= *ws->fc_mem)\n-\t\treturn 0;\n-\n-\tfor (i = 0; i < nb_events && rc; i++)\n-\t\trc = otx2_ssogws_new_event(ws, &ev[i]);\n-\n-\treturn nb_events;\n-}\n-\n-uint16_t __rte_hot\n-otx2_ssogws_enq_fwd_burst(void *port, const struct rte_event ev[],\n-\t\t\t uint16_t nb_events)\n-{\n-\tstruct otx2_ssogws *ws = port;\n-\n-\tRTE_SET_USED(nb_events);\n-\totx2_ssogws_forward_event(ws, ev);\n-\n-\treturn 1;\n-}\n-\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\\\n-otx2_ssogws_tx_adptr_enq_ ## name(void *port, struct rte_event ev[],\t\\\n-\t\t\t\t uint16_t nb_events)\t\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tstruct otx2_ssogws *ws = port;\t\t\t\t\t\\\n-\tuint64_t cmd[sz];\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n-\treturn otx2_ssogws_event_tx(ws->base, &ev[0], cmd,\t\t\\\n-\t\t\t\t (const uint64_t\t\t\t\\\n-\t\t\t\t (*)[RTE_MAX_QUEUES_PER_PORT])\t\\\n-\t\t\t\t &ws->tx_adptr_data,\t\t\t\\\n-\t\t\t\t flags);\t\t\t\t\\\n-}\n-SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef T\n-\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\\\n-otx2_ssogws_tx_adptr_enq_seg_ ## name(void *port, struct rte_event ev[],\\\n-\t\t\t\t uint16_t nb_events)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tuint64_t cmd[(sz) + NIX_TX_MSEG_SG_DWORDS - 2];\t\t\t\\\n-\tstruct otx2_ssogws *ws = port;\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n-\treturn otx2_ssogws_event_tx(ws->base, &ev[0], cmd,\t\t\\\n-\t\t\t\t (const uint64_t\t\t\t\\\n-\t\t\t\t (*)[RTE_MAX_QUEUES_PER_PORT])\t\\\n-\t\t\t\t &ws->tx_adptr_data,\t\t\t\\\n-\t\t\t\t (flags) | NIX_TX_MULTI_SEG_F);\t\\\n-}\n-SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef T\n-\n-void\n-ssogws_flush_events(struct otx2_ssogws *ws, uint8_t queue_id, uintptr_t base,\n-\t\t otx2_handle_event_t fn, void *arg)\n-{\n-\tuint64_t cq_ds_cnt = 1;\n-\tuint64_t aq_cnt = 1;\n-\tuint64_t ds_cnt = 1;\n-\tstruct rte_event ev;\n-\tuint64_t enable;\n-\tuint64_t val;\n-\n-\tenable = otx2_read64(base + SSO_LF_GGRP_QCTL);\n-\tif (!enable)\n-\t\treturn;\n-\n-\tval = queue_id;\t/* GGRP ID */\n-\tval |= BIT_ULL(18);\t/* Grouped */\n-\tval |= BIT_ULL(16);\t/* WAIT */\n-\n-\taq_cnt = otx2_read64(base + SSO_LF_GGRP_AQ_CNT);\n-\tds_cnt = otx2_read64(base + SSO_LF_GGRP_MISC_CNT);\n-\tcq_ds_cnt = otx2_read64(base + SSO_LF_GGRP_INT_CNT);\n-\tcq_ds_cnt &= 0x3FFF3FFF0000;\n-\n-\twhile (aq_cnt || cq_ds_cnt || ds_cnt) {\n-\t\totx2_write64(val, ws->getwrk_op);\n-\t\totx2_ssogws_get_work_empty(ws, &ev, 0);\n-\t\tif (fn != NULL && ev.u64 != 0)\n-\t\t\tfn(arg, ev);\n-\t\tif (ev.sched_type != SSO_TT_EMPTY)\n-\t\t\totx2_ssogws_swtag_flush(ws->tag_op, ws->swtag_flush_op);\n-\t\trte_mb();\n-\t\taq_cnt = otx2_read64(base + SSO_LF_GGRP_AQ_CNT);\n-\t\tds_cnt = otx2_read64(base + SSO_LF_GGRP_MISC_CNT);\n-\t\tcq_ds_cnt = otx2_read64(base + SSO_LF_GGRP_INT_CNT);\n-\t\t/* Extract cq and ds count */\n-\t\tcq_ds_cnt &= 0x3FFF3FFF0000;\n-\t}\n-\n-\totx2_write64(0, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) +\n-\t\t SSOW_LF_GWS_OP_GWC_INVAL);\n-\trte_mb();\n-}\n-\n-void\n-ssogws_reset(struct otx2_ssogws *ws)\n-{\n-\tuintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);\n-\tuint64_t pend_state;\n-\tuint8_t pend_tt;\n-\tuint64_t tag;\n-\n-\t/* Wait till getwork/swtp/waitw/desched completes. */\n-\tdo {\n-\t\tpend_state = otx2_read64(base + SSOW_LF_GWS_PENDSTATE);\n-\t\trte_mb();\n-\t} while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58)));\n-\n-\ttag = otx2_read64(base + SSOW_LF_GWS_TAG);\n-\tpend_tt = (tag >> 32) & 0x3;\n-\tif (pend_tt != SSO_TT_EMPTY) { /* Work was pending */\n-\t\tif (pend_tt == SSO_SYNC_ATOMIC || pend_tt == SSO_SYNC_ORDERED)\n-\t\t\totx2_ssogws_swtag_untag(ws);\n-\t\totx2_ssogws_desched(ws);\n-\t}\n-\trte_mb();\n-\n-\t/* Wait for desched to complete. */\n-\tdo {\n-\t\tpend_state = otx2_read64(base + SSOW_LF_GWS_PENDSTATE);\n-\t\trte_mb();\n-\t} while (pend_state & BIT_ULL(58));\n-}\ndiff --git a/drivers/event/octeontx2/otx2_worker.h b/drivers/event/octeontx2/otx2_worker.h\ndeleted file mode 100644\nindex aa766c6602..0000000000\n--- a/drivers/event/octeontx2/otx2_worker.h\n+++ /dev/null\n@@ -1,339 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_WORKER_H__\n-#define __OTX2_WORKER_H__\n-\n-#include <rte_common.h>\n-#include <rte_branch_prediction.h>\n-\n-#include <otx2_common.h>\n-#include \"otx2_evdev.h\"\n-#include \"otx2_evdev_crypto_adptr_rx.h\"\n-#include \"otx2_ethdev_sec_tx.h\"\n-\n-/* SSO Operations */\n-\n-static __rte_always_inline uint16_t\n-otx2_ssogws_get_work(struct otx2_ssogws *ws, struct rte_event *ev,\n-\t\t const uint32_t flags, const void * const lookup_mem)\n-{\n-\tunion otx2_sso_event event;\n-\tuint64_t tstamp_ptr;\n-\tuint64_t get_work1;\n-\tuint64_t mbuf;\n-\n-\totx2_write64(BIT_ULL(16) | /* wait for work. */\n-\t\t 1, /* Use Mask set 0. */\n-\t\t ws->getwrk_op);\n-\n-\tif (flags & NIX_RX_OFFLOAD_PTYPE_F)\n-\t\trte_prefetch_non_temporal(lookup_mem);\n-#ifdef RTE_ARCH_ARM64\n-\tasm volatile(\n-\t\t\t\"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n-\t\t\t\"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n-\t\t\t\"\t\ttbz %[tag], 63, done%=\t\t\\n\"\n-\t\t\t\"\t\tsevl\t\t\t\t\\n\"\n-\t\t\t\"rty%=:\t\twfe\t\t\t\t\\n\"\n-\t\t\t\"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n-\t\t\t\"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n-\t\t\t\"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n-\t\t\t\"done%=:\tdmb ld\t\t\t\t\\n\"\n-\t\t\t\"\t\tprfm pldl1keep, [%[wqp], #8]\t\\n\"\n-\t\t\t\"\t\tsub %[mbuf], %[wqp], #0x80\t\\n\"\n-\t\t\t\"\t\tprfm pldl1keep, [%[mbuf]]\t\\n\"\n-\t\t\t: [tag] \"=&r\" (event.get_work0),\n-\t\t\t [wqp] \"=&r\" (get_work1),\n-\t\t\t [mbuf] \"=&r\" (mbuf)\n-\t\t\t: [tag_loc] \"r\" (ws->tag_op),\n-\t\t\t [wqp_loc] \"r\" (ws->wqp_op)\n-\t\t\t);\n-#else\n-\tevent.get_work0 = otx2_read64(ws->tag_op);\n-\twhile ((BIT_ULL(63)) & event.get_work0)\n-\t\tevent.get_work0 = otx2_read64(ws->tag_op);\n-\n-\tget_work1 = otx2_read64(ws->wqp_op);\n-\trte_prefetch0((const void *)get_work1);\n-\tmbuf = (uint64_t)((char *)get_work1 - sizeof(struct rte_mbuf));\n-\trte_prefetch0((const void *)mbuf);\n-#endif\n-\n-\tevent.get_work0 = (event.get_work0 & (0x3ull << 32)) << 6 |\n-\t\t(event.get_work0 & (0x3FFull << 36)) << 4 |\n-\t\t(event.get_work0 & 0xffffffff);\n-\n-\tif (event.sched_type != SSO_TT_EMPTY) {\n-\t\tif ((flags & NIX_RX_OFFLOAD_SECURITY_F) &&\n-\t\t (event.event_type == RTE_EVENT_TYPE_CRYPTODEV)) {\n-\t\t\tget_work1 = otx2_handle_crypto_event(get_work1);\n-\t\t} else if (event.event_type == RTE_EVENT_TYPE_ETHDEV) {\n-\t\t\totx2_wqe_to_mbuf(get_work1, mbuf, event.sub_event_type,\n-\t\t\t\t\t (uint32_t) event.get_work0, flags,\n-\t\t\t\t\t lookup_mem);\n-\t\t\t/* Extracting tstamp, if PTP enabled*/\n-\t\t\ttstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)\n-\t\t\t\t\t\t get_work1) +\n-\t\t\t\t\t\t OTX2_SSO_WQE_SG_PTR);\n-\t\t\totx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf,\n-\t\t\t\t\t\tws->tstamp, flags,\n-\t\t\t\t\t\t(uint64_t *)tstamp_ptr);\n-\t\t\tget_work1 = mbuf;\n-\t\t}\n-\t}\n-\n-\tev->event = event.get_work0;\n-\tev->u64 = get_work1;\n-\n-\treturn !!get_work1;\n-}\n-\n-/* Used in cleaning up workslot. */\n-static __rte_always_inline uint16_t\n-otx2_ssogws_get_work_empty(struct otx2_ssogws *ws, struct rte_event *ev,\n-\t\t\t const uint32_t flags)\n-{\n-\tunion otx2_sso_event event;\n-\tuint64_t tstamp_ptr;\n-\tuint64_t get_work1;\n-\tuint64_t mbuf;\n-\n-#ifdef RTE_ARCH_ARM64\n-\tasm volatile(\n-\t\t\t\"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n-\t\t\t\"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n-\t\t\t\"\t\ttbz %[tag], 63, done%=\t\t\\n\"\n-\t\t\t\"\t\tsevl\t\t\t\t\\n\"\n-\t\t\t\"rty%=:\t\twfe\t\t\t\t\\n\"\n-\t\t\t\"\t\tldr %[tag], [%[tag_loc]]\t\\n\"\n-\t\t\t\"\t\tldr %[wqp], [%[wqp_loc]]\t\\n\"\n-\t\t\t\"\t\ttbnz %[tag], 63, rty%=\t\t\\n\"\n-\t\t\t\"done%=:\tdmb ld\t\t\t\t\\n\"\n-\t\t\t\"\t\tprfm pldl1keep, [%[wqp], #8]\t\\n\"\n-\t\t\t\"\t\tsub %[mbuf], %[wqp], #0x80\t\\n\"\n-\t\t\t\"\t\tprfm pldl1keep, [%[mbuf]]\t\\n\"\n-\t\t\t: [tag] \"=&r\" (event.get_work0),\n-\t\t\t [wqp] \"=&r\" (get_work1),\n-\t\t\t [mbuf] \"=&r\" (mbuf)\n-\t\t\t: [tag_loc] \"r\" (ws->tag_op),\n-\t\t\t [wqp_loc] \"r\" (ws->wqp_op)\n-\t\t\t);\n-#else\n-\tevent.get_work0 = otx2_read64(ws->tag_op);\n-\twhile ((BIT_ULL(63)) & event.get_work0)\n-\t\tevent.get_work0 = otx2_read64(ws->tag_op);\n-\n-\tget_work1 = otx2_read64(ws->wqp_op);\n-\trte_prefetch_non_temporal((const void *)get_work1);\n-\tmbuf = (uint64_t)((char *)get_work1 - sizeof(struct rte_mbuf));\n-\trte_prefetch_non_temporal((const void *)mbuf);\n-#endif\n-\n-\tevent.get_work0 = (event.get_work0 & (0x3ull << 32)) << 6 |\n-\t\t(event.get_work0 & (0x3FFull << 36)) << 4 |\n-\t\t(event.get_work0 & 0xffffffff);\n-\n-\tif (event.sched_type != SSO_TT_EMPTY &&\n-\t event.event_type == RTE_EVENT_TYPE_ETHDEV) {\n-\t\totx2_wqe_to_mbuf(get_work1, mbuf, event.sub_event_type,\n-\t\t\t\t (uint32_t) event.get_work0, flags, NULL);\n-\t\t/* Extracting tstamp, if PTP enabled*/\n-\t\ttstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)get_work1)\n-\t\t\t\t\t + OTX2_SSO_WQE_SG_PTR);\n-\t\totx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, ws->tstamp,\n-\t\t\t\t\tflags, (uint64_t *)tstamp_ptr);\n-\t\tget_work1 = mbuf;\n-\t}\n-\n-\tev->event = event.get_work0;\n-\tev->u64 = get_work1;\n-\n-\treturn !!get_work1;\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_add_work(struct otx2_ssogws *ws, const uint64_t event_ptr,\n-\t\t const uint32_t tag, const uint8_t new_tt,\n-\t\t const uint16_t grp)\n-{\n-\tuint64_t add_work0;\n-\n-\tadd_work0 = tag | ((uint64_t)(new_tt) << 32);\n-\totx2_store_pair(add_work0, event_ptr, ws->grps_base[grp]);\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_swtag_desched(struct otx2_ssogws *ws, uint32_t tag, uint8_t new_tt,\n-\t\t\t uint16_t grp)\n-{\n-\tuint64_t val;\n-\n-\tval = tag | ((uint64_t)(new_tt & 0x3) << 32) | ((uint64_t)grp << 34);\n-\totx2_write64(val, ws->swtag_desched_op);\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_swtag_norm(struct otx2_ssogws *ws, uint32_t tag, uint8_t new_tt)\n-{\n-\tuint64_t val;\n-\n-\tval = tag | ((uint64_t)(new_tt & 0x3) << 32);\n-\totx2_write64(val, ws->swtag_norm_op);\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_swtag_untag(struct otx2_ssogws *ws)\n-{\n-\totx2_write64(0, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) +\n-\t\t SSOW_LF_GWS_OP_SWTAG_UNTAG);\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_swtag_flush(uint64_t tag_op, uint64_t flush_op)\n-{\n-\tif (OTX2_SSOW_TT_FROM_TAG(otx2_read64(tag_op)) == SSO_TT_EMPTY)\n-\t\treturn;\n-\totx2_write64(0, flush_op);\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_desched(struct otx2_ssogws *ws)\n-{\n-\totx2_write64(0, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) +\n-\t\t SSOW_LF_GWS_OP_DESCHED);\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_swtag_wait(struct otx2_ssogws *ws)\n-{\n-#ifdef RTE_ARCH_ARM64\n-\tuint64_t swtp;\n-\n-\tasm volatile(\"\t\tldr %[swtb], [%[swtp_loc]]\t\\n\"\n-\t\t \"\t\ttbz %[swtb], 62, done%=\t\t\\n\"\n-\t\t \"\t\tsevl\t\t\t\t\\n\"\n-\t\t \"rty%=:\twfe\t\t\t\t\\n\"\n-\t\t \"\t\tldr %[swtb], [%[swtp_loc]]\t\\n\"\n-\t\t \"\t\ttbnz %[swtb], 62, rty%=\t\t\\n\"\n-\t\t \"done%=:\t\t\t\t\t\\n\"\n-\t\t : [swtb] \"=&r\" (swtp)\n-\t\t : [swtp_loc] \"r\" (ws->tag_op));\n-#else\n-\t/* Wait for the SWTAG/SWTAG_FULL operation */\n-\twhile (otx2_read64(ws->tag_op) & BIT_ULL(62))\n-\t\t;\n-#endif\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_head_wait(uint64_t tag_op)\n-{\n-#ifdef RTE_ARCH_ARM64\n-\tuint64_t tag;\n-\n-\tasm volatile (\n-\t\t\t\"\tldr %[tag], [%[tag_op]]\t\t\\n\"\n-\t\t\t\"\ttbnz %[tag], 35, done%=\t\t\\n\"\n-\t\t\t\"\tsevl\t\t\t\t\\n\"\n-\t\t\t\"rty%=:\twfe\t\t\t\t\\n\"\n-\t\t\t\"\tldr %[tag], [%[tag_op]]\t\t\\n\"\n-\t\t\t\"\ttbz %[tag], 35, rty%=\t\t\\n\"\n-\t\t\t\"done%=:\t\t\t\t\\n\"\n-\t\t\t: [tag] \"=&r\" (tag)\n-\t\t\t: [tag_op] \"r\" (tag_op)\n-\t\t\t);\n-#else\n-\t/* Wait for the HEAD to be set */\n-\twhile (!(otx2_read64(tag_op) & BIT_ULL(35)))\n-\t\t;\n-#endif\n-}\n-\n-static __rte_always_inline const struct otx2_eth_txq *\n-otx2_ssogws_xtract_meta(struct rte_mbuf *m,\n-\t\t\tconst uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT])\n-{\n-\treturn (const struct otx2_eth_txq *)txq_data[m->port][\n-\t\t\t\t\trte_event_eth_tx_adapter_txq_get(m)];\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_prepare_pkt(const struct otx2_eth_txq *txq, struct rte_mbuf *m,\n-\t\t\tuint64_t *cmd, const uint32_t flags)\n-{\n-\totx2_lmt_mov(cmd, txq->cmd, otx2_nix_tx_ext_subs(flags));\n-\totx2_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt);\n-}\n-\n-static __rte_always_inline uint16_t\n-otx2_ssogws_event_tx(uint64_t base, struct rte_event *ev, uint64_t *cmd,\n-\t\t const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],\n-\t\t const uint32_t flags)\n-{\n-\tstruct rte_mbuf *m = ev->mbuf;\n-\tconst struct otx2_eth_txq *txq;\n-\tuint16_t ref_cnt = m->refcnt;\n-\n-\tif ((flags & NIX_TX_OFFLOAD_SECURITY_F) &&\n-\t (m->ol_flags & RTE_MBUF_F_TX_SEC_OFFLOAD)) {\n-\t\ttxq = otx2_ssogws_xtract_meta(m, txq_data);\n-\t\treturn otx2_sec_event_tx(base, ev, m, txq, flags);\n-\t}\n-\n-\t/* Perform header writes before barrier for TSO */\n-\totx2_nix_xmit_prepare_tso(m, flags);\n-\t/* Lets commit any changes in the packet here in case when\n-\t * fast free is set as no further changes will be made to mbuf.\n-\t * In case of fast free is not set, both otx2_nix_prepare_mseg()\n-\t * and otx2_nix_xmit_prepare() has a barrier after refcnt update.\n-\t */\n-\tif (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))\n-\t\trte_io_wmb();\n-\ttxq = otx2_ssogws_xtract_meta(m, txq_data);\n-\totx2_ssogws_prepare_pkt(txq, m, cmd, flags);\n-\n-\tif (flags & NIX_TX_MULTI_SEG_F) {\n-\t\tconst uint16_t segdw = otx2_nix_prepare_mseg(m, cmd, flags);\n-\t\totx2_nix_xmit_prepare_tstamp(cmd, &txq->cmd[0],\n-\t\t\t\t\t m->ol_flags, segdw, flags);\n-\t\tif (!ev->sched_type) {\n-\t\t\totx2_nix_xmit_mseg_prep_lmt(cmd, txq->lmt_addr, segdw);\n-\t\t\totx2_ssogws_head_wait(base + SSOW_LF_GWS_TAG);\n-\t\t\tif (otx2_nix_xmit_submit_lmt(txq->io_addr) == 0)\n-\t\t\t\totx2_nix_xmit_mseg_one(cmd, txq->lmt_addr,\n-\t\t\t\t\t\t txq->io_addr, segdw);\n-\t\t} else {\n-\t\t\totx2_nix_xmit_mseg_one(cmd, txq->lmt_addr,\n-\t\t\t\t\t txq->io_addr, segdw);\n-\t\t}\n-\t} else {\n-\t\t/* Passing no of segdw as 4: HDR + EXT + SG + SMEM */\n-\t\totx2_nix_xmit_prepare_tstamp(cmd, &txq->cmd[0],\n-\t\t\t\t\t m->ol_flags, 4, flags);\n-\n-\t\tif (!ev->sched_type) {\n-\t\t\totx2_nix_xmit_prep_lmt(cmd, txq->lmt_addr, flags);\n-\t\t\totx2_ssogws_head_wait(base + SSOW_LF_GWS_TAG);\n-\t\t\tif (otx2_nix_xmit_submit_lmt(txq->io_addr) == 0)\n-\t\t\t\totx2_nix_xmit_one(cmd, txq->lmt_addr,\n-\t\t\t\t\t\t txq->io_addr, flags);\n-\t\t} else {\n-\t\t\totx2_nix_xmit_one(cmd, txq->lmt_addr, txq->io_addr,\n-\t\t\t\t\t flags);\n-\t\t}\n-\t}\n-\n-\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n-\t\tif (ref_cnt > 1)\n-\t\t\treturn 1;\n-\t}\n-\n-\totx2_ssogws_swtag_flush(base + SSOW_LF_GWS_TAG,\n-\t\t\t\tbase + SSOW_LF_GWS_OP_SWTAG_FLUSH);\n-\n-\treturn 1;\n-}\n-\n-#endif\ndiff --git a/drivers/event/octeontx2/otx2_worker_dual.c b/drivers/event/octeontx2/otx2_worker_dual.c\ndeleted file mode 100644\nindex 81af4ca904..0000000000\n--- a/drivers/event/octeontx2/otx2_worker_dual.c\n+++ /dev/null\n@@ -1,345 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_worker_dual.h\"\n-#include \"otx2_worker.h\"\n-\n-static __rte_noinline uint8_t\n-otx2_ssogws_dual_new_event(struct otx2_ssogws_dual *ws,\n-\t\t\t const struct rte_event *ev)\n-{\n-\tconst uint32_t tag = (uint32_t)ev->event;\n-\tconst uint8_t new_tt = ev->sched_type;\n-\tconst uint64_t event_ptr = ev->u64;\n-\tconst uint16_t grp = ev->queue_id;\n-\n-\tif (ws->xaq_lmt <= *ws->fc_mem)\n-\t\treturn 0;\n-\n-\totx2_ssogws_dual_add_work(ws, event_ptr, tag, new_tt, grp);\n-\n-\treturn 1;\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_dual_fwd_swtag(struct otx2_ssogws_state *ws,\n-\t\t\t const struct rte_event *ev)\n-{\n-\tconst uint8_t cur_tt = OTX2_SSOW_TT_FROM_TAG(otx2_read64(ws->tag_op));\n-\tconst uint32_t tag = (uint32_t)ev->event;\n-\tconst uint8_t new_tt = ev->sched_type;\n-\n-\t/* 96XX model\n-\t * cur_tt/new_tt SSO_SYNC_ORDERED SSO_SYNC_ATOMIC SSO_SYNC_UNTAGGED\n-\t *\n-\t * SSO_SYNC_ORDERED norm norm untag\n-\t * SSO_SYNC_ATOMIC norm norm\t\t untag\n-\t * SSO_SYNC_UNTAGGED norm norm NOOP\n-\t */\n-\tif (new_tt == SSO_SYNC_UNTAGGED) {\n-\t\tif (cur_tt != SSO_SYNC_UNTAGGED)\n-\t\t\totx2_ssogws_swtag_untag((struct otx2_ssogws *)ws);\n-\t} else {\n-\t\totx2_ssogws_swtag_norm((struct otx2_ssogws *)ws, tag, new_tt);\n-\t}\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_dual_fwd_group(struct otx2_ssogws_state *ws,\n-\t\t\t const struct rte_event *ev, const uint16_t grp)\n-{\n-\tconst uint32_t tag = (uint32_t)ev->event;\n-\tconst uint8_t new_tt = ev->sched_type;\n-\n-\totx2_write64(ev->u64, OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op) +\n-\t\t SSOW_LF_GWS_OP_UPD_WQP_GRP1);\n-\trte_smp_wmb();\n-\totx2_ssogws_swtag_desched((struct otx2_ssogws *)ws, tag, new_tt, grp);\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_dual_forward_event(struct otx2_ssogws_dual *ws,\n-\t\t\t struct otx2_ssogws_state *vws,\n-\t\t\t const struct rte_event *ev)\n-{\n-\tconst uint8_t grp = ev->queue_id;\n-\n-\t/* Group hasn't changed, Use SWTAG to forward the event */\n-\tif (OTX2_SSOW_GRP_FROM_TAG(otx2_read64(vws->tag_op)) == grp) {\n-\t\totx2_ssogws_dual_fwd_swtag(vws, ev);\n-\t\tws->swtag_req = 1;\n-\t} else {\n-\t\t/*\n-\t\t * Group has been changed for group based work pipelining,\n-\t\t * Use deschedule/add_work operation to transfer the event to\n-\t\t * new group/core\n-\t\t */\n-\t\totx2_ssogws_dual_fwd_group(vws, ev, grp);\n-\t}\n-}\n-\n-uint16_t __rte_hot\n-otx2_ssogws_dual_enq(void *port, const struct rte_event *ev)\n-{\n-\tstruct otx2_ssogws_dual *ws = port;\n-\tstruct otx2_ssogws_state *vws = &ws->ws_state[!ws->vws];\n-\n-\tswitch (ev->op) {\n-\tcase RTE_EVENT_OP_NEW:\n-\t\trte_smp_mb();\n-\t\treturn otx2_ssogws_dual_new_event(ws, ev);\n-\tcase RTE_EVENT_OP_FORWARD:\n-\t\totx2_ssogws_dual_forward_event(ws, vws, ev);\n-\t\tbreak;\n-\tcase RTE_EVENT_OP_RELEASE:\n-\t\totx2_ssogws_swtag_flush(vws->tag_op, vws->swtag_flush_op);\n-\t\tbreak;\n-\tdefault:\n-\t\treturn 0;\n-\t}\n-\n-\treturn 1;\n-}\n-\n-uint16_t __rte_hot\n-otx2_ssogws_dual_enq_burst(void *port, const struct rte_event ev[],\n-\t\t\t uint16_t nb_events)\n-{\n-\tRTE_SET_USED(nb_events);\n-\treturn otx2_ssogws_dual_enq(port, ev);\n-}\n-\n-uint16_t __rte_hot\n-otx2_ssogws_dual_enq_new_burst(void *port, const struct rte_event ev[],\n-\t\t\t uint16_t nb_events)\n-{\n-\tstruct otx2_ssogws_dual *ws = port;\n-\tuint16_t i, rc = 1;\n-\n-\trte_smp_mb();\n-\tif (ws->xaq_lmt <= *ws->fc_mem)\n-\t\treturn 0;\n-\n-\tfor (i = 0; i < nb_events && rc; i++)\n-\t\trc = otx2_ssogws_dual_new_event(ws, &ev[i]);\n-\n-\treturn nb_events;\n-}\n-\n-uint16_t __rte_hot\n-otx2_ssogws_dual_enq_fwd_burst(void *port, const struct rte_event ev[],\n-\t\t\t uint16_t nb_events)\n-{\n-\tstruct otx2_ssogws_dual *ws = port;\n-\tstruct otx2_ssogws_state *vws = &ws->ws_state[!ws->vws];\n-\n-\tRTE_SET_USED(nb_events);\n-\totx2_ssogws_dual_forward_event(ws, vws, ev);\n-\n-\treturn 1;\n-}\n-\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_dual_deq_ ##name(void *port, struct rte_event *ev,\t\t\\\n-\t\t\t uint64_t timeout_ticks)\t\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tstruct otx2_ssogws_dual *ws = port;\t\t\t\t\\\n-\tuint8_t gw;\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\trte_prefetch_non_temporal(ws);\t\t\t\t\t\\\n-\tRTE_SET_USED(timeout_ticks);\t\t\t\t\t\\\n-\tif (ws->swtag_req) {\t\t\t\t\t\t\\\n-\t\totx2_ssogws_swtag_wait((struct otx2_ssogws *)\t\t\\\n-\t\t\t\t &ws->ws_state[!ws->vws]);\t\\\n-\t\tws->swtag_req = 0;\t\t\t\t\t\\\n-\t\treturn 1;\t\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tgw = otx2_ssogws_dual_get_work(&ws->ws_state[ws->vws],\t\t\\\n-\t\t\t\t &ws->ws_state[!ws->vws], ev,\t\\\n-\t\t\t\t flags, ws->lookup_mem,\t\t\\\n-\t\t\t\t ws->tstamp);\t\t\t\\\n-\tws->vws = !ws->vws;\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn gw;\t\t\t\t\t\t\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_dual_deq_burst_ ##name(void *port, struct rte_event ev[],\t\\\n-\t\t\t\t uint16_t nb_events,\t\t\t\\\n-\t\t\t\t uint64_t timeout_ticks)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn otx2_ssogws_dual_deq_ ##name(port, ev, timeout_ticks);\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_dual_deq_timeout_ ##name(void *port, struct rte_event *ev,\t\\\n-\t\t\t\t uint64_t timeout_ticks)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tstruct otx2_ssogws_dual *ws = port;\t\t\t\t\\\n-\tuint64_t iter;\t\t\t\t\t\t\t\\\n-\tuint8_t gw;\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tif (ws->swtag_req) {\t\t\t\t\t\t\\\n-\t\totx2_ssogws_swtag_wait((struct otx2_ssogws *)\t\t\\\n-\t\t\t\t &ws->ws_state[!ws->vws]);\t\\\n-\t\tws->swtag_req = 0;\t\t\t\t\t\\\n-\t\treturn 1;\t\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tgw = otx2_ssogws_dual_get_work(&ws->ws_state[ws->vws],\t\t\\\n-\t\t\t\t &ws->ws_state[!ws->vws], ev,\t\\\n-\t\t\t\t flags, ws->lookup_mem,\t\t\\\n-\t\t\t\t ws->tstamp);\t\t\t\\\n-\tws->vws = !ws->vws;\t\t\t\t\t\t\\\n-\tfor (iter = 1; iter < timeout_ticks && (gw == 0); iter++) {\t\\\n-\t\tgw = otx2_ssogws_dual_get_work(&ws->ws_state[ws->vws],\t\\\n-\t\t\t\t\t &ws->ws_state[!ws->vws],\t\\\n-\t\t\t\t\t ev, flags,\t\t\\\n-\t\t\t\t\t ws->lookup_mem,\t\t\\\n-\t\t\t\t\t ws->tstamp);\t\t\\\n-\t\tws->vws = !ws->vws;\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn gw;\t\t\t\t\t\t\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_dual_deq_timeout_burst_ ##name(void *port,\t\t\t\\\n-\t\t\t\t\t struct rte_event ev[],\t\\\n-\t\t\t\t\t uint16_t nb_events,\t\t\\\n-\t\t\t\t\t uint64_t timeout_ticks)\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn otx2_ssogws_dual_deq_timeout_ ##name(port, ev,\t\t\\\n-\t\t\t\t\t\t timeout_ticks);\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_dual_deq_seg_ ##name(void *port, struct rte_event *ev,\t\\\n-\t\t\t\t uint64_t timeout_ticks)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tstruct otx2_ssogws_dual *ws = port;\t\t\t\t\\\n-\tuint8_t gw;\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(timeout_ticks);\t\t\t\t\t\\\n-\tif (ws->swtag_req) {\t\t\t\t\t\t\\\n-\t\totx2_ssogws_swtag_wait((struct otx2_ssogws *)\t\t\\\n-\t\t\t\t &ws->ws_state[!ws->vws]);\t\\\n-\t\tws->swtag_req = 0;\t\t\t\t\t\\\n-\t\treturn 1;\t\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tgw = otx2_ssogws_dual_get_work(&ws->ws_state[ws->vws],\t\t\\\n-\t\t\t\t &ws->ws_state[!ws->vws], ev,\t\\\n-\t\t\t\t flags | NIX_RX_MULTI_SEG_F,\t\\\n-\t\t\t\t ws->lookup_mem,\t\t\t\\\n-\t\t\t\t ws->tstamp);\t\t\t\\\n-\tws->vws = !ws->vws;\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn gw;\t\t\t\t\t\t\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_dual_deq_seg_burst_ ##name(void *port,\t\t\t\\\n-\t\t\t\t struct rte_event ev[],\t\t\\\n-\t\t\t\t uint16_t nb_events,\t\t\\\n-\t\t\t\t uint64_t timeout_ticks)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn otx2_ssogws_dual_deq_seg_ ##name(port, ev,\t\t\\\n-\t\t\t\t\t\ttimeout_ticks);\t\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_dual_deq_seg_timeout_ ##name(void *port,\t\t\t\\\n-\t\t\t\t\t struct rte_event *ev,\t\t\\\n-\t\t\t\t\t uint64_t timeout_ticks)\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tstruct otx2_ssogws_dual *ws = port;\t\t\t\t\\\n-\tuint64_t iter;\t\t\t\t\t\t\t\\\n-\tuint8_t gw;\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tif (ws->swtag_req) {\t\t\t\t\t\t\\\n-\t\totx2_ssogws_swtag_wait((struct otx2_ssogws *)\t\t\\\n-\t\t\t\t &ws->ws_state[!ws->vws]);\t\\\n-\t\tws->swtag_req = 0;\t\t\t\t\t\\\n-\t\treturn 1;\t\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tgw = otx2_ssogws_dual_get_work(&ws->ws_state[ws->vws],\t\t\\\n-\t\t\t\t &ws->ws_state[!ws->vws], ev,\t\\\n-\t\t\t\t flags | NIX_RX_MULTI_SEG_F,\t\\\n-\t\t\t\t ws->lookup_mem,\t\t\t\\\n-\t\t\t\t ws->tstamp);\t\t\t\\\n-\tws->vws = !ws->vws;\t\t\t\t\t\t\\\n-\tfor (iter = 1; iter < timeout_ticks && (gw == 0); iter++) {\t\\\n-\t\tgw = otx2_ssogws_dual_get_work(&ws->ws_state[ws->vws],\t\\\n-\t\t\t\t\t &ws->ws_state[!ws->vws],\t\\\n-\t\t\t\t\t ev, flags |\t\t\\\n-\t\t\t\t\t NIX_RX_MULTI_SEG_F,\t\\\n-\t\t\t\t\t ws->lookup_mem,\t\t\\\n-\t\t\t\t\t ws->tstamp);\t\t\\\n-\t\tws->vws = !ws->vws;\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn gw;\t\t\t\t\t\t\t\\\n-}\t\t\t\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\t\\\n-otx2_ssogws_dual_deq_seg_timeout_burst_ ##name(void *port,\t\t\\\n-\t\t\t\t\t struct rte_event ev[],\t\\\n-\t\t\t\t\t uint16_t nb_events,\t\\\n-\t\t\t\t\t uint64_t timeout_ticks)\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\treturn otx2_ssogws_dual_deq_seg_timeout_ ##name(port, ev,\t\\\n-\t\t\t\t\t\t\ttimeout_ticks);\t\\\n-}\n-\n-SSO_RX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef R\n-\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\\\n-otx2_ssogws_dual_tx_adptr_enq_ ## name(void *port,\t\t\t\\\n-\t\t\t\t struct rte_event ev[],\t\t\\\n-\t\t\t\t uint16_t nb_events)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tstruct otx2_ssogws_dual *ws = port;\t\t\t\t\\\n-\tuint64_t cmd[sz];\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n-\treturn otx2_ssogws_event_tx(ws->base[!ws->vws], &ev[0],\t\t\\\n-\t\t\t\t\t cmd, (const uint64_t\t\t\\\n-\t\t\t\t\t (*)[RTE_MAX_QUEUES_PER_PORT])\t\\\n-\t\t\t\t\t &ws->tx_adptr_data, flags);\t\\\n-}\n-SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef T\n-\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-uint16_t __rte_hot\t\t\t\t\t\t\t\\\n-otx2_ssogws_dual_tx_adptr_enq_seg_ ## name(void *port,\t\t\t\\\n-\t\t\t\t\t struct rte_event ev[],\t\\\n-\t\t\t\t\t uint16_t nb_events)\t\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tuint64_t cmd[(sz) + NIX_TX_MSEG_SG_DWORDS - 2];\t\t\t\\\n-\tstruct otx2_ssogws_dual *ws = port;\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\tRTE_SET_USED(nb_events);\t\t\t\t\t\\\n-\treturn otx2_ssogws_event_tx(ws->base[!ws->vws], &ev[0],\t\t\\\n-\t\t\t\t\t cmd, (const uint64_t\t\t\\\n-\t\t\t\t\t (*)[RTE_MAX_QUEUES_PER_PORT])\t\\\n-\t\t\t\t\t &ws->tx_adptr_data,\t\t\\\n-\t\t\t\t\t (flags) | NIX_TX_MULTI_SEG_F);\\\n-}\n-SSO_TX_ADPTR_ENQ_FASTPATH_FUNC\n-#undef T\ndiff --git a/drivers/event/octeontx2/otx2_worker_dual.h b/drivers/event/octeontx2/otx2_worker_dual.h\ndeleted file mode 100644\nindex 36ae4dd88f..0000000000\n--- a/drivers/event/octeontx2/otx2_worker_dual.h\n+++ /dev/null\n@@ -1,110 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_WORKER_DUAL_H__\n-#define __OTX2_WORKER_DUAL_H__\n-\n-#include <rte_branch_prediction.h>\n-#include <rte_common.h>\n-\n-#include <otx2_common.h>\n-#include \"otx2_evdev.h\"\n-#include \"otx2_evdev_crypto_adptr_rx.h\"\n-\n-/* SSO Operations */\n-static __rte_always_inline uint16_t\n-otx2_ssogws_dual_get_work(struct otx2_ssogws_state *ws,\n-\t\t\t struct otx2_ssogws_state *ws_pair,\n-\t\t\t struct rte_event *ev, const uint32_t flags,\n-\t\t\t const void * const lookup_mem,\n-\t\t\t struct otx2_timesync_info * const tstamp)\n-{\n-\tconst uint64_t set_gw = BIT_ULL(16) | 1;\n-\tunion otx2_sso_event event;\n-\tuint64_t tstamp_ptr;\n-\tuint64_t get_work1;\n-\tuint64_t mbuf;\n-\n-\tif (flags & NIX_RX_OFFLOAD_PTYPE_F)\n-\t\trte_prefetch_non_temporal(lookup_mem);\n-#ifdef RTE_ARCH_ARM64\n-\tasm volatile(\n-\t\t\t\"rty%=:\t \\n\"\n-\t\t\t\" ldr %[tag], [%[tag_loc]] \\n\"\n-\t\t\t\" ldr %[wqp], [%[wqp_loc]] \\n\"\n-\t\t\t\" tbnz %[tag], 63, rty%= \\n\"\n-\t\t\t\"done%=: str %[gw], [%[pong]] \\n\"\n-\t\t\t\" dmb ld \\n\"\n-\t\t\t\" prfm pldl1keep, [%[wqp], #8]\\n\"\n-\t\t\t\" sub %[mbuf], %[wqp], #0x80 \\n\"\n-\t\t\t\" prfm pldl1keep, [%[mbuf]] \\n\"\n-\t\t\t: [tag] \"=&r\" (event.get_work0),\n-\t\t\t [wqp] \"=&r\" (get_work1),\n-\t\t\t [mbuf] \"=&r\" (mbuf)\n-\t\t\t: [tag_loc] \"r\" (ws->tag_op),\n-\t\t\t [wqp_loc] \"r\" (ws->wqp_op),\n-\t\t\t [gw] \"r\" (set_gw),\n-\t\t\t [pong] \"r\" (ws_pair->getwrk_op)\n-\t\t\t);\n-#else\n-\tevent.get_work0 = otx2_read64(ws->tag_op);\n-\twhile ((BIT_ULL(63)) & event.get_work0)\n-\t\tevent.get_work0 = otx2_read64(ws->tag_op);\n-\tget_work1 = otx2_read64(ws->wqp_op);\n-\totx2_write64(set_gw, ws_pair->getwrk_op);\n-\n-\trte_prefetch0((const void *)get_work1);\n-\tmbuf = (uint64_t)((char *)get_work1 - sizeof(struct rte_mbuf));\n-\trte_prefetch0((const void *)mbuf);\n-#endif\n-\tevent.get_work0 = (event.get_work0 & (0x3ull << 32)) << 6 |\n-\t\t(event.get_work0 & (0x3FFull << 36)) << 4 |\n-\t\t(event.get_work0 & 0xffffffff);\n-\n-\tif (event.sched_type != SSO_TT_EMPTY) {\n-\t\tif ((flags & NIX_RX_OFFLOAD_SECURITY_F) &&\n-\t\t (event.event_type == RTE_EVENT_TYPE_CRYPTODEV)) {\n-\t\t\tget_work1 = otx2_handle_crypto_event(get_work1);\n-\t\t} else if (event.event_type == RTE_EVENT_TYPE_ETHDEV) {\n-\t\t\tuint8_t port = event.sub_event_type;\n-\n-\t\t\tevent.sub_event_type = 0;\n-\t\t\totx2_wqe_to_mbuf(get_work1, mbuf, port,\n-\t\t\t\t\t event.flow_id, flags, lookup_mem);\n-\t\t\t/* Extracting tstamp, if PTP enabled. CGX will prepend\n-\t\t\t * the timestamp at starting of packet data and it can\n-\t\t\t * be derieved from WQE 9 dword which corresponds to SG\n-\t\t\t * iova.\n-\t\t\t * rte_pktmbuf_mtod_offset can be used for this purpose\n-\t\t\t * but it brings down the performance as it reads\n-\t\t\t * mbuf->buf_addr which is not part of cache in general\n-\t\t\t * fast path.\n-\t\t\t */\n-\t\t\ttstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *)\n-\t\t\t\t\t\t get_work1) +\n-\t\t\t\t\t\t OTX2_SSO_WQE_SG_PTR);\n-\t\t\totx2_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp,\n-\t\t\t\t\t\tflags, (uint64_t *)tstamp_ptr);\n-\t\t\tget_work1 = mbuf;\n-\t\t}\n-\t}\n-\n-\tev->event = event.get_work0;\n-\tev->u64 = get_work1;\n-\n-\treturn !!get_work1;\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_dual_add_work(struct otx2_ssogws_dual *ws, const uint64_t event_ptr,\n-\t\t\t const uint32_t tag, const uint8_t new_tt,\n-\t\t\t const uint16_t grp)\n-{\n-\tuint64_t add_work0;\n-\n-\tadd_work0 = tag | ((uint64_t)(new_tt) << 32);\n-\totx2_store_pair(add_work0, event_ptr, ws->grps_base[grp]);\n-}\n-\n-#endif\ndiff --git a/drivers/event/octeontx2/version.map b/drivers/event/octeontx2/version.map\ndeleted file mode 100644\nindex c2e0723b4c..0000000000\n--- a/drivers/event/octeontx2/version.map\n+++ /dev/null\n@@ -1,3 +0,0 @@\n-DPDK_22 {\n-\tlocal: *;\n-};\ndiff --git a/drivers/mempool/cnxk/cnxk_mempool.c b/drivers/mempool/cnxk/cnxk_mempool.c\nindex 57be33b862..ea473552dd 100644\n--- a/drivers/mempool/cnxk/cnxk_mempool.c\n+++ b/drivers/mempool/cnxk/cnxk_mempool.c\n@@ -161,48 +161,20 @@ npa_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n }\n \n static const struct rte_pci_id npa_pci_map[] = {\n-\t{\n-\t\t.class_id = RTE_CLASS_ANY_ID,\n-\t\t.vendor_id = PCI_VENDOR_ID_CAVIUM,\n-\t\t.device_id = PCI_DEVID_CNXK_RVU_NPA_PF,\n-\t\t.subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,\n-\t\t.subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KA,\n-\t},\n-\t{\n-\t\t.class_id = RTE_CLASS_ANY_ID,\n-\t\t.vendor_id = PCI_VENDOR_ID_CAVIUM,\n-\t\t.device_id = PCI_DEVID_CNXK_RVU_NPA_PF,\n-\t\t.subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,\n-\t\t.subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KAS,\n-\t},\n-\t{\n-\t\t.class_id = RTE_CLASS_ANY_ID,\n-\t\t.vendor_id = PCI_VENDOR_ID_CAVIUM,\n-\t\t.device_id = PCI_DEVID_CNXK_RVU_NPA_PF,\n-\t\t.subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,\n-\t\t.subsystem_device_id = PCI_SUBSYSTEM_DEVID_CNF10KA,\n-\t},\n-\t{\n-\t\t.class_id = RTE_CLASS_ANY_ID,\n-\t\t.vendor_id = PCI_VENDOR_ID_CAVIUM,\n-\t\t.device_id = PCI_DEVID_CNXK_RVU_NPA_VF,\n-\t\t.subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,\n-\t\t.subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KA,\n-\t},\n-\t{\n-\t\t.class_id = RTE_CLASS_ANY_ID,\n-\t\t.vendor_id = PCI_VENDOR_ID_CAVIUM,\n-\t\t.device_id = PCI_DEVID_CNXK_RVU_NPA_VF,\n-\t\t.subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,\n-\t\t.subsystem_device_id = PCI_SUBSYSTEM_DEVID_CN10KAS,\n-\t},\n-\t{\n-\t\t.class_id = RTE_CLASS_ANY_ID,\n-\t\t.vendor_id = PCI_VENDOR_ID_CAVIUM,\n-\t\t.device_id = PCI_DEVID_CNXK_RVU_NPA_VF,\n-\t\t.subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,\n-\t\t.subsystem_device_id = PCI_SUBSYSTEM_DEVID_CNF10KA,\n-\t},\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_NPA_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_NPA_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_NPA_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_NPA_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_NPA_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_NPA_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_NPA_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_NPA_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_NPA_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_NPA_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_NPA_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_NPA_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_NPA_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_NPA_VF),\n \t{\n \t\t.vendor_id = 0,\n \t},\ndiff --git a/drivers/mempool/meson.build b/drivers/mempool/meson.build\nindex d295263b87..dc88812585 100644\n--- a/drivers/mempool/meson.build\n+++ b/drivers/mempool/meson.build\n@@ -7,7 +7,6 @@ drivers = [\n 'dpaa',\n 'dpaa2',\n 'octeontx',\n- 'octeontx2',\n 'ring',\n 'stack',\n ]\ndiff --git a/drivers/mempool/octeontx2/meson.build b/drivers/mempool/octeontx2/meson.build\ndeleted file mode 100644\nindex a4bea6d364..0000000000\n--- a/drivers/mempool/octeontx2/meson.build\n+++ /dev/null\n@@ -1,18 +0,0 @@\n-# SPDX-License-Identifier: BSD-3-Clause\n-# Copyright(C) 2019 Marvell International Ltd.\n-#\n-\n-if not is_linux or not dpdk_conf.get('RTE_ARCH_64')\n- build = false\n- reason = 'only supported on 64-bit Linux'\n- subdir_done()\n-endif\n-\n-sources = files(\n- 'otx2_mempool.c',\n- 'otx2_mempool_debug.c',\n- 'otx2_mempool_irq.c',\n- 'otx2_mempool_ops.c',\n-)\n-\n-deps += ['eal', 'mbuf', 'kvargs', 'bus_pci', 'common_octeontx2', 'mempool']\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool.c b/drivers/mempool/octeontx2/otx2_mempool.c\ndeleted file mode 100644\nindex f63dc06ef2..0000000000\n--- a/drivers/mempool/octeontx2/otx2_mempool.c\n+++ /dev/null\n@@ -1,457 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_atomic.h>\n-#include <rte_bus_pci.h>\n-#include <rte_common.h>\n-#include <rte_eal.h>\n-#include <rte_io.h>\n-#include <rte_kvargs.h>\n-#include <rte_malloc.h>\n-#include <rte_mbuf_pool_ops.h>\n-#include <rte_pci.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_dev.h\"\n-#include \"otx2_mempool.h\"\n-\n-#define OTX2_NPA_DEV_NAME\tRTE_STR(otx2_npa_dev_)\n-#define OTX2_NPA_DEV_NAME_LEN\t(sizeof(OTX2_NPA_DEV_NAME) + PCI_PRI_STR_SIZE)\n-\n-static inline int\n-npa_lf_alloc(struct otx2_npa_lf *lf)\n-{\n-\tstruct otx2_mbox *mbox = lf->mbox;\n-\tstruct npa_lf_alloc_req *req;\n-\tstruct npa_lf_alloc_rsp *rsp;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_npa_lf_alloc(mbox);\n-\treq->aura_sz = lf->aura_sz;\n-\treq->nr_pools = lf->nr_pools;\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn NPA_LF_ERR_ALLOC;\n-\n-\tlf->stack_pg_ptrs = rsp->stack_pg_ptrs;\n-\tlf->stack_pg_bytes = rsp->stack_pg_bytes;\n-\tlf->qints = rsp->qints;\n-\n-\treturn 0;\n-}\n-\n-static int\n-npa_lf_free(struct otx2_mbox *mbox)\n-{\n-\totx2_mbox_alloc_msg_npa_lf_free(mbox);\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static int\n-npa_lf_init(struct otx2_npa_lf *lf, uintptr_t base, uint8_t aura_sz,\n-\t uint32_t nr_pools, struct otx2_mbox *mbox)\n-{\n-\tuint32_t i, bmp_sz;\n-\tint rc;\n-\n-\t/* Sanity checks */\n-\tif (!lf || !base || !mbox || !nr_pools)\n-\t\treturn NPA_LF_ERR_PARAM;\n-\n-\tif (base & AURA_ID_MASK)\n-\t\treturn NPA_LF_ERR_BASE_INVALID;\n-\n-\tif (aura_sz == NPA_AURA_SZ_0 || aura_sz >= NPA_AURA_SZ_MAX)\n-\t\treturn NPA_LF_ERR_PARAM;\n-\n-\tmemset(lf, 0x0, sizeof(*lf));\n-\tlf->base = base;\n-\tlf->aura_sz = aura_sz;\n-\tlf->nr_pools = nr_pools;\n-\tlf->mbox = mbox;\n-\n-\trc = npa_lf_alloc(lf);\n-\tif (rc)\n-\t\tgoto exit;\n-\n-\tbmp_sz = rte_bitmap_get_memory_footprint(nr_pools);\n-\n-\t/* Allocate memory for bitmap */\n-\tlf->npa_bmp_mem = rte_zmalloc(\"npa_bmp_mem\", bmp_sz,\n-\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n-\tif (lf->npa_bmp_mem == NULL) {\n-\t\trc = -ENOMEM;\n-\t\tgoto lf_free;\n-\t}\n-\n-\t/* Initialize pool resource bitmap array */\n-\tlf->npa_bmp = rte_bitmap_init(nr_pools, lf->npa_bmp_mem, bmp_sz);\n-\tif (lf->npa_bmp == NULL) {\n-\t\trc = -EINVAL;\n-\t\tgoto bmap_mem_free;\n-\t}\n-\n-\t/* Mark all pools available */\n-\tfor (i = 0; i < nr_pools; i++)\n-\t\trte_bitmap_set(lf->npa_bmp, i);\n-\n-\t/* Allocate memory for qint context */\n-\tlf->npa_qint_mem = rte_zmalloc(\"npa_qint_mem\",\n-\t\t\tsizeof(struct otx2_npa_qint) * nr_pools, 0);\n-\tif (lf->npa_qint_mem == NULL) {\n-\t\trc = -ENOMEM;\n-\t\tgoto bmap_free;\n-\t}\n-\n-\t/* Allocate memory for nap_aura_lim memory */\n-\tlf->aura_lim = rte_zmalloc(\"npa_aura_lim_mem\",\n-\t\t\tsizeof(struct npa_aura_lim) * nr_pools, 0);\n-\tif (lf->aura_lim == NULL) {\n-\t\trc = -ENOMEM;\n-\t\tgoto qint_free;\n-\t}\n-\n-\t/* Init aura start & end limits */\n-\tfor (i = 0; i < nr_pools; i++) {\n-\t\tlf->aura_lim[i].ptr_start = UINT64_MAX;\n-\t\tlf->aura_lim[i].ptr_end = 0x0ull;\n-\t}\n-\n-\treturn 0;\n-\n-qint_free:\n-\trte_free(lf->npa_qint_mem);\n-bmap_free:\n-\trte_bitmap_free(lf->npa_bmp);\n-bmap_mem_free:\n-\trte_free(lf->npa_bmp_mem);\n-lf_free:\n-\tnpa_lf_free(lf->mbox);\n-exit:\n-\treturn rc;\n-}\n-\n-static int\n-npa_lf_fini(struct otx2_npa_lf *lf)\n-{\n-\tif (!lf)\n-\t\treturn NPA_LF_ERR_PARAM;\n-\n-\trte_free(lf->aura_lim);\n-\trte_free(lf->npa_qint_mem);\n-\trte_bitmap_free(lf->npa_bmp);\n-\trte_free(lf->npa_bmp_mem);\n-\n-\treturn npa_lf_free(lf->mbox);\n-\n-}\n-\n-static inline uint32_t\n-otx2_aura_size_to_u32(uint8_t val)\n-{\n-\tif (val == NPA_AURA_SZ_0)\n-\t\treturn 128;\n-\tif (val >= NPA_AURA_SZ_MAX)\n-\t\treturn BIT_ULL(20);\n-\n-\treturn 1 << (val + 6);\n-}\n-\n-static int\n-parse_max_pools(const char *key, const char *value, void *extra_args)\n-{\n-\tRTE_SET_USED(key);\n-\tuint32_t val;\n-\n-\tval = atoi(value);\n-\tif (val < otx2_aura_size_to_u32(NPA_AURA_SZ_128))\n-\t\tval = 128;\n-\tif (val > otx2_aura_size_to_u32(NPA_AURA_SZ_1M))\n-\t\tval = BIT_ULL(20);\n-\n-\t*(uint8_t *)extra_args = rte_log2_u32(val) - 6;\n-\treturn 0;\n-}\n-\n-#define OTX2_MAX_POOLS \"max_pools\"\n-\n-static uint8_t\n-otx2_parse_aura_size(struct rte_devargs *devargs)\n-{\n-\tuint8_t aura_sz = NPA_AURA_SZ_128;\n-\tstruct rte_kvargs *kvlist;\n-\n-\tif (devargs == NULL)\n-\t\tgoto exit;\n-\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n-\tif (kvlist == NULL)\n-\t\tgoto exit;\n-\n-\trte_kvargs_process(kvlist, OTX2_MAX_POOLS, &parse_max_pools, &aura_sz);\n-\totx2_parse_common_devargs(kvlist);\n-\trte_kvargs_free(kvlist);\n-exit:\n-\treturn aura_sz;\n-}\n-\n-static inline int\n-npa_lf_attach(struct otx2_mbox *mbox)\n-{\n-\tstruct rsrc_attach_req *req;\n-\n-\treq = otx2_mbox_alloc_msg_attach_resources(mbox);\n-\treq->npalf = true;\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static inline int\n-npa_lf_detach(struct otx2_mbox *mbox)\n-{\n-\tstruct rsrc_detach_req *req;\n-\n-\treq = otx2_mbox_alloc_msg_detach_resources(mbox);\n-\treq->npalf = true;\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static inline int\n-npa_lf_get_msix_offset(struct otx2_mbox *mbox, uint16_t *npa_msixoff)\n-{\n-\tstruct msix_offset_rsp *msix_rsp;\n-\tint rc;\n-\n-\t/* Get NPA and NIX MSIX vector offsets */\n-\totx2_mbox_alloc_msg_msix_offset(mbox);\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);\n-\n-\t*npa_msixoff = msix_rsp->npa_msixoff;\n-\n-\treturn rc;\n-}\n-\n-/**\n- * @internal\n- * Finalize NPA LF.\n- */\n-int\n-otx2_npa_lf_fini(void)\n-{\n-\tstruct otx2_idev_cfg *idev;\n-\tint rc = 0;\n-\n-\tidev = otx2_intra_dev_get_cfg();\n-\tif (idev == NULL)\n-\t\treturn -ENOMEM;\n-\n-\tif (rte_atomic16_add_return(&idev->npa_refcnt, -1) == 0) {\n-\t\totx2_npa_unregister_irqs(idev->npa_lf);\n-\t\trc |= npa_lf_fini(idev->npa_lf);\n-\t\trc |= npa_lf_detach(idev->npa_lf->mbox);\n-\t\totx2_npa_set_defaults(idev);\n-\t}\n-\n-\treturn rc;\n-}\n-\n-/**\n- * @internal\n- * Initialize NPA LF.\n- */\n-int\n-otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n-{\n-\tstruct otx2_dev *dev = otx2_dev;\n-\tstruct otx2_idev_cfg *idev;\n-\tstruct otx2_npa_lf *lf;\n-\tuint16_t npa_msixoff;\n-\tuint32_t nr_pools;\n-\tuint8_t aura_sz;\n-\tint rc;\n-\n-\tidev = otx2_intra_dev_get_cfg();\n-\tif (idev == NULL)\n-\t\treturn -ENOMEM;\n-\n-\t/* Is NPA LF initialized by any another driver? */\n-\tif (rte_atomic16_add_return(&idev->npa_refcnt, 1) == 1) {\n-\n-\t\trc = npa_lf_attach(dev->mbox);\n-\t\tif (rc)\n-\t\t\tgoto fail;\n-\n-\t\trc = npa_lf_get_msix_offset(dev->mbox, &npa_msixoff);\n-\t\tif (rc)\n-\t\t\tgoto npa_detach;\n-\n-\t\taura_sz = otx2_parse_aura_size(pci_dev->device.devargs);\n-\t\tnr_pools = otx2_aura_size_to_u32(aura_sz);\n-\n-\t\tlf = &dev->npalf;\n-\t\trc = npa_lf_init(lf, dev->bar2 + (RVU_BLOCK_ADDR_NPA << 20),\n-\t\t\t\t\taura_sz, nr_pools, dev->mbox);\n-\n-\t\tif (rc)\n-\t\t\tgoto npa_detach;\n-\n-\t\tlf->pf_func = dev->pf_func;\n-\t\tlf->npa_msixoff = npa_msixoff;\n-\t\tlf->intr_handle = pci_dev->intr_handle;\n-\t\tlf->pci_dev = pci_dev;\n-\n-\t\tidev->npa_pf_func = dev->pf_func;\n-\t\tidev->npa_lf = lf;\n-\t\trte_smp_wmb();\n-\t\trc = otx2_npa_register_irqs(lf);\n-\t\tif (rc)\n-\t\t\tgoto npa_fini;\n-\n-\t\trte_mbuf_set_platform_mempool_ops(\"octeontx2_npa\");\n-\t\totx2_npa_dbg(\"npa_lf=%p pools=%d sz=%d pf_func=0x%x msix=0x%x\",\n-\t\t\t lf, nr_pools, aura_sz, lf->pf_func, npa_msixoff);\n-\t}\n-\n-\treturn 0;\n-\n-npa_fini:\n-\tnpa_lf_fini(idev->npa_lf);\n-npa_detach:\n-\tnpa_lf_detach(dev->mbox);\n-fail:\n-\trte_atomic16_dec(&idev->npa_refcnt);\n-\treturn rc;\n-}\n-\n-static inline char*\n-otx2_npa_dev_to_name(struct rte_pci_device *pci_dev, char *name)\n-{\n-\tsnprintf(name, OTX2_NPA_DEV_NAME_LEN,\n-\t\t OTX2_NPA_DEV_NAME PCI_PRI_FMT,\n-\t\t pci_dev->addr.domain, pci_dev->addr.bus,\n-\t\t pci_dev->addr.devid, pci_dev->addr.function);\n-\n-\treturn name;\n-}\n-\n-static int\n-otx2_npa_init(struct rte_pci_device *pci_dev)\n-{\n-\tchar name[OTX2_NPA_DEV_NAME_LEN];\n-\tconst struct rte_memzone *mz;\n-\tstruct otx2_dev *dev;\n-\tint rc = -ENOMEM;\n-\n-\tmz = rte_memzone_reserve_aligned(otx2_npa_dev_to_name(pci_dev, name),\n-\t\t\t\t\t sizeof(*dev), SOCKET_ID_ANY,\n-\t\t\t\t\t 0, OTX2_ALIGN);\n-\tif (mz == NULL)\n-\t\tgoto error;\n-\n-\tdev = mz->addr;\n-\n-\t/* Initialize the base otx2_dev object */\n-\trc = otx2_dev_init(pci_dev, dev);\n-\tif (rc)\n-\t\tgoto malloc_fail;\n-\n-\t/* Grab the NPA LF if required */\n-\trc = otx2_npa_lf_init(pci_dev, dev);\n-\tif (rc)\n-\t\tgoto dev_uninit;\n-\n-\tdev->drv_inited = true;\n-\treturn 0;\n-\n-dev_uninit:\n-\totx2_npa_lf_fini();\n-\totx2_dev_fini(pci_dev, dev);\n-malloc_fail:\n-\trte_memzone_free(mz);\n-error:\n-\totx2_err(\"Failed to initialize npa device rc=%d\", rc);\n-\treturn rc;\n-}\n-\n-static int\n-otx2_npa_fini(struct rte_pci_device *pci_dev)\n-{\n-\tchar name[OTX2_NPA_DEV_NAME_LEN];\n-\tconst struct rte_memzone *mz;\n-\tstruct otx2_dev *dev;\n-\n-\tmz = rte_memzone_lookup(otx2_npa_dev_to_name(pci_dev, name));\n-\tif (mz == NULL)\n-\t\treturn -EINVAL;\n-\n-\tdev = mz->addr;\n-\tif (!dev->drv_inited)\n-\t\tgoto dev_fini;\n-\n-\tdev->drv_inited = false;\n-\totx2_npa_lf_fini();\n-\n-dev_fini:\n-\tif (otx2_npa_lf_active(dev)) {\n-\t\totx2_info(\"%s: common resource in use by other devices\",\n-\t\t\t pci_dev->name);\n-\t\treturn -EAGAIN;\n-\t}\n-\n-\totx2_dev_fini(pci_dev, dev);\n-\trte_memzone_free(mz);\n-\n-\treturn 0;\n-}\n-\n-static int\n-npa_remove(struct rte_pci_device *pci_dev)\n-{\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn 0;\n-\n-\treturn otx2_npa_fini(pci_dev);\n-}\n-\n-static int\n-npa_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n-{\n-\tRTE_SET_USED(pci_drv);\n-\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn 0;\n-\n-\treturn otx2_npa_init(pci_dev);\n-}\n-\n-static const struct rte_pci_id pci_npa_map[] = {\n-\t{\n-\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n-\t\t\t\t\tPCI_DEVID_OCTEONTX2_RVU_NPA_PF)\n-\t},\n-\t{\n-\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n-\t\t\t\t\tPCI_DEVID_OCTEONTX2_RVU_NPA_VF)\n-\t},\n-\t{\n-\t\t.vendor_id = 0,\n-\t},\n-};\n-\n-static struct rte_pci_driver pci_npa = {\n-\t.id_table = pci_npa_map,\n-\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,\n-\t.probe = npa_probe,\n-\t.remove = npa_remove,\n-};\n-\n-RTE_PMD_REGISTER_PCI(mempool_octeontx2, pci_npa);\n-RTE_PMD_REGISTER_PCI_TABLE(mempool_octeontx2, pci_npa_map);\n-RTE_PMD_REGISTER_KMOD_DEP(mempool_octeontx2, \"vfio-pci\");\n-RTE_PMD_REGISTER_PARAM_STRING(mempool_octeontx2,\n-\t\t\t OTX2_MAX_POOLS \"=<128-1048576>\"\n-\t\t\t OTX2_NPA_LOCK_MASK \"=<1-65535>\");\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool.h b/drivers/mempool/octeontx2/otx2_mempool.h\ndeleted file mode 100644\nindex 8aa548248d..0000000000\n--- a/drivers/mempool/octeontx2/otx2_mempool.h\n+++ /dev/null\n@@ -1,221 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_MEMPOOL_H__\n-#define __OTX2_MEMPOOL_H__\n-\n-#include <rte_bitmap.h>\n-#include <rte_bus_pci.h>\n-#include <rte_devargs.h>\n-#include <rte_mempool.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_mbox.h\"\n-\n-enum npa_lf_status {\n-\tNPA_LF_ERR_PARAM\t = -512,\n-\tNPA_LF_ERR_ALLOC\t = -513,\n-\tNPA_LF_ERR_INVALID_BLOCK_SZ = -514,\n-\tNPA_LF_ERR_AURA_ID_ALLOC = -515,\n-\tNPA_LF_ERR_AURA_POOL_INIT = -516,\n-\tNPA_LF_ERR_AURA_POOL_FINI = -517,\n-\tNPA_LF_ERR_BASE_INVALID = -518,\n-};\n-\n-struct otx2_npa_lf;\n-struct otx2_npa_qint {\n-\tstruct otx2_npa_lf *lf;\n-\tuint8_t qintx;\n-};\n-\n-struct npa_aura_lim {\n-\tuint64_t ptr_start;\n-\tuint64_t ptr_end;\n-};\n-\n-struct otx2_npa_lf {\n-\tuint16_t qints;\n-\tuintptr_t base;\n-\tuint8_t aura_sz;\n-\tuint16_t pf_func;\n-\tuint32_t nr_pools;\n-\tvoid *npa_bmp_mem;\n-\tvoid *npa_qint_mem;\n-\tuint16_t npa_msixoff;\n-\tstruct otx2_mbox *mbox;\n-\tuint32_t stack_pg_ptrs;\n-\tuint32_t stack_pg_bytes;\n-\tstruct rte_bitmap *npa_bmp;\n-\tstruct npa_aura_lim *aura_lim;\n-\tstruct rte_pci_device *pci_dev;\n-\tstruct rte_intr_handle *intr_handle;\n-};\n-\n-#define AURA_ID_MASK (BIT_ULL(16) - 1)\n-\n-/*\n- * Generate 64bit handle to have optimized alloc and free aura operation.\n- * 0 - AURA_ID_MASK for storing the aura_id.\n- * AURA_ID_MASK+1 - (2^64 - 1) for storing the lf base address.\n- * This scheme is valid when OS can give AURA_ID_MASK\n- * aligned address for lf base address.\n- */\n-static inline uint64_t\n-npa_lf_aura_handle_gen(uint32_t aura_id, uintptr_t addr)\n-{\n-\tuint64_t val;\n-\n-\tval = aura_id & AURA_ID_MASK;\n-\treturn (uint64_t)addr | val;\n-}\n-\n-static inline uint64_t\n-npa_lf_aura_handle_to_aura(uint64_t aura_handle)\n-{\n-\treturn aura_handle & AURA_ID_MASK;\n-}\n-\n-static inline uintptr_t\n-npa_lf_aura_handle_to_base(uint64_t aura_handle)\n-{\n-\treturn (uintptr_t)(aura_handle & ~AURA_ID_MASK);\n-}\n-\n-static inline uint64_t\n-npa_lf_aura_op_alloc(uint64_t aura_handle, const int drop)\n-{\n-\tuint64_t wdata = npa_lf_aura_handle_to_aura(aura_handle);\n-\n-\tif (drop)\n-\t\twdata |= BIT_ULL(63); /* DROP */\n-\n-\treturn otx2_atomic64_add_nosync(wdata,\n-\t\t(int64_t *)(npa_lf_aura_handle_to_base(aura_handle) +\n-\t\tNPA_LF_AURA_OP_ALLOCX(0)));\n-}\n-\n-static inline void\n-npa_lf_aura_op_free(uint64_t aura_handle, const int fabs, uint64_t iova)\n-{\n-\tuint64_t reg = npa_lf_aura_handle_to_aura(aura_handle);\n-\n-\tif (fabs)\n-\t\treg |= BIT_ULL(63); /* FABS */\n-\n-\totx2_store_pair(iova, reg,\n-\t\tnpa_lf_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_FREE0);\n-}\n-\n-static inline uint64_t\n-npa_lf_aura_op_cnt_get(uint64_t aura_handle)\n-{\n-\tuint64_t wdata;\n-\tuint64_t reg;\n-\n-\twdata = npa_lf_aura_handle_to_aura(aura_handle) << 44;\n-\n-\treg = otx2_atomic64_add_nosync(wdata,\n-\t\t\t(int64_t *)(npa_lf_aura_handle_to_base(aura_handle) +\n-\t\t\t NPA_LF_AURA_OP_CNT));\n-\n-\tif (reg & BIT_ULL(42) /* OP_ERR */)\n-\t\treturn 0;\n-\telse\n-\t\treturn reg & 0xFFFFFFFFF;\n-}\n-\n-static inline void\n-npa_lf_aura_op_cnt_set(uint64_t aura_handle, const int sign, uint64_t count)\n-{\n-\tuint64_t reg = count & (BIT_ULL(36) - 1);\n-\n-\tif (sign)\n-\t\treg |= BIT_ULL(43); /* CNT_ADD */\n-\n-\treg |= (npa_lf_aura_handle_to_aura(aura_handle) << 44);\n-\n-\totx2_write64(reg,\n-\t\tnpa_lf_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_CNT);\n-}\n-\n-static inline uint64_t\n-npa_lf_aura_op_limit_get(uint64_t aura_handle)\n-{\n-\tuint64_t wdata;\n-\tuint64_t reg;\n-\n-\twdata = npa_lf_aura_handle_to_aura(aura_handle) << 44;\n-\n-\treg = otx2_atomic64_add_nosync(wdata,\n-\t\t\t(int64_t *)(npa_lf_aura_handle_to_base(aura_handle) +\n-\t\t\t NPA_LF_AURA_OP_LIMIT));\n-\n-\tif (reg & BIT_ULL(42) /* OP_ERR */)\n-\t\treturn 0;\n-\telse\n-\t\treturn reg & 0xFFFFFFFFF;\n-}\n-\n-static inline void\n-npa_lf_aura_op_limit_set(uint64_t aura_handle, uint64_t limit)\n-{\n-\tuint64_t reg = limit & (BIT_ULL(36) - 1);\n-\n-\treg |= (npa_lf_aura_handle_to_aura(aura_handle) << 44);\n-\n-\totx2_write64(reg,\n-\t\tnpa_lf_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_LIMIT);\n-}\n-\n-static inline uint64_t\n-npa_lf_aura_op_available(uint64_t aura_handle)\n-{\n-\tuint64_t wdata;\n-\tuint64_t reg;\n-\n-\twdata = npa_lf_aura_handle_to_aura(aura_handle) << 44;\n-\n-\treg = otx2_atomic64_add_nosync(wdata,\n-\t\t\t (int64_t *)(npa_lf_aura_handle_to_base(\n-\t\t\t aura_handle) + NPA_LF_POOL_OP_AVAILABLE));\n-\n-\tif (reg & BIT_ULL(42) /* OP_ERR */)\n-\t\treturn 0;\n-\telse\n-\t\treturn reg & 0xFFFFFFFFF;\n-}\n-\n-static inline void\n-npa_lf_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova,\n-\t\t\t\tuint64_t end_iova)\n-{\n-\tuint64_t reg = npa_lf_aura_handle_to_aura(aura_handle);\n-\tstruct otx2_npa_lf *lf = otx2_npa_lf_obj_get();\n-\tstruct npa_aura_lim *lim = lf->aura_lim;\n-\n-\tlim[reg].ptr_start = RTE_MIN(lim[reg].ptr_start, start_iova);\n-\tlim[reg].ptr_end = RTE_MAX(lim[reg].ptr_end, end_iova);\n-\n-\totx2_store_pair(lim[reg].ptr_start, reg,\n-\t\t\tnpa_lf_aura_handle_to_base(aura_handle) +\n-\t\t\tNPA_LF_POOL_OP_PTR_START0);\n-\totx2_store_pair(lim[reg].ptr_end, reg,\n-\t\t\tnpa_lf_aura_handle_to_base(aura_handle) +\n-\t\t\tNPA_LF_POOL_OP_PTR_END0);\n-}\n-\n-/* NPA LF */\n-__rte_internal\n-int otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev);\n-__rte_internal\n-int otx2_npa_lf_fini(void);\n-\n-/* IRQ */\n-int otx2_npa_register_irqs(struct otx2_npa_lf *lf);\n-void otx2_npa_unregister_irqs(struct otx2_npa_lf *lf);\n-\n-/* Debug */\n-int otx2_mempool_ctx_dump(struct otx2_npa_lf *lf);\n-\n-#endif /* __OTX2_MEMPOOL_H__ */\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool_debug.c b/drivers/mempool/octeontx2/otx2_mempool_debug.c\ndeleted file mode 100644\nindex 279ea2e25f..0000000000\n--- a/drivers/mempool/octeontx2/otx2_mempool_debug.c\n+++ /dev/null\n@@ -1,135 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_mempool.h\"\n-\n-#define npa_dump(fmt, ...) fprintf(stderr, fmt \"\\n\", ##__VA_ARGS__)\n-\n-static inline void\n-npa_lf_pool_dump(__otx2_io struct npa_pool_s *pool)\n-{\n-\tnpa_dump(\"W0: Stack base\\t\\t0x%\"PRIx64\"\", pool->stack_base);\n-\tnpa_dump(\"W1: ena \\t\\t%d\\nW1: nat_align \\t\\t%d\\nW1: stack_caching \\t%d\",\n-\t\tpool->ena, pool->nat_align, pool->stack_caching);\n-\tnpa_dump(\"W1: stack_way_mask\\t%d\\nW1: buf_offset\\t\\t%d\",\n-\t\tpool->stack_way_mask, pool->buf_offset);\n-\tnpa_dump(\"W1: buf_size \\t\\t%d\", pool->buf_size);\n-\n-\tnpa_dump(\"W2: stack_max_pages \\t%d\\nW2: stack_pages\\t\\t%d\",\n-\t\tpool->stack_max_pages, pool->stack_pages);\n-\n-\tnpa_dump(\"W3: op_pc \\t\\t0x%\"PRIx64\"\", (uint64_t)pool->op_pc);\n-\n-\tnpa_dump(\"W4: stack_offset\\t%d\\nW4: shift\\t\\t%d\\nW4: avg_level\\t\\t%d\",\n-\t\tpool->stack_offset, pool->shift, pool->avg_level);\n-\tnpa_dump(\"W4: avg_con \\t\\t%d\\nW4: fc_ena\\t\\t%d\\nW4: fc_stype\\t\\t%d\",\n-\t\tpool->avg_con, pool->fc_ena, pool->fc_stype);\n-\tnpa_dump(\"W4: fc_hyst_bits\\t%d\\nW4: fc_up_crossing\\t%d\",\n-\t\tpool->fc_hyst_bits, pool->fc_up_crossing);\n-\tnpa_dump(\"W4: update_time\\t\\t%d\\n\", pool->update_time);\n-\n-\tnpa_dump(\"W5: fc_addr\\t\\t0x%\"PRIx64\"\\n\", pool->fc_addr);\n-\n-\tnpa_dump(\"W6: ptr_start\\t\\t0x%\"PRIx64\"\\n\", pool->ptr_start);\n-\n-\tnpa_dump(\"W7: ptr_end\\t\\t0x%\"PRIx64\"\\n\", pool->ptr_end);\n-\tnpa_dump(\"W8: err_int\\t\\t%d\\nW8: err_int_ena\\t\\t%d\",\n-\t\tpool->err_int, pool->err_int_ena);\n-\tnpa_dump(\"W8: thresh_int\\t\\t%d\", pool->thresh_int);\n-\n-\tnpa_dump(\"W8: thresh_int_ena\\t%d\\nW8: thresh_up\\t\\t%d\",\n-\t\tpool->thresh_int_ena, pool->thresh_up);\n-\tnpa_dump(\"W8: thresh_qint_idx\\t%d\\nW8: err_qint_idx\\t%d\",\n-\t\tpool->thresh_qint_idx, pool->err_qint_idx);\n-}\n-\n-static inline void\n-npa_lf_aura_dump(__otx2_io struct npa_aura_s *aura)\n-{\n-\tnpa_dump(\"W0: Pool addr\\t\\t0x%\"PRIx64\"\\n\", aura->pool_addr);\n-\n-\tnpa_dump(\"W1: ena\\t\\t\\t%d\\nW1: pool caching\\t%d\\nW1: pool way mask\\t%d\",\n-\t\taura->ena, aura->pool_caching, aura->pool_way_mask);\n-\tnpa_dump(\"W1: avg con\\t\\t%d\\nW1: pool drop ena\\t%d\",\n-\t\taura->avg_con, aura->pool_drop_ena);\n-\tnpa_dump(\"W1: aura drop ena\\t%d\", aura->aura_drop_ena);\n-\tnpa_dump(\"W1: bp_ena\\t\\t%d\\nW1: aura drop\\t\\t%d\\nW1: aura shift\\t\\t%d\",\n-\t\taura->bp_ena, aura->aura_drop, aura->shift);\n-\tnpa_dump(\"W1: avg_level\\t\\t%d\\n\", aura->avg_level);\n-\n-\tnpa_dump(\"W2: count\\t\\t%\"PRIx64\"\\nW2: nix0_bpid\\t\\t%d\",\n-\t\t(uint64_t)aura->count, aura->nix0_bpid);\n-\tnpa_dump(\"W2: nix1_bpid\\t\\t%d\", aura->nix1_bpid);\n-\n-\tnpa_dump(\"W3: limit\\t\\t%\"PRIx64\"\\nW3: bp\\t\\t\\t%d\\nW3: fc_ena\\t\\t%d\\n\",\n-\t\t(uint64_t)aura->limit, aura->bp, aura->fc_ena);\n-\tnpa_dump(\"W3: fc_up_crossing\\t%d\\nW3: fc_stype\\t\\t%d\",\n-\t\taura->fc_up_crossing, aura->fc_stype);\n-\n-\tnpa_dump(\"W3: fc_hyst_bits\\t%d\", aura->fc_hyst_bits);\n-\n-\tnpa_dump(\"W4: fc_addr\\t\\t0x%\"PRIx64\"\\n\", aura->fc_addr);\n-\n-\tnpa_dump(\"W5: pool_drop\\t\\t%d\\nW5: update_time\\t\\t%d\",\n-\t\taura->pool_drop, aura->update_time);\n-\tnpa_dump(\"W5: err_int\\t\\t%d\", aura->err_int);\n-\tnpa_dump(\"W5: err_int_ena\\t\\t%d\\nW5: thresh_int\\t\\t%d\",\n-\t\taura->err_int_ena, aura->thresh_int);\n-\tnpa_dump(\"W5: thresh_int_ena\\t%d\", aura->thresh_int_ena);\n-\n-\tnpa_dump(\"W5: thresh_up\\t\\t%d\\nW5: thresh_qint_idx\\t%d\",\n-\t\taura->thresh_up, aura->thresh_qint_idx);\n-\tnpa_dump(\"W5: err_qint_idx\\t%d\", aura->err_qint_idx);\n-\n-\tnpa_dump(\"W6: thresh\\t\\t%\"PRIx64\"\\n\", (uint64_t)aura->thresh);\n-}\n-\n-int\n-otx2_mempool_ctx_dump(struct otx2_npa_lf *lf)\n-{\n-\tstruct npa_aq_enq_req *aq;\n-\tstruct npa_aq_enq_rsp *rsp;\n-\tuint32_t q;\n-\tint rc = 0;\n-\n-\tfor (q = 0; q < lf->nr_pools; q++) {\n-\t\t/* Skip disabled POOL */\n-\t\tif (rte_bitmap_get(lf->npa_bmp, q))\n-\t\t\tcontinue;\n-\n-\t\taq = otx2_mbox_alloc_msg_npa_aq_enq(lf->mbox);\n-\t\taq->aura_id = q;\n-\t\taq->ctype = NPA_AQ_CTYPE_POOL;\n-\t\taq->op = NPA_AQ_INSTOP_READ;\n-\n-\t\trc = otx2_mbox_process_msg(lf->mbox, (void *)&rsp);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to get pool(%d) context\", q);\n-\t\t\treturn rc;\n-\t\t}\n-\t\tnpa_dump(\"============== pool=%d ===============\\n\", q);\n-\t\tnpa_lf_pool_dump(&rsp->pool);\n-\t}\n-\n-\tfor (q = 0; q < lf->nr_pools; q++) {\n-\t\t/* Skip disabled AURA */\n-\t\tif (rte_bitmap_get(lf->npa_bmp, q))\n-\t\t\tcontinue;\n-\n-\t\taq = otx2_mbox_alloc_msg_npa_aq_enq(lf->mbox);\n-\t\taq->aura_id = q;\n-\t\taq->ctype = NPA_AQ_CTYPE_AURA;\n-\t\taq->op = NPA_AQ_INSTOP_READ;\n-\n-\t\trc = otx2_mbox_process_msg(lf->mbox, (void *)&rsp);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to get aura(%d) context\", q);\n-\t\t\treturn rc;\n-\t\t}\n-\t\tnpa_dump(\"============== aura=%d ===============\\n\", q);\n-\t\tnpa_lf_aura_dump(&rsp->aura);\n-\t}\n-\n-\treturn rc;\n-}\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool_irq.c b/drivers/mempool/octeontx2/otx2_mempool_irq.c\ndeleted file mode 100644\nindex 5fa22b9612..0000000000\n--- a/drivers/mempool/octeontx2/otx2_mempool_irq.c\n+++ /dev/null\n@@ -1,303 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <inttypes.h>\n-\n-#include <rte_common.h>\n-#include <rte_bus_pci.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_irq.h\"\n-#include \"otx2_mempool.h\"\n-\n-static void\n-npa_lf_err_irq(void *param)\n-{\n-\tstruct otx2_npa_lf *lf = (struct otx2_npa_lf *)param;\n-\tuint64_t intr;\n-\n-\tintr = otx2_read64(lf->base + NPA_LF_ERR_INT);\n-\tif (intr == 0)\n-\t\treturn;\n-\n-\totx2_err(\"Err_intr=0x%\" PRIx64 \"\", intr);\n-\n-\t/* Clear interrupt */\n-\totx2_write64(intr, lf->base + NPA_LF_ERR_INT);\n-}\n-\n-static int\n-npa_lf_register_err_irq(struct otx2_npa_lf *lf)\n-{\n-\tstruct rte_intr_handle *handle = lf->intr_handle;\n-\tint rc, vec;\n-\n-\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_ERR_INT;\n-\n-\t/* Clear err interrupt */\n-\totx2_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1C);\n-\t/* Register err interrupt vector */\n-\trc = otx2_register_irq(handle, npa_lf_err_irq, lf, vec);\n-\n-\t/* Enable hw interrupt */\n-\totx2_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1S);\n-\n-\treturn rc;\n-}\n-\n-static void\n-npa_lf_unregister_err_irq(struct otx2_npa_lf *lf)\n-{\n-\tstruct rte_intr_handle *handle = lf->intr_handle;\n-\tint vec;\n-\n-\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_ERR_INT;\n-\n-\t/* Clear err interrupt */\n-\totx2_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1C);\n-\totx2_unregister_irq(handle, npa_lf_err_irq, lf, vec);\n-}\n-\n-static void\n-npa_lf_ras_irq(void *param)\n-{\n-\tstruct otx2_npa_lf *lf = (struct otx2_npa_lf *)param;\n-\tuint64_t intr;\n-\n-\tintr = otx2_read64(lf->base + NPA_LF_RAS);\n-\tif (intr == 0)\n-\t\treturn;\n-\n-\totx2_err(\"Ras_intr=0x%\" PRIx64 \"\", intr);\n-\n-\t/* Clear interrupt */\n-\totx2_write64(intr, lf->base + NPA_LF_RAS);\n-}\n-\n-static int\n-npa_lf_register_ras_irq(struct otx2_npa_lf *lf)\n-{\n-\tstruct rte_intr_handle *handle = lf->intr_handle;\n-\tint rc, vec;\n-\n-\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_POISON;\n-\n-\t/* Clear err interrupt */\n-\totx2_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C);\n-\t/* Set used interrupt vectors */\n-\trc = otx2_register_irq(handle, npa_lf_ras_irq, lf, vec);\n-\t/* Enable hw interrupt */\n-\totx2_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1S);\n-\n-\treturn rc;\n-}\n-\n-static void\n-npa_lf_unregister_ras_irq(struct otx2_npa_lf *lf)\n-{\n-\tint vec;\n-\tstruct rte_intr_handle *handle = lf->intr_handle;\n-\n-\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_POISON;\n-\n-\t/* Clear err interrupt */\n-\totx2_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C);\n-\totx2_unregister_irq(handle, npa_lf_ras_irq, lf, vec);\n-}\n-\n-static inline uint8_t\n-npa_lf_q_irq_get_and_clear(struct otx2_npa_lf *lf, uint32_t q,\n-\t\t\tuint32_t off, uint64_t mask)\n-{\n-\tuint64_t reg, wdata;\n-\tuint8_t qint;\n-\n-\twdata = (uint64_t)q << 44;\n-\treg = otx2_atomic64_add_nosync(wdata, (int64_t *)(lf->base + off));\n-\n-\tif (reg & BIT_ULL(42) /* OP_ERR */) {\n-\t\totx2_err(\"Failed execute irq get off=0x%x\", off);\n-\t\treturn 0;\n-\t}\n-\n-\tqint = reg & 0xff;\n-\twdata &= mask;\n-\totx2_write64(wdata | qint, lf->base + off);\n-\n-\treturn qint;\n-}\n-\n-static inline uint8_t\n-npa_lf_pool_irq_get_and_clear(struct otx2_npa_lf *lf, uint32_t p)\n-{\n-\treturn npa_lf_q_irq_get_and_clear(lf, p, NPA_LF_POOL_OP_INT, ~0xff00);\n-}\n-\n-static inline uint8_t\n-npa_lf_aura_irq_get_and_clear(struct otx2_npa_lf *lf, uint32_t a)\n-{\n-\treturn npa_lf_q_irq_get_and_clear(lf, a, NPA_LF_AURA_OP_INT, ~0xff00);\n-}\n-\n-static void\n-npa_lf_q_irq(void *param)\n-{\n-\tstruct otx2_npa_qint *qint = (struct otx2_npa_qint *)param;\n-\tstruct otx2_npa_lf *lf = qint->lf;\n-\tuint8_t irq, qintx = qint->qintx;\n-\tuint32_t q, pool, aura;\n-\tuint64_t intr;\n-\n-\tintr = otx2_read64(lf->base + NPA_LF_QINTX_INT(qintx));\n-\tif (intr == 0)\n-\t\treturn;\n-\n-\totx2_err(\"queue_intr=0x%\" PRIx64 \" qintx=%d\", intr, qintx);\n-\n-\t/* Handle pool queue interrupts */\n-\tfor (q = 0; q < lf->nr_pools; q++) {\n-\t\t/* Skip disabled POOL */\n-\t\tif (rte_bitmap_get(lf->npa_bmp, q))\n-\t\t\tcontinue;\n-\n-\t\tpool = q % lf->qints;\n-\t\tirq = npa_lf_pool_irq_get_and_clear(lf, pool);\n-\n-\t\tif (irq & BIT_ULL(NPA_POOL_ERR_INT_OVFLS))\n-\t\t\totx2_err(\"Pool=%d NPA_POOL_ERR_INT_OVFLS\", pool);\n-\n-\t\tif (irq & BIT_ULL(NPA_POOL_ERR_INT_RANGE))\n-\t\t\totx2_err(\"Pool=%d NPA_POOL_ERR_INT_RANGE\", pool);\n-\n-\t\tif (irq & BIT_ULL(NPA_POOL_ERR_INT_PERR))\n-\t\t\totx2_err(\"Pool=%d NPA_POOL_ERR_INT_PERR\", pool);\n-\t}\n-\n-\t/* Handle aura queue interrupts */\n-\tfor (q = 0; q < lf->nr_pools; q++) {\n-\n-\t\t/* Skip disabled AURA */\n-\t\tif (rte_bitmap_get(lf->npa_bmp, q))\n-\t\t\tcontinue;\n-\n-\t\taura = q % lf->qints;\n-\t\tirq = npa_lf_aura_irq_get_and_clear(lf, aura);\n-\n-\t\tif (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_ADD_OVER))\n-\t\t\totx2_err(\"Aura=%d NPA_AURA_ERR_INT_ADD_OVER\", aura);\n-\n-\t\tif (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_ADD_UNDER))\n-\t\t\totx2_err(\"Aura=%d NPA_AURA_ERR_INT_ADD_UNDER\", aura);\n-\n-\t\tif (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_FREE_UNDER))\n-\t\t\totx2_err(\"Aura=%d NPA_AURA_ERR_INT_FREE_UNDER\", aura);\n-\n-\t\tif (irq & BIT_ULL(NPA_AURA_ERR_INT_POOL_DIS))\n-\t\t\totx2_err(\"Aura=%d NPA_AURA_ERR_POOL_DIS\", aura);\n-\t}\n-\n-\t/* Clear interrupt */\n-\totx2_write64(intr, lf->base + NPA_LF_QINTX_INT(qintx));\n-\totx2_mempool_ctx_dump(lf);\n-}\n-\n-static int\n-npa_lf_register_queue_irqs(struct otx2_npa_lf *lf)\n-{\n-\tstruct rte_intr_handle *handle = lf->intr_handle;\n-\tint vec, q, qs, rc = 0;\n-\n-\t/* Figure out max qintx required */\n-\tqs = RTE_MIN(lf->qints, lf->nr_pools);\n-\n-\tfor (q = 0; q < qs; q++) {\n-\t\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_QINT_START + q;\n-\n-\t\t/* Clear QINT CNT */\n-\t\totx2_write64(0, lf->base + NPA_LF_QINTX_CNT(q));\n-\n-\t\t/* Clear interrupt */\n-\t\totx2_write64(~0ull, lf->base + NPA_LF_QINTX_ENA_W1C(q));\n-\n-\t\tstruct otx2_npa_qint *qintmem = lf->npa_qint_mem;\n-\t\tqintmem += q;\n-\n-\t\tqintmem->lf = lf;\n-\t\tqintmem->qintx = q;\n-\n-\t\t/* Sync qints_mem update */\n-\t\trte_smp_wmb();\n-\n-\t\t/* Register queue irq vector */\n-\t\trc = otx2_register_irq(handle, npa_lf_q_irq, qintmem, vec);\n-\t\tif (rc)\n-\t\t\tbreak;\n-\n-\t\totx2_write64(0, lf->base + NPA_LF_QINTX_CNT(q));\n-\t\totx2_write64(0, lf->base + NPA_LF_QINTX_INT(q));\n-\t\t/* Enable QINT interrupt */\n-\t\totx2_write64(~0ull, lf->base + NPA_LF_QINTX_ENA_W1S(q));\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static void\n-npa_lf_unregister_queue_irqs(struct otx2_npa_lf *lf)\n-{\n-\tstruct rte_intr_handle *handle = lf->intr_handle;\n-\tint vec, q, qs;\n-\n-\t/* Figure out max qintx required */\n-\tqs = RTE_MIN(lf->qints, lf->nr_pools);\n-\n-\tfor (q = 0; q < qs; q++) {\n-\t\tvec = lf->npa_msixoff + NPA_LF_INT_VEC_QINT_START + q;\n-\n-\t\t/* Clear QINT CNT */\n-\t\totx2_write64(0, lf->base + NPA_LF_QINTX_CNT(q));\n-\t\totx2_write64(0, lf->base + NPA_LF_QINTX_INT(q));\n-\n-\t\t/* Clear interrupt */\n-\t\totx2_write64(~0ull, lf->base + NPA_LF_QINTX_ENA_W1C(q));\n-\n-\t\tstruct otx2_npa_qint *qintmem = lf->npa_qint_mem;\n-\t\tqintmem += q;\n-\n-\t\t/* Unregister queue irq vector */\n-\t\totx2_unregister_irq(handle, npa_lf_q_irq, qintmem, vec);\n-\n-\t\tqintmem->lf = NULL;\n-\t\tqintmem->qintx = 0;\n-\t}\n-}\n-\n-int\n-otx2_npa_register_irqs(struct otx2_npa_lf *lf)\n-{\n-\tint rc;\n-\n-\tif (lf->npa_msixoff == MSIX_VECTOR_INVALID) {\n-\t\totx2_err(\"Invalid NPALF MSIX vector offset vector: 0x%x\",\n-\t\t\tlf->npa_msixoff);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Register lf err interrupt */\n-\trc = npa_lf_register_err_irq(lf);\n-\t/* Register RAS interrupt */\n-\trc |= npa_lf_register_ras_irq(lf);\n-\t/* Register queue interrupts */\n-\trc |= npa_lf_register_queue_irqs(lf);\n-\n-\treturn rc;\n-}\n-\n-void\n-otx2_npa_unregister_irqs(struct otx2_npa_lf *lf)\n-{\n-\tnpa_lf_unregister_err_irq(lf);\n-\tnpa_lf_unregister_ras_irq(lf);\n-\tnpa_lf_unregister_queue_irqs(lf);\n-}\ndiff --git a/drivers/mempool/octeontx2/otx2_mempool_ops.c b/drivers/mempool/octeontx2/otx2_mempool_ops.c\ndeleted file mode 100644\nindex 332e4f1cb2..0000000000\n--- a/drivers/mempool/octeontx2/otx2_mempool_ops.c\n+++ /dev/null\n@@ -1,901 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_mempool.h>\n-#include <rte_vect.h>\n-\n-#include \"otx2_mempool.h\"\n-\n-static int __rte_hot\n-otx2_npa_enq(struct rte_mempool *mp, void * const *obj_table, unsigned int n)\n-{\n-\tunsigned int index; const uint64_t aura_handle = mp->pool_id;\n-\tconst uint64_t reg = npa_lf_aura_handle_to_aura(aura_handle);\n-\tconst uint64_t addr = npa_lf_aura_handle_to_base(aura_handle) +\n-\t\t\t\t NPA_LF_AURA_OP_FREE0;\n-\n-\t/* Ensure mbuf init changes are written before the free pointers\n-\t * are enqueued to the stack.\n-\t */\n-\trte_io_wmb();\n-\tfor (index = 0; index < n; index++)\n-\t\totx2_store_pair((uint64_t)obj_table[index], reg, addr);\n-\n-\treturn 0;\n-}\n-\n-static __rte_noinline int\n-npa_lf_aura_op_alloc_one(const int64_t wdata, int64_t * const addr,\n-\t\t\t void **obj_table, uint8_t i)\n-{\n-\tuint8_t retry = 4;\n-\n-\tdo {\n-\t\tobj_table[i] = (void *)otx2_atomic64_add_nosync(wdata, addr);\n-\t\tif (obj_table[i] != NULL)\n-\t\t\treturn 0;\n-\n-\t} while (retry--);\n-\n-\treturn -ENOENT;\n-}\n-\n-#if defined(RTE_ARCH_ARM64)\n-static __rte_noinline int\n-npa_lf_aura_op_search_alloc(const int64_t wdata, int64_t * const addr,\n-\t\tvoid **obj_table, unsigned int n)\n-{\n-\tuint8_t i;\n-\n-\tfor (i = 0; i < n; i++) {\n-\t\tif (obj_table[i] != NULL)\n-\t\t\tcontinue;\n-\t\tif (npa_lf_aura_op_alloc_one(wdata, addr, obj_table, i))\n-\t\t\treturn -ENOENT;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static __rte_noinline int\n-npa_lf_aura_op_alloc_bulk(const int64_t wdata, int64_t * const addr,\n-\t\t\t unsigned int n, void **obj_table)\n-{\n-\tregister const uint64_t wdata64 __asm(\"x26\") = wdata;\n-\tregister const uint64_t wdata128 __asm(\"x27\") = wdata;\n-\tuint64x2_t failed = vdupq_n_u64(~0);\n-\n-\tswitch (n) {\n-\tcase 32:\n-\t{\n-\t\tasm volatile (\n-\t\t\".cpu generic+lse\\n\"\n-\t\t\"casp x0, x1, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x2, x3, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x4, x5, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x6, x7, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x8, x9, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x10, x11, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x12, x13, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x14, x15, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x16, x17, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x18, x19, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x20, x21, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x22, x23, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"fmov d16, x0\\n\"\n-\t\t\"fmov v16.D[1], x1\\n\"\n-\t\t\"casp x0, x1, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"fmov d17, x2\\n\"\n-\t\t\"fmov v17.D[1], x3\\n\"\n-\t\t\"casp x2, x3, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"fmov d18, x4\\n\"\n-\t\t\"fmov v18.D[1], x5\\n\"\n-\t\t\"casp x4, x5, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"fmov d19, x6\\n\"\n-\t\t\"fmov v19.D[1], x7\\n\"\n-\t\t\"casp x6, x7, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v18.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v19.16B\\n\"\n-\t\t\"fmov d20, x8\\n\"\n-\t\t\"fmov v20.D[1], x9\\n\"\n-\t\t\"fmov d21, x10\\n\"\n-\t\t\"fmov v21.D[1], x11\\n\"\n-\t\t\"fmov d22, x12\\n\"\n-\t\t\"fmov v22.D[1], x13\\n\"\n-\t\t\"fmov d23, x14\\n\"\n-\t\t\"fmov v23.D[1], x15\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v20.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v21.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v22.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v23.16B\\n\"\n-\t\t\"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\\n\"\n-\t\t\"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\\n\"\n-\t\t\"fmov d16, x16\\n\"\n-\t\t\"fmov v16.D[1], x17\\n\"\n-\t\t\"fmov d17, x18\\n\"\n-\t\t\"fmov v17.D[1], x19\\n\"\n-\t\t\"fmov d18, x20\\n\"\n-\t\t\"fmov v18.D[1], x21\\n\"\n-\t\t\"fmov d19, x22\\n\"\n-\t\t\"fmov v19.D[1], x23\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v18.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v19.16B\\n\"\n-\t\t\"fmov d20, x0\\n\"\n-\t\t\"fmov v20.D[1], x1\\n\"\n-\t\t\"fmov d21, x2\\n\"\n-\t\t\"fmov v21.D[1], x3\\n\"\n-\t\t\"fmov d22, x4\\n\"\n-\t\t\"fmov v22.D[1], x5\\n\"\n-\t\t\"fmov d23, x6\\n\"\n-\t\t\"fmov v23.D[1], x7\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v20.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v21.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v22.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v23.16B\\n\"\n-\t\t\"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\\n\"\n-\t\t\"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\\n\"\n-\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed)\n-\t\t: [wdata64] \"r\" (wdata64), [wdata128] \"r\" (wdata128),\n-\t\t[dst] \"r\" (obj_table), [loc] \"r\" (addr)\n-\t\t: \"memory\", \"x0\", \"x1\", \"x2\", \"x3\", \"x4\", \"x5\", \"x6\", \"x7\",\n-\t\t\"x8\", \"x9\", \"x10\", \"x11\", \"x12\", \"x13\", \"x14\", \"x15\", \"x16\",\n-\t\t\"x17\", \"x18\", \"x19\", \"x20\", \"x21\", \"x22\", \"x23\", \"v16\", \"v17\",\n-\t\t\"v18\", \"v19\", \"v20\", \"v21\", \"v22\", \"v23\"\n-\t\t);\n-\t\tbreak;\n-\t}\n-\tcase 16:\n-\t{\n-\t\tasm volatile (\n-\t\t\".cpu generic+lse\\n\"\n-\t\t\"casp x0, x1, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x2, x3, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x4, x5, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x6, x7, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x8, x9, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x10, x11, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x12, x13, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x14, x15, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"fmov d16, x0\\n\"\n-\t\t\"fmov v16.D[1], x1\\n\"\n-\t\t\"fmov d17, x2\\n\"\n-\t\t\"fmov v17.D[1], x3\\n\"\n-\t\t\"fmov d18, x4\\n\"\n-\t\t\"fmov v18.D[1], x5\\n\"\n-\t\t\"fmov d19, x6\\n\"\n-\t\t\"fmov v19.D[1], x7\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v18.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v19.16B\\n\"\n-\t\t\"fmov d20, x8\\n\"\n-\t\t\"fmov v20.D[1], x9\\n\"\n-\t\t\"fmov d21, x10\\n\"\n-\t\t\"fmov v21.D[1], x11\\n\"\n-\t\t\"fmov d22, x12\\n\"\n-\t\t\"fmov v22.D[1], x13\\n\"\n-\t\t\"fmov d23, x14\\n\"\n-\t\t\"fmov v23.D[1], x15\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v20.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v21.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v22.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v23.16B\\n\"\n-\t\t\"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\\n\"\n-\t\t\"st1 { v20.2d, v21.2d, v22.2d, v23.2d}, [%[dst]], 64\\n\"\n-\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed)\n-\t\t: [wdata64] \"r\" (wdata64), [wdata128] \"r\" (wdata128),\n-\t\t[dst] \"r\" (obj_table), [loc] \"r\" (addr)\n-\t\t: \"memory\", \"x0\", \"x1\", \"x2\", \"x3\", \"x4\", \"x5\", \"x6\", \"x7\",\n-\t\t\"x8\", \"x9\", \"x10\", \"x11\", \"x12\", \"x13\", \"x14\", \"x15\", \"v16\",\n-\t\t\"v17\", \"v18\", \"v19\", \"v20\", \"v21\", \"v22\", \"v23\"\n-\t\t);\n-\t\tbreak;\n-\t}\n-\tcase 8:\n-\t{\n-\t\tasm volatile (\n-\t\t\".cpu generic+lse\\n\"\n-\t\t\"casp x0, x1, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x2, x3, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x4, x5, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x6, x7, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"fmov d16, x0\\n\"\n-\t\t\"fmov v16.D[1], x1\\n\"\n-\t\t\"fmov d17, x2\\n\"\n-\t\t\"fmov v17.D[1], x3\\n\"\n-\t\t\"fmov d18, x4\\n\"\n-\t\t\"fmov v18.D[1], x5\\n\"\n-\t\t\"fmov d19, x6\\n\"\n-\t\t\"fmov v19.D[1], x7\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v18.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v19.16B\\n\"\n-\t\t\"st1 { v16.2d, v17.2d, v18.2d, v19.2d}, [%[dst]], 64\\n\"\n-\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed)\n-\t\t: [wdata64] \"r\" (wdata64), [wdata128] \"r\" (wdata128),\n-\t\t[dst] \"r\" (obj_table), [loc] \"r\" (addr)\n-\t\t: \"memory\", \"x0\", \"x1\", \"x2\", \"x3\", \"x4\", \"x5\", \"x6\", \"x7\",\n-\t\t\"v16\", \"v17\", \"v18\", \"v19\"\n-\t\t);\n-\t\tbreak;\n-\t}\n-\tcase 4:\n-\t{\n-\t\tasm volatile (\n-\t\t\".cpu generic+lse\\n\"\n-\t\t\"casp x0, x1, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"casp x2, x3, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"fmov d16, x0\\n\"\n-\t\t\"fmov v16.D[1], x1\\n\"\n-\t\t\"fmov d17, x2\\n\"\n-\t\t\"fmov v17.D[1], x3\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v17.16B\\n\"\n-\t\t\"st1 { v16.2d, v17.2d}, [%[dst]], 32\\n\"\n-\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed)\n-\t\t: [wdata64] \"r\" (wdata64), [wdata128] \"r\" (wdata128),\n-\t\t[dst] \"r\" (obj_table), [loc] \"r\" (addr)\n-\t\t: \"memory\", \"x0\", \"x1\", \"x2\", \"x3\", \"v16\", \"v17\"\n-\t\t);\n-\t\tbreak;\n-\t}\n-\tcase 2:\n-\t{\n-\t\tasm volatile (\n-\t\t\".cpu generic+lse\\n\"\n-\t\t\"casp x0, x1, %[wdata64], %[wdata128], [%[loc]]\\n\"\n-\t\t\"fmov d16, x0\\n\"\n-\t\t\"fmov v16.D[1], x1\\n\"\n-\t\t\"and %[failed].16B, %[failed].16B, v16.16B\\n\"\n-\t\t\"st1 { v16.2d}, [%[dst]], 16\\n\"\n-\t\t: \"+Q\" (*addr), [failed] \"=&w\" (failed)\n-\t\t: [wdata64] \"r\" (wdata64), [wdata128] \"r\" (wdata128),\n-\t\t[dst] \"r\" (obj_table), [loc] \"r\" (addr)\n-\t\t: \"memory\", \"x0\", \"x1\", \"v16\"\n-\t\t);\n-\t\tbreak;\n-\t}\n-\tcase 1:\n-\t\treturn npa_lf_aura_op_alloc_one(wdata, addr, obj_table, 0);\n-\t}\n-\n-\tif (unlikely(!(vgetq_lane_u64(failed, 0) & vgetq_lane_u64(failed, 1))))\n-\t\treturn npa_lf_aura_op_search_alloc(wdata, addr, (void **)\n-\t\t\t((char *)obj_table - (sizeof(uint64_t) * n)), n);\n-\n-\treturn 0;\n-}\n-\n-static __rte_noinline void\n-otx2_npa_clear_alloc(struct rte_mempool *mp, void **obj_table, unsigned int n)\n-{\n-\tunsigned int i;\n-\n-\tfor (i = 0; i < n; i++) {\n-\t\tif (obj_table[i] != NULL) {\n-\t\t\totx2_npa_enq(mp, &obj_table[i], 1);\n-\t\t\tobj_table[i] = NULL;\n-\t\t}\n-\t}\n-}\n-\n-static __rte_noinline int __rte_hot\n-otx2_npa_deq_arm64(struct rte_mempool *mp, void **obj_table, unsigned int n)\n-{\n-\tconst int64_t wdata = npa_lf_aura_handle_to_aura(mp->pool_id);\n-\tvoid **obj_table_bak = obj_table;\n-\tconst unsigned int nfree = n;\n-\tunsigned int parts;\n-\n-\tint64_t * const addr = (int64_t * const)\n-\t\t\t(npa_lf_aura_handle_to_base(mp->pool_id) +\n-\t\t\t\tNPA_LF_AURA_OP_ALLOCX(0));\n-\twhile (n) {\n-\t\tparts = n > 31 ? 32 : rte_align32prevpow2(n);\n-\t\tn -= parts;\n-\t\tif (unlikely(npa_lf_aura_op_alloc_bulk(wdata, addr,\n-\t\t\t\tparts, obj_table))) {\n-\t\t\totx2_npa_clear_alloc(mp, obj_table_bak, nfree - n);\n-\t\t\treturn -ENOENT;\n-\t\t}\n-\t\tobj_table += parts;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-#else\n-\n-static inline int __rte_hot\n-otx2_npa_deq(struct rte_mempool *mp, void **obj_table, unsigned int n)\n-{\n-\tconst int64_t wdata = npa_lf_aura_handle_to_aura(mp->pool_id);\n-\tunsigned int index;\n-\tuint64_t obj;\n-\n-\tint64_t * const addr = (int64_t *)\n-\t\t\t(npa_lf_aura_handle_to_base(mp->pool_id) +\n-\t\t\t\tNPA_LF_AURA_OP_ALLOCX(0));\n-\tfor (index = 0; index < n; index++, obj_table++) {\n-\t\tobj = npa_lf_aura_op_alloc_one(wdata, addr, obj_table, 0);\n-\t\tif (obj == 0) {\n-\t\t\tfor (; index > 0; index--) {\n-\t\t\t\tobj_table--;\n-\t\t\t\totx2_npa_enq(mp, obj_table, 1);\n-\t\t\t}\n-\t\t\treturn -ENOENT;\n-\t\t}\n-\t\t*obj_table = (void *)obj;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-#endif\n-\n-static unsigned int\n-otx2_npa_get_count(const struct rte_mempool *mp)\n-{\n-\treturn (unsigned int)npa_lf_aura_op_available(mp->pool_id);\n-}\n-\n-static int\n-npa_lf_aura_pool_init(struct otx2_mbox *mbox, uint32_t aura_id,\n-\t\t struct npa_aura_s *aura, struct npa_pool_s *pool)\n-{\n-\tstruct npa_aq_enq_req *aura_init_req, *pool_init_req;\n-\tstruct npa_aq_enq_rsp *aura_init_rsp, *pool_init_rsp;\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];\n-\tstruct otx2_idev_cfg *idev;\n-\tint rc, off;\n-\n-\tidev = otx2_intra_dev_get_cfg();\n-\tif (idev == NULL)\n-\t\treturn -ENOMEM;\n-\n-\taura_init_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\n-\taura_init_req->aura_id = aura_id;\n-\taura_init_req->ctype = NPA_AQ_CTYPE_AURA;\n-\taura_init_req->op = NPA_AQ_INSTOP_INIT;\n-\totx2_mbox_memcpy(&aura_init_req->aura, aura, sizeof(*aura));\n-\n-\tpool_init_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\n-\tpool_init_req->aura_id = aura_id;\n-\tpool_init_req->ctype = NPA_AQ_CTYPE_POOL;\n-\tpool_init_req->op = NPA_AQ_INSTOP_INIT;\n-\totx2_mbox_memcpy(&pool_init_req->pool, pool, sizeof(*pool));\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\tif (rc < 0)\n-\t\treturn rc;\n-\n-\toff = mbox->rx_start +\n-\t\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n-\taura_init_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);\n-\toff = mbox->rx_start + aura_init_rsp->hdr.next_msgoff;\n-\tpool_init_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);\n-\n-\tif (rc == 2 && aura_init_rsp->hdr.rc == 0 && pool_init_rsp->hdr.rc == 0)\n-\t\treturn 0;\n-\telse\n-\t\treturn NPA_LF_ERR_AURA_POOL_INIT;\n-\n-\tif (!(idev->npa_lock_mask & BIT_ULL(aura_id)))\n-\t\treturn 0;\n-\n-\taura_init_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\taura_init_req->aura_id = aura_id;\n-\taura_init_req->ctype = NPA_AQ_CTYPE_AURA;\n-\taura_init_req->op = NPA_AQ_INSTOP_LOCK;\n-\n-\tpool_init_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\tif (!pool_init_req) {\n-\t\t/* The shared memory buffer can be full.\n-\t\t * Flush it and retry\n-\t\t */\n-\t\totx2_mbox_msg_send(mbox, 0);\n-\t\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\t\tif (rc < 0) {\n-\t\t\totx2_err(\"Failed to LOCK AURA context\");\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\n-\t\tpool_init_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\t\tif (!pool_init_req) {\n-\t\t\totx2_err(\"Failed to LOCK POOL context\");\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t}\n-\tpool_init_req->aura_id = aura_id;\n-\tpool_init_req->ctype = NPA_AQ_CTYPE_POOL;\n-\tpool_init_req->op = NPA_AQ_INSTOP_LOCK;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to lock POOL ctx to NDC\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-npa_lf_aura_pool_fini(struct otx2_mbox *mbox,\n-\t\t uint32_t aura_id,\n-\t\t uint64_t aura_handle)\n-{\n-\tstruct npa_aq_enq_req *aura_req, *pool_req;\n-\tstruct npa_aq_enq_rsp *aura_rsp, *pool_rsp;\n-\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];\n-\tstruct ndc_sync_op *ndc_req;\n-\tstruct otx2_idev_cfg *idev;\n-\tint rc, off;\n-\n-\tidev = otx2_intra_dev_get_cfg();\n-\tif (idev == NULL)\n-\t\treturn -EINVAL;\n-\n-\t/* Procedure for disabling an aura/pool */\n-\trte_delay_us(10);\n-\tnpa_lf_aura_op_alloc(aura_handle, 0);\n-\n-\tpool_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\tpool_req->aura_id = aura_id;\n-\tpool_req->ctype = NPA_AQ_CTYPE_POOL;\n-\tpool_req->op = NPA_AQ_INSTOP_WRITE;\n-\tpool_req->pool.ena = 0;\n-\tpool_req->pool_mask.ena = ~pool_req->pool_mask.ena;\n-\n-\taura_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\taura_req->aura_id = aura_id;\n-\taura_req->ctype = NPA_AQ_CTYPE_AURA;\n-\taura_req->op = NPA_AQ_INSTOP_WRITE;\n-\taura_req->aura.ena = 0;\n-\taura_req->aura_mask.ena = ~aura_req->aura_mask.ena;\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\tif (rc < 0)\n-\t\treturn rc;\n-\n-\toff = mbox->rx_start +\n-\t\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n-\tpool_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);\n-\n-\toff = mbox->rx_start + pool_rsp->hdr.next_msgoff;\n-\taura_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);\n-\n-\tif (rc != 2 || aura_rsp->hdr.rc != 0 || pool_rsp->hdr.rc != 0)\n-\t\treturn NPA_LF_ERR_AURA_POOL_FINI;\n-\n-\t/* Sync NDC-NPA for LF */\n-\tndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);\n-\tndc_req->npa_lf_sync = 1;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc) {\n-\t\totx2_err(\"Error on NDC-NPA LF sync, rc %d\", rc);\n-\t\treturn NPA_LF_ERR_AURA_POOL_FINI;\n-\t}\n-\n-\tif (!(idev->npa_lock_mask & BIT_ULL(aura_id)))\n-\t\treturn 0;\n-\n-\taura_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\taura_req->aura_id = aura_id;\n-\taura_req->ctype = NPA_AQ_CTYPE_AURA;\n-\taura_req->op = NPA_AQ_INSTOP_UNLOCK;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to unlock AURA ctx to NDC\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tpool_req = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\tpool_req->aura_id = aura_id;\n-\tpool_req->ctype = NPA_AQ_CTYPE_POOL;\n-\tpool_req->op = NPA_AQ_INSTOP_UNLOCK;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to unlock POOL ctx to NDC\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static inline char*\n-npa_lf_stack_memzone_name(struct otx2_npa_lf *lf, int pool_id, char *name)\n-{\n-\tsnprintf(name, RTE_MEMZONE_NAMESIZE, \"otx2_npa_stack_%x_%d\",\n-\t\t\tlf->pf_func, pool_id);\n-\n-\treturn name;\n-}\n-\n-static inline const struct rte_memzone *\n-npa_lf_stack_dma_alloc(struct otx2_npa_lf *lf, char *name,\n-\t\t int pool_id, size_t size)\n-{\n-\treturn rte_memzone_reserve_aligned(\n-\t\tnpa_lf_stack_memzone_name(lf, pool_id, name), size, 0,\n-\t\t\tRTE_MEMZONE_IOVA_CONTIG, OTX2_ALIGN);\n-}\n-\n-static inline int\n-npa_lf_stack_dma_free(struct otx2_npa_lf *lf, char *name, int pool_id)\n-{\n-\tconst struct rte_memzone *mz;\n-\n-\tmz = rte_memzone_lookup(npa_lf_stack_memzone_name(lf, pool_id, name));\n-\tif (mz == NULL)\n-\t\treturn -EINVAL;\n-\n-\treturn rte_memzone_free(mz);\n-}\n-\n-static inline int\n-bitmap_ctzll(uint64_t slab)\n-{\n-\tif (slab == 0)\n-\t\treturn 0;\n-\n-\treturn __builtin_ctzll(slab);\n-}\n-\n-static int\n-npa_lf_aura_pool_pair_alloc(struct otx2_npa_lf *lf, const uint32_t block_size,\n-\t\t\t const uint32_t block_count, struct npa_aura_s *aura,\n-\t\t\t struct npa_pool_s *pool, uint64_t *aura_handle)\n-{\n-\tint rc, aura_id, pool_id, stack_size, alloc_size;\n-\tchar name[RTE_MEMZONE_NAMESIZE];\n-\tconst struct rte_memzone *mz;\n-\tuint64_t slab;\n-\tuint32_t pos;\n-\n-\t/* Sanity check */\n-\tif (!lf || !block_size || !block_count ||\n-\t !pool || !aura || !aura_handle)\n-\t\treturn NPA_LF_ERR_PARAM;\n-\n-\t/* Block size should be cache line aligned and in range of 128B-128KB */\n-\tif (block_size % OTX2_ALIGN || block_size < 128 ||\n-\t block_size > 128 * 1024)\n-\t\treturn NPA_LF_ERR_INVALID_BLOCK_SZ;\n-\n-\tpos = slab = 0;\n-\t/* Scan from the beginning */\n-\t__rte_bitmap_scan_init(lf->npa_bmp);\n-\t/* Scan bitmap to get the free pool */\n-\trc = rte_bitmap_scan(lf->npa_bmp, &pos, &slab);\n-\t/* Empty bitmap */\n-\tif (rc == 0) {\n-\t\totx2_err(\"Mempools exhausted, 'max_pools' devargs to increase\");\n-\t\treturn -ERANGE;\n-\t}\n-\n-\t/* Get aura_id from resource bitmap */\n-\taura_id = pos + bitmap_ctzll(slab);\n-\t/* Mark pool as reserved */\n-\trte_bitmap_clear(lf->npa_bmp, aura_id);\n-\n-\t/* Configuration based on each aura has separate pool(aura-pool pair) */\n-\tpool_id = aura_id;\n-\trc = (aura_id < 0 || pool_id >= (int)lf->nr_pools || aura_id >=\n-\t (int)BIT_ULL(6 + lf->aura_sz)) ? NPA_LF_ERR_AURA_ID_ALLOC : 0;\n-\tif (rc)\n-\t\tgoto exit;\n-\n-\t/* Allocate stack memory */\n-\tstack_size = (block_count + lf->stack_pg_ptrs - 1) / lf->stack_pg_ptrs;\n-\talloc_size = stack_size * lf->stack_pg_bytes;\n-\n-\tmz = npa_lf_stack_dma_alloc(lf, name, pool_id, alloc_size);\n-\tif (mz == NULL) {\n-\t\trc = -ENOMEM;\n-\t\tgoto aura_res_put;\n-\t}\n-\n-\t/* Update aura fields */\n-\taura->pool_addr = pool_id;/* AF will translate to associated poolctx */\n-\taura->ena = 1;\n-\taura->shift = rte_log2_u32(block_count);\n-\taura->shift = aura->shift < 8 ? 0 : aura->shift - 8;\n-\taura->limit = block_count;\n-\taura->pool_caching = 1;\n-\taura->err_int_ena = BIT(NPA_AURA_ERR_INT_AURA_ADD_OVER);\n-\taura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_ADD_UNDER);\n-\taura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_FREE_UNDER);\n-\taura->err_int_ena |= BIT(NPA_AURA_ERR_INT_POOL_DIS);\n-\t/* Many to one reduction */\n-\taura->err_qint_idx = aura_id % lf->qints;\n-\n-\t/* Update pool fields */\n-\tpool->stack_base = mz->iova;\n-\tpool->ena = 1;\n-\tpool->buf_size = block_size / OTX2_ALIGN;\n-\tpool->stack_max_pages = stack_size;\n-\tpool->shift = rte_log2_u32(block_count);\n-\tpool->shift = pool->shift < 8 ? 0 : pool->shift - 8;\n-\tpool->ptr_start = 0;\n-\tpool->ptr_end = ~0;\n-\tpool->stack_caching = 1;\n-\tpool->err_int_ena = BIT(NPA_POOL_ERR_INT_OVFLS);\n-\tpool->err_int_ena |= BIT(NPA_POOL_ERR_INT_RANGE);\n-\tpool->err_int_ena |= BIT(NPA_POOL_ERR_INT_PERR);\n-\n-\t/* Many to one reduction */\n-\tpool->err_qint_idx = pool_id % lf->qints;\n-\n-\t/* Issue AURA_INIT and POOL_INIT op */\n-\trc = npa_lf_aura_pool_init(lf->mbox, aura_id, aura, pool);\n-\tif (rc)\n-\t\tgoto stack_mem_free;\n-\n-\t*aura_handle = npa_lf_aura_handle_gen(aura_id, lf->base);\n-\n-\t/* Update aura count */\n-\tnpa_lf_aura_op_cnt_set(*aura_handle, 0, block_count);\n-\t/* Read it back to make sure aura count is updated */\n-\tnpa_lf_aura_op_cnt_get(*aura_handle);\n-\n-\treturn 0;\n-\n-stack_mem_free:\n-\trte_memzone_free(mz);\n-aura_res_put:\n-\trte_bitmap_set(lf->npa_bmp, aura_id);\n-exit:\n-\treturn rc;\n-}\n-\n-static int\n-npa_lf_aura_pool_pair_free(struct otx2_npa_lf *lf, uint64_t aura_handle)\n-{\n-\tchar name[RTE_MEMZONE_NAMESIZE];\n-\tint aura_id, pool_id, rc;\n-\n-\tif (!lf || !aura_handle)\n-\t\treturn NPA_LF_ERR_PARAM;\n-\n-\taura_id = pool_id = npa_lf_aura_handle_to_aura(aura_handle);\n-\trc = npa_lf_aura_pool_fini(lf->mbox, aura_id, aura_handle);\n-\trc |= npa_lf_stack_dma_free(lf, name, pool_id);\n-\n-\trte_bitmap_set(lf->npa_bmp, aura_id);\n-\n-\treturn rc;\n-}\n-\n-static int\n-npa_lf_aura_range_update_check(uint64_t aura_handle)\n-{\n-\tuint64_t aura_id = npa_lf_aura_handle_to_aura(aura_handle);\n-\tstruct otx2_npa_lf *lf = otx2_npa_lf_obj_get();\n-\tstruct npa_aura_lim *lim = lf->aura_lim;\n-\t__otx2_io struct npa_pool_s *pool;\n-\tstruct npa_aq_enq_req *req;\n-\tstruct npa_aq_enq_rsp *rsp;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_npa_aq_enq(lf->mbox);\n-\n-\treq->aura_id = aura_id;\n-\treq->ctype = NPA_AQ_CTYPE_POOL;\n-\treq->op = NPA_AQ_INSTOP_READ;\n-\n-\trc = otx2_mbox_process_msg(lf->mbox, (void *)&rsp);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to get pool(0x%\"PRIx64\") context\", aura_id);\n-\t\treturn rc;\n-\t}\n-\n-\tpool = &rsp->pool;\n-\n-\tif (lim[aura_id].ptr_start != pool->ptr_start ||\n-\t\tlim[aura_id].ptr_end != pool->ptr_end) {\n-\t\totx2_err(\"Range update failed on pool(0x%\"PRIx64\")\", aura_id);\n-\t\treturn -ERANGE;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_npa_alloc(struct rte_mempool *mp)\n-{\n-\tuint32_t block_size, block_count;\n-\tuint64_t aura_handle = 0;\n-\tstruct otx2_npa_lf *lf;\n-\tstruct npa_aura_s aura;\n-\tstruct npa_pool_s pool;\n-\tsize_t padding;\n-\tint rc;\n-\n-\tlf = otx2_npa_lf_obj_get();\n-\tif (lf == NULL) {\n-\t\trc = -EINVAL;\n-\t\tgoto error;\n-\t}\n-\n-\tblock_size = mp->elt_size + mp->header_size + mp->trailer_size;\n-\t/*\n-\t * OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate\n-\t * the set selection.\n-\t * Add additional padding to ensure that the element size always\n-\t * occupies odd number of cachelines to ensure even distribution\n-\t * of elements among L1D cache sets.\n-\t */\n-\tpadding = ((block_size / RTE_CACHE_LINE_SIZE) % 2) ? 0 :\n-\t\t\t\tRTE_CACHE_LINE_SIZE;\n-\tmp->trailer_size += padding;\n-\tblock_size += padding;\n-\n-\tblock_count = mp->size;\n-\n-\tif (block_size % OTX2_ALIGN != 0) {\n-\t\totx2_err(\"Block size should be multiple of 128B\");\n-\t\trc = -ERANGE;\n-\t\tgoto error;\n-\t}\n-\n-\tmemset(&aura, 0, sizeof(struct npa_aura_s));\n-\tmemset(&pool, 0, sizeof(struct npa_pool_s));\n-\tpool.nat_align = 1;\n-\tpool.buf_offset = 1;\n-\n-\tif ((uint32_t)pool.buf_offset * OTX2_ALIGN != mp->header_size) {\n-\t\totx2_err(\"Unsupported mp->header_size=%d\", mp->header_size);\n-\t\trc = -EINVAL;\n-\t\tgoto error;\n-\t}\n-\n-\t/* Use driver specific mp->pool_config to override aura config */\n-\tif (mp->pool_config != NULL)\n-\t\tmemcpy(&aura, mp->pool_config, sizeof(struct npa_aura_s));\n-\n-\trc = npa_lf_aura_pool_pair_alloc(lf, block_size, block_count,\n-\t\t\t &aura, &pool, &aura_handle);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to alloc pool or aura rc=%d\", rc);\n-\t\tgoto error;\n-\t}\n-\n-\t/* Store aura_handle for future queue operations */\n-\tmp->pool_id = aura_handle;\n-\totx2_npa_dbg(\"lf=%p block_sz=%d block_count=%d aura_handle=0x%\"PRIx64,\n-\t\t lf, block_size, block_count, aura_handle);\n-\n-\t/* Just hold the reference of the object */\n-\totx2_npa_lf_obj_ref();\n-\treturn 0;\n-error:\n-\treturn rc;\n-}\n-\n-static void\n-otx2_npa_free(struct rte_mempool *mp)\n-{\n-\tstruct otx2_npa_lf *lf = otx2_npa_lf_obj_get();\n-\tint rc = 0;\n-\n-\totx2_npa_dbg(\"lf=%p aura_handle=0x%\"PRIx64, lf, mp->pool_id);\n-\tif (lf != NULL)\n-\t\trc = npa_lf_aura_pool_pair_free(lf, mp->pool_id);\n-\n-\tif (rc)\n-\t\totx2_err(\"Failed to free pool or aura rc=%d\", rc);\n-\n-\t/* Release the reference of npalf */\n-\totx2_npa_lf_fini();\n-}\n-\n-static ssize_t\n-otx2_npa_calc_mem_size(const struct rte_mempool *mp, uint32_t obj_num,\n-\t\t uint32_t pg_shift, size_t *min_chunk_size, size_t *align)\n-{\n-\tsize_t total_elt_sz;\n-\n-\t/* Need space for one more obj on each chunk to fulfill\n-\t * alignment requirements.\n-\t */\n-\ttotal_elt_sz = mp->header_size + mp->elt_size + mp->trailer_size;\n-\treturn rte_mempool_op_calc_mem_size_helper(mp, obj_num, pg_shift,\n-\t\t\t\t\t\ttotal_elt_sz, min_chunk_size,\n-\t\t\t\t\t\talign);\n-}\n-\n-static uint8_t\n-otx2_npa_l1d_way_set_get(uint64_t iova)\n-{\n-\treturn (iova >> rte_log2_u32(RTE_CACHE_LINE_SIZE)) & 0x7;\n-}\n-\n-static int\n-otx2_npa_populate(struct rte_mempool *mp, unsigned int max_objs, void *vaddr,\n-\t\t rte_iova_t iova, size_t len,\n-\t\t rte_mempool_populate_obj_cb_t *obj_cb, void *obj_cb_arg)\n-{\n-#define OTX2_L1D_NB_SETS\t8\n-\tuint64_t distribution[OTX2_L1D_NB_SETS];\n-\trte_iova_t start_iova;\n-\tsize_t total_elt_sz;\n-\tuint8_t set;\n-\tsize_t off;\n-\tint i;\n-\n-\tif (iova == RTE_BAD_IOVA)\n-\t\treturn -EINVAL;\n-\n-\ttotal_elt_sz = mp->header_size + mp->elt_size + mp->trailer_size;\n-\n-\t/* Align object start address to a multiple of total_elt_sz */\n-\toff = total_elt_sz - ((((uintptr_t)vaddr - 1) % total_elt_sz) + 1);\n-\n-\tif (len < off)\n-\t\treturn -EINVAL;\n-\n-\n-\tvaddr = (char *)vaddr + off;\n-\tiova += off;\n-\tlen -= off;\n-\n-\tmemset(distribution, 0, sizeof(uint64_t) * OTX2_L1D_NB_SETS);\n-\tstart_iova = iova;\n-\twhile (start_iova < iova + len) {\n-\t\tset = otx2_npa_l1d_way_set_get(start_iova + mp->header_size);\n-\t\tdistribution[set]++;\n-\t\tstart_iova += total_elt_sz;\n-\t}\n-\n-\totx2_npa_dbg(\"iova %\"PRIx64\", aligned iova %\"PRIx64\"\", iova - off,\n-\t\t iova);\n-\totx2_npa_dbg(\"length %\"PRIu64\", aligned length %\"PRIu64\"\",\n-\t\t (uint64_t)(len + off), (uint64_t)len);\n-\totx2_npa_dbg(\"element size %\"PRIu64\"\", (uint64_t)total_elt_sz);\n-\totx2_npa_dbg(\"requested objects %\"PRIu64\", possible objects %\"PRIu64\"\",\n-\t\t (uint64_t)max_objs, (uint64_t)(len / total_elt_sz));\n-\totx2_npa_dbg(\"L1D set distribution :\");\n-\tfor (i = 0; i < OTX2_L1D_NB_SETS; i++)\n-\t\totx2_npa_dbg(\"set[%d] : objects : %\"PRIu64\"\", i,\n-\t\t\t distribution[i]);\n-\n-\tnpa_lf_aura_op_range_set(mp->pool_id, iova, iova + len);\n-\n-\tif (npa_lf_aura_range_update_check(mp->pool_id) < 0)\n-\t\treturn -EBUSY;\n-\n-\treturn rte_mempool_op_populate_helper(mp,\n-\t\t\t\t\tRTE_MEMPOOL_POPULATE_F_ALIGN_OBJ,\n-\t\t\t\t\tmax_objs, vaddr, iova, len,\n-\t\t\t\t\tobj_cb, obj_cb_arg);\n-}\n-\n-static struct rte_mempool_ops otx2_npa_ops = {\n-\t.name = \"octeontx2_npa\",\n-\t.alloc = otx2_npa_alloc,\n-\t.free = otx2_npa_free,\n-\t.enqueue = otx2_npa_enq,\n-\t.get_count = otx2_npa_get_count,\n-\t.calc_mem_size = otx2_npa_calc_mem_size,\n-\t.populate = otx2_npa_populate,\n-#if defined(RTE_ARCH_ARM64)\n-\t.dequeue = otx2_npa_deq_arm64,\n-#else\n-\t.dequeue = otx2_npa_deq,\n-#endif\n-};\n-\n-RTE_MEMPOOL_REGISTER_OPS(otx2_npa_ops);\ndiff --git a/drivers/mempool/octeontx2/version.map b/drivers/mempool/octeontx2/version.map\ndeleted file mode 100644\nindex e6887ceb8f..0000000000\n--- a/drivers/mempool/octeontx2/version.map\n+++ /dev/null\n@@ -1,8 +0,0 @@\n-INTERNAL {\n-\tglobal:\n-\n-\totx2_npa_lf_fini;\n-\totx2_npa_lf_init;\n-\n-\tlocal: *;\n-};\ndiff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c\nindex f8f3d3895e..d34bc6898f 100644\n--- a/drivers/net/cnxk/cn9k_ethdev.c\n+++ b/drivers/net/cnxk/cn9k_ethdev.c\n@@ -579,6 +579,21 @@ cn9k_nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n }\n \n static const struct rte_pci_id cn9k_pci_nix_map[] = {\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_PF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KA, PCI_DEVID_CNXK_RVU_AF_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KB, PCI_DEVID_CNXK_RVU_AF_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KC, PCI_DEVID_CNXK_RVU_AF_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KD, PCI_DEVID_CNXK_RVU_AF_VF),\n+\tCNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN9KE, PCI_DEVID_CNXK_RVU_AF_VF),\n \t{\n \t\t.vendor_id = 0,\n \t},\ndiff --git a/drivers/net/meson.build b/drivers/net/meson.build\nindex 2355d1cde8..e35652fe63 100644\n--- a/drivers/net/meson.build\n+++ b/drivers/net/meson.build\n@@ -45,7 +45,6 @@ drivers = [\n 'ngbe',\n 'null',\n 'octeontx',\n- 'octeontx2',\n 'octeontx_ep',\n 'pcap',\n 'pfe',\ndiff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build\ndeleted file mode 100644\nindex ab15844cbc..0000000000\n--- a/drivers/net/octeontx2/meson.build\n+++ /dev/null\n@@ -1,47 +0,0 @@\n-# SPDX-License-Identifier: BSD-3-Clause\n-# Copyright(C) 2019 Marvell International Ltd.\n-#\n-\n-if not is_linux or not dpdk_conf.get('RTE_ARCH_64')\n- build = false\n- reason = 'only supported on 64-bit Linux'\n- subdir_done()\n-endif\n-\n-sources = files(\n- 'otx2_rx.c',\n- 'otx2_tx.c',\n- 'otx2_tm.c',\n- 'otx2_rss.c',\n- 'otx2_mac.c',\n- 'otx2_ptp.c',\n- 'otx2_flow.c',\n- 'otx2_link.c',\n- 'otx2_vlan.c',\n- 'otx2_stats.c',\n- 'otx2_mcast.c',\n- 'otx2_lookup.c',\n- 'otx2_ethdev.c',\n- 'otx2_flow_ctrl.c',\n- 'otx2_flow_dump.c',\n- 'otx2_flow_parse.c',\n- 'otx2_flow_utils.c',\n- 'otx2_ethdev_irq.c',\n- 'otx2_ethdev_ops.c',\n- 'otx2_ethdev_sec.c',\n- 'otx2_ethdev_debug.c',\n- 'otx2_ethdev_devargs.c',\n-)\n-\n-deps += ['bus_pci', 'cryptodev', 'eventdev', 'security']\n-deps += ['common_octeontx2', 'mempool_octeontx2']\n-\n-extra_flags = ['-flax-vector-conversions']\n-foreach flag: extra_flags\n- if cc.has_argument(flag)\n- cflags += flag\n- endif\n-endforeach\n-\n-includes += include_directories('../../common/cpt')\n-includes += include_directories('../../crypto/octeontx2')\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c\ndeleted file mode 100644\nindex 4f1c0b98de..0000000000\n--- a/drivers/net/octeontx2/otx2_ethdev.c\n+++ /dev/null\n@@ -1,2814 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <inttypes.h>\n-\n-#include <ethdev_pci.h>\n-#include <rte_io.h>\n-#include <rte_malloc.h>\n-#include <rte_mbuf.h>\n-#include <rte_mbuf_pool_ops.h>\n-#include <rte_mempool.h>\n-\n-#include \"otx2_ethdev.h\"\n-#include \"otx2_ethdev_sec.h\"\n-\n-static inline uint64_t\n-nix_get_rx_offload_capa(struct otx2_eth_dev *dev)\n-{\n-\tuint64_t capa = NIX_RX_OFFLOAD_CAPA;\n-\n-\tif (otx2_dev_is_vf(dev) ||\n-\t dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)\n-\t\tcapa &= ~RTE_ETH_RX_OFFLOAD_TIMESTAMP;\n-\n-\treturn capa;\n-}\n-\n-static inline uint64_t\n-nix_get_tx_offload_capa(struct otx2_eth_dev *dev)\n-{\n-\tuint64_t capa = NIX_TX_OFFLOAD_CAPA;\n-\n-\t/* TSO not supported for earlier chip revisions */\n-\tif (otx2_dev_is_96xx_A0(dev) || otx2_dev_is_95xx_Ax(dev))\n-\t\tcapa &= ~(RTE_ETH_TX_OFFLOAD_TCP_TSO |\n-\t\t\t RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |\n-\t\t\t RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |\n-\t\t\t RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO);\n-\treturn capa;\n-}\n-\n-static const struct otx2_dev_ops otx2_dev_ops = {\n-\t.link_status_update = otx2_eth_dev_link_status_update,\n-\t.ptp_info_update = otx2_eth_dev_ptp_info_update,\n-\t.link_status_get = otx2_eth_dev_link_status_get,\n-};\n-\n-static int\n-nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_lf_alloc_req *req;\n-\tstruct nix_lf_alloc_rsp *rsp;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);\n-\treq->rq_cnt = nb_rxq;\n-\treq->sq_cnt = nb_txq;\n-\treq->cq_cnt = nb_rxq;\n-\t/* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */\n-\tRTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);\n-\treq->xqe_sz = NIX_XQESZ_W16;\n-\treq->rss_sz = dev->rss_info.rss_size;\n-\treq->rss_grps = NIX_RSS_GRPS;\n-\treq->npa_func = otx2_npa_pf_func_get();\n-\treq->sso_func = otx2_sso_pf_func_get();\n-\treq->rx_cfg = BIT_ULL(35 /* DIS_APAD */);\n-\tif (dev->rx_offloads & (RTE_ETH_RX_OFFLOAD_TCP_CKSUM |\n-\t\t\t RTE_ETH_RX_OFFLOAD_UDP_CKSUM)) {\n-\t\treq->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);\n-\t\treq->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);\n-\t}\n-\treq->rx_cfg |= (BIT_ULL(32 /* DROP_RE */) |\n-\t\t\tBIT_ULL(33 /* Outer L2 Length */) |\n-\t\t\tBIT_ULL(38 /* Inner L4 UDP Length */) |\n-\t\t\tBIT_ULL(39 /* Inner L3 Length */) |\n-\t\t\tBIT_ULL(40 /* Outer L4 UDP Length */) |\n-\t\t\tBIT_ULL(41 /* Outer L3 Length */));\n-\n-\tif (dev->rss_tag_as_xor == 0)\n-\t\treq->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER;\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tdev->sqb_size = rsp->sqb_size;\n-\tdev->tx_chan_base = rsp->tx_chan_base;\n-\tdev->rx_chan_base = rsp->rx_chan_base;\n-\tdev->rx_chan_cnt = rsp->rx_chan_cnt;\n-\tdev->tx_chan_cnt = rsp->tx_chan_cnt;\n-\tdev->lso_tsov4_idx = rsp->lso_tsov4_idx;\n-\tdev->lso_tsov6_idx = rsp->lso_tsov6_idx;\n-\tdev->lf_tx_stats = rsp->lf_tx_stats;\n-\tdev->lf_rx_stats = rsp->lf_rx_stats;\n-\tdev->cints = rsp->cints;\n-\tdev->qints = rsp->qints;\n-\tdev->npc_flow.channel = dev->rx_chan_base;\n-\tdev->ptp_en = rsp->hw_rx_tstamp_en;\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct npc_set_pkind *req;\n-\tstruct msg_resp *rsp;\n-\tint rc;\n-\n-\tif (dev->npc_flow.switch_header_type == 0)\n-\t\treturn 0;\n-\n-\t/* Notify AF about higig2 config */\n-\treq = otx2_mbox_alloc_msg_npc_set_pkind(mbox);\n-\treq->mode = dev->npc_flow.switch_header_type;\n-\tif (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B) {\n-\t\treq->mode = OTX2_PRIV_FLAGS_CUSTOM;\n-\t\treq->pkind = NPC_RX_CHLEN90B_PKIND;\n-\t} else if (dev->npc_flow.switch_header_type ==\n-\t\t OTX2_PRIV_FLAGS_CH_LEN_24B) {\n-\t\treq->mode = OTX2_PRIV_FLAGS_CUSTOM;\n-\t\treq->pkind = NPC_RX_CHLEN24B_PKIND;\n-\t} else if (dev->npc_flow.switch_header_type ==\n-\t\t OTX2_PRIV_FLAGS_EXDSA) {\n-\t\treq->mode = OTX2_PRIV_FLAGS_CUSTOM;\n-\t\treq->pkind = NPC_RX_EXDSA_PKIND;\n-\t} else if (dev->npc_flow.switch_header_type ==\n-\t\t OTX2_PRIV_FLAGS_VLAN_EXDSA) {\n-\t\treq->mode = OTX2_PRIV_FLAGS_CUSTOM;\n-\t\treq->pkind = NPC_RX_VLAN_EXDSA_PKIND;\n-\t}\n-\n-\tif (enable == 0)\n-\t\treq->mode = OTX2_PRIV_FLAGS_DEFAULT;\n-\treq->dir = PKIND_RX;\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\treq = otx2_mbox_alloc_msg_npc_set_pkind(mbox);\n-\treq->mode = dev->npc_flow.switch_header_type;\n-\tif (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B ||\n-\t dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_24B)\n-\t\treq->mode = OTX2_PRIV_FLAGS_DEFAULT;\n-\n-\tif (enable == 0)\n-\t\treq->mode = OTX2_PRIV_FLAGS_DEFAULT;\n-\treq->dir = PKIND_TX;\n-\treturn otx2_mbox_process_msg(mbox, (void *)&rsp);\n-}\n-\n-static int\n-nix_lf_free(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_lf_free_req *req;\n-\tstruct ndc_sync_op *ndc_req;\n-\tint rc;\n-\n-\t/* Sync NDC-NIX for LF */\n-\tndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);\n-\tndc_req->nix_lf_tx_sync = 1;\n-\tndc_req->nix_lf_rx_sync = 1;\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\totx2_err(\"Error on NDC-NIX-[TX, RX] LF sync, rc %d\", rc);\n-\n-\treq = otx2_mbox_alloc_msg_nix_lf_free(mbox);\n-\t/* Let AF driver free all this nix lf's\n-\t * NPC entries allocated using NPC MBOX.\n-\t */\n-\treq->flags = 0;\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-int\n-otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev))\n-\t\treturn 0;\n-\n-\totx2_mbox_alloc_msg_cgx_start_rxtx(mbox);\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-int\n-otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev))\n-\t\treturn 0;\n-\n-\totx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static int\n-npc_rx_enable(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\n-\totx2_mbox_alloc_msg_nix_lf_start_rx(mbox);\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static int\n-npc_rx_disable(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\n-\totx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static int\n-nix_cgx_start_link_event(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev))\n-\t\treturn 0;\n-\n-\totx2_mbox_alloc_msg_cgx_start_linkevents(mbox);\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static int\n-cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\n-\tif (en && otx2_dev_is_vf_or_sdp(dev))\n-\t\treturn -ENOTSUP;\n-\n-\tif (en)\n-\t\totx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);\n-\telse\n-\t\totx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static int\n-nix_cgx_stop_link_event(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev))\n-\t\treturn 0;\n-\n-\totx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static inline void\n-nix_rx_queue_reset(struct otx2_eth_rxq *rxq)\n-{\n-\trxq->head = 0;\n-\trxq->available = 0;\n-}\n-\n-static inline uint32_t\n-nix_qsize_to_val(enum nix_q_size_e qsize)\n-{\n-\treturn (16UL << (qsize * 2));\n-}\n-\n-static inline enum nix_q_size_e\n-nix_qsize_clampup_get(struct otx2_eth_dev *dev, uint32_t val)\n-{\n-\tint i;\n-\n-\tif (otx2_ethdev_fixup_is_min_4k_q(dev))\n-\t\ti = nix_q_size_4K;\n-\telse\n-\t\ti = nix_q_size_16;\n-\n-\tfor (; i < nix_q_size_max; i++)\n-\t\tif (val <= nix_qsize_to_val(i))\n-\t\t\tbreak;\n-\n-\tif (i >= nix_q_size_max)\n-\t\ti = nix_q_size_max - 1;\n-\n-\treturn i;\n-}\n-\n-static int\n-nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev,\n-\t uint16_t qid, struct otx2_eth_rxq *rxq, struct rte_mempool *mp)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tconst struct rte_memzone *rz;\n-\tuint32_t ring_size, cq_size;\n-\tstruct nix_aq_enq_req *aq;\n-\tuint16_t first_skip;\n-\tint rc;\n-\n-\tcq_size = rxq->qlen;\n-\tring_size = cq_size * NIX_CQ_ENTRY_SZ;\n-\trz = rte_eth_dma_zone_reserve(eth_dev, \"cq\", qid, ring_size,\n-\t\t\t\t NIX_CQ_ALIGN, dev->node);\n-\tif (rz == NULL) {\n-\t\totx2_err(\"Failed to allocate mem for cq hw ring\");\n-\t\treturn -ENOMEM;\n-\t}\n-\tmemset(rz->addr, 0, rz->len);\n-\trxq->desc = (uintptr_t)rz->addr;\n-\trxq->qmask = cq_size - 1;\n-\n-\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\taq->qidx = qid;\n-\taq->ctype = NIX_AQ_CTYPE_CQ;\n-\taq->op = NIX_AQ_INSTOP_INIT;\n-\n-\taq->cq.ena = 1;\n-\taq->cq.caching = 1;\n-\taq->cq.qsize = rxq->qsize;\n-\taq->cq.base = rz->iova;\n-\taq->cq.avg_level = 0xff;\n-\taq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);\n-\taq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);\n-\n-\t/* Many to one reduction */\n-\taq->cq.qint_idx = qid % dev->qints;\n-\t/* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */\n-\taq->cq.cint_idx = qid;\n-\n-\tif (otx2_ethdev_fixup_is_limit_cq_full(dev)) {\n-\t\tconst float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;\n-\t\tuint16_t min_rx_drop;\n-\n-\t\tmin_rx_drop = ceil(rx_cq_skid / (float)cq_size);\n-\t\taq->cq.drop = min_rx_drop;\n-\t\taq->cq.drop_ena = 1;\n-\t\trxq->cq_drop = min_rx_drop;\n-\t} else {\n-\t\trxq->cq_drop = NIX_CQ_THRESH_LEVEL;\n-\t\taq->cq.drop = rxq->cq_drop;\n-\t\taq->cq.drop_ena = 1;\n-\t}\n-\n-\t/* TX pause frames enable flowctrl on RX side */\n-\tif (dev->fc_info.tx_pause) {\n-\t\t/* Single bpid is allocated for all rx channels for now */\n-\t\taq->cq.bpid = dev->fc_info.bpid[0];\n-\t\taq->cq.bp = rxq->cq_drop;\n-\t\taq->cq.bp_ena = 1;\n-\t}\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to init cq context\");\n-\t\treturn rc;\n-\t}\n-\n-\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\taq->qidx = qid;\n-\taq->ctype = NIX_AQ_CTYPE_RQ;\n-\taq->op = NIX_AQ_INSTOP_INIT;\n-\n-\taq->rq.sso_ena = 0;\n-\n-\tif (rxq->offloads & RTE_ETH_RX_OFFLOAD_SECURITY)\n-\t\taq->rq.ipsech_ena = 1;\n-\n-\taq->rq.cq = qid; /* RQ to CQ 1:1 mapped */\n-\taq->rq.spb_ena = 0;\n-\taq->rq.lpb_aura = npa_lf_aura_handle_to_aura(mp->pool_id);\n-\tfirst_skip = (sizeof(struct rte_mbuf));\n-\tfirst_skip += RTE_PKTMBUF_HEADROOM;\n-\tfirst_skip += rte_pktmbuf_priv_size(mp);\n-\trxq->data_off = first_skip;\n-\n-\tfirst_skip /= 8; /* Expressed in number of dwords */\n-\taq->rq.first_skip = first_skip;\n-\taq->rq.later_skip = (sizeof(struct rte_mbuf) / 8);\n-\taq->rq.flow_tagw = 32; /* 32-bits */\n-\taq->rq.lpb_sizem1 = mp->elt_size / 8;\n-\taq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */\n-\taq->rq.ena = 1;\n-\taq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */\n-\taq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */\n-\taq->rq.rq_int_ena = 0;\n-\t/* Many to one reduction */\n-\taq->rq.qint_idx = qid % dev->qints;\n-\n-\taq->rq.xqe_drop_ena = 1;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to init rq context\");\n-\t\treturn rc;\n-\t}\n-\n-\tif (dev->lock_rx_ctx) {\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\taq->qidx = qid;\n-\t\taq->ctype = NIX_AQ_CTYPE_CQ;\n-\t\taq->op = NIX_AQ_INSTOP_LOCK;\n-\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq) {\n-\t\t\t/* The shared memory buffer can be full.\n-\t\t\t * Flush it and retry\n-\t\t\t */\n-\t\t\totx2_mbox_msg_send(mbox, 0);\n-\t\t\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\t\t\tif (rc < 0) {\n-\t\t\t\totx2_err(\"Failed to LOCK cq context\");\n-\t\t\t\treturn rc;\n-\t\t\t}\n-\n-\t\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\t\tif (!aq) {\n-\t\t\t\totx2_err(\"Failed to LOCK rq context\");\n-\t\t\t\treturn -ENOMEM;\n-\t\t\t}\n-\t\t}\n-\t\taq->qidx = qid;\n-\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n-\t\taq->op = NIX_AQ_INSTOP_LOCK;\n-\t\trc = otx2_mbox_process(mbox);\n-\t\tif (rc < 0) {\n-\t\t\totx2_err(\"Failed to LOCK rq context\");\n-\t\t\treturn rc;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_rq_enb_dis(struct rte_eth_dev *eth_dev,\n-\t struct otx2_eth_rxq *rxq, const bool enb)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_aq_enq_req *aq;\n-\n-\t/* Pkts will be dropped silently if RQ is disabled */\n-\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\taq->qidx = rxq->rq;\n-\taq->ctype = NIX_AQ_CTYPE_RQ;\n-\taq->op = NIX_AQ_INSTOP_WRITE;\n-\n-\taq->rq.ena = enb;\n-\taq->rq_mask.ena = ~(aq->rq_mask.ena);\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static int\n-nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_aq_enq_req *aq;\n-\tint rc;\n-\n-\t/* RQ is already disabled */\n-\t/* Disable CQ */\n-\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\taq->qidx = rxq->rq;\n-\taq->ctype = NIX_AQ_CTYPE_CQ;\n-\taq->op = NIX_AQ_INSTOP_WRITE;\n-\n-\taq->cq.ena = 0;\n-\taq->cq_mask.ena = ~(aq->cq_mask.ena);\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to disable cq context\");\n-\t\treturn rc;\n-\t}\n-\n-\tif (dev->lock_rx_ctx) {\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\taq->qidx = rxq->rq;\n-\t\taq->ctype = NIX_AQ_CTYPE_CQ;\n-\t\taq->op = NIX_AQ_INSTOP_UNLOCK;\n-\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq) {\n-\t\t\t/* The shared memory buffer can be full.\n-\t\t\t * Flush it and retry\n-\t\t\t */\n-\t\t\totx2_mbox_msg_send(mbox, 0);\n-\t\t\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\t\t\tif (rc < 0) {\n-\t\t\t\totx2_err(\"Failed to UNLOCK cq context\");\n-\t\t\t\treturn rc;\n-\t\t\t}\n-\n-\t\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\t\tif (!aq) {\n-\t\t\t\totx2_err(\"Failed to UNLOCK rq context\");\n-\t\t\t\treturn -ENOMEM;\n-\t\t\t}\n-\t\t}\n-\t\taq->qidx = rxq->rq;\n-\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n-\t\taq->op = NIX_AQ_INSTOP_UNLOCK;\n-\t\trc = otx2_mbox_process(mbox);\n-\t\tif (rc < 0) {\n-\t\t\totx2_err(\"Failed to UNLOCK rq context\");\n-\t\t\treturn rc;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static inline int\n-nix_get_data_off(struct otx2_eth_dev *dev)\n-{\n-\treturn otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;\n-}\n-\n-uint64_t\n-otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id)\n-{\n-\tstruct rte_mbuf mb_def;\n-\tuint64_t *tmp;\n-\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -\n-\t\t\t\toffsetof(struct rte_mbuf, data_off) != 2);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -\n-\t\t\t\toffsetof(struct rte_mbuf, data_off) != 4);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -\n-\t\t\t\toffsetof(struct rte_mbuf, data_off) != 6);\n-\tmb_def.nb_segs = 1;\n-\tmb_def.data_off = RTE_PKTMBUF_HEADROOM + nix_get_data_off(dev);\n-\tmb_def.port = port_id;\n-\trte_mbuf_refcnt_set(&mb_def, 1);\n-\n-\t/* Prevent compiler reordering: rearm_data covers previous fields */\n-\trte_compiler_barrier();\n-\ttmp = (uint64_t *)&mb_def.rearm_data;\n-\n-\treturn *tmp;\n-}\n-\n-static void\n-otx2_nix_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)\n-{\n-\tstruct otx2_eth_rxq *rxq = dev->data->rx_queues[qid];\n-\n-\tif (!rxq)\n-\t\treturn;\n-\n-\totx2_nix_dbg(\"Releasing rxq %u\", rxq->rq);\n-\tnix_cq_rq_uninit(rxq->eth_dev, rxq);\n-\trte_free(rxq);\n-\tdev->data->rx_queues[qid] = NULL;\n-}\n-\n-static int\n-otx2_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t rq,\n-\t\t\tuint16_t nb_desc, unsigned int socket,\n-\t\t\tconst struct rte_eth_rxconf *rx_conf,\n-\t\t\tstruct rte_mempool *mp)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct rte_mempool_ops *ops;\n-\tstruct otx2_eth_rxq *rxq;\n-\tconst char *platform_ops;\n-\tenum nix_q_size_e qsize;\n-\tuint64_t offloads;\n-\tint rc;\n-\n-\trc = -EINVAL;\n-\n-\t/* Compile time check to make sure all fast path elements in a CL */\n-\tRTE_BUILD_BUG_ON(offsetof(struct otx2_eth_rxq, slow_path_start) >= 128);\n-\n-\t/* Sanity checks */\n-\tif (rx_conf->rx_deferred_start == 1) {\n-\t\totx2_err(\"Deferred Rx start is not supported\");\n-\t\tgoto fail;\n-\t}\n-\n-\tplatform_ops = rte_mbuf_platform_mempool_ops();\n-\t/* This driver needs octeontx2_npa mempool ops to work */\n-\tops = rte_mempool_get_ops(mp->ops_index);\n-\tif (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {\n-\t\totx2_err(\"mempool ops should be of octeontx2_npa type\");\n-\t\tgoto fail;\n-\t}\n-\n-\tif (mp->pool_id == 0) {\n-\t\totx2_err(\"Invalid pool_id\");\n-\t\tgoto fail;\n-\t}\n-\n-\t/* Free memory prior to re-allocation if needed */\n-\tif (eth_dev->data->rx_queues[rq] != NULL) {\n-\t\totx2_nix_dbg(\"Freeing memory prior to re-allocation %d\", rq);\n-\t\totx2_nix_rx_queue_release(eth_dev, rq);\n-\t\trte_eth_dma_zone_free(eth_dev, \"cq\", rq);\n-\t}\n-\n-\toffloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;\n-\tdev->rx_offloads |= offloads;\n-\n-\t/* Find the CQ queue size */\n-\tqsize = nix_qsize_clampup_get(dev, nb_desc);\n-\t/* Allocate rxq memory */\n-\trxq = rte_zmalloc_socket(\"otx2 rxq\", sizeof(*rxq), OTX2_ALIGN, socket);\n-\tif (rxq == NULL) {\n-\t\totx2_err(\"Failed to allocate rq=%d\", rq);\n-\t\trc = -ENOMEM;\n-\t\tgoto fail;\n-\t}\n-\n-\trxq->eth_dev = eth_dev;\n-\trxq->rq = rq;\n-\trxq->cq_door = dev->base + NIX_LF_CQ_OP_DOOR;\n-\trxq->cq_status = (int64_t *)(dev->base + NIX_LF_CQ_OP_STATUS);\n-\trxq->wdata = (uint64_t)rq << 32;\n-\trxq->aura = npa_lf_aura_handle_to_aura(mp->pool_id);\n-\trxq->mbuf_initializer = otx2_nix_rxq_mbuf_setup(dev,\n-\t\t\t\t\t\t\teth_dev->data->port_id);\n-\trxq->offloads = offloads;\n-\trxq->pool = mp;\n-\trxq->qlen = nix_qsize_to_val(qsize);\n-\trxq->qsize = qsize;\n-\trxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();\n-\trxq->tstamp = &dev->tstamp;\n-\n-\teth_dev->data->rx_queues[rq] = rxq;\n-\n-\t/* Alloc completion queue */\n-\trc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to allocate rxq=%u\", rq);\n-\t\tgoto free_rxq;\n-\t}\n-\n-\trxq->qconf.socket_id = socket;\n-\trxq->qconf.nb_desc = nb_desc;\n-\trxq->qconf.mempool = mp;\n-\tmemcpy(&rxq->qconf.conf.rx, rx_conf, sizeof(struct rte_eth_rxconf));\n-\n-\tnix_rx_queue_reset(rxq);\n-\totx2_nix_dbg(\"rq=%d pool=%s qsize=%d nb_desc=%d->%d\",\n-\t\t rq, mp->name, qsize, nb_desc, rxq->qlen);\n-\n-\teth_dev->data->rx_queue_state[rq] = RTE_ETH_QUEUE_STATE_STOPPED;\n-\n-\t/* Calculating delta and freq mult between PTP HI clock and tsc.\n-\t * These are needed in deriving raw clock value from tsc counter.\n-\t * read_clock eth op returns raw clock value.\n-\t */\n-\tif ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) ||\n-\t otx2_ethdev_is_ptp_en(dev)) {\n-\t\trc = otx2_nix_raw_clock_tsc_conv(dev);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to calculate delta and freq mult\");\n-\t\t\tgoto fail;\n-\t\t}\n-\t}\n-\n-\t/* Setup scatter mode if needed by jumbo */\n-\totx2_nix_enable_mseg_on_jumbo(rxq);\n-\n-\treturn 0;\n-\n-free_rxq:\n-\totx2_nix_rx_queue_release(eth_dev, rq);\n-fail:\n-\treturn rc;\n-}\n-\n-static inline uint8_t\n-nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)\n-{\n-\t/*\n-\t * Maximum three segments can be supported with W8, Choose\n-\t * NIX_MAXSQESZ_W16 for multi segment offload.\n-\t */\n-\tif (txq->offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)\n-\t\treturn NIX_MAXSQESZ_W16;\n-\telse\n-\t\treturn NIX_MAXSQESZ_W8;\n-}\n-\n-static uint16_t\n-nix_rx_offload_flags(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct rte_eth_dev_data *data = eth_dev->data;\n-\tstruct rte_eth_conf *conf = &data->dev_conf;\n-\tstruct rte_eth_rxmode *rxmode = &conf->rxmode;\n-\tuint16_t flags = 0;\n-\n-\tif (rxmode->mq_mode == RTE_ETH_MQ_RX_RSS &&\n-\t\t\t(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_RSS_HASH))\n-\t\tflags |= NIX_RX_OFFLOAD_RSS_F;\n-\n-\tif (dev->rx_offloads & (RTE_ETH_RX_OFFLOAD_TCP_CKSUM |\n-\t\t\t RTE_ETH_RX_OFFLOAD_UDP_CKSUM))\n-\t\tflags |= NIX_RX_OFFLOAD_CHECKSUM_F;\n-\n-\tif (dev->rx_offloads & (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |\n-\t\t\t\tRTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM))\n-\t\tflags |= NIX_RX_OFFLOAD_CHECKSUM_F;\n-\n-\tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)\n-\t\tflags |= NIX_RX_MULTI_SEG_F;\n-\n-\tif (dev->rx_offloads & (RTE_ETH_RX_OFFLOAD_VLAN_STRIP |\n-\t\t\t\tRTE_ETH_RX_OFFLOAD_QINQ_STRIP))\n-\t\tflags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;\n-\n-\tif ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))\n-\t\tflags |= NIX_RX_OFFLOAD_TSTAMP_F;\n-\n-\tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)\n-\t\tflags |= NIX_RX_OFFLOAD_SECURITY_F;\n-\n-\tif (!dev->ptype_disable)\n-\t\tflags |= NIX_RX_OFFLOAD_PTYPE_F;\n-\n-\treturn flags;\n-}\n-\n-static uint16_t\n-nix_tx_offload_flags(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint64_t conf = dev->tx_offloads;\n-\tuint16_t flags = 0;\n-\n-\t/* Fastpath is dependent on these enums */\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_F_TX_TCP_CKSUM != (1ULL << 52));\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_F_TX_SCTP_CKSUM != (2ULL << 52));\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_F_TX_UDP_CKSUM != (3ULL << 52));\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_F_TX_IP_CKSUM != (1ULL << 54));\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_F_TX_IPV4 != (1ULL << 55));\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IP_CKSUM != (1ULL << 58));\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IPV4 != (1ULL << 59));\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_IPV6 != (1ULL << 60));\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_F_TX_OUTER_UDP_CKSUM != (1ULL << 41));\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);\n-\tRTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=\n-\t\t\t offsetof(struct rte_mbuf, buf_iova) + 8);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=\n-\t\t\t offsetof(struct rte_mbuf, buf_iova) + 16);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=\n-\t\t\t offsetof(struct rte_mbuf, ol_flags) + 12);\n-\tRTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=\n-\t\t\t offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));\n-\n-\tif (conf & RTE_ETH_TX_OFFLOAD_VLAN_INSERT ||\n-\t conf & RTE_ETH_TX_OFFLOAD_QINQ_INSERT)\n-\t\tflags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;\n-\n-\tif (conf & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM ||\n-\t conf & RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM)\n-\t\tflags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;\n-\n-\tif (conf & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM ||\n-\t conf & RTE_ETH_TX_OFFLOAD_TCP_CKSUM ||\n-\t conf & RTE_ETH_TX_OFFLOAD_UDP_CKSUM ||\n-\t conf & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM)\n-\t\tflags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;\n-\n-\tif (!(conf & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE))\n-\t\tflags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;\n-\n-\tif (conf & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)\n-\t\tflags |= NIX_TX_MULTI_SEG_F;\n-\n-\t/* Enable Inner checksum for TSO */\n-\tif (conf & RTE_ETH_TX_OFFLOAD_TCP_TSO)\n-\t\tflags |= (NIX_TX_OFFLOAD_TSO_F |\n-\t\t\t NIX_TX_OFFLOAD_L3_L4_CSUM_F);\n-\n-\t/* Enable Inner and Outer checksum for Tunnel TSO */\n-\tif (conf & (RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |\n-\t\t RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |\n-\t\t RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO))\n-\t\tflags |= (NIX_TX_OFFLOAD_TSO_F |\n-\t\t\t NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |\n-\t\t\t NIX_TX_OFFLOAD_L3_L4_CSUM_F);\n-\n-\tif (conf & RTE_ETH_TX_OFFLOAD_SECURITY)\n-\t\tflags |= NIX_TX_OFFLOAD_SECURITY_F;\n-\n-\tif ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP))\n-\t\tflags |= NIX_TX_OFFLOAD_TSTAMP_F;\n-\n-\treturn flags;\n-}\n-\n-static int\n-nix_sqb_lock(struct rte_mempool *mp)\n-{\n-\tstruct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;\n-\tstruct npa_aq_enq_req *req;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n-\treq->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);\n-\treq->ctype = NPA_AQ_CTYPE_AURA;\n-\treq->op = NPA_AQ_INSTOP_LOCK;\n-\n-\treq = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n-\tif (!req) {\n-\t\t/* The shared memory buffer can be full.\n-\t\t * Flush it and retry\n-\t\t */\n-\t\totx2_mbox_msg_send(npa_lf->mbox, 0);\n-\t\trc = otx2_mbox_wait_for_rsp(npa_lf->mbox, 0);\n-\t\tif (rc < 0) {\n-\t\t\totx2_err(\"Failed to LOCK AURA context\");\n-\t\t\treturn rc;\n-\t\t}\n-\n-\t\treq = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n-\t\tif (!req) {\n-\t\t\totx2_err(\"Failed to LOCK POOL context\");\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t}\n-\n-\treq->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);\n-\treq->ctype = NPA_AQ_CTYPE_POOL;\n-\treq->op = NPA_AQ_INSTOP_LOCK;\n-\n-\trc = otx2_mbox_process(npa_lf->mbox);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Unable to lock POOL in NDC\");\n-\t\treturn rc;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_sqb_unlock(struct rte_mempool *mp)\n-{\n-\tstruct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;\n-\tstruct npa_aq_enq_req *req;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n-\treq->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);\n-\treq->ctype = NPA_AQ_CTYPE_AURA;\n-\treq->op = NPA_AQ_INSTOP_UNLOCK;\n-\n-\treq = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n-\tif (!req) {\n-\t\t/* The shared memory buffer can be full.\n-\t\t * Flush it and retry\n-\t\t */\n-\t\totx2_mbox_msg_send(npa_lf->mbox, 0);\n-\t\trc = otx2_mbox_wait_for_rsp(npa_lf->mbox, 0);\n-\t\tif (rc < 0) {\n-\t\t\totx2_err(\"Failed to UNLOCK AURA context\");\n-\t\t\treturn rc;\n-\t\t}\n-\n-\t\treq = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n-\t\tif (!req) {\n-\t\t\totx2_err(\"Failed to UNLOCK POOL context\");\n-\t\t\treturn -ENOMEM;\n-\t\t}\n-\t}\n-\treq = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n-\treq->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);\n-\treq->ctype = NPA_AQ_CTYPE_POOL;\n-\treq->op = NPA_AQ_INSTOP_UNLOCK;\n-\n-\trc = otx2_mbox_process(npa_lf->mbox);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Unable to UNLOCK AURA in NDC\");\n-\t\treturn rc;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-void\n-otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq)\n-{\n-\tstruct rte_pktmbuf_pool_private *mbp_priv;\n-\tstruct rte_eth_dev *eth_dev;\n-\tstruct otx2_eth_dev *dev;\n-\tuint32_t buffsz;\n-\n-\teth_dev = rxq->eth_dev;\n-\tdev = otx2_eth_pmd_priv(eth_dev);\n-\n-\t/* Get rx buffer size */\n-\tmbp_priv = rte_mempool_get_priv(rxq->pool);\n-\tbuffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;\n-\n-\tif (eth_dev->data->mtu + (uint32_t)NIX_L2_OVERHEAD > buffsz) {\n-\t\tdev->rx_offloads |= RTE_ETH_RX_OFFLOAD_SCATTER;\n-\t\tdev->tx_offloads |= RTE_ETH_TX_OFFLOAD_MULTI_SEGS;\n-\n-\t\t/* Setting up the rx[tx]_offload_flags due to change\n-\t\t * in rx[tx]_offloads.\n-\t\t */\n-\t\tdev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);\n-\t\tdev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);\n-\t}\n-}\n-\n-static int\n-nix_sq_init(struct otx2_eth_txq *txq)\n-{\n-\tstruct otx2_eth_dev *dev = txq->dev;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_aq_enq_req *sq;\n-\tuint32_t rr_quantum;\n-\tuint16_t smq;\n-\tint rc;\n-\n-\tif (txq->sqb_pool->pool_id == 0)\n-\t\treturn -EINVAL;\n-\n-\trc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to get sq->smq(leaf node), rc=%d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\tsq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\tsq->qidx = txq->sq;\n-\tsq->ctype = NIX_AQ_CTYPE_SQ;\n-\tsq->op = NIX_AQ_INSTOP_INIT;\n-\tsq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);\n-\n-\tsq->sq.smq = smq;\n-\tsq->sq.smq_rr_quantum = rr_quantum;\n-\tsq->sq.default_chan = dev->tx_chan_base;\n-\tsq->sq.sqe_stype = NIX_STYPE_STF;\n-\tsq->sq.ena = 1;\n-\tif (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)\n-\t\tsq->sq.sqe_stype = NIX_STYPE_STP;\n-\tsq->sq.sqb_aura =\n-\t\tnpa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);\n-\tsq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);\n-\tsq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);\n-\tsq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);\n-\tsq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);\n-\n-\t/* Many to one reduction */\n-\tsq->sq.qint_idx = txq->sq % dev->qints;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc < 0)\n-\t\treturn rc;\n-\n-\tif (dev->lock_tx_ctx) {\n-\t\tsq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tsq->qidx = txq->sq;\n-\t\tsq->ctype = NIX_AQ_CTYPE_SQ;\n-\t\tsq->op = NIX_AQ_INSTOP_LOCK;\n-\n-\t\trc = otx2_mbox_process(mbox);\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static int\n-nix_sq_uninit(struct otx2_eth_txq *txq)\n-{\n-\tstruct otx2_eth_dev *dev = txq->dev;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct ndc_sync_op *ndc_req;\n-\tstruct nix_aq_enq_rsp *rsp;\n-\tstruct nix_aq_enq_req *aq;\n-\tuint16_t sqes_per_sqb;\n-\tvoid *sqb_buf;\n-\tint rc, count;\n-\n-\totx2_nix_dbg(\"Cleaning up sq %u\", txq->sq);\n-\n-\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\taq->qidx = txq->sq;\n-\taq->ctype = NIX_AQ_CTYPE_SQ;\n-\taq->op = NIX_AQ_INSTOP_READ;\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\t/* Check if sq is already cleaned up */\n-\tif (!rsp->sq.ena)\n-\t\treturn 0;\n-\n-\t/* Disable sq */\n-\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\taq->qidx = txq->sq;\n-\taq->ctype = NIX_AQ_CTYPE_SQ;\n-\taq->op = NIX_AQ_INSTOP_WRITE;\n-\n-\taq->sq_mask.ena = ~aq->sq_mask.ena;\n-\taq->sq.ena = 0;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tif (dev->lock_tx_ctx) {\n-\t\t/* Unlock sq */\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\taq->qidx = txq->sq;\n-\t\taq->ctype = NIX_AQ_CTYPE_SQ;\n-\t\taq->op = NIX_AQ_INSTOP_UNLOCK;\n-\n-\t\trc = otx2_mbox_process(mbox);\n-\t\tif (rc < 0)\n-\t\t\treturn rc;\n-\n-\t\tnix_sqb_unlock(txq->sqb_pool);\n-\t}\n-\n-\t/* Read SQ and free sqb's */\n-\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\taq->qidx = txq->sq;\n-\taq->ctype = NIX_AQ_CTYPE_SQ;\n-\taq->op = NIX_AQ_INSTOP_READ;\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tif (aq->sq.smq_pend)\n-\t\totx2_err(\"SQ has pending sqe's\");\n-\n-\tcount = aq->sq.sqb_count;\n-\tsqes_per_sqb = 1 << txq->sqes_per_sqb_log2;\n-\t/* Free SQB's that are used */\n-\tsqb_buf = (void *)rsp->sq.head_sqb;\n-\twhile (count) {\n-\t\tvoid *next_sqb;\n-\n-\t\tnext_sqb = *(void **)((uintptr_t)sqb_buf + (uint32_t)\n-\t\t\t\t ((sqes_per_sqb - 1) *\n-\t\t\t\t nix_sq_max_sqe_sz(txq)));\n-\t\tnpa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,\n-\t\t\t\t (uint64_t)sqb_buf);\n-\t\tsqb_buf = next_sqb;\n-\t\tcount--;\n-\t}\n-\n-\t/* Free next to use sqb */\n-\tif (rsp->sq.next_sqb)\n-\t\tnpa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,\n-\t\t\t\t rsp->sq.next_sqb);\n-\n-\t/* Sync NDC-NIX-TX for LF */\n-\tndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);\n-\tndc_req->nix_lf_tx_sync = 1;\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\totx2_err(\"Error on NDC-NIX-TX LF sync, rc %d\", rc);\n-\n-\treturn rc;\n-}\n-\n-static int\n-nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)\n-{\n-\tstruct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;\n-\tstruct npa_aq_enq_req *aura_req;\n-\n-\taura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n-\taura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);\n-\taura_req->ctype = NPA_AQ_CTYPE_AURA;\n-\taura_req->op = NPA_AQ_INSTOP_WRITE;\n-\n-\taura_req->aura.limit = nb_sqb_bufs;\n-\taura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);\n-\n-\treturn otx2_mbox_process(npa_lf->mbox);\n-}\n-\n-static int\n-nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)\n-{\n-\tstruct otx2_eth_dev *dev = txq->dev;\n-\tuint16_t sqes_per_sqb, nb_sqb_bufs;\n-\tchar name[RTE_MEMPOOL_NAMESIZE];\n-\tstruct rte_mempool_objsz sz;\n-\tstruct npa_aura_s *aura;\n-\tuint32_t tmp, blk_sz;\n-\n-\taura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);\n-\tsnprintf(name, sizeof(name), \"otx2_sqb_pool_%d_%d\", port, txq->sq);\n-\tblk_sz = dev->sqb_size;\n-\n-\tif (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)\n-\t\tsqes_per_sqb = (dev->sqb_size / 8) / 16;\n-\telse\n-\t\tsqes_per_sqb = (dev->sqb_size / 8) / 8;\n-\n-\tnb_sqb_bufs = nb_desc / sqes_per_sqb;\n-\t/* Clamp up to devarg passed SQB count */\n-\tnb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_DEF_SQB,\n-\t\t\t nb_sqb_bufs + NIX_SQB_LIST_SPACE));\n-\n-\ttxq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,\n-\t\t\t\t\t\t 0, 0, dev->node,\n-\t\t\t\t\t\t RTE_MEMPOOL_F_NO_SPREAD);\n-\ttxq->nb_sqb_bufs = nb_sqb_bufs;\n-\ttxq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);\n-\ttxq->nb_sqb_bufs_adj = nb_sqb_bufs -\n-\t\tRTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;\n-\ttxq->nb_sqb_bufs_adj =\n-\t\t(NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;\n-\n-\tif (txq->sqb_pool == NULL) {\n-\t\totx2_err(\"Failed to allocate sqe mempool\");\n-\t\tgoto fail;\n-\t}\n-\n-\tmemset(aura, 0, sizeof(*aura));\n-\taura->fc_ena = 1;\n-\taura->fc_addr = txq->fc_iova;\n-\taura->fc_hyst_bits = 0; /* Store count on all updates */\n-\tif (rte_mempool_set_ops_byname(txq->sqb_pool, \"octeontx2_npa\", aura)) {\n-\t\totx2_err(\"Failed to set ops for sqe mempool\");\n-\t\tgoto fail;\n-\t}\n-\tif (rte_mempool_populate_default(txq->sqb_pool) < 0) {\n-\t\totx2_err(\"Failed to populate sqe mempool\");\n-\t\tgoto fail;\n-\t}\n-\n-\ttmp = rte_mempool_calc_obj_size(blk_sz, RTE_MEMPOOL_F_NO_SPREAD, &sz);\n-\tif (dev->sqb_size != sz.elt_size) {\n-\t\totx2_err(\"sqe pool block size is not expected %d != %d\",\n-\t\t\t dev->sqb_size, tmp);\n-\t\tgoto fail;\n-\t}\n-\n-\tnix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);\n-\tif (dev->lock_tx_ctx)\n-\t\tnix_sqb_lock(txq->sqb_pool);\n-\n-\treturn 0;\n-fail:\n-\treturn -ENOMEM;\n-}\n-\n-void\n-otx2_nix_form_default_desc(struct otx2_eth_txq *txq)\n-{\n-\tstruct nix_send_ext_s *send_hdr_ext;\n-\tstruct nix_send_hdr_s *send_hdr;\n-\tstruct nix_send_mem_s *send_mem;\n-\tunion nix_send_sg_s *sg;\n-\n-\t/* Initialize the fields based on basic single segment packet */\n-\tmemset(&txq->cmd, 0, sizeof(txq->cmd));\n-\n-\tif (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {\n-\t\tsend_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];\n-\t\t/* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */\n-\t\tsend_hdr->w0.sizem1 = 2;\n-\n-\t\tsend_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];\n-\t\tsend_hdr_ext->w0.subdc = NIX_SUBDC_EXT;\n-\t\tif (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n-\t\t\t/* Default: one seg packet would have:\n-\t\t\t * 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)\n-\t\t\t * => 8/2 - 1 = 3\n-\t\t\t */\n-\t\t\tsend_hdr->w0.sizem1 = 3;\n-\t\t\tsend_hdr_ext->w0.tstmp = 1;\n-\n-\t\t\t/* To calculate the offset for send_mem,\n-\t\t\t * send_hdr->w0.sizem1 * 2\n-\t\t\t */\n-\t\t\tsend_mem = (struct nix_send_mem_s *)(txq->cmd +\n-\t\t\t\t\t\t(send_hdr->w0.sizem1 << 1));\n-\t\t\tsend_mem->subdc = NIX_SUBDC_MEM;\n-\t\t\tsend_mem->alg = NIX_SENDMEMALG_SETTSTMP;\n-\t\t\tsend_mem->addr = txq->dev->tstamp.tx_tstamp_iova;\n-\t\t}\n-\t\tsg = (union nix_send_sg_s *)&txq->cmd[4];\n-\t} else {\n-\t\tsend_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];\n-\t\t/* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */\n-\t\tsend_hdr->w0.sizem1 = 1;\n-\t\tsg = (union nix_send_sg_s *)&txq->cmd[2];\n-\t}\n-\n-\tsend_hdr->w0.sq = txq->sq;\n-\tsg->subdc = NIX_SUBDC_SG;\n-\tsg->segs = 1;\n-\tsg->ld_type = NIX_SENDLDTYPE_LDD;\n-\n-\trte_smp_wmb();\n-}\n-\n-static void\n-otx2_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)\n-{\n-\tstruct otx2_eth_txq *txq = eth_dev->data->tx_queues[qid];\n-\n-\tif (!txq)\n-\t\treturn;\n-\n-\totx2_nix_dbg(\"Releasing txq %u\", txq->sq);\n-\n-\t/* Flush and disable tm */\n-\totx2_nix_sq_flush_pre(txq, eth_dev->data->dev_started);\n-\n-\t/* Free sqb's and disable sq */\n-\tnix_sq_uninit(txq);\n-\n-\tif (txq->sqb_pool) {\n-\t\trte_mempool_free(txq->sqb_pool);\n-\t\ttxq->sqb_pool = NULL;\n-\t}\n-\totx2_nix_sq_flush_post(txq);\n-\trte_free(txq);\n-\teth_dev->data->tx_queues[qid] = NULL;\n-}\n-\n-\n-static int\n-otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,\n-\t\t\tuint16_t nb_desc, unsigned int socket_id,\n-\t\t\tconst struct rte_eth_txconf *tx_conf)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tconst struct rte_memzone *fc;\n-\tstruct otx2_eth_txq *txq;\n-\tuint64_t offloads;\n-\tint rc;\n-\n-\trc = -EINVAL;\n-\n-\t/* Compile time check to make sure all fast path elements in a CL */\n-\tRTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);\n-\n-\tif (tx_conf->tx_deferred_start) {\n-\t\totx2_err(\"Tx deferred start is not supported\");\n-\t\tgoto fail;\n-\t}\n-\n-\t/* Free memory prior to re-allocation if needed. */\n-\tif (eth_dev->data->tx_queues[sq] != NULL) {\n-\t\totx2_nix_dbg(\"Freeing memory prior to re-allocation %d\", sq);\n-\t\totx2_nix_tx_queue_release(eth_dev, sq);\n-\t}\n-\n-\t/* Find the expected offloads for this queue */\n-\toffloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;\n-\n-\t/* Allocating tx queue data structure */\n-\ttxq = rte_zmalloc_socket(\"otx2_ethdev TX queue\", sizeof(*txq),\n-\t\t\t\t OTX2_ALIGN, socket_id);\n-\tif (txq == NULL) {\n-\t\totx2_err(\"Failed to alloc txq=%d\", sq);\n-\t\trc = -ENOMEM;\n-\t\tgoto fail;\n-\t}\n-\ttxq->sq = sq;\n-\ttxq->dev = dev;\n-\ttxq->sqb_pool = NULL;\n-\ttxq->offloads = offloads;\n-\tdev->tx_offloads |= offloads;\n-\teth_dev->data->tx_queues[sq] = txq;\n-\n-\t/*\n-\t * Allocate memory for flow control updates from HW.\n-\t * Alloc one cache line, so that fits all FC_STYPE modes.\n-\t */\n-\tfc = rte_eth_dma_zone_reserve(eth_dev, \"fcmem\", sq,\n-\t\t\t\t OTX2_ALIGN + sizeof(struct npa_aura_s),\n-\t\t\t\t OTX2_ALIGN, dev->node);\n-\tif (fc == NULL) {\n-\t\totx2_err(\"Failed to allocate mem for fcmem\");\n-\t\trc = -ENOMEM;\n-\t\tgoto free_txq;\n-\t}\n-\ttxq->fc_iova = fc->iova;\n-\ttxq->fc_mem = fc->addr;\n-\n-\t/* Initialize the aura sqb pool */\n-\trc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to alloc sqe pool rc=%d\", rc);\n-\t\tgoto free_txq;\n-\t}\n-\n-\t/* Initialize the SQ */\n-\trc = nix_sq_init(txq);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to init sq=%d context\", sq);\n-\t\tgoto free_txq;\n-\t}\n-\n-\ttxq->fc_cache_pkts = 0;\n-\ttxq->io_addr = dev->base + NIX_LF_OP_SENDX(0);\n-\t/* Evenly distribute LMT slot for each sq */\n-\ttxq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));\n-\n-\ttxq->qconf.socket_id = socket_id;\n-\ttxq->qconf.nb_desc = nb_desc;\n-\tmemcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));\n-\n-\ttxq->lso_tun_fmt = dev->lso_tun_fmt;\n-\totx2_nix_form_default_desc(txq);\n-\n-\totx2_nix_dbg(\"sq=%d fc=%p offload=0x%\" PRIx64 \" sqb=0x%\" PRIx64 \"\"\n-\t\t \" lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d\", sq,\n-\t\t fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,\n-\t\t txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);\n-\teth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;\n-\treturn 0;\n-\n-free_txq:\n-\totx2_nix_tx_queue_release(eth_dev, sq);\n-fail:\n-\treturn rc;\n-}\n-\n-static int\n-nix_store_queue_cfg_and_then_release(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_eth_qconf *tx_qconf = NULL;\n-\tstruct otx2_eth_qconf *rx_qconf = NULL;\n-\tstruct otx2_eth_txq **txq;\n-\tstruct otx2_eth_rxq **rxq;\n-\tint i, nb_rxq, nb_txq;\n-\n-\tnb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);\n-\tnb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);\n-\n-\ttx_qconf = malloc(nb_txq * sizeof(*tx_qconf));\n-\tif (tx_qconf == NULL) {\n-\t\totx2_err(\"Failed to allocate memory for tx_qconf\");\n-\t\tgoto fail;\n-\t}\n-\n-\trx_qconf = malloc(nb_rxq * sizeof(*rx_qconf));\n-\tif (rx_qconf == NULL) {\n-\t\totx2_err(\"Failed to allocate memory for rx_qconf\");\n-\t\tgoto fail;\n-\t}\n-\n-\ttxq = (struct otx2_eth_txq **)eth_dev->data->tx_queues;\n-\tfor (i = 0; i < nb_txq; i++) {\n-\t\tif (txq[i] == NULL) {\n-\t\t\ttx_qconf[i].valid = false;\n-\t\t\totx2_info(\"txq[%d] is already released\", i);\n-\t\t\tcontinue;\n-\t\t}\n-\t\tmemcpy(&tx_qconf[i], &txq[i]->qconf, sizeof(*tx_qconf));\n-\t\ttx_qconf[i].valid = true;\n-\t\totx2_nix_tx_queue_release(eth_dev, i);\n-\t}\n-\n-\trxq = (struct otx2_eth_rxq **)eth_dev->data->rx_queues;\n-\tfor (i = 0; i < nb_rxq; i++) {\n-\t\tif (rxq[i] == NULL) {\n-\t\t\trx_qconf[i].valid = false;\n-\t\t\totx2_info(\"rxq[%d] is already released\", i);\n-\t\t\tcontinue;\n-\t\t}\n-\t\tmemcpy(&rx_qconf[i], &rxq[i]->qconf, sizeof(*rx_qconf));\n-\t\trx_qconf[i].valid = true;\n-\t\totx2_nix_rx_queue_release(eth_dev, i);\n-\t}\n-\n-\tdev->tx_qconf = tx_qconf;\n-\tdev->rx_qconf = rx_qconf;\n-\treturn 0;\n-\n-fail:\n-\tfree(tx_qconf);\n-\tfree(rx_qconf);\n-\n-\treturn -ENOMEM;\n-}\n-\n-static int\n-nix_restore_queue_cfg(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_eth_qconf *tx_qconf = dev->tx_qconf;\n-\tstruct otx2_eth_qconf *rx_qconf = dev->rx_qconf;\n-\tint rc, i, nb_rxq, nb_txq;\n-\n-\tnb_rxq = RTE_MIN(dev->configured_nb_rx_qs, eth_dev->data->nb_rx_queues);\n-\tnb_txq = RTE_MIN(dev->configured_nb_tx_qs, eth_dev->data->nb_tx_queues);\n-\n-\trc = -ENOMEM;\n-\t/* Setup tx & rx queues with previous configuration so\n-\t * that the queues can be functional in cases like ports\n-\t * are started without re configuring queues.\n-\t *\n-\t * Usual re config sequence is like below:\n-\t * port_configure() {\n-\t * if(reconfigure) {\n-\t * queue_release()\n-\t * queue_setup()\n-\t * }\n-\t * queue_configure() {\n-\t * queue_release()\n-\t * queue_setup()\n-\t * }\n-\t * }\n-\t * port_start()\n-\t *\n-\t * In some application's control path, queue_configure() would\n-\t * NOT be invoked for TXQs/RXQs in port_configure().\n-\t * In such cases, queues can be functional after start as the\n-\t * queues are already setup in port_configure().\n-\t */\n-\tfor (i = 0; i < nb_txq; i++) {\n-\t\tif (!tx_qconf[i].valid)\n-\t\t\tcontinue;\n-\t\trc = otx2_nix_tx_queue_setup(eth_dev, i, tx_qconf[i].nb_desc,\n-\t\t\t\t\t tx_qconf[i].socket_id,\n-\t\t\t\t\t &tx_qconf[i].conf.tx);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to setup tx queue rc=%d\", rc);\n-\t\t\tfor (i -= 1; i >= 0; i--)\n-\t\t\t\totx2_nix_tx_queue_release(eth_dev, i);\n-\t\t\tgoto fail;\n-\t\t}\n-\t}\n-\n-\tfree(tx_qconf); tx_qconf = NULL;\n-\n-\tfor (i = 0; i < nb_rxq; i++) {\n-\t\tif (!rx_qconf[i].valid)\n-\t\t\tcontinue;\n-\t\trc = otx2_nix_rx_queue_setup(eth_dev, i, rx_qconf[i].nb_desc,\n-\t\t\t\t\t rx_qconf[i].socket_id,\n-\t\t\t\t\t &rx_qconf[i].conf.rx,\n-\t\t\t\t\t rx_qconf[i].mempool);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to setup rx queue rc=%d\", rc);\n-\t\t\tfor (i -= 1; i >= 0; i--)\n-\t\t\t\totx2_nix_rx_queue_release(eth_dev, i);\n-\t\t\tgoto release_tx_queues;\n-\t\t}\n-\t}\n-\n-\tfree(rx_qconf); rx_qconf = NULL;\n-\n-\treturn 0;\n-\n-release_tx_queues:\n-\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++)\n-\t\totx2_nix_tx_queue_release(eth_dev, i);\n-fail:\n-\tif (tx_qconf)\n-\t\tfree(tx_qconf);\n-\tif (rx_qconf)\n-\t\tfree(rx_qconf);\n-\n-\treturn rc;\n-}\n-\n-static uint16_t\n-nix_eth_nop_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)\n-{\n-\tRTE_SET_USED(queue);\n-\tRTE_SET_USED(mbufs);\n-\tRTE_SET_USED(pkts);\n-\n-\treturn 0;\n-}\n-\n-static void\n-nix_set_nop_rxtx_function(struct rte_eth_dev *eth_dev)\n-{\n-\t/* These dummy functions are required for supporting\n-\t * some applications which reconfigure queues without\n-\t * stopping tx burst and rx burst threads(eg kni app)\n-\t * When the queues context is saved, txq/rxqs are released\n-\t * which caused app crash since rx/tx burst is still\n-\t * on different lcores\n-\t */\n-\teth_dev->tx_pkt_burst = nix_eth_nop_burst;\n-\teth_dev->rx_pkt_burst = nix_eth_nop_burst;\n-\trte_mb();\n-}\n-\n-static void\n-nix_lso_tcp(struct nix_lso_format_cfg *req, bool v4)\n-{\n-\tvolatile struct nix_lso_format *field;\n-\n-\t/* Format works only with TCP packet marked by OL3/OL4 */\n-\tfield = (volatile struct nix_lso_format *)&req->fields[0];\n-\treq->field_mask = NIX_LSO_FIELD_MASK;\n-\t/* Outer IPv4/IPv6 */\n-\tfield->layer = NIX_TXLAYER_OL3;\n-\tfield->offset = v4 ? 2 : 4;\n-\tfield->sizem1 = 1; /* 2B */\n-\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n-\tfield++;\n-\tif (v4) {\n-\t\t/* IPID field */\n-\t\tfield->layer = NIX_TXLAYER_OL3;\n-\t\tfield->offset = 4;\n-\t\tfield->sizem1 = 1;\n-\t\t/* Incremented linearly per segment */\n-\t\tfield->alg = NIX_LSOALG_ADD_SEGNUM;\n-\t\tfield++;\n-\t}\n-\n-\t/* TCP sequence number update */\n-\tfield->layer = NIX_TXLAYER_OL4;\n-\tfield->offset = 4;\n-\tfield->sizem1 = 3; /* 4 bytes */\n-\tfield->alg = NIX_LSOALG_ADD_OFFSET;\n-\tfield++;\n-\t/* TCP flags field */\n-\tfield->layer = NIX_TXLAYER_OL4;\n-\tfield->offset = 12;\n-\tfield->sizem1 = 1;\n-\tfield->alg = NIX_LSOALG_TCP_FLAGS;\n-\tfield++;\n-}\n-\n-static void\n-nix_lso_udp_tun_tcp(struct nix_lso_format_cfg *req,\n-\t\t bool outer_v4, bool inner_v4)\n-{\n-\tvolatile struct nix_lso_format *field;\n-\n-\tfield = (volatile struct nix_lso_format *)&req->fields[0];\n-\treq->field_mask = NIX_LSO_FIELD_MASK;\n-\t/* Outer IPv4/IPv6 len */\n-\tfield->layer = NIX_TXLAYER_OL3;\n-\tfield->offset = outer_v4 ? 2 : 4;\n-\tfield->sizem1 = 1; /* 2B */\n-\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n-\tfield++;\n-\tif (outer_v4) {\n-\t\t/* IPID */\n-\t\tfield->layer = NIX_TXLAYER_OL3;\n-\t\tfield->offset = 4;\n-\t\tfield->sizem1 = 1;\n-\t\t/* Incremented linearly per segment */\n-\t\tfield->alg = NIX_LSOALG_ADD_SEGNUM;\n-\t\tfield++;\n-\t}\n-\n-\t/* Outer UDP length */\n-\tfield->layer = NIX_TXLAYER_OL4;\n-\tfield->offset = 4;\n-\tfield->sizem1 = 1;\n-\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n-\tfield++;\n-\n-\t/* Inner IPv4/IPv6 */\n-\tfield->layer = NIX_TXLAYER_IL3;\n-\tfield->offset = inner_v4 ? 2 : 4;\n-\tfield->sizem1 = 1; /* 2B */\n-\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n-\tfield++;\n-\tif (inner_v4) {\n-\t\t/* IPID field */\n-\t\tfield->layer = NIX_TXLAYER_IL3;\n-\t\tfield->offset = 4;\n-\t\tfield->sizem1 = 1;\n-\t\t/* Incremented linearly per segment */\n-\t\tfield->alg = NIX_LSOALG_ADD_SEGNUM;\n-\t\tfield++;\n-\t}\n-\n-\t/* TCP sequence number update */\n-\tfield->layer = NIX_TXLAYER_IL4;\n-\tfield->offset = 4;\n-\tfield->sizem1 = 3; /* 4 bytes */\n-\tfield->alg = NIX_LSOALG_ADD_OFFSET;\n-\tfield++;\n-\n-\t/* TCP flags field */\n-\tfield->layer = NIX_TXLAYER_IL4;\n-\tfield->offset = 12;\n-\tfield->sizem1 = 1;\n-\tfield->alg = NIX_LSOALG_TCP_FLAGS;\n-\tfield++;\n-}\n-\n-static void\n-nix_lso_tun_tcp(struct nix_lso_format_cfg *req,\n-\t\tbool outer_v4, bool inner_v4)\n-{\n-\tvolatile struct nix_lso_format *field;\n-\n-\tfield = (volatile struct nix_lso_format *)&req->fields[0];\n-\treq->field_mask = NIX_LSO_FIELD_MASK;\n-\t/* Outer IPv4/IPv6 len */\n-\tfield->layer = NIX_TXLAYER_OL3;\n-\tfield->offset = outer_v4 ? 2 : 4;\n-\tfield->sizem1 = 1; /* 2B */\n-\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n-\tfield++;\n-\tif (outer_v4) {\n-\t\t/* IPID */\n-\t\tfield->layer = NIX_TXLAYER_OL3;\n-\t\tfield->offset = 4;\n-\t\tfield->sizem1 = 1;\n-\t\t/* Incremented linearly per segment */\n-\t\tfield->alg = NIX_LSOALG_ADD_SEGNUM;\n-\t\tfield++;\n-\t}\n-\n-\t/* Inner IPv4/IPv6 */\n-\tfield->layer = NIX_TXLAYER_IL3;\n-\tfield->offset = inner_v4 ? 2 : 4;\n-\tfield->sizem1 = 1; /* 2B */\n-\tfield->alg = NIX_LSOALG_ADD_PAYLEN;\n-\tfield++;\n-\tif (inner_v4) {\n-\t\t/* IPID field */\n-\t\tfield->layer = NIX_TXLAYER_IL3;\n-\t\tfield->offset = 4;\n-\t\tfield->sizem1 = 1;\n-\t\t/* Incremented linearly per segment */\n-\t\tfield->alg = NIX_LSOALG_ADD_SEGNUM;\n-\t\tfield++;\n-\t}\n-\n-\t/* TCP sequence number update */\n-\tfield->layer = NIX_TXLAYER_IL4;\n-\tfield->offset = 4;\n-\tfield->sizem1 = 3; /* 4 bytes */\n-\tfield->alg = NIX_LSOALG_ADD_OFFSET;\n-\tfield++;\n-\n-\t/* TCP flags field */\n-\tfield->layer = NIX_TXLAYER_IL4;\n-\tfield->offset = 12;\n-\tfield->sizem1 = 1;\n-\tfield->alg = NIX_LSOALG_TCP_FLAGS;\n-\tfield++;\n-}\n-\n-static int\n-nix_setup_lso_formats(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_lso_format_cfg_rsp *rsp;\n-\tstruct nix_lso_format_cfg *req;\n-\tuint8_t *fmt;\n-\tint rc;\n-\n-\t/* Skip if TSO was not requested */\n-\tif (!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F))\n-\t\treturn 0;\n-\t/*\n-\t * IPv4/TCP LSO\n-\t */\n-\treq = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tnix_lso_tcp(req, true);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tif (rsp->lso_format_idx != NIX_LSO_FORMAT_IDX_TSOV4)\n-\t\treturn -EFAULT;\n-\totx2_nix_dbg(\"tcpv4 lso fmt=%u\", rsp->lso_format_idx);\n-\n-\n-\t/*\n-\t * IPv6/TCP LSO\n-\t */\n-\treq = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tnix_lso_tcp(req, false);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tif (rsp->lso_format_idx != NIX_LSO_FORMAT_IDX_TSOV6)\n-\t\treturn -EFAULT;\n-\totx2_nix_dbg(\"tcpv6 lso fmt=%u\\n\", rsp->lso_format_idx);\n-\n-\t/*\n-\t * IPv4/UDP/TUN HDR/IPv4/TCP LSO\n-\t */\n-\treq = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tnix_lso_udp_tun_tcp(req, true, true);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tdev->lso_udp_tun_idx[NIX_LSO_TUN_V4V4] = rsp->lso_format_idx;\n-\totx2_nix_dbg(\"udp tun v4v4 fmt=%u\\n\", rsp->lso_format_idx);\n-\n-\t/*\n-\t * IPv4/UDP/TUN HDR/IPv6/TCP LSO\n-\t */\n-\treq = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tnix_lso_udp_tun_tcp(req, true, false);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tdev->lso_udp_tun_idx[NIX_LSO_TUN_V4V6] = rsp->lso_format_idx;\n-\totx2_nix_dbg(\"udp tun v4v6 fmt=%u\\n\", rsp->lso_format_idx);\n-\n-\t/*\n-\t * IPv6/UDP/TUN HDR/IPv4/TCP LSO\n-\t */\n-\treq = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tnix_lso_udp_tun_tcp(req, false, true);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tdev->lso_udp_tun_idx[NIX_LSO_TUN_V6V4] = rsp->lso_format_idx;\n-\totx2_nix_dbg(\"udp tun v6v4 fmt=%u\\n\", rsp->lso_format_idx);\n-\n-\t/*\n-\t * IPv6/UDP/TUN HDR/IPv6/TCP LSO\n-\t */\n-\treq = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tnix_lso_udp_tun_tcp(req, false, false);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tdev->lso_udp_tun_idx[NIX_LSO_TUN_V6V6] = rsp->lso_format_idx;\n-\totx2_nix_dbg(\"udp tun v6v6 fmt=%u\\n\", rsp->lso_format_idx);\n-\n-\t/*\n-\t * IPv4/TUN HDR/IPv4/TCP LSO\n-\t */\n-\treq = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tnix_lso_tun_tcp(req, true, true);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tdev->lso_tun_idx[NIX_LSO_TUN_V4V4] = rsp->lso_format_idx;\n-\totx2_nix_dbg(\"tun v4v4 fmt=%u\\n\", rsp->lso_format_idx);\n-\n-\t/*\n-\t * IPv4/TUN HDR/IPv6/TCP LSO\n-\t */\n-\treq = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tnix_lso_tun_tcp(req, true, false);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tdev->lso_tun_idx[NIX_LSO_TUN_V4V6] = rsp->lso_format_idx;\n-\totx2_nix_dbg(\"tun v4v6 fmt=%u\\n\", rsp->lso_format_idx);\n-\n-\t/*\n-\t * IPv6/TUN HDR/IPv4/TCP LSO\n-\t */\n-\treq = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tnix_lso_tun_tcp(req, false, true);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tdev->lso_tun_idx[NIX_LSO_TUN_V6V4] = rsp->lso_format_idx;\n-\totx2_nix_dbg(\"tun v6v4 fmt=%u\\n\", rsp->lso_format_idx);\n-\n-\t/*\n-\t * IPv6/TUN HDR/IPv6/TCP LSO\n-\t */\n-\treq = otx2_mbox_alloc_msg_nix_lso_format_cfg(mbox);\n-\tnix_lso_tun_tcp(req, false, false);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tdev->lso_tun_idx[NIX_LSO_TUN_V6V6] = rsp->lso_format_idx;\n-\totx2_nix_dbg(\"tun v6v6 fmt=%u\\n\", rsp->lso_format_idx);\n-\n-\t/* Save all tun formats into u64 for fast path.\n-\t * Lower 32bit has non-udp tunnel formats.\n-\t * Upper 32bit has udp tunnel formats.\n-\t */\n-\tfmt = dev->lso_tun_idx;\n-\tdev->lso_tun_fmt = ((uint64_t)fmt[NIX_LSO_TUN_V4V4] |\n-\t\t\t (uint64_t)fmt[NIX_LSO_TUN_V4V6] << 8 |\n-\t\t\t (uint64_t)fmt[NIX_LSO_TUN_V6V4] << 16 |\n-\t\t\t (uint64_t)fmt[NIX_LSO_TUN_V6V6] << 24);\n-\n-\tfmt = dev->lso_udp_tun_idx;\n-\tdev->lso_tun_fmt |= ((uint64_t)fmt[NIX_LSO_TUN_V4V4] << 32 |\n-\t\t\t (uint64_t)fmt[NIX_LSO_TUN_V4V6] << 40 |\n-\t\t\t (uint64_t)fmt[NIX_LSO_TUN_V6V4] << 48 |\n-\t\t\t (uint64_t)fmt[NIX_LSO_TUN_V6V6] << 56);\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_configure(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct rte_eth_dev_data *data = eth_dev->data;\n-\tstruct rte_eth_conf *conf = &data->dev_conf;\n-\tstruct rte_eth_rxmode *rxmode = &conf->rxmode;\n-\tstruct rte_eth_txmode *txmode = &conf->txmode;\n-\tchar ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];\n-\tstruct rte_ether_addr *ea;\n-\tuint8_t nb_rxq, nb_txq;\n-\tint rc;\n-\n-\trc = -EINVAL;\n-\n-\t/* Sanity checks */\n-\tif (rte_eal_has_hugepages() == 0) {\n-\t\totx2_err(\"Huge page is not configured\");\n-\t\tgoto fail_configure;\n-\t}\n-\n-\tif (conf->dcb_capability_en == 1) {\n-\t\totx2_err(\"dcb enable is not supported\");\n-\t\tgoto fail_configure;\n-\t}\n-\n-\tif (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {\n-\t\totx2_err(\"Flow director is not supported\");\n-\t\tgoto fail_configure;\n-\t}\n-\n-\tif (rxmode->mq_mode != RTE_ETH_MQ_RX_NONE &&\n-\t rxmode->mq_mode != RTE_ETH_MQ_RX_RSS) {\n-\t\totx2_err(\"Unsupported mq rx mode %d\", rxmode->mq_mode);\n-\t\tgoto fail_configure;\n-\t}\n-\n-\tif (txmode->mq_mode != RTE_ETH_MQ_TX_NONE) {\n-\t\totx2_err(\"Unsupported mq tx mode %d\", txmode->mq_mode);\n-\t\tgoto fail_configure;\n-\t}\n-\n-\tif (otx2_dev_is_Ax(dev) &&\n-\t (txmode->offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM) &&\n-\t ((txmode->offloads & RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||\n-\t (txmode->offloads & RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM))) {\n-\t\totx2_err(\"Outer IP and SCTP checksum unsupported\");\n-\t\tgoto fail_configure;\n-\t}\n-\n-\t/* Free the resources allocated from the previous configure */\n-\tif (dev->configured == 1) {\n-\t\totx2_eth_sec_fini(eth_dev);\n-\t\totx2_nix_rxchan_bpid_cfg(eth_dev, false);\n-\t\totx2_nix_vlan_fini(eth_dev);\n-\t\totx2_nix_mc_addr_list_uninstall(eth_dev);\n-\t\totx2_flow_free_all_resources(dev);\n-\t\toxt2_nix_unregister_queue_irqs(eth_dev);\n-\t\tif (eth_dev->data->dev_conf.intr_conf.rxq)\n-\t\t\toxt2_nix_unregister_cq_irqs(eth_dev);\n-\t\tnix_set_nop_rxtx_function(eth_dev);\n-\t\trc = nix_store_queue_cfg_and_then_release(eth_dev);\n-\t\tif (rc)\n-\t\t\tgoto fail_configure;\n-\t\totx2_nix_tm_fini(eth_dev);\n-\t\tnix_lf_free(dev);\n-\t}\n-\n-\tdev->rx_offloads = rxmode->offloads;\n-\tdev->tx_offloads = txmode->offloads;\n-\tdev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);\n-\tdev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);\n-\tdev->rss_info.rss_grps = NIX_RSS_GRPS;\n-\n-\tnb_rxq = RTE_MAX(data->nb_rx_queues, 1);\n-\tnb_txq = RTE_MAX(data->nb_tx_queues, 1);\n-\n-\t/* Alloc a nix lf */\n-\trc = nix_lf_alloc(dev, nb_rxq, nb_txq);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to init nix_lf rc=%d\", rc);\n-\t\tgoto fail_offloads;\n-\t}\n-\n-\totx2_nix_err_intr_enb_dis(eth_dev, true);\n-\totx2_nix_ras_intr_enb_dis(eth_dev, true);\n-\n-\tif (dev->ptp_en &&\n-\t dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {\n-\t\totx2_err(\"Both PTP and switch header enabled\");\n-\t\tgoto free_nix_lf;\n-\t}\n-\n-\trc = nix_lf_switch_header_type_enable(dev, true);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to enable switch type nix_lf rc=%d\", rc);\n-\t\tgoto free_nix_lf;\n-\t}\n-\n-\trc = nix_setup_lso_formats(dev);\n-\tif (rc) {\n-\t\totx2_err(\"failed to setup nix lso format fields, rc=%d\", rc);\n-\t\tgoto free_nix_lf;\n-\t}\n-\n-\t/* Configure RSS */\n-\trc = otx2_nix_rss_config(eth_dev);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to configure rss rc=%d\", rc);\n-\t\tgoto free_nix_lf;\n-\t}\n-\n-\t/* Init the default TM scheduler hierarchy */\n-\trc = otx2_nix_tm_init_default(eth_dev);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to init traffic manager rc=%d\", rc);\n-\t\tgoto free_nix_lf;\n-\t}\n-\n-\trc = otx2_nix_vlan_offload_init(eth_dev);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to init vlan offload rc=%d\", rc);\n-\t\tgoto tm_fini;\n-\t}\n-\n-\t/* Register queue IRQs */\n-\trc = oxt2_nix_register_queue_irqs(eth_dev);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to register queue interrupts rc=%d\", rc);\n-\t\tgoto vlan_fini;\n-\t}\n-\n-\t/* Register cq IRQs */\n-\tif (eth_dev->data->dev_conf.intr_conf.rxq) {\n-\t\tif (eth_dev->data->nb_rx_queues > dev->cints) {\n-\t\t\totx2_err(\"Rx interrupt cannot be enabled, rxq > %d\",\n-\t\t\t\t dev->cints);\n-\t\t\tgoto q_irq_fini;\n-\t\t}\n-\t\t/* Rx interrupt feature cannot work with vector mode because,\n-\t\t * vector mode doesn't process packets unless min 4 pkts are\n-\t\t * received, while cq interrupts are generated even for 1 pkt\n-\t\t * in the CQ.\n-\t\t */\n-\t\tdev->scalar_ena = true;\n-\n-\t\trc = oxt2_nix_register_cq_irqs(eth_dev);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to register CQ interrupts rc=%d\", rc);\n-\t\t\tgoto q_irq_fini;\n-\t\t}\n-\t}\n-\n-\t/* Configure loop back mode */\n-\trc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to configure cgx loop back mode rc=%d\", rc);\n-\t\tgoto cq_fini;\n-\t}\n-\n-\trc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to configure nix rx chan bpid cfg rc=%d\", rc);\n-\t\tgoto cq_fini;\n-\t}\n-\n-\t/* Enable security */\n-\trc = otx2_eth_sec_init(eth_dev);\n-\tif (rc)\n-\t\tgoto cq_fini;\n-\n-\trc = otx2_nix_flow_ctrl_init(eth_dev);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to init flow ctrl mode %d\", rc);\n-\t\tgoto cq_fini;\n-\t}\n-\n-\trc = otx2_nix_mc_addr_list_install(eth_dev);\n-\tif (rc < 0) {\n-\t\totx2_err(\"Failed to install mc address list rc=%d\", rc);\n-\t\tgoto sec_fini;\n-\t}\n-\n-\t/*\n-\t * Restore queue config when reconfigure followed by\n-\t * reconfigure and no queue configure invoked from application case.\n-\t */\n-\tif (dev->configured == 1) {\n-\t\trc = nix_restore_queue_cfg(eth_dev);\n-\t\tif (rc)\n-\t\t\tgoto uninstall_mc_list;\n-\t}\n-\n-\t/* Update the mac address */\n-\tea = eth_dev->data->mac_addrs;\n-\tmemcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);\n-\tif (rte_is_zero_ether_addr(ea))\n-\t\trte_eth_random_addr((uint8_t *)ea);\n-\n-\trte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);\n-\n-\t/* Apply new link configurations if changed */\n-\trc = otx2_apply_link_speed(eth_dev);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to set link configuration\");\n-\t\tgoto uninstall_mc_list;\n-\t}\n-\n-\totx2_nix_dbg(\"Configured port%d mac=%s nb_rxq=%d nb_txq=%d\"\n-\t\t\" rx_offloads=0x%\" PRIx64 \" tx_offloads=0x%\" PRIx64 \"\"\n-\t\t\" rx_flags=0x%x tx_flags=0x%x\",\n-\t\teth_dev->data->port_id, ea_fmt, nb_rxq,\n-\t\tnb_txq, dev->rx_offloads, dev->tx_offloads,\n-\t\tdev->rx_offload_flags, dev->tx_offload_flags);\n-\n-\t/* All good */\n-\tdev->configured = 1;\n-\tdev->configured_nb_rx_qs = data->nb_rx_queues;\n-\tdev->configured_nb_tx_qs = data->nb_tx_queues;\n-\treturn 0;\n-\n-uninstall_mc_list:\n-\totx2_nix_mc_addr_list_uninstall(eth_dev);\n-sec_fini:\n-\totx2_eth_sec_fini(eth_dev);\n-cq_fini:\n-\toxt2_nix_unregister_cq_irqs(eth_dev);\n-q_irq_fini:\n-\toxt2_nix_unregister_queue_irqs(eth_dev);\n-vlan_fini:\n-\totx2_nix_vlan_fini(eth_dev);\n-tm_fini:\n-\totx2_nix_tm_fini(eth_dev);\n-free_nix_lf:\n-\tnix_lf_free(dev);\n-fail_offloads:\n-\tdev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);\n-\tdev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);\n-fail_configure:\n-\tdev->configured = 0;\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)\n-{\n-\tstruct rte_eth_dev_data *data = eth_dev->data;\n-\tstruct otx2_eth_txq *txq;\n-\tint rc = -EINVAL;\n-\n-\ttxq = eth_dev->data->tx_queues[qidx];\n-\n-\tif (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)\n-\t\treturn 0;\n-\n-\trc = otx2_nix_sq_sqb_aura_fc(txq, true);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to enable sqb aura fc, txq=%u, rc=%d\",\n-\t\t\t qidx, rc);\n-\t\tgoto done;\n-\t}\n-\n-\tdata->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;\n-\n-done:\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)\n-{\n-\tstruct rte_eth_dev_data *data = eth_dev->data;\n-\tstruct otx2_eth_txq *txq;\n-\tint rc;\n-\n-\ttxq = eth_dev->data->tx_queues[qidx];\n-\n-\tif (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)\n-\t\treturn 0;\n-\n-\ttxq->fc_cache_pkts = 0;\n-\n-\trc = otx2_nix_sq_sqb_aura_fc(txq, false);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to disable sqb aura fc, txq=%u, rc=%d\",\n-\t\t\t qidx, rc);\n-\t\tgoto done;\n-\t}\n-\n-\tdata->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;\n-\n-done:\n-\treturn rc;\n-}\n-\n-static int\n-otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)\n-{\n-\tstruct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];\n-\tstruct rte_eth_dev_data *data = eth_dev->data;\n-\tint rc;\n-\n-\tif (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)\n-\t\treturn 0;\n-\n-\trc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to enable rxq=%u, rc=%d\", qidx, rc);\n-\t\tgoto done;\n-\t}\n-\n-\tdata->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;\n-\n-done:\n-\treturn rc;\n-}\n-\n-static int\n-otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)\n-{\n-\tstruct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];\n-\tstruct rte_eth_dev_data *data = eth_dev->data;\n-\tint rc;\n-\n-\tif (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)\n-\t\treturn 0;\n-\n-\trc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to disable rxq=%u, rc=%d\", qidx, rc);\n-\t\tgoto done;\n-\t}\n-\n-\tdata->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;\n-\n-done:\n-\treturn rc;\n-}\n-\n-static int\n-otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct rte_mbuf *rx_pkts[32];\n-\tstruct otx2_eth_rxq *rxq;\n-\tstruct rte_eth_link link;\n-\tint count, i, j, rc;\n-\n-\tnix_lf_switch_header_type_enable(dev, false);\n-\tnix_cgx_stop_link_event(dev);\n-\tnpc_rx_disable(dev);\n-\n-\t/* Stop rx queues and free up pkts pending */\n-\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n-\t\trc = otx2_nix_rx_queue_stop(eth_dev, i);\n-\t\tif (rc)\n-\t\t\tcontinue;\n-\n-\t\trxq = eth_dev->data->rx_queues[i];\n-\t\tcount = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);\n-\t\twhile (count) {\n-\t\t\tfor (j = 0; j < count; j++)\n-\t\t\t\trte_pktmbuf_free(rx_pkts[j]);\n-\t\t\tcount = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);\n-\t\t}\n-\t}\n-\n-\t/* Stop tx queues */\n-\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++)\n-\t\totx2_nix_tx_queue_stop(eth_dev, i);\n-\n-\t/* Bring down link status internally */\n-\tmemset(&link, 0, sizeof(link));\n-\trte_eth_linkstatus_set(eth_dev, &link);\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_dev_start(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint rc, i;\n-\n-\t/* MTU recalculate should be avoided here if PTP is enabled by PF, as\n-\t * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf\n-\t * call below.\n-\t */\n-\tif (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {\n-\t\trc = otx2_nix_recalc_mtu(eth_dev);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\t}\n-\n-\t/* Start rx queues */\n-\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n-\t\trc = otx2_nix_rx_queue_start(eth_dev, i);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\t}\n-\n-\t/* Start tx queues */\n-\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n-\t\trc = otx2_nix_tx_queue_start(eth_dev, i);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\t}\n-\n-\trc = otx2_nix_update_flow_ctrl_mode(eth_dev);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to update flow ctrl mode %d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\t/* Enable PTP if it was requested by the app or if it is already\n-\t * enabled in PF owning this VF\n-\t */\n-\tmemset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));\n-\tif ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) ||\n-\t otx2_ethdev_is_ptp_en(dev))\n-\t\totx2_nix_timesync_enable(eth_dev);\n-\telse\n-\t\totx2_nix_timesync_disable(eth_dev);\n-\n-\t/* Update VF about data off shifted by 8 bytes if PTP already\n-\t * enabled in PF owning this VF\n-\t */\n-\tif (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))\n-\t\totx2_nix_ptp_enable_vf(eth_dev);\n-\n-\tif (dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F) {\n-\t\trc = rte_mbuf_dyn_rx_timestamp_register(\n-\t\t\t\t&dev->tstamp.tstamp_dynfield_offset,\n-\t\t\t\t&dev->tstamp.rx_tstamp_dynflag);\n-\t\tif (rc != 0) {\n-\t\t\totx2_err(\"Failed to register Rx timestamp field/flag\");\n-\t\t\treturn -rte_errno;\n-\t\t}\n-\t}\n-\n-\trc = npc_rx_enable(dev);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to enable NPC rx %d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\totx2_nix_toggle_flag_link_cfg(dev, true);\n-\n-\trc = nix_cgx_start_link_event(dev);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to start cgx link event %d\", rc);\n-\t\tgoto rx_disable;\n-\t}\n-\n-\totx2_nix_toggle_flag_link_cfg(dev, false);\n-\totx2_eth_set_tx_function(eth_dev);\n-\totx2_eth_set_rx_function(eth_dev);\n-\n-\treturn 0;\n-\n-rx_disable:\n-\tnpc_rx_disable(dev);\n-\totx2_nix_toggle_flag_link_cfg(dev, false);\n-\treturn rc;\n-}\n-\n-static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);\n-static int otx2_nix_dev_close(struct rte_eth_dev *eth_dev);\n-\n-/* Initialize and register driver with DPDK Application */\n-static const struct eth_dev_ops otx2_eth_dev_ops = {\n-\t.dev_infos_get = otx2_nix_info_get,\n-\t.dev_configure = otx2_nix_configure,\n-\t.link_update = otx2_nix_link_update,\n-\t.tx_queue_setup = otx2_nix_tx_queue_setup,\n-\t.tx_queue_release = otx2_nix_tx_queue_release,\n-\t.tm_ops_get = otx2_nix_tm_ops_get,\n-\t.rx_queue_setup = otx2_nix_rx_queue_setup,\n-\t.rx_queue_release = otx2_nix_rx_queue_release,\n-\t.dev_start = otx2_nix_dev_start,\n-\t.dev_stop = otx2_nix_dev_stop,\n-\t.dev_close = otx2_nix_dev_close,\n-\t.tx_queue_start = otx2_nix_tx_queue_start,\n-\t.tx_queue_stop = otx2_nix_tx_queue_stop,\n-\t.rx_queue_start = otx2_nix_rx_queue_start,\n-\t.rx_queue_stop = otx2_nix_rx_queue_stop,\n-\t.dev_set_link_up = otx2_nix_dev_set_link_up,\n-\t.dev_set_link_down = otx2_nix_dev_set_link_down,\n-\t.dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,\n-\t.dev_ptypes_set = otx2_nix_ptypes_set,\n-\t.dev_reset = otx2_nix_dev_reset,\n-\t.stats_get = otx2_nix_dev_stats_get,\n-\t.stats_reset = otx2_nix_dev_stats_reset,\n-\t.get_reg = otx2_nix_dev_get_reg,\n-\t.mtu_set = otx2_nix_mtu_set,\n-\t.mac_addr_add = otx2_nix_mac_addr_add,\n-\t.mac_addr_remove = otx2_nix_mac_addr_del,\n-\t.mac_addr_set = otx2_nix_mac_addr_set,\n-\t.set_mc_addr_list = otx2_nix_set_mc_addr_list,\n-\t.promiscuous_enable = otx2_nix_promisc_enable,\n-\t.promiscuous_disable = otx2_nix_promisc_disable,\n-\t.allmulticast_enable = otx2_nix_allmulticast_enable,\n-\t.allmulticast_disable = otx2_nix_allmulticast_disable,\n-\t.queue_stats_mapping_set = otx2_nix_queue_stats_mapping,\n-\t.reta_update = otx2_nix_dev_reta_update,\n-\t.reta_query = otx2_nix_dev_reta_query,\n-\t.rss_hash_update = otx2_nix_rss_hash_update,\n-\t.rss_hash_conf_get = otx2_nix_rss_hash_conf_get,\n-\t.xstats_get = otx2_nix_xstats_get,\n-\t.xstats_get_names = otx2_nix_xstats_get_names,\n-\t.xstats_reset = otx2_nix_xstats_reset,\n-\t.xstats_get_by_id = otx2_nix_xstats_get_by_id,\n-\t.xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,\n-\t.rxq_info_get = otx2_nix_rxq_info_get,\n-\t.txq_info_get = otx2_nix_txq_info_get,\n-\t.rx_burst_mode_get = otx2_rx_burst_mode_get,\n-\t.tx_burst_mode_get = otx2_tx_burst_mode_get,\n-\t.tx_done_cleanup = otx2_nix_tx_done_cleanup,\n-\t.set_queue_rate_limit = otx2_nix_tm_set_queue_rate_limit,\n-\t.pool_ops_supported = otx2_nix_pool_ops_supported,\n-\t.flow_ops_get = otx2_nix_dev_flow_ops_get,\n-\t.get_module_info = otx2_nix_get_module_info,\n-\t.get_module_eeprom = otx2_nix_get_module_eeprom,\n-\t.fw_version_get = otx2_nix_fw_version_get,\n-\t.flow_ctrl_get = otx2_nix_flow_ctrl_get,\n-\t.flow_ctrl_set = otx2_nix_flow_ctrl_set,\n-\t.timesync_enable = otx2_nix_timesync_enable,\n-\t.timesync_disable = otx2_nix_timesync_disable,\n-\t.timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,\n-\t.timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,\n-\t.timesync_adjust_time = otx2_nix_timesync_adjust_time,\n-\t.timesync_read_time = otx2_nix_timesync_read_time,\n-\t.timesync_write_time = otx2_nix_timesync_write_time,\n-\t.vlan_offload_set = otx2_nix_vlan_offload_set,\n-\t.vlan_filter_set\t = otx2_nix_vlan_filter_set,\n-\t.vlan_strip_queue_set\t = otx2_nix_vlan_strip_queue_set,\n-\t.vlan_tpid_set\t\t = otx2_nix_vlan_tpid_set,\n-\t.vlan_pvid_set\t\t = otx2_nix_vlan_pvid_set,\n-\t.rx_queue_intr_enable\t = otx2_nix_rx_queue_intr_enable,\n-\t.rx_queue_intr_disable\t = otx2_nix_rx_queue_intr_disable,\n-\t.read_clock\t\t = otx2_nix_read_clock,\n-};\n-\n-static inline int\n-nix_lf_attach(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct rsrc_attach_req *req;\n-\n-\t/* Attach NIX(lf) */\n-\treq = otx2_mbox_alloc_msg_attach_resources(mbox);\n-\treq->modify = true;\n-\treq->nixlf = true;\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static inline int\n-nix_lf_get_msix_offset(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct msix_offset_rsp *msix_rsp;\n-\tint rc;\n-\n-\t/* Get NPA and NIX MSIX vector offsets */\n-\totx2_mbox_alloc_msg_msix_offset(mbox);\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&msix_rsp);\n-\n-\tdev->nix_msixoff = msix_rsp->nix_msixoff;\n-\n-\treturn rc;\n-}\n-\n-static inline int\n-otx2_eth_dev_lf_detach(struct otx2_mbox *mbox)\n-{\n-\tstruct rsrc_detach_req *req;\n-\n-\treq = otx2_mbox_alloc_msg_detach_resources(mbox);\n-\n-\t/* Detach all except npa lf */\n-\treq->partial = true;\n-\treq->nixlf = true;\n-\treq->sso = true;\n-\treq->ssow = true;\n-\treq->timlfs = true;\n-\treq->cptlfs = true;\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static bool\n-otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)\n-{\n-\tif (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||\n-\t pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)\n-\t\treturn true;\n-\treturn false;\n-}\n-\n-static inline uint64_t\n-nix_get_blkaddr(struct otx2_eth_dev *dev)\n-{\n-\tuint64_t reg;\n-\n-\t/* Reading the discovery register to know which NIX is the LF\n-\t * attached to.\n-\t */\n-\treg = otx2_read64(dev->bar2 +\n-\t\t\t RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_NIX0));\n-\n-\treturn reg & 0x1FFULL ? RVU_BLOCK_ADDR_NIX0 : RVU_BLOCK_ADDR_NIX1;\n-}\n-\n-static int\n-otx2_eth_dev_init(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct rte_pci_device *pci_dev;\n-\tint rc, max_entries;\n-\n-\teth_dev->dev_ops = &otx2_eth_dev_ops;\n-\teth_dev->rx_queue_count = otx2_nix_rx_queue_count;\n-\teth_dev->rx_descriptor_status = otx2_nix_rx_descriptor_status;\n-\teth_dev->tx_descriptor_status = otx2_nix_tx_descriptor_status;\n-\n-\t/* For secondary processes, the primary has done all the work */\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n-\t\t/* Setup callbacks for secondary process */\n-\t\totx2_eth_set_tx_function(eth_dev);\n-\t\totx2_eth_set_rx_function(eth_dev);\n-\t\treturn 0;\n-\t}\n-\n-\tpci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\n-\trte_eth_copy_pci_info(eth_dev, pci_dev);\n-\teth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;\n-\n-\t/* Zero out everything after OTX2_DEV to allow proper dev_reset() */\n-\tmemset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -\n-\t\toffsetof(struct otx2_eth_dev, otx2_eth_dev_data_start));\n-\n-\t/* Parse devargs string */\n-\trc = otx2_ethdev_parse_devargs(eth_dev->device->devargs, dev);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to parse devargs rc=%d\", rc);\n-\t\tgoto error;\n-\t}\n-\n-\tif (!dev->mbox_active) {\n-\t\t/* Initialize the base otx2_dev object\n-\t\t * only if already present\n-\t\t */\n-\t\trc = otx2_dev_init(pci_dev, dev);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to initialize otx2_dev rc=%d\", rc);\n-\t\t\tgoto error;\n-\t\t}\n-\t}\n-\tif (otx2_eth_dev_is_sdp(pci_dev))\n-\t\tdev->sdp_link = true;\n-\telse\n-\t\tdev->sdp_link = false;\n-\t/* Device generic callbacks */\n-\tdev->ops = &otx2_dev_ops;\n-\tdev->eth_dev = eth_dev;\n-\n-\t/* Grab the NPA LF if required */\n-\trc = otx2_npa_lf_init(pci_dev, dev);\n-\tif (rc)\n-\t\tgoto otx2_dev_uninit;\n-\n-\tdev->configured = 0;\n-\tdev->drv_inited = true;\n-\tdev->ptype_disable = 0;\n-\tdev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);\n-\n-\t/* Attach NIX LF */\n-\trc = nix_lf_attach(dev);\n-\tif (rc)\n-\t\tgoto otx2_npa_uninit;\n-\n-\tdev->base = dev->bar2 + (nix_get_blkaddr(dev) << 20);\n-\n-\t/* Get NIX MSIX offset */\n-\trc = nix_lf_get_msix_offset(dev);\n-\tif (rc)\n-\t\tgoto otx2_npa_uninit;\n-\n-\t/* Register LF irq handlers */\n-\trc = otx2_nix_register_irqs(eth_dev);\n-\tif (rc)\n-\t\tgoto mbox_detach;\n-\n-\t/* Get maximum number of supported MAC entries */\n-\tmax_entries = otx2_cgx_mac_max_entries_get(dev);\n-\tif (max_entries < 0) {\n-\t\totx2_err(\"Failed to get max entries for mac addr\");\n-\t\trc = -ENOTSUP;\n-\t\tgoto unregister_irq;\n-\t}\n-\n-\t/* For VFs, returned max_entries will be 0. But to keep default MAC\n-\t * address, one entry must be allocated. So setting up to 1.\n-\t */\n-\tif (max_entries == 0)\n-\t\tmax_entries = 1;\n-\n-\teth_dev->data->mac_addrs = rte_zmalloc(\"mac_addr\", max_entries *\n-\t\t\t\t\t RTE_ETHER_ADDR_LEN, 0);\n-\tif (eth_dev->data->mac_addrs == NULL) {\n-\t\totx2_err(\"Failed to allocate memory for mac addr\");\n-\t\trc = -ENOMEM;\n-\t\tgoto unregister_irq;\n-\t}\n-\n-\tdev->max_mac_entries = max_entries;\n-\n-\trc = otx2_nix_mac_addr_get(eth_dev, dev->mac_addr);\n-\tif (rc)\n-\t\tgoto free_mac_addrs;\n-\n-\t/* Update the mac address */\n-\tmemcpy(eth_dev->data->mac_addrs, dev->mac_addr, RTE_ETHER_ADDR_LEN);\n-\n-\t/* Also sync same MAC address to CGX table */\n-\totx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);\n-\n-\t/* Initialize the tm data structures */\n-\totx2_nix_tm_conf_init(eth_dev);\n-\n-\tdev->tx_offload_capa = nix_get_tx_offload_capa(dev);\n-\tdev->rx_offload_capa = nix_get_rx_offload_capa(dev);\n-\n-\tif (otx2_dev_is_96xx_A0(dev) ||\n-\t otx2_dev_is_95xx_Ax(dev)) {\n-\t\tdev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;\n-\t\tdev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;\n-\t}\n-\n-\t/* Create security ctx */\n-\trc = otx2_eth_sec_ctx_create(eth_dev);\n-\tif (rc)\n-\t\tgoto free_mac_addrs;\n-\tdev->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_SECURITY;\n-\tdev->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_SECURITY;\n-\n-\t/* Initialize rte-flow */\n-\trc = otx2_flow_init(dev);\n-\tif (rc)\n-\t\tgoto sec_ctx_destroy;\n-\n-\totx2_nix_mc_filter_init(dev);\n-\n-\totx2_nix_dbg(\"Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%\" PRIx64\n-\t\t \" rxoffload_capa=0x%\" PRIx64 \" txoffload_capa=0x%\" PRIx64,\n-\t\t eth_dev->data->port_id, dev->pf, dev->vf,\n-\t\t OTX2_ETH_DEV_PMD_VERSION, dev->nix_msixoff, dev->hwcap,\n-\t\t dev->rx_offload_capa, dev->tx_offload_capa);\n-\treturn 0;\n-\n-sec_ctx_destroy:\n-\totx2_eth_sec_ctx_destroy(eth_dev);\n-free_mac_addrs:\n-\trte_free(eth_dev->data->mac_addrs);\n-unregister_irq:\n-\totx2_nix_unregister_irqs(eth_dev);\n-mbox_detach:\n-\totx2_eth_dev_lf_detach(dev->mbox);\n-otx2_npa_uninit:\n-\totx2_npa_lf_fini();\n-otx2_dev_uninit:\n-\totx2_dev_fini(pci_dev, dev);\n-error:\n-\totx2_err(\"Failed to init nix eth_dev rc=%d\", rc);\n-\treturn rc;\n-}\n-\n-static int\n-otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct rte_pci_device *pci_dev;\n-\tint rc, i;\n-\n-\t/* Nothing to be done for secondary processes */\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn 0;\n-\n-\t/* Clear the flag since we are closing down */\n-\tdev->configured = 0;\n-\n-\t/* Disable nix bpid config */\n-\totx2_nix_rxchan_bpid_cfg(eth_dev, false);\n-\n-\tnpc_rx_disable(dev);\n-\n-\t/* Disable vlan offloads */\n-\totx2_nix_vlan_fini(eth_dev);\n-\n-\t/* Disable other rte_flow entries */\n-\totx2_flow_fini(dev);\n-\n-\t/* Free multicast filter list */\n-\totx2_nix_mc_filter_fini(dev);\n-\n-\t/* Disable PTP if already enabled */\n-\tif (otx2_ethdev_is_ptp_en(dev))\n-\t\totx2_nix_timesync_disable(eth_dev);\n-\n-\tnix_cgx_stop_link_event(dev);\n-\n-\t/* Unregister the dev ops, this is required to stop VFs from\n-\t * receiving link status updates on exit path.\n-\t */\n-\tdev->ops = NULL;\n-\n-\t/* Free up SQs */\n-\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++)\n-\t\totx2_nix_tx_queue_release(eth_dev, i);\n-\teth_dev->data->nb_tx_queues = 0;\n-\n-\t/* Free up RQ's and CQ's */\n-\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++)\n-\t\totx2_nix_rx_queue_release(eth_dev, i);\n-\teth_dev->data->nb_rx_queues = 0;\n-\n-\t/* Free tm resources */\n-\trc = otx2_nix_tm_fini(eth_dev);\n-\tif (rc)\n-\t\totx2_err(\"Failed to cleanup tm, rc=%d\", rc);\n-\n-\t/* Unregister queue irqs */\n-\toxt2_nix_unregister_queue_irqs(eth_dev);\n-\n-\t/* Unregister cq irqs */\n-\tif (eth_dev->data->dev_conf.intr_conf.rxq)\n-\t\toxt2_nix_unregister_cq_irqs(eth_dev);\n-\n-\trc = nix_lf_free(dev);\n-\tif (rc)\n-\t\totx2_err(\"Failed to free nix lf, rc=%d\", rc);\n-\n-\trc = otx2_npa_lf_fini();\n-\tif (rc)\n-\t\totx2_err(\"Failed to cleanup npa lf, rc=%d\", rc);\n-\n-\t/* Disable security */\n-\totx2_eth_sec_fini(eth_dev);\n-\n-\t/* Destroy security ctx */\n-\totx2_eth_sec_ctx_destroy(eth_dev);\n-\n-\trte_free(eth_dev->data->mac_addrs);\n-\teth_dev->data->mac_addrs = NULL;\n-\tdev->drv_inited = false;\n-\n-\tpci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\totx2_nix_unregister_irqs(eth_dev);\n-\n-\trc = otx2_eth_dev_lf_detach(dev->mbox);\n-\tif (rc)\n-\t\totx2_err(\"Failed to detach resources, rc=%d\", rc);\n-\n-\t/* Check if mbox close is needed */\n-\tif (!mbox_close)\n-\t\treturn 0;\n-\n-\tif (otx2_npa_lf_active(dev) || otx2_dev_active_vfs(dev)) {\n-\t\t/* Will be freed later by PMD */\n-\t\teth_dev->data->dev_private = NULL;\n-\t\treturn 0;\n-\t}\n-\n-\totx2_dev_fini(pci_dev, dev);\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_dev_close(struct rte_eth_dev *eth_dev)\n-{\n-\totx2_eth_dev_uninit(eth_dev, true);\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)\n-{\n-\tint rc;\n-\n-\trc = otx2_eth_dev_uninit(eth_dev, false);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\treturn otx2_eth_dev_init(eth_dev);\n-}\n-\n-static int\n-nix_remove(struct rte_pci_device *pci_dev)\n-{\n-\tstruct rte_eth_dev *eth_dev;\n-\tstruct otx2_idev_cfg *idev;\n-\tstruct otx2_dev *otx2_dev;\n-\tint rc;\n-\n-\teth_dev = rte_eth_dev_allocated(pci_dev->device.name);\n-\tif (eth_dev) {\n-\t\t/* Cleanup eth dev */\n-\t\trc = otx2_eth_dev_uninit(eth_dev, true);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\n-\t\trte_eth_dev_release_port(eth_dev);\n-\t}\n-\n-\t/* Nothing to be done for secondary processes */\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n-\t\treturn 0;\n-\n-\t/* Check for common resources */\n-\tidev = otx2_intra_dev_get_cfg();\n-\tif (!idev || !idev->npa_lf || idev->npa_lf->pci_dev != pci_dev)\n-\t\treturn 0;\n-\n-\totx2_dev = container_of(idev->npa_lf, struct otx2_dev, npalf);\n-\n-\tif (otx2_npa_lf_active(otx2_dev) || otx2_dev_active_vfs(otx2_dev))\n-\t\tgoto exit;\n-\n-\t/* Safe to cleanup mbox as no more users */\n-\totx2_dev_fini(pci_dev, otx2_dev);\n-\trte_free(otx2_dev);\n-\treturn 0;\n-\n-exit:\n-\totx2_info(\"%s: common resource in use by other devices\", pci_dev->name);\n-\treturn -EAGAIN;\n-}\n-\n-static int\n-nix_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n-{\n-\tint rc;\n-\n-\tRTE_SET_USED(pci_drv);\n-\n-\trc = rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct otx2_eth_dev),\n-\t\t\t\t\t otx2_eth_dev_init);\n-\n-\t/* On error on secondary, recheck if port exists in primary or\n-\t * in mid of detach state.\n-\t */\n-\tif (rte_eal_process_type() != RTE_PROC_PRIMARY && rc)\n-\t\tif (!rte_eth_dev_allocated(pci_dev->device.name))\n-\t\t\treturn 0;\n-\treturn rc;\n-}\n-\n-static const struct rte_pci_id pci_nix_map[] = {\n-\t{\n-\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF)\n-\t},\n-\t{\n-\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF)\n-\t},\n-\t{\n-\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n-\t\t\t PCI_DEVID_OCTEONTX2_RVU_AF_VF)\n-\t},\n-\t{\n-\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n-\t\t\t PCI_DEVID_OCTEONTX2_RVU_SDP_PF)\n-\t},\n-\t{\n-\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n-\t\t\t PCI_DEVID_OCTEONTX2_RVU_SDP_VF)\n-\t},\n-\t{\n-\t\t.vendor_id = 0,\n-\t},\n-};\n-\n-static struct rte_pci_driver pci_nix = {\n-\t.id_table = pci_nix_map,\n-\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |\n-\t\t\tRTE_PCI_DRV_INTR_LSC,\n-\t.probe = nix_probe,\n-\t.remove = nix_remove,\n-};\n-\n-RTE_PMD_REGISTER_PCI(OCTEONTX2_PMD, pci_nix);\n-RTE_PMD_REGISTER_PCI_TABLE(OCTEONTX2_PMD, pci_nix_map);\n-RTE_PMD_REGISTER_KMOD_DEP(OCTEONTX2_PMD, \"vfio-pci\");\ndiff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h\ndeleted file mode 100644\nindex a5282c6c12..0000000000\n--- a/drivers/net/octeontx2/otx2_ethdev.h\n+++ /dev/null\n@@ -1,619 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_ETHDEV_H__\n-#define __OTX2_ETHDEV_H__\n-\n-#include <math.h>\n-#include <stdint.h>\n-\n-#include <rte_common.h>\n-#include <rte_ethdev.h>\n-#include <rte_kvargs.h>\n-#include <rte_mbuf.h>\n-#include <rte_mempool.h>\n-#include <rte_security_driver.h>\n-#include <rte_spinlock.h>\n-#include <rte_string_fns.h>\n-#include <rte_time.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_dev.h\"\n-#include \"otx2_flow.h\"\n-#include \"otx2_irq.h\"\n-#include \"otx2_mempool.h\"\n-#include \"otx2_rx.h\"\n-#include \"otx2_tm.h\"\n-#include \"otx2_tx.h\"\n-\n-#define OTX2_ETH_DEV_PMD_VERSION\t\"1.0\"\n-\n-/* Ethdev HWCAP and Fixup flags. Use from MSB bits to avoid conflict with dev */\n-\n-/* Minimum CQ size should be 4K */\n-#define OTX2_FIXUP_F_MIN_4K_Q\t\tBIT_ULL(63)\n-#define otx2_ethdev_fixup_is_min_4k_q(dev)\t\\\n-\t\t\t\t((dev)->hwcap & OTX2_FIXUP_F_MIN_4K_Q)\n-/* Limit CQ being full */\n-#define OTX2_FIXUP_F_LIMIT_CQ_FULL\tBIT_ULL(62)\n-#define otx2_ethdev_fixup_is_limit_cq_full(dev) \\\n-\t\t\t\t((dev)->hwcap & OTX2_FIXUP_F_LIMIT_CQ_FULL)\n-\n-/* Used for struct otx2_eth_dev::flags */\n-#define OTX2_LINK_CFG_IN_PROGRESS_F\tBIT_ULL(0)\n-\n-/* VLAN tag inserted by NIX_TX_VTAG_ACTION.\n- * In Tx space is always reserved for this in FRS.\n- */\n-#define NIX_MAX_VTAG_INS\t\t2\n-#define NIX_MAX_VTAG_ACT_SIZE\t\t(4 * NIX_MAX_VTAG_INS)\n-\n-/* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */\n-#define NIX_L2_OVERHEAD \\\n-\t(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)\n-#define NIX_L2_MAX_LEN \\\n-\t(RTE_ETHER_MTU + NIX_L2_OVERHEAD)\n-\n-/* HW config of frame size doesn't include FCS */\n-#define NIX_MAX_HW_FRS\t\t\t9212\n-#define NIX_MIN_HW_FRS\t\t\t60\n-\n-/* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */\n-#define NIX_MAX_FRS\t\\\n-\t(NIX_MAX_HW_FRS + RTE_ETHER_CRC_LEN - NIX_MAX_VTAG_ACT_SIZE)\n-\n-#define NIX_MIN_FRS\t\\\n-\t(NIX_MIN_HW_FRS + RTE_ETHER_CRC_LEN)\n-\n-#define NIX_MAX_MTU\t\\\n-\t(NIX_MAX_FRS - NIX_L2_OVERHEAD)\n-\n-#define NIX_MAX_SQB\t\t\t512\n-#define NIX_DEF_SQB\t\t\t16\n-#define NIX_MIN_SQB\t\t\t8\n-#define NIX_SQB_LIST_SPACE\t\t2\n-#define NIX_RSS_RETA_SIZE_MAX\t\t256\n-/* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/\n-#define NIX_RSS_GRPS\t\t\t8\n-#define NIX_HASH_KEY_SIZE\t\t48 /* 352 Bits */\n-#define NIX_RSS_RETA_SIZE\t\t64\n-#define\tNIX_RX_MIN_DESC\t\t\t16\n-#define NIX_RX_MIN_DESC_ALIGN\t\t16\n-#define NIX_RX_NB_SEG_MAX\t\t6\n-#define NIX_CQ_ENTRY_SZ\t\t\t128\n-#define NIX_CQ_ALIGN\t\t\t512\n-#define NIX_SQB_LOWER_THRESH\t\t70\n-#define LMT_SLOT_MASK\t\t\t0x7f\n-#define NIX_RX_DEFAULT_RING_SZ\t\t4096\n-\n-/* If PTP is enabled additional SEND MEM DESC is required which\n- * takes 2 words, hence max 7 iova address are possible\n- */\n-#if defined(RTE_LIBRTE_IEEE1588)\n-#define NIX_TX_NB_SEG_MAX\t\t7\n-#else\n-#define NIX_TX_NB_SEG_MAX\t\t9\n-#endif\n-\n-#define NIX_TX_MSEG_SG_DWORDS\t\t\t\t\\\n-\t((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3)\t\\\n-\t + NIX_TX_NB_SEG_MAX)\n-\n-/* Apply BP/DROP when CQ is 95% full */\n-#define NIX_CQ_THRESH_LEVEL\t(5 * 256 / 100)\n-#define NIX_CQ_FULL_ERRATA_SKID\t(1024ull * 256)\n-\n-#define CQ_OP_STAT_OP_ERR\t63\n-#define CQ_OP_STAT_CQ_ERR\t46\n-\n-#define OP_ERR\t\t\tBIT_ULL(CQ_OP_STAT_OP_ERR)\n-#define CQ_ERR\t\t\tBIT_ULL(CQ_OP_STAT_CQ_ERR)\n-\n-#define CQ_CQE_THRESH_DEFAULT\t0x1ULL /* IRQ triggered when\n-\t\t\t\t\t* NIX_LF_CINTX_CNT[QCOUNT]\n-\t\t\t\t\t* crosses this value\n-\t\t\t\t\t*/\n-#define CQ_TIMER_THRESH_DEFAULT\t0xAULL /* ~1usec i.e (0xA * 100nsec) */\n-#define CQ_TIMER_THRESH_MAX 255\n-\n-#define NIX_RSS_L3_L4_SRC_DST (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY \\\n-\t\t\t\t| RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)\n-\n-#define NIX_RSS_OFFLOAD\t\t(RTE_ETH_RSS_PORT | RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP |\\\n-\t\t\t\t RTE_ETH_RSS_TCP | RTE_ETH_RSS_SCTP | \\\n-\t\t\t\t RTE_ETH_RSS_TUNNEL | RTE_ETH_RSS_L2_PAYLOAD | \\\n-\t\t\t\t NIX_RSS_L3_L4_SRC_DST | RTE_ETH_RSS_LEVEL_MASK | \\\n-\t\t\t\t RTE_ETH_RSS_C_VLAN)\n-\n-#define NIX_TX_OFFLOAD_CAPA ( \\\n-\tRTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE\t| \\\n-\tRTE_ETH_TX_OFFLOAD_MT_LOCKFREE\t| \\\n-\tRTE_ETH_TX_OFFLOAD_VLAN_INSERT\t| \\\n-\tRTE_ETH_TX_OFFLOAD_QINQ_INSERT\t| \\\n-\tRTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM\t| \\\n-\tRTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM\t| \\\n-\tRTE_ETH_TX_OFFLOAD_TCP_CKSUM\t| \\\n-\tRTE_ETH_TX_OFFLOAD_UDP_CKSUM\t| \\\n-\tRTE_ETH_TX_OFFLOAD_SCTP_CKSUM\t| \\\n-\tRTE_ETH_TX_OFFLOAD_TCP_TSO\t\t| \\\n-\tRTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO | \\\n-\tRTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO | \\\n-\tRTE_ETH_TX_OFFLOAD_GRE_TNL_TSO\t| \\\n-\tRTE_ETH_TX_OFFLOAD_MULTI_SEGS\t| \\\n-\tRTE_ETH_TX_OFFLOAD_IPV4_CKSUM)\n-\n-#define NIX_RX_OFFLOAD_CAPA ( \\\n-\tRTE_ETH_RX_OFFLOAD_CHECKSUM\t\t| \\\n-\tRTE_ETH_RX_OFFLOAD_SCTP_CKSUM\t| \\\n-\tRTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | \\\n-\tRTE_ETH_RX_OFFLOAD_SCATTER\t\t| \\\n-\tRTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM\t| \\\n-\tRTE_ETH_RX_OFFLOAD_VLAN_STRIP\t| \\\n-\tRTE_ETH_RX_OFFLOAD_VLAN_FILTER\t| \\\n-\tRTE_ETH_RX_OFFLOAD_QINQ_STRIP\t| \\\n-\tRTE_ETH_RX_OFFLOAD_TIMESTAMP\t| \\\n-\tRTE_ETH_RX_OFFLOAD_RSS_HASH)\n-\n-#define NIX_DEFAULT_RSS_CTX_GROUP 0\n-#define NIX_DEFAULT_RSS_MCAM_IDX -1\n-\n-#define otx2_ethdev_is_ptp_en(dev)\t((dev)->ptp_en)\n-\n-#define NIX_TIMESYNC_TX_CMD_LEN\t\t8\n-/* Additional timesync values. */\n-#define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL\n-\n-#define OCTEONTX2_PMD\t\t\tnet_octeontx2\n-\n-#define otx2_ethdev_is_same_driver(dev) \\\n-\t(strcmp((dev)->device->driver->name, RTE_STR(OCTEONTX2_PMD)) == 0)\n-\n-enum nix_q_size_e {\n-\tnix_q_size_16,\t/* 16 entries */\n-\tnix_q_size_64,\t/* 64 entries */\n-\tnix_q_size_256,\n-\tnix_q_size_1K,\n-\tnix_q_size_4K,\n-\tnix_q_size_16K,\n-\tnix_q_size_64K,\n-\tnix_q_size_256K,\n-\tnix_q_size_1M,\t/* Million entries */\n-\tnix_q_size_max\n-};\n-\n-enum nix_lso_tun_type {\n-\tNIX_LSO_TUN_V4V4,\n-\tNIX_LSO_TUN_V4V6,\n-\tNIX_LSO_TUN_V6V4,\n-\tNIX_LSO_TUN_V6V6,\n-\tNIX_LSO_TUN_MAX,\n-};\n-\n-struct otx2_qint {\n-\tstruct rte_eth_dev *eth_dev;\n-\tuint8_t qintx;\n-};\n-\n-struct otx2_rss_info {\n-\tuint64_t nix_rss;\n-\tuint32_t flowkey_cfg;\n-\tuint16_t rss_size;\n-\tuint8_t rss_grps;\n-\tuint8_t alg_idx; /* Selected algo index */\n-\tuint16_t ind_tbl[NIX_RSS_RETA_SIZE_MAX];\n-\tuint8_t key[NIX_HASH_KEY_SIZE];\n-};\n-\n-struct otx2_eth_qconf {\n-\tunion {\n-\t\tstruct rte_eth_txconf tx;\n-\t\tstruct rte_eth_rxconf rx;\n-\t} conf;\n-\tvoid *mempool;\n-\tuint32_t socket_id;\n-\tuint16_t nb_desc;\n-\tuint8_t valid;\n-};\n-\n-struct otx2_fc_info {\n-\tenum rte_eth_fc_mode mode; /**< Link flow control mode */\n-\tuint8_t rx_pause;\n-\tuint8_t tx_pause;\n-\tuint8_t chan_cnt;\n-\tuint16_t bpid[NIX_MAX_CHAN];\n-};\n-\n-struct vlan_mkex_info {\n-\tstruct npc_xtract_info la_xtract;\n-\tstruct npc_xtract_info lb_xtract;\n-\tuint64_t lb_lt_offset;\n-};\n-\n-struct mcast_entry {\n-\tstruct rte_ether_addr mcast_mac;\n-\tuint16_t mcam_index;\n-\tTAILQ_ENTRY(mcast_entry) next;\n-};\n-\n-TAILQ_HEAD(otx2_nix_mc_filter_tbl, mcast_entry);\n-\n-struct vlan_entry {\n-\tuint32_t mcam_idx;\n-\tuint16_t vlan_id;\n-\tTAILQ_ENTRY(vlan_entry) next;\n-};\n-\n-TAILQ_HEAD(otx2_vlan_filter_tbl, vlan_entry);\n-\n-struct otx2_vlan_info {\n-\tstruct otx2_vlan_filter_tbl fltr_tbl;\n-\t/* MKEX layer info */\n-\tstruct mcam_entry def_tx_mcam_ent;\n-\tstruct mcam_entry def_rx_mcam_ent;\n-\tstruct vlan_mkex_info mkex;\n-\t/* Default mcam entry that matches vlan packets */\n-\tuint32_t def_rx_mcam_idx;\n-\tuint32_t def_tx_mcam_idx;\n-\t/* MCAM entry that matches double vlan packets */\n-\tuint32_t qinq_mcam_idx;\n-\t/* Indices of tx_vtag def registers */\n-\tuint32_t outer_vlan_idx;\n-\tuint32_t inner_vlan_idx;\n-\tuint16_t outer_vlan_tpid;\n-\tuint16_t inner_vlan_tpid;\n-\tuint16_t pvid;\n-\t/* QinQ entry allocated before default one */\n-\tuint8_t qinq_before_def;\n-\tuint8_t pvid_insert_on;\n-\t/* Rx vtag action type */\n-\tuint8_t vtag_type_idx;\n-\tuint8_t filter_on;\n-\tuint8_t strip_on;\n-\tuint8_t qinq_on;\n-\tuint8_t promisc_on;\n-};\n-\n-struct otx2_eth_dev {\n-\tOTX2_DEV; /* Base class */\n-\tRTE_MARKER otx2_eth_dev_data_start;\n-\tuint16_t sqb_size;\n-\tuint16_t rx_chan_base;\n-\tuint16_t tx_chan_base;\n-\tuint8_t rx_chan_cnt;\n-\tuint8_t tx_chan_cnt;\n-\tuint8_t lso_tsov4_idx;\n-\tuint8_t lso_tsov6_idx;\n-\tuint8_t lso_udp_tun_idx[NIX_LSO_TUN_MAX];\n-\tuint8_t lso_tun_idx[NIX_LSO_TUN_MAX];\n-\tuint64_t lso_tun_fmt;\n-\tuint8_t mac_addr[RTE_ETHER_ADDR_LEN];\n-\tuint8_t mkex_pfl_name[MKEX_NAME_LEN];\n-\tuint8_t max_mac_entries;\n-\tbool dmac_filter_enable;\n-\tuint8_t lf_tx_stats;\n-\tuint8_t lf_rx_stats;\n-\tuint8_t lock_rx_ctx;\n-\tuint8_t lock_tx_ctx;\n-\tuint16_t flags;\n-\tuint16_t cints;\n-\tuint16_t qints;\n-\tuint8_t configured;\n-\tuint8_t configured_qints;\n-\tuint8_t configured_cints;\n-\tuint8_t configured_nb_rx_qs;\n-\tuint8_t configured_nb_tx_qs;\n-\tuint8_t ptype_disable;\n-\tuint16_t nix_msixoff;\n-\tuintptr_t base;\n-\tuintptr_t lmt_addr;\n-\tuint16_t scalar_ena;\n-\tuint16_t rss_tag_as_xor;\n-\tuint16_t max_sqb_count;\n-\tuint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */\n-\tuint64_t rx_offloads;\n-\tuint16_t tx_offload_flags; /* Selected Tx offload flags(NIX_TX_*_F) */\n-\tuint64_t tx_offloads;\n-\tuint64_t rx_offload_capa;\n-\tuint64_t tx_offload_capa;\n-\tstruct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];\n-\tstruct otx2_qint cints_mem[RTE_MAX_QUEUES_PER_PORT];\n-\tuint16_t txschq[NIX_TXSCH_LVL_CNT];\n-\tuint16_t txschq_contig[NIX_TXSCH_LVL_CNT];\n-\tuint16_t txschq_index[NIX_TXSCH_LVL_CNT];\n-\tuint16_t txschq_contig_index[NIX_TXSCH_LVL_CNT];\n-\t/* Dis-contiguous queues */\n-\tuint16_t txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];\n-\t/* Contiguous queues */\n-\tuint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];\n-\tuint16_t otx2_tm_root_lvl;\n-\tuint16_t link_cfg_lvl;\n-\tuint16_t tm_flags;\n-\tuint16_t tm_leaf_cnt;\n-\tuint64_t tm_rate_min;\n-\tstruct otx2_nix_tm_node_list node_list;\n-\tstruct otx2_nix_tm_shaper_profile_list shaper_profile_list;\n-\tstruct otx2_rss_info rss_info;\n-\tstruct otx2_fc_info fc_info;\n-\tuint32_t txmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n-\tuint32_t rxmap[RTE_ETHDEV_QUEUE_STAT_CNTRS];\n-\tstruct otx2_npc_flow_info npc_flow;\n-\tstruct otx2_vlan_info vlan_info;\n-\tstruct otx2_eth_qconf *tx_qconf;\n-\tstruct otx2_eth_qconf *rx_qconf;\n-\tstruct rte_eth_dev *eth_dev;\n-\teth_rx_burst_t rx_pkt_burst_no_offload;\n-\t/* PTP counters */\n-\tbool ptp_en;\n-\tstruct otx2_timesync_info tstamp;\n-\tstruct rte_timecounter systime_tc;\n-\tstruct rte_timecounter rx_tstamp_tc;\n-\tstruct rte_timecounter tx_tstamp_tc;\n-\tdouble clk_freq_mult;\n-\tuint64_t clk_delta;\n-\tbool mc_tbl_set;\n-\tstruct otx2_nix_mc_filter_tbl mc_fltr_tbl;\n-\tbool sdp_link; /* SDP flag */\n-\t/* Inline IPsec params */\n-\tuint16_t ipsec_in_max_spi;\n-\trte_spinlock_t ipsec_tbl_lock;\n-\tuint8_t duplex;\n-\tuint32_t speed;\n-} __rte_cache_aligned;\n-\n-struct otx2_eth_txq {\n-\tuint64_t cmd[8];\n-\tint64_t fc_cache_pkts;\n-\tuint64_t *fc_mem;\n-\tvoid *lmt_addr;\n-\trte_iova_t io_addr;\n-\trte_iova_t fc_iova;\n-\tuint16_t sqes_per_sqb_log2;\n-\tint16_t nb_sqb_bufs_adj;\n-\tuint64_t lso_tun_fmt;\n-\tRTE_MARKER slow_path_start;\n-\tuint16_t nb_sqb_bufs;\n-\tuint16_t sq;\n-\tuint64_t offloads;\n-\tstruct otx2_eth_dev *dev;\n-\tstruct rte_mempool *sqb_pool;\n-\tstruct otx2_eth_qconf qconf;\n-} __rte_cache_aligned;\n-\n-struct otx2_eth_rxq {\n-\tuint64_t mbuf_initializer;\n-\tuint64_t data_off;\n-\tuintptr_t desc;\n-\tvoid *lookup_mem;\n-\tuintptr_t cq_door;\n-\tuint64_t wdata;\n-\tint64_t *cq_status;\n-\tuint32_t head;\n-\tuint32_t qmask;\n-\tuint32_t available;\n-\tuint16_t rq;\n-\tstruct otx2_timesync_info *tstamp;\n-\tRTE_MARKER slow_path_start;\n-\tuint64_t aura;\n-\tuint64_t offloads;\n-\tuint32_t qlen;\n-\tstruct rte_mempool *pool;\n-\tenum nix_q_size_e qsize;\n-\tstruct rte_eth_dev *eth_dev;\n-\tstruct otx2_eth_qconf qconf;\n-\tuint16_t cq_drop;\n-} __rte_cache_aligned;\n-\n-static inline struct otx2_eth_dev *\n-otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)\n-{\n-\treturn eth_dev->data->dev_private;\n-}\n-\n-/* Ops */\n-int otx2_nix_info_get(struct rte_eth_dev *eth_dev,\n-\t\t struct rte_eth_dev_info *dev_info);\n-int otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev,\n-\t\t\t const struct rte_flow_ops **ops);\n-int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,\n-\t\t\t size_t fw_size);\n-int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_dev_module_info *modinfo);\n-int otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_dev_eeprom_info *info);\n-int otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool);\n-void otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,\n-\t\t\t struct rte_eth_rxq_info *qinfo);\n-void otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,\n-\t\t\t struct rte_eth_txq_info *qinfo);\n-int otx2_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,\n-\t\t\t struct rte_eth_burst_mode *mode);\n-int otx2_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,\n-\t\t\t struct rte_eth_burst_mode *mode);\n-uint32_t otx2_nix_rx_queue_count(void *rx_queue);\n-int otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt);\n-int otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset);\n-int otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset);\n-\n-void otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en);\n-int otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev);\n-int otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev);\n-int otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev);\n-int otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev);\n-int otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx);\n-int otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx);\n-uint64_t otx2_nix_rxq_mbuf_setup(struct otx2_eth_dev *dev, uint16_t port_id);\n-\n-/* Multicast filter APIs */\n-void otx2_nix_mc_filter_init(struct otx2_eth_dev *dev);\n-void otx2_nix_mc_filter_fini(struct otx2_eth_dev *dev);\n-int otx2_nix_mc_addr_list_install(struct rte_eth_dev *eth_dev);\n-int otx2_nix_mc_addr_list_uninstall(struct rte_eth_dev *eth_dev);\n-int otx2_nix_set_mc_addr_list(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_ether_addr *mc_addr_set,\n-\t\t\t uint32_t nb_mc_addr);\n-\n-/* MTU */\n-int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);\n-int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);\n-void otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq);\n-\n-\n-/* Link */\n-void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);\n-int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);\n-void otx2_eth_dev_link_status_update(struct otx2_dev *dev,\n-\t\t\t\t struct cgx_link_user_info *link);\n-void otx2_eth_dev_link_status_get(struct otx2_dev *dev,\n-\t\t\t\t struct cgx_link_user_info *link);\n-int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);\n-int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);\n-int otx2_apply_link_speed(struct rte_eth_dev *eth_dev);\n-\n-/* IRQ */\n-int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);\n-int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);\n-int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);\n-void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);\n-void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);\n-void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);\n-void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);\n-void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);\n-\n-int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,\n-\t\t\t\t uint16_t rx_queue_id);\n-int otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,\n-\t\t\t\t uint16_t rx_queue_id);\n-\n-/* Debug */\n-int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);\n-int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_dev_reg_info *regs);\n-int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);\n-void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);\n-void otx2_nix_tm_dump(struct otx2_eth_dev *dev);\n-\n-/* Stats */\n-int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_stats *stats);\n-int otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev);\n-\n-int otx2_nix_queue_stats_mapping(struct rte_eth_dev *dev,\n-\t\t\t\t uint16_t queue_id, uint8_t stat_idx,\n-\t\t\t\t uint8_t is_rx);\n-int otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,\n-\t\t\tstruct rte_eth_xstat *xstats, unsigned int n);\n-int otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_xstat_name *xstats_names,\n-\t\t\t unsigned int limit);\n-int otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev);\n-\n-int otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev,\n-\t\t\t const uint64_t *ids,\n-\t\t\t uint64_t *values, unsigned int n);\n-int otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,\n-\t\t\t\t const uint64_t *ids,\n-\t\t\t\t struct rte_eth_xstat_name *xstats_names,\n-\t\t\t\t unsigned int limit);\n-\n-/* RSS */\n-void otx2_nix_rss_set_key(struct otx2_eth_dev *dev,\n-\t\t\t uint8_t *key, uint32_t key_len);\n-uint32_t otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev,\n-\t\t\t\tuint64_t ethdev_rss, uint8_t rss_level);\n-int otx2_rss_set_hf(struct otx2_eth_dev *dev,\n-\t\t uint32_t flowkey_cfg, uint8_t *alg_idx,\n-\t\t uint8_t group, int mcam_index);\n-int otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev, uint8_t group,\n-\t\t\t uint16_t *ind_tbl);\n-int otx2_nix_rss_config(struct rte_eth_dev *eth_dev);\n-\n-int otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n-\t\t\t uint16_t reta_size);\n-int otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n-\t\t\t uint16_t reta_size);\n-int otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_rss_conf *rss_conf);\n-\n-int otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_rss_conf *rss_conf);\n-\n-/* CGX */\n-int otx2_cgx_rxtx_start(struct otx2_eth_dev *dev);\n-int otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev);\n-int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_ether_addr *addr);\n-\n-/* Flow Control */\n-int otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev);\n-\n-int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_fc_conf *fc_conf);\n-\n-int otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_fc_conf *fc_conf);\n-\n-int otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb);\n-\n-int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev);\n-\n-/* VLAN */\n-int otx2_nix_vlan_offload_init(struct rte_eth_dev *eth_dev);\n-int otx2_nix_vlan_fini(struct rte_eth_dev *eth_dev);\n-int otx2_nix_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);\n-void otx2_nix_vlan_update_promisc(struct rte_eth_dev *eth_dev, int enable);\n-int otx2_nix_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,\n-\t\t\t int on);\n-void otx2_nix_vlan_strip_queue_set(struct rte_eth_dev *dev,\n-\t\t\t\t uint16_t queue, int on);\n-int otx2_nix_vlan_tpid_set(struct rte_eth_dev *eth_dev,\n-\t\t\t enum rte_vlan_type type, uint16_t tpid);\n-int otx2_nix_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);\n-\n-/* Lookup configuration */\n-void *otx2_nix_fastpath_lookup_mem_get(void);\n-\n-/* PTYPES */\n-const uint32_t *otx2_nix_supported_ptypes_get(struct rte_eth_dev *dev);\n-int otx2_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask);\n-\n-/* Mac address handling */\n-int otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_ether_addr *addr);\n-int otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr);\n-int otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_ether_addr *addr,\n-\t\t\t uint32_t index, uint32_t pool);\n-void otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index);\n-int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);\n-\n-/* Devargs */\n-int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,\n-\t\t\t struct otx2_eth_dev *dev);\n-\n-/* Rx and Tx routines */\n-void otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev);\n-void otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev);\n-void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);\n-\n-/* Timesync - PTP routines */\n-int otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev);\n-int otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev);\n-int otx2_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,\n-\t\t\t\t\tstruct timespec *timestamp,\n-\t\t\t\t\tuint32_t flags);\n-int otx2_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,\n-\t\t\t\t\tstruct timespec *timestamp);\n-int otx2_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);\n-int otx2_nix_timesync_write_time(struct rte_eth_dev *eth_dev,\n-\t\t\t\t const struct timespec *ts);\n-int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev,\n-\t\t\t\tstruct timespec *ts);\n-int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en);\n-int otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *time);\n-int otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev);\n-void otx2_nix_ptp_enable_vf(struct rte_eth_dev *eth_dev);\n-\n-#endif /* __OTX2_ETHDEV_H__ */\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_debug.c b/drivers/net/octeontx2/otx2_ethdev_debug.c\ndeleted file mode 100644\nindex 6d951bc7e2..0000000000\n--- a/drivers/net/octeontx2/otx2_ethdev_debug.c\n+++ /dev/null\n@@ -1,811 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_ethdev.h\"\n-\n-#define nix_dump(fmt, ...) fprintf(stderr, fmt \"\\n\", ##__VA_ARGS__)\n-#define NIX_REG_INFO(reg) {reg, #reg}\n-#define NIX_REG_NAME_SZ 48\n-\n-struct nix_lf_reg_info {\n-\tuint32_t offset;\n-\tconst char *name;\n-};\n-\n-static const struct\n-nix_lf_reg_info nix_lf_reg[] = {\n-\tNIX_REG_INFO(NIX_LF_RX_SECRETX(0)),\n-\tNIX_REG_INFO(NIX_LF_RX_SECRETX(1)),\n-\tNIX_REG_INFO(NIX_LF_RX_SECRETX(2)),\n-\tNIX_REG_INFO(NIX_LF_RX_SECRETX(3)),\n-\tNIX_REG_INFO(NIX_LF_RX_SECRETX(4)),\n-\tNIX_REG_INFO(NIX_LF_RX_SECRETX(5)),\n-\tNIX_REG_INFO(NIX_LF_CFG),\n-\tNIX_REG_INFO(NIX_LF_GINT),\n-\tNIX_REG_INFO(NIX_LF_GINT_W1S),\n-\tNIX_REG_INFO(NIX_LF_GINT_ENA_W1C),\n-\tNIX_REG_INFO(NIX_LF_GINT_ENA_W1S),\n-\tNIX_REG_INFO(NIX_LF_ERR_INT),\n-\tNIX_REG_INFO(NIX_LF_ERR_INT_W1S),\n-\tNIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1C),\n-\tNIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1S),\n-\tNIX_REG_INFO(NIX_LF_RAS),\n-\tNIX_REG_INFO(NIX_LF_RAS_W1S),\n-\tNIX_REG_INFO(NIX_LF_RAS_ENA_W1C),\n-\tNIX_REG_INFO(NIX_LF_RAS_ENA_W1S),\n-\tNIX_REG_INFO(NIX_LF_SQ_OP_ERR_DBG),\n-\tNIX_REG_INFO(NIX_LF_MNQ_ERR_DBG),\n-\tNIX_REG_INFO(NIX_LF_SEND_ERR_DBG),\n-};\n-\n-static int\n-nix_lf_get_reg_count(struct otx2_eth_dev *dev)\n-{\n-\tint reg_count = 0;\n-\n-\treg_count = RTE_DIM(nix_lf_reg);\n-\t/* NIX_LF_TX_STATX */\n-\treg_count += dev->lf_tx_stats;\n-\t/* NIX_LF_RX_STATX */\n-\treg_count += dev->lf_rx_stats;\n-\t/* NIX_LF_QINTX_CNT*/\n-\treg_count += dev->qints;\n-\t/* NIX_LF_QINTX_INT */\n-\treg_count += dev->qints;\n-\t/* NIX_LF_QINTX_ENA_W1S */\n-\treg_count += dev->qints;\n-\t/* NIX_LF_QINTX_ENA_W1C */\n-\treg_count += dev->qints;\n-\t/* NIX_LF_CINTX_CNT */\n-\treg_count += dev->cints;\n-\t/* NIX_LF_CINTX_WAIT */\n-\treg_count += dev->cints;\n-\t/* NIX_LF_CINTX_INT */\n-\treg_count += dev->cints;\n-\t/* NIX_LF_CINTX_INT_W1S */\n-\treg_count += dev->cints;\n-\t/* NIX_LF_CINTX_ENA_W1S */\n-\treg_count += dev->cints;\n-\t/* NIX_LF_CINTX_ENA_W1C */\n-\treg_count += dev->cints;\n-\n-\treturn reg_count;\n-}\n-\n-int\n-otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data)\n-{\n-\tuintptr_t nix_lf_base = dev->base;\n-\tbool dump_stdout;\n-\tuint64_t reg;\n-\tuint32_t i;\n-\n-\tdump_stdout = data ? 0 : 1;\n-\n-\tfor (i = 0; i < RTE_DIM(nix_lf_reg); i++) {\n-\t\treg = otx2_read64(nix_lf_base + nix_lf_reg[i].offset);\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s = 0x%\" PRIx64,\n-\t\t\t\t nix_lf_reg[i].name, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\n-\t/* NIX_LF_TX_STATX */\n-\tfor (i = 0; i < dev->lf_tx_stats; i++) {\n-\t\treg = otx2_read64(nix_lf_base + NIX_LF_TX_STATX(i));\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n-\t\t\t\t \"NIX_LF_TX_STATX\", i, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\n-\t/* NIX_LF_RX_STATX */\n-\tfor (i = 0; i < dev->lf_rx_stats; i++) {\n-\t\treg = otx2_read64(nix_lf_base + NIX_LF_RX_STATX(i));\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n-\t\t\t\t \"NIX_LF_RX_STATX\", i, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\n-\t/* NIX_LF_QINTX_CNT*/\n-\tfor (i = 0; i < dev->qints; i++) {\n-\t\treg = otx2_read64(nix_lf_base + NIX_LF_QINTX_CNT(i));\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n-\t\t\t\t \"NIX_LF_QINTX_CNT\", i, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\n-\t/* NIX_LF_QINTX_INT */\n-\tfor (i = 0; i < dev->qints; i++) {\n-\t\treg = otx2_read64(nix_lf_base + NIX_LF_QINTX_INT(i));\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n-\t\t\t\t \"NIX_LF_QINTX_INT\", i, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\n-\t/* NIX_LF_QINTX_ENA_W1S */\n-\tfor (i = 0; i < dev->qints; i++) {\n-\t\treg = otx2_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1S(i));\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n-\t\t\t\t \"NIX_LF_QINTX_ENA_W1S\", i, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\n-\t/* NIX_LF_QINTX_ENA_W1C */\n-\tfor (i = 0; i < dev->qints; i++) {\n-\t\treg = otx2_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1C(i));\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n-\t\t\t\t \"NIX_LF_QINTX_ENA_W1C\", i, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\n-\t/* NIX_LF_CINTX_CNT */\n-\tfor (i = 0; i < dev->cints; i++) {\n-\t\treg = otx2_read64(nix_lf_base + NIX_LF_CINTX_CNT(i));\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n-\t\t\t\t \"NIX_LF_CINTX_CNT\", i, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\n-\t/* NIX_LF_CINTX_WAIT */\n-\tfor (i = 0; i < dev->cints; i++) {\n-\t\treg = otx2_read64(nix_lf_base + NIX_LF_CINTX_WAIT(i));\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n-\t\t\t\t \"NIX_LF_CINTX_WAIT\", i, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\n-\t/* NIX_LF_CINTX_INT */\n-\tfor (i = 0; i < dev->cints; i++) {\n-\t\treg = otx2_read64(nix_lf_base + NIX_LF_CINTX_INT(i));\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n-\t\t\t\t \"NIX_LF_CINTX_INT\", i, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\n-\t/* NIX_LF_CINTX_INT_W1S */\n-\tfor (i = 0; i < dev->cints; i++) {\n-\t\treg = otx2_read64(nix_lf_base + NIX_LF_CINTX_INT_W1S(i));\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n-\t\t\t\t \"NIX_LF_CINTX_INT_W1S\", i, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\n-\t/* NIX_LF_CINTX_ENA_W1S */\n-\tfor (i = 0; i < dev->cints; i++) {\n-\t\treg = otx2_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1S(i));\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n-\t\t\t\t \"NIX_LF_CINTX_ENA_W1S\", i, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\n-\t/* NIX_LF_CINTX_ENA_W1C */\n-\tfor (i = 0; i < dev->cints; i++) {\n-\t\treg = otx2_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1C(i));\n-\t\tif (dump_stdout && reg)\n-\t\t\tnix_dump(\"%32s_%d = 0x%\" PRIx64,\n-\t\t\t\t \"NIX_LF_CINTX_ENA_W1C\", i, reg);\n-\t\tif (data)\n-\t\t\t*data++ = reg;\n-\t}\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev, struct rte_dev_reg_info *regs)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint64_t *data = regs->data;\n-\n-\tif (data == NULL) {\n-\t\tregs->length = nix_lf_get_reg_count(dev);\n-\t\tregs->width = 8;\n-\t\treturn 0;\n-\t}\n-\n-\tif (!regs->length ||\n-\t regs->length == (uint32_t)nix_lf_get_reg_count(dev)) {\n-\t\totx2_nix_reg_dump(dev, data);\n-\t\treturn 0;\n-\t}\n-\n-\treturn -ENOTSUP;\n-}\n-\n-static inline void\n-nix_lf_sq_dump(__otx2_io struct nix_sq_ctx_s *ctx)\n-{\n-\tnix_dump(\"W0: sqe_way_mask \\t\\t%d\\nW0: cq \\t\\t\\t\\t%d\",\n-\t\t ctx->sqe_way_mask, ctx->cq);\n-\tnix_dump(\"W0: sdp_mcast \\t\\t\\t%d\\nW0: substream \\t\\t\\t0x%03x\",\n-\t\t ctx->sdp_mcast, ctx->substream);\n-\tnix_dump(\"W0: qint_idx \\t\\t\\t%d\\nW0: ena \\t\\t\\t%d\\n\",\n-\t\t ctx->qint_idx, ctx->ena);\n-\n-\tnix_dump(\"W1: sqb_count \\t\\t\\t%d\\nW1: default_chan \\t\\t%d\",\n-\t\t ctx->sqb_count, ctx->default_chan);\n-\tnix_dump(\"W1: smq_rr_quantum \\t\\t%d\\nW1: sso_ena \\t\\t\\t%d\",\n-\t\t ctx->smq_rr_quantum, ctx->sso_ena);\n-\tnix_dump(\"W1: xoff \\t\\t\\t%d\\nW1: cq_ena \\t\\t\\t%d\\nW1: smq\\t\\t\\t\\t%d\\n\",\n-\t\t ctx->xoff, ctx->cq_ena, ctx->smq);\n-\n-\tnix_dump(\"W2: sqe_stype \\t\\t\\t%d\\nW2: sq_int_ena \\t\\t\\t%d\",\n-\t\t ctx->sqe_stype, ctx->sq_int_ena);\n-\tnix_dump(\"W2: sq_int \\t\\t\\t%d\\nW2: sqb_aura \\t\\t\\t%d\",\n-\t\t ctx->sq_int, ctx->sqb_aura);\n-\tnix_dump(\"W2: smq_rr_count \\t\\t%d\\n\", ctx->smq_rr_count);\n-\n-\tnix_dump(\"W3: smq_next_sq_vld\\t\\t%d\\nW3: smq_pend\\t\\t\\t%d\",\n-\t\t ctx->smq_next_sq_vld, ctx->smq_pend);\n-\tnix_dump(\"W3: smenq_next_sqb_vld \\t%d\\nW3: head_offset\\t\\t\\t%d\",\n-\t\t ctx->smenq_next_sqb_vld, ctx->head_offset);\n-\tnix_dump(\"W3: smenq_offset\\t\\t%d\\nW3: tail_offset \\t\\t%d\",\n-\t\t ctx->smenq_offset, ctx->tail_offset);\n-\tnix_dump(\"W3: smq_lso_segnum \\t\\t%d\\nW3: smq_next_sq \\t\\t%d\",\n-\t\t ctx->smq_lso_segnum, ctx->smq_next_sq);\n-\tnix_dump(\"W3: mnq_dis \\t\\t\\t%d\\nW3: lmt_dis \\t\\t\\t%d\",\n-\t\t ctx->mnq_dis, ctx->lmt_dis);\n-\tnix_dump(\"W3: cq_limit\\t\\t\\t%d\\nW3: max_sqe_size\\t\\t%d\\n\",\n-\t\t ctx->cq_limit, ctx->max_sqe_size);\n-\n-\tnix_dump(\"W4: next_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->next_sqb);\n-\tnix_dump(\"W5: tail_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->tail_sqb);\n-\tnix_dump(\"W6: smenq_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->smenq_sqb);\n-\tnix_dump(\"W7: smenq_next_sqb \\t\\t0x%\" PRIx64 \"\", ctx->smenq_next_sqb);\n-\tnix_dump(\"W8: head_sqb \\t\\t\\t0x%\" PRIx64 \"\", ctx->head_sqb);\n-\n-\tnix_dump(\"W9: vfi_lso_vld \\t\\t%d\\nW9: vfi_lso_vlan1_ins_ena\\t%d\",\n-\t\t ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);\n-\tnix_dump(\"W9: vfi_lso_vlan0_ins_ena\\t%d\\nW9: vfi_lso_mps\\t\\t\\t%d\",\n-\t\t ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);\n-\tnix_dump(\"W9: vfi_lso_sb \\t\\t\\t%d\\nW9: vfi_lso_sizem1\\t\\t%d\",\n-\t\t ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);\n-\tnix_dump(\"W9: vfi_lso_total\\t\\t%d\", ctx->vfi_lso_total);\n-\n-\tnix_dump(\"W10: scm_lso_rem \\t\\t0x%\" PRIx64 \"\",\n-\t\t (uint64_t)ctx->scm_lso_rem);\n-\tnix_dump(\"W11: octs \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->octs);\n-\tnix_dump(\"W12: pkts \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->pkts);\n-\tnix_dump(\"W14: dropped_octs \\t\\t0x%\" PRIx64 \"\",\n-\t\t (uint64_t)ctx->drop_octs);\n-\tnix_dump(\"W15: dropped_pkts \\t\\t0x%\" PRIx64 \"\",\n-\t\t (uint64_t)ctx->drop_pkts);\n-}\n-\n-static inline void\n-nix_lf_rq_dump(__otx2_io struct nix_rq_ctx_s *ctx)\n-{\n-\tnix_dump(\"W0: wqe_aura \\t\\t\\t%d\\nW0: substream \\t\\t\\t0x%03x\",\n-\t\t ctx->wqe_aura, ctx->substream);\n-\tnix_dump(\"W0: cq \\t\\t\\t\\t%d\\nW0: ena_wqwd \\t\\t\\t%d\",\n-\t\t ctx->cq, ctx->ena_wqwd);\n-\tnix_dump(\"W0: ipsech_ena \\t\\t\\t%d\\nW0: sso_ena \\t\\t\\t%d\",\n-\t\t ctx->ipsech_ena, ctx->sso_ena);\n-\tnix_dump(\"W0: ena \\t\\t\\t%d\\n\", ctx->ena);\n-\n-\tnix_dump(\"W1: lpb_drop_ena \\t\\t%d\\nW1: spb_drop_ena \\t\\t%d\",\n-\t\t ctx->lpb_drop_ena, ctx->spb_drop_ena);\n-\tnix_dump(\"W1: xqe_drop_ena \\t\\t%d\\nW1: wqe_caching \\t\\t%d\",\n-\t\t ctx->xqe_drop_ena, ctx->wqe_caching);\n-\tnix_dump(\"W1: pb_caching \\t\\t\\t%d\\nW1: sso_tt \\t\\t\\t%d\",\n-\t\t ctx->pb_caching, ctx->sso_tt);\n-\tnix_dump(\"W1: sso_grp \\t\\t\\t%d\\nW1: lpb_aura \\t\\t\\t%d\",\n-\t\t ctx->sso_grp, ctx->lpb_aura);\n-\tnix_dump(\"W1: spb_aura \\t\\t\\t%d\\n\", ctx->spb_aura);\n-\n-\tnix_dump(\"W2: xqe_hdr_split \\t\\t%d\\nW2: xqe_imm_copy \\t\\t%d\",\n-\t\t ctx->xqe_hdr_split, ctx->xqe_imm_copy);\n-\tnix_dump(\"W2: xqe_imm_size \\t\\t%d\\nW2: later_skip \\t\\t\\t%d\",\n-\t\t ctx->xqe_imm_size, ctx->later_skip);\n-\tnix_dump(\"W2: first_skip \\t\\t\\t%d\\nW2: lpb_sizem1 \\t\\t\\t%d\",\n-\t\t ctx->first_skip, ctx->lpb_sizem1);\n-\tnix_dump(\"W2: spb_ena \\t\\t\\t%d\\nW2: wqe_skip \\t\\t\\t%d\",\n-\t\t ctx->spb_ena, ctx->wqe_skip);\n-\tnix_dump(\"W2: spb_sizem1 \\t\\t\\t%d\\n\", ctx->spb_sizem1);\n-\n-\tnix_dump(\"W3: spb_pool_pass \\t\\t%d\\nW3: spb_pool_drop \\t\\t%d\",\n-\t\t ctx->spb_pool_pass, ctx->spb_pool_drop);\n-\tnix_dump(\"W3: spb_aura_pass \\t\\t%d\\nW3: spb_aura_drop \\t\\t%d\",\n-\t\t ctx->spb_aura_pass, ctx->spb_aura_drop);\n-\tnix_dump(\"W3: wqe_pool_pass \\t\\t%d\\nW3: wqe_pool_drop \\t\\t%d\",\n-\t\t ctx->wqe_pool_pass, ctx->wqe_pool_drop);\n-\tnix_dump(\"W3: xqe_pass \\t\\t\\t%d\\nW3: xqe_drop \\t\\t\\t%d\\n\",\n-\t\t ctx->xqe_pass, ctx->xqe_drop);\n-\n-\tnix_dump(\"W4: qint_idx \\t\\t\\t%d\\nW4: rq_int_ena \\t\\t\\t%d\",\n-\t\t ctx->qint_idx, ctx->rq_int_ena);\n-\tnix_dump(\"W4: rq_int \\t\\t\\t%d\\nW4: lpb_pool_pass \\t\\t%d\",\n-\t\t ctx->rq_int, ctx->lpb_pool_pass);\n-\tnix_dump(\"W4: lpb_pool_drop \\t\\t%d\\nW4: lpb_aura_pass \\t\\t%d\",\n-\t\t ctx->lpb_pool_drop, ctx->lpb_aura_pass);\n-\tnix_dump(\"W4: lpb_aura_drop \\t\\t%d\\n\", ctx->lpb_aura_drop);\n-\n-\tnix_dump(\"W5: flow_tagw \\t\\t\\t%d\\nW5: bad_utag \\t\\t\\t%d\",\n-\t\t ctx->flow_tagw, ctx->bad_utag);\n-\tnix_dump(\"W5: good_utag \\t\\t\\t%d\\nW5: ltag \\t\\t\\t%d\\n\",\n-\t\t ctx->good_utag, ctx->ltag);\n-\n-\tnix_dump(\"W6: octs \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->octs);\n-\tnix_dump(\"W7: pkts \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->pkts);\n-\tnix_dump(\"W8: drop_octs \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->drop_octs);\n-\tnix_dump(\"W9: drop_pkts \\t\\t\\t0x%\" PRIx64 \"\", (uint64_t)ctx->drop_pkts);\n-\tnix_dump(\"W10: re_pkts \\t\\t\\t0x%\" PRIx64 \"\\n\", (uint64_t)ctx->re_pkts);\n-}\n-\n-static inline void\n-nix_lf_cq_dump(__otx2_io struct nix_cq_ctx_s *ctx)\n-{\n-\tnix_dump(\"W0: base \\t\\t\\t0x%\" PRIx64 \"\\n\", ctx->base);\n-\n-\tnix_dump(\"W1: wrptr \\t\\t\\t%\" PRIx64 \"\", (uint64_t)ctx->wrptr);\n-\tnix_dump(\"W1: avg_con \\t\\t\\t%d\\nW1: cint_idx \\t\\t\\t%d\",\n-\t\t ctx->avg_con, ctx->cint_idx);\n-\tnix_dump(\"W1: cq_err \\t\\t\\t%d\\nW1: qint_idx \\t\\t\\t%d\",\n-\t\t ctx->cq_err, ctx->qint_idx);\n-\tnix_dump(\"W1: bpid \\t\\t\\t%d\\nW1: bp_ena \\t\\t\\t%d\\n\",\n-\t\t ctx->bpid, ctx->bp_ena);\n-\n-\tnix_dump(\"W2: update_time \\t\\t%d\\nW2: avg_level \\t\\t\\t%d\",\n-\t\t ctx->update_time, ctx->avg_level);\n-\tnix_dump(\"W2: head \\t\\t\\t%d\\nW2: tail \\t\\t\\t%d\\n\",\n-\t\t ctx->head, ctx->tail);\n-\n-\tnix_dump(\"W3: cq_err_int_ena \\t\\t%d\\nW3: cq_err_int \\t\\t\\t%d\",\n-\t\t ctx->cq_err_int_ena, ctx->cq_err_int);\n-\tnix_dump(\"W3: qsize \\t\\t\\t%d\\nW3: caching \\t\\t\\t%d\",\n-\t\t ctx->qsize, ctx->caching);\n-\tnix_dump(\"W3: substream \\t\\t\\t0x%03x\\nW3: ena \\t\\t\\t%d\",\n-\t\t ctx->substream, ctx->ena);\n-\tnix_dump(\"W3: drop_ena \\t\\t\\t%d\\nW3: drop \\t\\t\\t%d\",\n-\t\t ctx->drop_ena, ctx->drop);\n-\tnix_dump(\"W3: bp \\t\\t\\t\\t%d\\n\", ctx->bp);\n-}\n-\n-int\n-otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint rc, q, rq = eth_dev->data->nb_rx_queues;\n-\tint sq = eth_dev->data->nb_tx_queues;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct npa_aq_enq_rsp *npa_rsp;\n-\tstruct npa_aq_enq_req *npa_aq;\n-\tstruct otx2_npa_lf *npa_lf;\n-\tstruct nix_aq_enq_rsp *rsp;\n-\tstruct nix_aq_enq_req *aq;\n-\n-\tnpa_lf = otx2_npa_lf_obj_get();\n-\n-\tfor (q = 0; q < rq; q++) {\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\taq->qidx = q;\n-\t\taq->ctype = NIX_AQ_CTYPE_CQ;\n-\t\taq->op = NIX_AQ_INSTOP_READ;\n-\n-\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to get cq context\");\n-\t\t\tgoto fail;\n-\t\t}\n-\t\tnix_dump(\"============== port=%d cq=%d ===============\",\n-\t\t\t eth_dev->data->port_id, q);\n-\t\tnix_lf_cq_dump(&rsp->cq);\n-\t}\n-\n-\tfor (q = 0; q < rq; q++) {\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\taq->qidx = q;\n-\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n-\t\taq->op = NIX_AQ_INSTOP_READ;\n-\n-\t\trc = otx2_mbox_process_msg(mbox, (void **)&rsp);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to get rq context\");\n-\t\t\tgoto fail;\n-\t\t}\n-\t\tnix_dump(\"============== port=%d rq=%d ===============\",\n-\t\t\t eth_dev->data->port_id, q);\n-\t\tnix_lf_rq_dump(&rsp->rq);\n-\t}\n-\tfor (q = 0; q < sq; q++) {\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\taq->qidx = q;\n-\t\taq->ctype = NIX_AQ_CTYPE_SQ;\n-\t\taq->op = NIX_AQ_INSTOP_READ;\n-\n-\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to get sq context\");\n-\t\t\tgoto fail;\n-\t\t}\n-\t\tnix_dump(\"============== port=%d sq=%d ===============\",\n-\t\t\t eth_dev->data->port_id, q);\n-\t\tnix_lf_sq_dump(&rsp->sq);\n-\n-\t\tif (!npa_lf) {\n-\t\t\totx2_err(\"NPA LF doesn't exist\");\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\t/* Dump SQB Aura minimal info */\n-\t\tnpa_aq = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);\n-\t\tnpa_aq->aura_id = rsp->sq.sqb_aura;\n-\t\tnpa_aq->ctype = NPA_AQ_CTYPE_AURA;\n-\t\tnpa_aq->op = NPA_AQ_INSTOP_READ;\n-\n-\t\trc = otx2_mbox_process_msg(npa_lf->mbox, (void *)&npa_rsp);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to get sq's sqb_aura context\");\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\tnix_dump(\"\\nSQB Aura W0: Pool addr\\t\\t0x%\"PRIx64\"\",\n-\t\t\t npa_rsp->aura.pool_addr);\n-\t\tnix_dump(\"SQB Aura W1: ena\\t\\t\\t%d\",\n-\t\t\t npa_rsp->aura.ena);\n-\t\tnix_dump(\"SQB Aura W2: count\\t\\t%\"PRIx64\"\",\n-\t\t\t (uint64_t)npa_rsp->aura.count);\n-\t\tnix_dump(\"SQB Aura W3: limit\\t\\t%\"PRIx64\"\",\n-\t\t\t (uint64_t)npa_rsp->aura.limit);\n-\t\tnix_dump(\"SQB Aura W3: fc_ena\\t\\t%d\",\n-\t\t\t npa_rsp->aura.fc_ena);\n-\t\tnix_dump(\"SQB Aura W4: fc_addr\\t\\t0x%\"PRIx64\"\\n\",\n-\t\t\t npa_rsp->aura.fc_addr);\n-\t}\n-\n-fail:\n-\treturn rc;\n-}\n-\n-/* Dumps struct nix_cqe_hdr_s and struct nix_rx_parse_s */\n-void\n-otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)\n-{\n-\tconst struct nix_rx_parse_s *rx =\n-\t\t (const struct nix_rx_parse_s *)((const uint64_t *)cq + 1);\n-\n-\tnix_dump(\"tag \\t\\t0x%x\\tq \\t\\t%d\\t\\tnode \\t\\t%d\\tcqe_type \\t%d\",\n-\t\t cq->tag, cq->q, cq->node, cq->cqe_type);\n-\n-\tnix_dump(\"W0: chan \\t%d\\t\\tdesc_sizem1 \\t%d\",\n-\t\t rx->chan, rx->desc_sizem1);\n-\tnix_dump(\"W0: imm_copy \\t%d\\t\\texpress \\t%d\",\n-\t\t rx->imm_copy, rx->express);\n-\tnix_dump(\"W0: wqwd \\t%d\\t\\terrlev \\t\\t%d\\t\\terrcode \\t%d\",\n-\t\t rx->wqwd, rx->errlev, rx->errcode);\n-\tnix_dump(\"W0: latype \\t%d\\t\\tlbtype \\t\\t%d\\t\\tlctype \\t\\t%d\",\n-\t\t rx->latype, rx->lbtype, rx->lctype);\n-\tnix_dump(\"W0: ldtype \\t%d\\t\\tletype \\t\\t%d\\t\\tlftype \\t\\t%d\",\n-\t\t rx->ldtype, rx->letype, rx->lftype);\n-\tnix_dump(\"W0: lgtype \\t%d \\t\\tlhtype \\t\\t%d\",\n-\t\t rx->lgtype, rx->lhtype);\n-\n-\tnix_dump(\"W1: pkt_lenm1 \\t%d\", rx->pkt_lenm1);\n-\tnix_dump(\"W1: l2m \\t%d\\t\\tl2b \\t\\t%d\\t\\tl3m \\t\\t%d\\tl3b \\t\\t%d\",\n-\t\t rx->l2m, rx->l2b, rx->l3m, rx->l3b);\n-\tnix_dump(\"W1: vtag0_valid %d\\t\\tvtag0_gone \\t%d\",\n-\t\t rx->vtag0_valid, rx->vtag0_gone);\n-\tnix_dump(\"W1: vtag1_valid %d\\t\\tvtag1_gone \\t%d\",\n-\t\t rx->vtag1_valid, rx->vtag1_gone);\n-\tnix_dump(\"W1: pkind \\t%d\", rx->pkind);\n-\tnix_dump(\"W1: vtag0_tci \\t%d\\t\\tvtag1_tci \\t%d\",\n-\t\t rx->vtag0_tci, rx->vtag1_tci);\n-\n-\tnix_dump(\"W2: laflags \\t%d\\t\\tlbflags\\t\\t%d\\t\\tlcflags \\t%d\",\n-\t\t rx->laflags, rx->lbflags, rx->lcflags);\n-\tnix_dump(\"W2: ldflags \\t%d\\t\\tleflags\\t\\t%d\\t\\tlfflags \\t%d\",\n-\t\t rx->ldflags, rx->leflags, rx->lfflags);\n-\tnix_dump(\"W2: lgflags \\t%d\\t\\tlhflags \\t%d\",\n-\t\t rx->lgflags, rx->lhflags);\n-\n-\tnix_dump(\"W3: eoh_ptr \\t%d\\t\\twqe_aura \\t%d\\t\\tpb_aura \\t%d\",\n-\t\t rx->eoh_ptr, rx->wqe_aura, rx->pb_aura);\n-\tnix_dump(\"W3: match_id \\t%d\", rx->match_id);\n-\n-\tnix_dump(\"W4: laptr \\t%d\\t\\tlbptr \\t\\t%d\\t\\tlcptr \\t\\t%d\",\n-\t\t rx->laptr, rx->lbptr, rx->lcptr);\n-\tnix_dump(\"W4: ldptr \\t%d\\t\\tleptr \\t\\t%d\\t\\tlfptr \\t\\t%d\",\n-\t\t rx->ldptr, rx->leptr, rx->lfptr);\n-\tnix_dump(\"W4: lgptr \\t%d\\t\\tlhptr \\t\\t%d\", rx->lgptr, rx->lhptr);\n-\n-\tnix_dump(\"W5: vtag0_ptr \\t%d\\t\\tvtag1_ptr \\t%d\\t\\tflow_key_alg \\t%d\",\n-\t\t rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg);\n-}\n-\n-static uint8_t\n-prepare_nix_tm_reg_dump(uint16_t hw_lvl, uint16_t schq, uint16_t link,\n-\t\t\tuint64_t *reg, char regstr[][NIX_REG_NAME_SZ])\n-{\n-\tuint8_t k = 0;\n-\n-\tswitch (hw_lvl) {\n-\tcase NIX_TXSCH_LVL_SMQ:\n-\t\treg[k] = NIX_AF_SMQX_CFG(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_SMQ[%u]_CFG\", schq);\n-\n-\t\treg[k] = NIX_AF_MDQX_PARENT(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_MDQ[%u]_PARENT\", schq);\n-\n-\t\treg[k] = NIX_AF_MDQX_SCHEDULE(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_MDQ[%u]_SCHEDULE\", schq);\n-\n-\t\treg[k] = NIX_AF_MDQX_PIR(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_MDQ[%u]_PIR\", schq);\n-\n-\t\treg[k] = NIX_AF_MDQX_CIR(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_MDQ[%u]_CIR\", schq);\n-\n-\t\treg[k] = NIX_AF_MDQX_SHAPE(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_MDQ[%u]_SHAPE\", schq);\n-\n-\t\treg[k] = NIX_AF_MDQX_SW_XOFF(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_MDQ[%u]_SW_XOFF\", schq);\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL4:\n-\t\treg[k] = NIX_AF_TL4X_PARENT(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL4[%u]_PARENT\", schq);\n-\n-\t\treg[k] = NIX_AF_TL4X_TOPOLOGY(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL4[%u]_TOPOLOGY\", schq);\n-\n-\t\treg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL4[%u]_SDP_LINK_CFG\", schq);\n-\n-\t\treg[k] = NIX_AF_TL4X_SCHEDULE(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL4[%u]_SCHEDULE\", schq);\n-\n-\t\treg[k] = NIX_AF_TL4X_PIR(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL4[%u]_PIR\", schq);\n-\n-\t\treg[k] = NIX_AF_TL4X_CIR(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL4[%u]_CIR\", schq);\n-\n-\t\treg[k] = NIX_AF_TL4X_SHAPE(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL4[%u]_SHAPE\", schq);\n-\n-\t\treg[k] = NIX_AF_TL4X_SW_XOFF(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL4[%u]_SW_XOFF\", schq);\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL3:\n-\t\treg[k] = NIX_AF_TL3X_PARENT(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL3[%u]_PARENT\", schq);\n-\n-\t\treg[k] = NIX_AF_TL3X_TOPOLOGY(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL3[%u]_TOPOLOGY\", schq);\n-\n-\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG\", schq, link);\n-\n-\t\treg[k] = NIX_AF_TL3X_SCHEDULE(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL3[%u]_SCHEDULE\", schq);\n-\n-\t\treg[k] = NIX_AF_TL3X_PIR(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL3[%u]_PIR\", schq);\n-\n-\t\treg[k] = NIX_AF_TL3X_CIR(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL3[%u]_CIR\", schq);\n-\n-\t\treg[k] = NIX_AF_TL3X_SHAPE(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL3[%u]_SHAPE\", schq);\n-\n-\t\treg[k] = NIX_AF_TL3X_SW_XOFF(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL3[%u]_SW_XOFF\", schq);\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL2:\n-\t\treg[k] = NIX_AF_TL2X_PARENT(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL2[%u]_PARENT\", schq);\n-\n-\t\treg[k] = NIX_AF_TL2X_TOPOLOGY(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL2[%u]_TOPOLOGY\", schq);\n-\n-\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG\", schq, link);\n-\n-\t\treg[k] = NIX_AF_TL2X_SCHEDULE(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL2[%u]_SCHEDULE\", schq);\n-\n-\t\treg[k] = NIX_AF_TL2X_PIR(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL2[%u]_PIR\", schq);\n-\n-\t\treg[k] = NIX_AF_TL2X_CIR(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL2[%u]_CIR\", schq);\n-\n-\t\treg[k] = NIX_AF_TL2X_SHAPE(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL2[%u]_SHAPE\", schq);\n-\n-\t\treg[k] = NIX_AF_TL2X_SW_XOFF(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL2[%u]_SW_XOFF\", schq);\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL1:\n-\n-\t\treg[k] = NIX_AF_TL1X_TOPOLOGY(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL1[%u]_TOPOLOGY\", schq);\n-\n-\t\treg[k] = NIX_AF_TL1X_SCHEDULE(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL1[%u]_SCHEDULE\", schq);\n-\n-\t\treg[k] = NIX_AF_TL1X_CIR(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL1[%u]_CIR\", schq);\n-\n-\t\treg[k] = NIX_AF_TL1X_SW_XOFF(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL1[%u]_SW_XOFF\", schq);\n-\n-\t\treg[k] = NIX_AF_TL1X_DROPPED_PACKETS(schq);\n-\t\tsnprintf(regstr[k++], NIX_REG_NAME_SZ,\n-\t\t\t \"NIX_AF_TL1[%u]_DROPPED_PACKETS\", schq);\n-\t\tbreak;\n-\tdefault:\n-\t\tbreak;\n-\t}\n-\n-\tif (k > MAX_REGS_PER_MBOX_MSG) {\n-\t\tnix_dump(\"\\t!!!NIX TM Registers request overflow!!!\");\n-\t\treturn 0;\n-\t}\n-\treturn k;\n-}\n-\n-/* Dump TM hierarchy and registers */\n-void\n-otx2_nix_tm_dump(struct otx2_eth_dev *dev)\n-{\n-\tchar regstr[MAX_REGS_PER_MBOX_MSG * 2][NIX_REG_NAME_SZ];\n-\tstruct otx2_nix_tm_node *tm_node, *root_node, *parent;\n-\tuint64_t reg[MAX_REGS_PER_MBOX_MSG * 2];\n-\tstruct nix_txschq_config *req;\n-\tconst char *lvlstr, *parent_lvlstr;\n-\tstruct nix_txschq_config *rsp;\n-\tuint32_t schq, parent_schq;\n-\tint hw_lvl, j, k, rc;\n-\n-\tnix_dump(\"===TM hierarchy and registers dump of %s===\",\n-\t\t dev->eth_dev->data->name);\n-\n-\troot_node = NULL;\n-\n-\tfor (hw_lvl = 0; hw_lvl <= NIX_TXSCH_LVL_CNT; hw_lvl++) {\n-\t\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\t\tif (tm_node->hw_lvl != hw_lvl)\n-\t\t\t\tcontinue;\n-\n-\t\t\tparent = tm_node->parent;\n-\t\t\tif (hw_lvl == NIX_TXSCH_LVL_CNT) {\n-\t\t\t\tlvlstr = \"SQ\";\n-\t\t\t\tschq = tm_node->id;\n-\t\t\t} else {\n-\t\t\t\tlvlstr = nix_hwlvl2str(tm_node->hw_lvl);\n-\t\t\t\tschq = tm_node->hw_id;\n-\t\t\t}\n-\n-\t\t\tif (parent) {\n-\t\t\t\tparent_schq = parent->hw_id;\n-\t\t\t\tparent_lvlstr =\n-\t\t\t\t\tnix_hwlvl2str(parent->hw_lvl);\n-\t\t\t} else if (tm_node->hw_lvl == NIX_TXSCH_LVL_TL1) {\n-\t\t\t\tparent_schq = otx2_nix_get_link(dev);\n-\t\t\t\tparent_lvlstr = \"LINK\";\n-\t\t\t} else {\n-\t\t\t\tparent_schq = tm_node->parent_hw_id;\n-\t\t\t\tparent_lvlstr =\n-\t\t\t\t\tnix_hwlvl2str(tm_node->hw_lvl + 1);\n-\t\t\t}\n-\n-\t\t\tnix_dump(\"%s_%d->%s_%d\", lvlstr, schq,\n-\t\t\t\t parent_lvlstr, parent_schq);\n-\n-\t\t\tif (!(tm_node->flags & NIX_TM_NODE_HWRES))\n-\t\t\t\tcontinue;\n-\n-\t\t\t/* Need to dump TL1 when root is TL2 */\n-\t\t\tif (tm_node->hw_lvl == dev->otx2_tm_root_lvl)\n-\t\t\t\troot_node = tm_node;\n-\n-\t\t\t/* Dump registers only when HWRES is present */\n-\t\t\tk = prepare_nix_tm_reg_dump(tm_node->hw_lvl, schq,\n-\t\t\t\t\t\t otx2_nix_get_link(dev), reg,\n-\t\t\t\t\t\t regstr);\n-\t\t\tif (!k)\n-\t\t\t\tcontinue;\n-\n-\t\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);\n-\t\t\treq->read = 1;\n-\t\t\treq->lvl = tm_node->hw_lvl;\n-\t\t\treq->num_regs = k;\n-\t\t\totx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);\n-\t\t\trc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);\n-\t\t\tif (!rc) {\n-\t\t\t\tfor (j = 0; j < k; j++)\n-\t\t\t\t\tnix_dump(\"\\t%s=0x%016\"PRIx64,\n-\t\t\t\t\t\t regstr[j], rsp->regval[j]);\n-\t\t\t} else {\n-\t\t\t\tnix_dump(\"\\t!!!Failed to dump registers!!!\");\n-\t\t\t}\n-\t\t}\n-\t\tnix_dump(\"\\n\");\n-\t}\n-\n-\t/* Dump TL1 node data when root level is TL2 */\n-\tif (root_node && root_node->hw_lvl == NIX_TXSCH_LVL_TL2) {\n-\t\tk = prepare_nix_tm_reg_dump(NIX_TXSCH_LVL_TL1,\n-\t\t\t\t\t root_node->parent_hw_id,\n-\t\t\t\t\t otx2_nix_get_link(dev),\n-\t\t\t\t\t reg, regstr);\n-\t\tif (!k)\n-\t\t\treturn;\n-\n-\n-\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);\n-\t\treq->read = 1;\n-\t\treq->lvl = NIX_TXSCH_LVL_TL1;\n-\t\treq->num_regs = k;\n-\t\totx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);\n-\t\trc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);\n-\t\tif (!rc) {\n-\t\t\tfor (j = 0; j < k; j++)\n-\t\t\t\tnix_dump(\"\\t%s=0x%016\"PRIx64,\n-\t\t\t\t\t regstr[j], rsp->regval[j]);\n-\t\t} else {\n-\t\t\tnix_dump(\"\\t!!!Failed to dump registers!!!\");\n-\t\t}\n-\t}\n-\n-\totx2_nix_queues_ctx_dump(dev->eth_dev);\n-}\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_devargs.c b/drivers/net/octeontx2/otx2_ethdev_devargs.c\ndeleted file mode 100644\nindex 60bf6c3f5f..0000000000\n--- a/drivers/net/octeontx2/otx2_ethdev_devargs.c\n+++ /dev/null\n@@ -1,215 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <inttypes.h>\n-#include <math.h>\n-\n-#include \"otx2_ethdev.h\"\n-\n-static int\n-parse_flow_max_priority(const char *key, const char *value, void *extra_args)\n-{\n-\tRTE_SET_USED(key);\n-\tuint16_t val;\n-\n-\tval = atoi(value);\n-\n-\t/* Limit the max priority to 32 */\n-\tif (val < 1 || val > 32)\n-\t\treturn -EINVAL;\n-\n-\t*(uint16_t *)extra_args = val;\n-\n-\treturn 0;\n-}\n-\n-static int\n-parse_flow_prealloc_size(const char *key, const char *value, void *extra_args)\n-{\n-\tRTE_SET_USED(key);\n-\tuint16_t val;\n-\n-\tval = atoi(value);\n-\n-\t/* Limit the prealloc size to 32 */\n-\tif (val < 1 || val > 32)\n-\t\treturn -EINVAL;\n-\n-\t*(uint16_t *)extra_args = val;\n-\n-\treturn 0;\n-}\n-\n-static int\n-parse_reta_size(const char *key, const char *value, void *extra_args)\n-{\n-\tRTE_SET_USED(key);\n-\tuint32_t val;\n-\n-\tval = atoi(value);\n-\n-\tif (val <= RTE_ETH_RSS_RETA_SIZE_64)\n-\t\tval = RTE_ETH_RSS_RETA_SIZE_64;\n-\telse if (val > RTE_ETH_RSS_RETA_SIZE_64 && val <= RTE_ETH_RSS_RETA_SIZE_128)\n-\t\tval = RTE_ETH_RSS_RETA_SIZE_128;\n-\telse if (val > RTE_ETH_RSS_RETA_SIZE_128 && val <= RTE_ETH_RSS_RETA_SIZE_256)\n-\t\tval = RTE_ETH_RSS_RETA_SIZE_256;\n-\telse\n-\t\tval = NIX_RSS_RETA_SIZE;\n-\n-\t*(uint16_t *)extra_args = val;\n-\n-\treturn 0;\n-}\n-\n-static int\n-parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args)\n-{\n-\tRTE_SET_USED(key);\n-\tuint32_t val;\n-\n-\tval = atoi(value);\n-\n-\t*(uint16_t *)extra_args = val;\n-\n-\treturn 0;\n-}\n-\n-static int\n-parse_flag(const char *key, const char *value, void *extra_args)\n-{\n-\tRTE_SET_USED(key);\n-\n-\t*(uint16_t *)extra_args = atoi(value);\n-\n-\treturn 0;\n-}\n-\n-static int\n-parse_sqb_count(const char *key, const char *value, void *extra_args)\n-{\n-\tRTE_SET_USED(key);\n-\tuint32_t val;\n-\n-\tval = atoi(value);\n-\n-\tif (val < NIX_MIN_SQB || val > NIX_MAX_SQB)\n-\t\treturn -EINVAL;\n-\n-\t*(uint16_t *)extra_args = val;\n-\n-\treturn 0;\n-}\n-\n-static int\n-parse_switch_header_type(const char *key, const char *value, void *extra_args)\n-{\n-\tRTE_SET_USED(key);\n-\n-\tif (strcmp(value, \"higig2\") == 0)\n-\t\t*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_HIGIG;\n-\n-\tif (strcmp(value, \"dsa\") == 0)\n-\t\t*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA;\n-\n-\tif (strcmp(value, \"chlen90b\") == 0)\n-\t\t*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_CH_LEN_90B;\n-\n-\tif (strcmp(value, \"chlen24b\") == 0)\n-\t\t*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_CH_LEN_24B;\n-\n-\tif (strcmp(value, \"exdsa\") == 0)\n-\t\t*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EXDSA;\n-\n-\tif (strcmp(value, \"vlan_exdsa\") == 0)\n-\t\t*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_VLAN_EXDSA;\n-\n-\treturn 0;\n-}\n-\n-#define OTX2_RSS_RETA_SIZE \"reta_size\"\n-#define OTX2_IPSEC_IN_MAX_SPI \"ipsec_in_max_spi\"\n-#define OTX2_SCL_ENABLE \"scalar_enable\"\n-#define OTX2_MAX_SQB_COUNT \"max_sqb_count\"\n-#define OTX2_FLOW_PREALLOC_SIZE \"flow_prealloc_size\"\n-#define OTX2_FLOW_MAX_PRIORITY \"flow_max_priority\"\n-#define OTX2_SWITCH_HEADER_TYPE \"switch_header\"\n-#define OTX2_RSS_TAG_AS_XOR \"tag_as_xor\"\n-#define OTX2_LOCK_RX_CTX \"lock_rx_ctx\"\n-#define OTX2_LOCK_TX_CTX \"lock_tx_ctx\"\n-\n-int\n-otx2_ethdev_parse_devargs(struct rte_devargs *devargs, struct otx2_eth_dev *dev)\n-{\n-\tuint16_t rss_size = NIX_RSS_RETA_SIZE;\n-\tuint16_t sqb_count = NIX_MAX_SQB;\n-\tuint16_t flow_prealloc_size = 8;\n-\tuint16_t switch_header_type = 0;\n-\tuint16_t flow_max_priority = 3;\n-\tuint16_t ipsec_in_max_spi = 1;\n-\tuint16_t rss_tag_as_xor = 0;\n-\tuint16_t scalar_enable = 0;\n-\tstruct rte_kvargs *kvlist;\n-\tuint16_t lock_rx_ctx = 0;\n-\tuint16_t lock_tx_ctx = 0;\n-\n-\tif (devargs == NULL)\n-\t\tgoto null_devargs;\n-\n-\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n-\tif (kvlist == NULL)\n-\t\tgoto exit;\n-\n-\trte_kvargs_process(kvlist, OTX2_RSS_RETA_SIZE,\n-\t\t\t &parse_reta_size, &rss_size);\n-\trte_kvargs_process(kvlist, OTX2_IPSEC_IN_MAX_SPI,\n-\t\t\t &parse_ipsec_in_max_spi, &ipsec_in_max_spi);\n-\trte_kvargs_process(kvlist, OTX2_SCL_ENABLE,\n-\t\t\t &parse_flag, &scalar_enable);\n-\trte_kvargs_process(kvlist, OTX2_MAX_SQB_COUNT,\n-\t\t\t &parse_sqb_count, &sqb_count);\n-\trte_kvargs_process(kvlist, OTX2_FLOW_PREALLOC_SIZE,\n-\t\t\t &parse_flow_prealloc_size, &flow_prealloc_size);\n-\trte_kvargs_process(kvlist, OTX2_FLOW_MAX_PRIORITY,\n-\t\t\t &parse_flow_max_priority, &flow_max_priority);\n-\trte_kvargs_process(kvlist, OTX2_SWITCH_HEADER_TYPE,\n-\t\t\t &parse_switch_header_type, &switch_header_type);\n-\trte_kvargs_process(kvlist, OTX2_RSS_TAG_AS_XOR,\n-\t\t\t &parse_flag, &rss_tag_as_xor);\n-\trte_kvargs_process(kvlist, OTX2_LOCK_RX_CTX,\n-\t\t\t &parse_flag, &lock_rx_ctx);\n-\trte_kvargs_process(kvlist, OTX2_LOCK_TX_CTX,\n-\t\t\t &parse_flag, &lock_tx_ctx);\n-\totx2_parse_common_devargs(kvlist);\n-\trte_kvargs_free(kvlist);\n-\n-null_devargs:\n-\tdev->ipsec_in_max_spi = ipsec_in_max_spi;\n-\tdev->scalar_ena = scalar_enable;\n-\tdev->rss_tag_as_xor = rss_tag_as_xor;\n-\tdev->max_sqb_count = sqb_count;\n-\tdev->lock_rx_ctx = lock_rx_ctx;\n-\tdev->lock_tx_ctx = lock_tx_ctx;\n-\tdev->rss_info.rss_size = rss_size;\n-\tdev->npc_flow.flow_prealloc_size = flow_prealloc_size;\n-\tdev->npc_flow.flow_max_priority = flow_max_priority;\n-\tdev->npc_flow.switch_header_type = switch_header_type;\n-\treturn 0;\n-\n-exit:\n-\treturn -EINVAL;\n-}\n-\n-RTE_PMD_REGISTER_PARAM_STRING(OCTEONTX2_PMD,\n-\t\t\t OTX2_RSS_RETA_SIZE \"=<64|128|256>\"\n-\t\t\t OTX2_IPSEC_IN_MAX_SPI \"=<1-65535>\"\n-\t\t\t OTX2_SCL_ENABLE \"=1\"\n-\t\t\t OTX2_MAX_SQB_COUNT \"=<8-512>\"\n-\t\t\t OTX2_FLOW_PREALLOC_SIZE \"=<1-32>\"\n-\t\t\t OTX2_FLOW_MAX_PRIORITY \"=<1-32>\"\n-\t\t\t OTX2_SWITCH_HEADER_TYPE \"=<higig2|dsa|chlen90b|chlen24b>\"\n-\t\t\t OTX2_RSS_TAG_AS_XOR \"=1\"\n-\t\t\t OTX2_NPA_LOCK_MASK \"=<1-65535>\"\n-\t\t\t OTX2_LOCK_RX_CTX \"=1\"\n-\t\t\t OTX2_LOCK_TX_CTX \"=1\");\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_irq.c b/drivers/net/octeontx2/otx2_ethdev_irq.c\ndeleted file mode 100644\nindex cc573bb2e8..0000000000\n--- a/drivers/net/octeontx2/otx2_ethdev_irq.c\n+++ /dev/null\n@@ -1,493 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <inttypes.h>\n-\n-#include <rte_bus_pci.h>\n-#include <rte_malloc.h>\n-\n-#include \"otx2_ethdev.h\"\n-\n-static void\n-nix_lf_err_irq(void *param)\n-{\n-\tstruct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint64_t intr;\n-\n-\tintr = otx2_read64(dev->base + NIX_LF_ERR_INT);\n-\tif (intr == 0)\n-\t\treturn;\n-\n-\totx2_err(\"Err_intr=0x%\" PRIx64 \" pf=%d, vf=%d\", intr, dev->pf, dev->vf);\n-\n-\t/* Clear interrupt */\n-\totx2_write64(intr, dev->base + NIX_LF_ERR_INT);\n-\n-\t/* Dump registers to std out */\n-\totx2_nix_reg_dump(dev, NULL);\n-\totx2_nix_queues_ctx_dump(eth_dev);\n-}\n-\n-static int\n-nix_lf_register_err_irq(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint rc, vec;\n-\n-\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;\n-\n-\t/* Clear err interrupt */\n-\totx2_nix_err_intr_enb_dis(eth_dev, false);\n-\t/* Set used interrupt vectors */\n-\trc = otx2_register_irq(handle, nix_lf_err_irq, eth_dev, vec);\n-\t/* Enable all dev interrupt except for RQ_DISABLED */\n-\totx2_nix_err_intr_enb_dis(eth_dev, true);\n-\n-\treturn rc;\n-}\n-\n-static void\n-nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint vec;\n-\n-\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;\n-\n-\t/* Clear err interrupt */\n-\totx2_nix_err_intr_enb_dis(eth_dev, false);\n-\totx2_unregister_irq(handle, nix_lf_err_irq, eth_dev, vec);\n-}\n-\n-static void\n-nix_lf_ras_irq(void *param)\n-{\n-\tstruct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint64_t intr;\n-\n-\tintr = otx2_read64(dev->base + NIX_LF_RAS);\n-\tif (intr == 0)\n-\t\treturn;\n-\n-\totx2_err(\"Ras_intr=0x%\" PRIx64 \" pf=%d, vf=%d\", intr, dev->pf, dev->vf);\n-\n-\t/* Clear interrupt */\n-\totx2_write64(intr, dev->base + NIX_LF_RAS);\n-\n-\t/* Dump registers to std out */\n-\totx2_nix_reg_dump(dev, NULL);\n-\totx2_nix_queues_ctx_dump(eth_dev);\n-}\n-\n-static int\n-nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint rc, vec;\n-\n-\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;\n-\n-\t/* Clear err interrupt */\n-\totx2_nix_ras_intr_enb_dis(eth_dev, false);\n-\t/* Set used interrupt vectors */\n-\trc = otx2_register_irq(handle, nix_lf_ras_irq, eth_dev, vec);\n-\t/* Enable dev interrupt */\n-\totx2_nix_ras_intr_enb_dis(eth_dev, true);\n-\n-\treturn rc;\n-}\n-\n-static void\n-nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint vec;\n-\n-\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;\n-\n-\t/* Clear err interrupt */\n-\totx2_nix_ras_intr_enb_dis(eth_dev, false);\n-\totx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec);\n-}\n-\n-static inline uint8_t\n-nix_lf_q_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t q,\n-\t\t\t uint32_t off, uint64_t mask)\n-{\n-\tuint64_t reg, wdata;\n-\tuint8_t qint;\n-\n-\twdata = (uint64_t)q << 44;\n-\treg = otx2_atomic64_add_nosync(wdata, (int64_t *)(dev->base + off));\n-\n-\tif (reg & BIT_ULL(42) /* OP_ERR */) {\n-\t\totx2_err(\"Failed execute irq get off=0x%x\", off);\n-\t\treturn 0;\n-\t}\n-\n-\tqint = reg & 0xff;\n-\twdata &= mask;\n-\totx2_write64(wdata | qint, dev->base + off);\n-\n-\treturn qint;\n-}\n-\n-static inline uint8_t\n-nix_lf_rq_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t rq)\n-{\n-\treturn nix_lf_q_irq_get_and_clear(dev, rq, NIX_LF_RQ_OP_INT, ~0xff00);\n-}\n-\n-static inline uint8_t\n-nix_lf_cq_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t cq)\n-{\n-\treturn nix_lf_q_irq_get_and_clear(dev, cq, NIX_LF_CQ_OP_INT, ~0xff00);\n-}\n-\n-static inline uint8_t\n-nix_lf_sq_irq_get_and_clear(struct otx2_eth_dev *dev, uint16_t sq)\n-{\n-\treturn nix_lf_q_irq_get_and_clear(dev, sq, NIX_LF_SQ_OP_INT, ~0x1ff00);\n-}\n-\n-static inline void\n-nix_lf_sq_debug_reg(struct otx2_eth_dev *dev, uint32_t off)\n-{\n-\tuint64_t reg;\n-\n-\treg = otx2_read64(dev->base + off);\n-\tif (reg & BIT_ULL(44))\n-\t\totx2_err(\"SQ=%d err_code=0x%x\",\n-\t\t\t (int)((reg >> 8) & 0xfffff), (uint8_t)(reg & 0xff));\n-}\n-\n-static void\n-nix_lf_cq_irq(void *param)\n-{\n-\tstruct otx2_qint *cint = (struct otx2_qint *)param;\n-\tstruct rte_eth_dev *eth_dev = cint->eth_dev;\n-\tstruct otx2_eth_dev *dev;\n-\n-\tdev = otx2_eth_pmd_priv(eth_dev);\n-\t/* Clear interrupt */\n-\totx2_write64(BIT_ULL(0), dev->base + NIX_LF_CINTX_INT(cint->qintx));\n-}\n-\n-static void\n-nix_lf_q_irq(void *param)\n-{\n-\tstruct otx2_qint *qint = (struct otx2_qint *)param;\n-\tstruct rte_eth_dev *eth_dev = qint->eth_dev;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint8_t irq, qintx = qint->qintx;\n-\tint q, cq, rq, sq;\n-\tuint64_t intr;\n-\n-\tintr = otx2_read64(dev->base + NIX_LF_QINTX_INT(qintx));\n-\tif (intr == 0)\n-\t\treturn;\n-\n-\totx2_err(\"Queue_intr=0x%\" PRIx64 \" qintx=%d pf=%d, vf=%d\",\n-\t\t intr, qintx, dev->pf, dev->vf);\n-\n-\t/* Handle RQ interrupts */\n-\tfor (q = 0; q < eth_dev->data->nb_rx_queues; q++) {\n-\t\trq = q % dev->qints;\n-\t\tirq = nix_lf_rq_irq_get_and_clear(dev, rq);\n-\n-\t\tif (irq & BIT_ULL(NIX_RQINT_DROP))\n-\t\t\totx2_err(\"RQ=%d NIX_RQINT_DROP\", rq);\n-\n-\t\tif (irq & BIT_ULL(NIX_RQINT_RED))\n-\t\t\totx2_err(\"RQ=%d NIX_RQINT_RED\",\trq);\n-\t}\n-\n-\t/* Handle CQ interrupts */\n-\tfor (q = 0; q < eth_dev->data->nb_rx_queues; q++) {\n-\t\tcq = q % dev->qints;\n-\t\tirq = nix_lf_cq_irq_get_and_clear(dev, cq);\n-\n-\t\tif (irq & BIT_ULL(NIX_CQERRINT_DOOR_ERR))\n-\t\t\totx2_err(\"CQ=%d NIX_CQERRINT_DOOR_ERR\", cq);\n-\n-\t\tif (irq & BIT_ULL(NIX_CQERRINT_WR_FULL))\n-\t\t\totx2_err(\"CQ=%d NIX_CQERRINT_WR_FULL\", cq);\n-\n-\t\tif (irq & BIT_ULL(NIX_CQERRINT_CQE_FAULT))\n-\t\t\totx2_err(\"CQ=%d NIX_CQERRINT_CQE_FAULT\", cq);\n-\t}\n-\n-\t/* Handle SQ interrupts */\n-\tfor (q = 0; q < eth_dev->data->nb_tx_queues; q++) {\n-\t\tsq = q % dev->qints;\n-\t\tirq = nix_lf_sq_irq_get_and_clear(dev, sq);\n-\n-\t\tif (irq & BIT_ULL(NIX_SQINT_LMT_ERR)) {\n-\t\t\totx2_err(\"SQ=%d NIX_SQINT_LMT_ERR\", sq);\n-\t\t\tnix_lf_sq_debug_reg(dev, NIX_LF_SQ_OP_ERR_DBG);\n-\t\t}\n-\t\tif (irq & BIT_ULL(NIX_SQINT_MNQ_ERR)) {\n-\t\t\totx2_err(\"SQ=%d NIX_SQINT_MNQ_ERR\", sq);\n-\t\t\tnix_lf_sq_debug_reg(dev, NIX_LF_MNQ_ERR_DBG);\n-\t\t}\n-\t\tif (irq & BIT_ULL(NIX_SQINT_SEND_ERR)) {\n-\t\t\totx2_err(\"SQ=%d NIX_SQINT_SEND_ERR\", sq);\n-\t\t\tnix_lf_sq_debug_reg(dev, NIX_LF_SEND_ERR_DBG);\n-\t\t}\n-\t\tif (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) {\n-\t\t\totx2_err(\"SQ=%d NIX_SQINT_SQB_ALLOC_FAIL\", sq);\n-\t\t\tnix_lf_sq_debug_reg(dev, NIX_LF_SEND_ERR_DBG);\n-\t\t}\n-\t}\n-\n-\t/* Clear interrupt */\n-\totx2_write64(intr, dev->base + NIX_LF_QINTX_INT(qintx));\n-\n-\t/* Dump registers to std out */\n-\totx2_nix_reg_dump(dev, NULL);\n-\totx2_nix_queues_ctx_dump(eth_dev);\n-}\n-\n-int\n-oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint vec, q, sqs, rqs, qs, rc = 0;\n-\n-\t/* Figure out max qintx required */\n-\trqs = RTE_MIN(dev->qints, eth_dev->data->nb_rx_queues);\n-\tsqs = RTE_MIN(dev->qints, eth_dev->data->nb_tx_queues);\n-\tqs = RTE_MAX(rqs, sqs);\n-\n-\tdev->configured_qints = qs;\n-\n-\tfor (q = 0; q < qs; q++) {\n-\t\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_QINT_START + q;\n-\n-\t\t/* Clear QINT CNT */\n-\t\totx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q));\n-\n-\t\t/* Clear interrupt */\n-\t\totx2_write64(~0ull, dev->base + NIX_LF_QINTX_ENA_W1C(q));\n-\n-\t\tdev->qints_mem[q].eth_dev = eth_dev;\n-\t\tdev->qints_mem[q].qintx = q;\n-\n-\t\t/* Sync qints_mem update */\n-\t\trte_smp_wmb();\n-\n-\t\t/* Register queue irq vector */\n-\t\trc = otx2_register_irq(handle, nix_lf_q_irq,\n-\t\t\t\t &dev->qints_mem[q], vec);\n-\t\tif (rc)\n-\t\t\tbreak;\n-\n-\t\totx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q));\n-\t\totx2_write64(0, dev->base + NIX_LF_QINTX_INT(q));\n-\t\t/* Enable QINT interrupt */\n-\t\totx2_write64(~0ull, dev->base + NIX_LF_QINTX_ENA_W1S(q));\n-\t}\n-\n-\treturn rc;\n-}\n-\n-void\n-oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint vec, q;\n-\n-\tfor (q = 0; q < dev->configured_qints; q++) {\n-\t\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_QINT_START + q;\n-\n-\t\t/* Clear QINT CNT */\n-\t\totx2_write64(0, dev->base + NIX_LF_QINTX_CNT(q));\n-\t\totx2_write64(0, dev->base + NIX_LF_QINTX_INT(q));\n-\n-\t\t/* Clear interrupt */\n-\t\totx2_write64(~0ull, dev->base + NIX_LF_QINTX_ENA_W1C(q));\n-\n-\t\t/* Unregister queue irq vector */\n-\t\totx2_unregister_irq(handle, nix_lf_q_irq,\n-\t\t\t\t &dev->qints_mem[q], vec);\n-\t}\n-}\n-\n-int\n-oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint8_t rc = 0, vec, q;\n-\n-\tdev->configured_cints = RTE_MIN(dev->cints,\n-\t\t\t\t\teth_dev->data->nb_rx_queues);\n-\n-\tfor (q = 0; q < dev->configured_cints; q++) {\n-\t\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_CINT_START + q;\n-\n-\t\t/* Clear CINT CNT */\n-\t\totx2_write64(0, dev->base + NIX_LF_CINTX_CNT(q));\n-\n-\t\t/* Clear interrupt */\n-\t\totx2_write64(BIT_ULL(0), dev->base + NIX_LF_CINTX_ENA_W1C(q));\n-\n-\t\tdev->cints_mem[q].eth_dev = eth_dev;\n-\t\tdev->cints_mem[q].qintx = q;\n-\n-\t\t/* Sync cints_mem update */\n-\t\trte_smp_wmb();\n-\n-\t\t/* Register queue irq vector */\n-\t\trc = otx2_register_irq(handle, nix_lf_cq_irq,\n-\t\t\t\t &dev->cints_mem[q], vec);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Fail to register CQ irq, rc=%d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\n-\t\trc = rte_intr_vec_list_alloc(handle, \"intr_vec\",\n-\t\t\t\t\t\tdev->configured_cints);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Fail to allocate intr vec list, \"\n-\t\t\t\t \"rc=%d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t\t/* VFIO vector zero is resereved for misc interrupt so\n-\t\t * doing required adjustment. (b13bfab4cd)\n-\t\t */\n-\t\tif (rte_intr_vec_list_index_set(handle, q,\n-\t\t\t\t\t\tRTE_INTR_VEC_RXTX_OFFSET + vec))\n-\t\t\treturn -1;\n-\n-\t\t/* Configure CQE interrupt coalescing parameters */\n-\t\totx2_write64(((CQ_CQE_THRESH_DEFAULT) |\n-\t\t\t (CQ_CQE_THRESH_DEFAULT << 32) |\n-\t\t\t (CQ_TIMER_THRESH_DEFAULT << 48)),\n-\t\t\t dev->base + NIX_LF_CINTX_WAIT((q)));\n-\n-\t\t/* Keeping the CQ interrupt disabled as the rx interrupt\n-\t\t * feature needs to be enabled/disabled on demand.\n-\t\t */\n-\t}\n-\n-\treturn rc;\n-}\n-\n-void\n-oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\tstruct rte_intr_handle *handle = pci_dev->intr_handle;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint vec, q;\n-\n-\tfor (q = 0; q < dev->configured_cints; q++) {\n-\t\tvec = dev->nix_msixoff + NIX_LF_INT_VEC_CINT_START + q;\n-\n-\t\t/* Clear CINT CNT */\n-\t\totx2_write64(0, dev->base + NIX_LF_CINTX_CNT(q));\n-\n-\t\t/* Clear interrupt */\n-\t\totx2_write64(BIT_ULL(0), dev->base + NIX_LF_CINTX_ENA_W1C(q));\n-\n-\t\t/* Unregister queue irq vector */\n-\t\totx2_unregister_irq(handle, nix_lf_cq_irq,\n-\t\t\t\t &dev->cints_mem[q], vec);\n-\t}\n-}\n-\n-int\n-otx2_nix_register_irqs(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint rc;\n-\n-\tif (dev->nix_msixoff == MSIX_VECTOR_INVALID) {\n-\t\totx2_err(\"Invalid NIXLF MSIX vector offset vector: 0x%x\",\n-\t\t\t dev->nix_msixoff);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Register lf err interrupt */\n-\trc = nix_lf_register_err_irq(eth_dev);\n-\t/* Register RAS interrupt */\n-\trc |= nix_lf_register_ras_irq(eth_dev);\n-\n-\treturn rc;\n-}\n-\n-void\n-otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev)\n-{\n-\tnix_lf_unregister_err_irq(eth_dev);\n-\tnix_lf_unregister_ras_irq(eth_dev);\n-}\n-\n-int\n-otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,\n-\t\t\t uint16_t rx_queue_id)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\t/* Enable CINT interrupt */\n-\totx2_write64(BIT_ULL(0), dev->base +\n-\t\t NIX_LF_CINTX_ENA_W1S(rx_queue_id));\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,\n-\t\t\t uint16_t rx_queue_id)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\t/* Clear and disable CINT interrupt */\n-\totx2_write64(BIT_ULL(0), dev->base +\n-\t\t NIX_LF_CINTX_ENA_W1C(rx_queue_id));\n-\n-\treturn 0;\n-}\n-\n-void\n-otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\t/* Enable all nix lf error interrupts except\n-\t * RQ_DISABLED and CQ_DISABLED.\n-\t */\n-\tif (enb)\n-\t\totx2_write64(~(BIT_ULL(11) | BIT_ULL(24)),\n-\t\t\t dev->base + NIX_LF_ERR_INT_ENA_W1S);\n-\telse\n-\t\totx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);\n-}\n-\n-void\n-otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tif (enb)\n-\t\totx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);\n-\telse\n-\t\totx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);\n-}\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_ops.c b/drivers/net/octeontx2/otx2_ethdev_ops.c\ndeleted file mode 100644\nindex 48781514c3..0000000000\n--- a/drivers/net/octeontx2/otx2_ethdev_ops.c\n+++ /dev/null\n@@ -1,589 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_ethdev.h>\n-#include <rte_mbuf_pool_ops.h>\n-\n-#include \"otx2_ethdev.h\"\n-\n-int\n-otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)\n-{\n-\tuint32_t buffsz, frame_size = mtu + NIX_L2_OVERHEAD;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct rte_eth_dev_data *data = eth_dev->data;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_frs_cfg *req;\n-\tint rc;\n-\n-\tif (dev->configured && otx2_ethdev_is_ptp_en(dev))\n-\t\tframe_size += NIX_TIMESYNC_RX_OFFSET;\n-\n-\tbuffsz = data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;\n-\n-\t/* Refuse MTU that requires the support of scattered packets\n-\t * when this feature has not been enabled before.\n-\t */\n-\tif (data->dev_started && frame_size > buffsz &&\n-\t !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER))\n-\t\treturn -EINVAL;\n-\n-\t/* Check <seg size> * <max_seg> >= max_frame */\n-\tif ((dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)\t&&\n-\t (frame_size > buffsz * NIX_RX_NB_SEG_MAX))\n-\t\treturn -EINVAL;\n-\n-\treq = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);\n-\treq->update_smq = true;\n-\tif (otx2_dev_is_sdp(dev))\n-\t\treq->sdp_link = true;\n-\t/* FRS HW config should exclude FCS but include NPC VTAG insert size */\n-\treq->maxlen = frame_size - RTE_ETHER_CRC_LEN + NIX_MAX_VTAG_ACT_SIZE;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\t/* Now just update Rx MAXLEN */\n-\treq = otx2_mbox_alloc_msg_nix_set_hw_frs(mbox);\n-\treq->maxlen = frame_size - RTE_ETHER_CRC_LEN;\n-\tif (otx2_dev_is_sdp(dev))\n-\t\treq->sdp_link = true;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct rte_eth_dev_data *data = eth_dev->data;\n-\tstruct otx2_eth_rxq *rxq;\n-\tint rc;\n-\n-\trxq = data->rx_queues[0];\n-\n-\t/* Setup scatter mode if needed by jumbo */\n-\totx2_nix_enable_mseg_on_jumbo(rxq);\n-\n-\trc = otx2_nix_mtu_set(eth_dev, data->mtu);\n-\tif (rc)\n-\t\totx2_err(\"Failed to set default MTU size %d\", rc);\n-\n-\treturn rc;\n-}\n-\n-static void\n-nix_cgx_promisc_config(struct rte_eth_dev *eth_dev, int en)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev))\n-\t\treturn;\n-\n-\tif (en)\n-\t\totx2_mbox_alloc_msg_cgx_promisc_enable(mbox);\n-\telse\n-\t\totx2_mbox_alloc_msg_cgx_promisc_disable(mbox);\n-\n-\totx2_mbox_process(mbox);\n-}\n-\n-void\n-otx2_nix_promisc_config(struct rte_eth_dev *eth_dev, int en)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_rx_mode *req;\n-\n-\tif (otx2_dev_is_vf(dev))\n-\t\treturn;\n-\n-\treq = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);\n-\n-\tif (en)\n-\t\treq->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;\n-\n-\totx2_mbox_process(mbox);\n-\teth_dev->data->promiscuous = en;\n-\totx2_nix_vlan_update_promisc(eth_dev, en);\n-}\n-\n-int\n-otx2_nix_promisc_enable(struct rte_eth_dev *eth_dev)\n-{\n-\totx2_nix_promisc_config(eth_dev, 1);\n-\tnix_cgx_promisc_config(eth_dev, 1);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_promisc_disable(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\totx2_nix_promisc_config(eth_dev, dev->dmac_filter_enable);\n-\tnix_cgx_promisc_config(eth_dev, 0);\n-\tdev->dmac_filter_enable = false;\n-\n-\treturn 0;\n-}\n-\n-static void\n-nix_allmulticast_config(struct rte_eth_dev *eth_dev, int en)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_rx_mode *req;\n-\n-\tif (otx2_dev_is_vf(dev))\n-\t\treturn;\n-\n-\treq = otx2_mbox_alloc_msg_nix_set_rx_mode(mbox);\n-\n-\tif (en)\n-\t\treq->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_ALLMULTI;\n-\telse if (eth_dev->data->promiscuous)\n-\t\treq->mode = NIX_RX_MODE_UCAST | NIX_RX_MODE_PROMISC;\n-\n-\totx2_mbox_process(mbox);\n-}\n-\n-int\n-otx2_nix_allmulticast_enable(struct rte_eth_dev *eth_dev)\n-{\n-\tnix_allmulticast_config(eth_dev, 1);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_allmulticast_disable(struct rte_eth_dev *eth_dev)\n-{\n-\tnix_allmulticast_config(eth_dev, 0);\n-\n-\treturn 0;\n-}\n-\n-void\n-otx2_nix_rxq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,\n-\t\t struct rte_eth_rxq_info *qinfo)\n-{\n-\tstruct otx2_eth_rxq *rxq;\n-\n-\trxq = eth_dev->data->rx_queues[queue_id];\n-\n-\tqinfo->mp = rxq->pool;\n-\tqinfo->scattered_rx = eth_dev->data->scattered_rx;\n-\tqinfo->nb_desc = rxq->qconf.nb_desc;\n-\n-\tqinfo->conf.rx_free_thresh = 0;\n-\tqinfo->conf.rx_drop_en = 0;\n-\tqinfo->conf.rx_deferred_start = 0;\n-\tqinfo->conf.offloads = rxq->offloads;\n-}\n-\n-void\n-otx2_nix_txq_info_get(struct rte_eth_dev *eth_dev, uint16_t queue_id,\n-\t\t struct rte_eth_txq_info *qinfo)\n-{\n-\tstruct otx2_eth_txq *txq;\n-\n-\ttxq = eth_dev->data->tx_queues[queue_id];\n-\n-\tqinfo->nb_desc = txq->qconf.nb_desc;\n-\n-\tqinfo->conf.tx_thresh.pthresh = 0;\n-\tqinfo->conf.tx_thresh.hthresh = 0;\n-\tqinfo->conf.tx_thresh.wthresh = 0;\n-\n-\tqinfo->conf.tx_free_thresh = 0;\n-\tqinfo->conf.tx_rs_thresh = 0;\n-\tqinfo->conf.offloads = txq->offloads;\n-\tqinfo->conf.tx_deferred_start = 0;\n-}\n-\n-int\n-otx2_rx_burst_mode_get(struct rte_eth_dev *eth_dev,\n-\t\t __rte_unused uint16_t queue_id,\n-\t\t struct rte_eth_burst_mode *mode)\n-{\n-\tssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tconst struct burst_info {\n-\t\tuint16_t flags;\n-\t\tconst char *output;\n-\t} rx_offload_map[] = {\n-\t\t\t{NIX_RX_OFFLOAD_RSS_F, \"RSS,\"},\n-\t\t\t{NIX_RX_OFFLOAD_PTYPE_F, \" Ptype,\"},\n-\t\t\t{NIX_RX_OFFLOAD_CHECKSUM_F, \" Checksum,\"},\n-\t\t\t{NIX_RX_OFFLOAD_VLAN_STRIP_F, \" VLAN Strip,\"},\n-\t\t\t{NIX_RX_OFFLOAD_MARK_UPDATE_F, \" Mark Update,\"},\n-\t\t\t{NIX_RX_OFFLOAD_TSTAMP_F, \" Timestamp,\"},\n-\t\t\t{NIX_RX_MULTI_SEG_F, \" Scattered,\"}\n-\t};\n-\tstatic const char *const burst_mode[] = {\"Vector Neon, Rx Offloads:\",\n-\t\t\t\t\t\t \"Scalar, Rx Offloads:\"\n-\t};\n-\tuint32_t i;\n-\n-\t/* Update burst mode info */\n-\trc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],\n-\t\t\t str_size - bytes);\n-\tif (rc < 0)\n-\t\tgoto done;\n-\n-\tbytes += rc;\n-\n-\t/* Update Rx offload info */\n-\tfor (i = 0; i < RTE_DIM(rx_offload_map); i++) {\n-\t\tif (dev->rx_offload_flags & rx_offload_map[i].flags) {\n-\t\t\trc = rte_strscpy(mode->info + bytes,\n-\t\t\t\t\t rx_offload_map[i].output,\n-\t\t\t\t\t str_size - bytes);\n-\t\t\tif (rc < 0)\n-\t\t\t\tgoto done;\n-\n-\t\t\tbytes += rc;\n-\t\t}\n-\t}\n-\n-done:\n-\treturn 0;\n-}\n-\n-int\n-otx2_tx_burst_mode_get(struct rte_eth_dev *eth_dev,\n-\t\t __rte_unused uint16_t queue_id,\n-\t\t struct rte_eth_burst_mode *mode)\n-{\n-\tssize_t bytes = 0, str_size = RTE_ETH_BURST_MODE_INFO_SIZE, rc;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tconst struct burst_info {\n-\t\tuint16_t flags;\n-\t\tconst char *output;\n-\t} tx_offload_map[] = {\n-\t\t\t{NIX_TX_OFFLOAD_L3_L4_CSUM_F, \" Inner L3/L4 csum,\"},\n-\t\t\t{NIX_TX_OFFLOAD_OL3_OL4_CSUM_F, \" Outer L3/L4 csum,\"},\n-\t\t\t{NIX_TX_OFFLOAD_VLAN_QINQ_F, \" VLAN Insertion,\"},\n-\t\t\t{NIX_TX_OFFLOAD_MBUF_NOFF_F, \" MBUF free disable,\"},\n-\t\t\t{NIX_TX_OFFLOAD_TSTAMP_F, \" Timestamp,\"},\n-\t\t\t{NIX_TX_OFFLOAD_TSO_F, \" TSO,\"},\n-\t\t\t{NIX_TX_MULTI_SEG_F, \" Scattered,\"}\n-\t};\n-\tstatic const char *const burst_mode[] = {\"Vector Neon, Tx Offloads:\",\n-\t\t\t\t\t\t \"Scalar, Tx Offloads:\"\n-\t};\n-\tuint32_t i;\n-\n-\t/* Update burst mode info */\n-\trc = rte_strscpy(mode->info + bytes, burst_mode[dev->scalar_ena],\n-\t\t\t str_size - bytes);\n-\tif (rc < 0)\n-\t\tgoto done;\n-\n-\tbytes += rc;\n-\n-\t/* Update Tx offload info */\n-\tfor (i = 0; i < RTE_DIM(tx_offload_map); i++) {\n-\t\tif (dev->tx_offload_flags & tx_offload_map[i].flags) {\n-\t\t\trc = rte_strscpy(mode->info + bytes,\n-\t\t\t\t\t tx_offload_map[i].output,\n-\t\t\t\t\t str_size - bytes);\n-\t\t\tif (rc < 0)\n-\t\t\t\tgoto done;\n-\n-\t\t\tbytes += rc;\n-\t\t}\n-\t}\n-\n-done:\n-\treturn 0;\n-}\n-\n-static void\n-nix_rx_head_tail_get(struct otx2_eth_dev *dev,\n-\t\t uint32_t *head, uint32_t *tail, uint16_t queue_idx)\n-{\n-\tuint64_t reg, val;\n-\n-\tif (head == NULL || tail == NULL)\n-\t\treturn;\n-\n-\treg = (((uint64_t)queue_idx) << 32);\n-\tval = otx2_atomic64_add_nosync(reg, (int64_t *)\n-\t\t\t\t (dev->base + NIX_LF_CQ_OP_STATUS));\n-\tif (val & (OP_ERR | CQ_ERR))\n-\t\tval = 0;\n-\n-\t*tail = (uint32_t)(val & 0xFFFFF);\n-\t*head = (uint32_t)((val >> 20) & 0xFFFFF);\n-}\n-\n-uint32_t\n-otx2_nix_rx_queue_count(void *rx_queue)\n-{\n-\tstruct otx2_eth_rxq *rxq = rx_queue;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(rxq->eth_dev);\n-\tuint32_t head, tail;\n-\n-\tnix_rx_head_tail_get(dev, &head, &tail, rxq->rq);\n-\treturn (tail - head) % rxq->qlen;\n-}\n-\n-static inline int\n-nix_offset_has_packet(uint32_t head, uint32_t tail, uint16_t offset)\n-{\n-\t/* Check given offset(queue index) has packet filled by HW */\n-\tif (tail > head && offset <= tail && offset >= head)\n-\t\treturn 1;\n-\t/* Wrap around case */\n-\tif (head > tail && (offset >= head || offset <= tail))\n-\t\treturn 1;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_rx_descriptor_status(void *rx_queue, uint16_t offset)\n-{\n-\tstruct otx2_eth_rxq *rxq = rx_queue;\n-\tuint32_t head, tail;\n-\n-\tif (rxq->qlen <= offset)\n-\t\treturn -EINVAL;\n-\n-\tnix_rx_head_tail_get(otx2_eth_pmd_priv(rxq->eth_dev),\n-\t\t\t &head, &tail, rxq->rq);\n-\n-\tif (nix_offset_has_packet(head, tail, offset))\n-\t\treturn RTE_ETH_RX_DESC_DONE;\n-\telse\n-\t\treturn RTE_ETH_RX_DESC_AVAIL;\n-}\n-\n-static void\n-nix_tx_head_tail_get(struct otx2_eth_dev *dev,\n-\t\t uint32_t *head, uint32_t *tail, uint16_t queue_idx)\n-{\n-\tuint64_t reg, val;\n-\n-\tif (head == NULL || tail == NULL)\n-\t\treturn;\n-\n-\treg = (((uint64_t)queue_idx) << 32);\n-\tval = otx2_atomic64_add_nosync(reg, (int64_t *)\n-\t\t\t\t (dev->base + NIX_LF_SQ_OP_STATUS));\n-\tif (val & OP_ERR)\n-\t\tval = 0;\n-\n-\t*tail = (uint32_t)((val >> 28) & 0x3F);\n-\t*head = (uint32_t)((val >> 20) & 0x3F);\n-}\n-\n-int\n-otx2_nix_tx_descriptor_status(void *tx_queue, uint16_t offset)\n-{\n-\tstruct otx2_eth_txq *txq = tx_queue;\n-\tuint32_t head, tail;\n-\n-\tif (txq->qconf.nb_desc <= offset)\n-\t\treturn -EINVAL;\n-\n-\tnix_tx_head_tail_get(txq->dev, &head, &tail, txq->sq);\n-\n-\tif (nix_offset_has_packet(head, tail, offset))\n-\t\treturn RTE_ETH_TX_DESC_DONE;\n-\telse\n-\t\treturn RTE_ETH_TX_DESC_FULL;\n-}\n-\n-/* It is a NOP for octeontx2 as HW frees the buffer on xmit */\n-int\n-otx2_nix_tx_done_cleanup(void *txq, uint32_t free_cnt)\n-{\n-\tRTE_SET_USED(txq);\n-\tRTE_SET_USED(free_cnt);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,\n-\t\t\tsize_t fw_size)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint rc = (int)fw_size;\n-\n-\tif (fw_size > sizeof(dev->mkex_pfl_name))\n-\t\trc = sizeof(dev->mkex_pfl_name);\n-\n-\trc = strlcpy(fw_version, (char *)dev->mkex_pfl_name, rc);\n-\n-\trc += 1; /* Add the size of '\\0' */\n-\tif (fw_size < (size_t)rc)\n-\t\treturn rc;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_pool_ops_supported(struct rte_eth_dev *eth_dev, const char *pool)\n-{\n-\tRTE_SET_USED(eth_dev);\n-\n-\tif (!strcmp(pool, rte_mbuf_platform_mempool_ops()))\n-\t\treturn 0;\n-\n-\treturn -ENOTSUP;\n-}\n-\n-int\n-otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev __rte_unused,\n-\t\t\t const struct rte_flow_ops **ops)\n-{\n-\t*ops = &otx2_flow_ops;\n-\treturn 0;\n-}\n-\n-static struct cgx_fw_data *\n-nix_get_fwdata(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct cgx_fw_data *rsp = NULL;\n-\tint rc;\n-\n-\totx2_mbox_alloc_msg_cgx_get_aux_link_info(mbox);\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to get fw data: %d\", rc);\n-\t\treturn NULL;\n-\t}\n-\n-\treturn rsp;\n-}\n-\n-int\n-otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_dev_module_info *modinfo)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct cgx_fw_data *rsp;\n-\n-\trsp = nix_get_fwdata(dev);\n-\tif (rsp == NULL)\n-\t\treturn -EIO;\n-\n-\tmodinfo->type = rsp->fwdata.sfp_eeprom.sff_id;\n-\tmodinfo->eeprom_len = SFP_EEPROM_SIZE;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_get_module_eeprom(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_dev_eeprom_info *info)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct cgx_fw_data *rsp;\n-\n-\tif (info->offset + info->length > SFP_EEPROM_SIZE)\n-\t\treturn -EINVAL;\n-\n-\trsp = nix_get_fwdata(dev);\n-\tif (rsp == NULL)\n-\t\treturn -EIO;\n-\n-\totx2_mbox_memcpy(info->data, rsp->fwdata.sfp_eeprom.buf + info->offset,\n-\t\t\t info->length);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tdevinfo->min_rx_bufsize = NIX_MIN_FRS;\n-\tdevinfo->max_rx_pktlen = NIX_MAX_FRS;\n-\tdevinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT;\n-\tdevinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT;\n-\tdevinfo->max_mac_addrs = dev->max_mac_entries;\n-\tdevinfo->max_vfs = pci_dev->max_vfs;\n-\tdevinfo->max_mtu = devinfo->max_rx_pktlen - NIX_L2_OVERHEAD;\n-\tdevinfo->min_mtu = devinfo->min_rx_bufsize - NIX_L2_OVERHEAD;\n-\tif (dev->configured && otx2_ethdev_is_ptp_en(dev)) {\n-\t\tdevinfo->max_mtu -= NIX_TIMESYNC_RX_OFFSET;\n-\t\tdevinfo->min_mtu -= NIX_TIMESYNC_RX_OFFSET;\n-\t\tdevinfo->max_rx_pktlen -= NIX_TIMESYNC_RX_OFFSET;\n-\t}\n-\n-\tdevinfo->rx_offload_capa = dev->rx_offload_capa;\n-\tdevinfo->tx_offload_capa = dev->tx_offload_capa;\n-\tdevinfo->rx_queue_offload_capa = 0;\n-\tdevinfo->tx_queue_offload_capa = 0;\n-\n-\tdevinfo->reta_size = dev->rss_info.rss_size;\n-\tdevinfo->hash_key_size = NIX_HASH_KEY_SIZE;\n-\tdevinfo->flow_type_rss_offloads = NIX_RSS_OFFLOAD;\n-\n-\tdevinfo->default_rxconf = (struct rte_eth_rxconf) {\n-\t\t.rx_drop_en = 0,\n-\t\t.offloads = 0,\n-\t};\n-\n-\tdevinfo->default_txconf = (struct rte_eth_txconf) {\n-\t\t.offloads = 0,\n-\t};\n-\n-\tdevinfo->default_rxportconf = (struct rte_eth_dev_portconf) {\n-\t\t.ring_size = NIX_RX_DEFAULT_RING_SZ,\n-\t};\n-\n-\tdevinfo->rx_desc_lim = (struct rte_eth_desc_lim) {\n-\t\t.nb_max = UINT16_MAX,\n-\t\t.nb_min = NIX_RX_MIN_DESC,\n-\t\t.nb_align = NIX_RX_MIN_DESC_ALIGN,\n-\t\t.nb_seg_max = NIX_RX_NB_SEG_MAX,\n-\t\t.nb_mtu_seg_max = NIX_RX_NB_SEG_MAX,\n-\t};\n-\tdevinfo->rx_desc_lim.nb_max =\n-\t\tRTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max,\n-\t\t\t\t NIX_RX_MIN_DESC_ALIGN);\n-\n-\tdevinfo->tx_desc_lim = (struct rte_eth_desc_lim) {\n-\t\t.nb_max = UINT16_MAX,\n-\t\t.nb_min = 1,\n-\t\t.nb_align = 1,\n-\t\t.nb_seg_max = NIX_TX_NB_SEG_MAX,\n-\t\t.nb_mtu_seg_max = NIX_TX_NB_SEG_MAX,\n-\t};\n-\n-\t/* Auto negotiation disabled */\n-\tdevinfo->speed_capa = RTE_ETH_LINK_SPEED_FIXED;\n-\tif (!otx2_dev_is_vf_or_sdp(dev) && !otx2_dev_is_lbk(dev)) {\n-\t\tdevinfo->speed_capa |= RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G |\n-\t\t\tRTE_ETH_LINK_SPEED_25G | RTE_ETH_LINK_SPEED_40G;\n-\n-\t\t/* 50G and 100G to be supported for board version C0\n-\t\t * and above.\n-\t\t */\n-\t\tif (!otx2_dev_is_Ax(dev))\n-\t\t\tdevinfo->speed_capa |= RTE_ETH_LINK_SPEED_50G |\n-\t\t\t\t\t RTE_ETH_LINK_SPEED_100G;\n-\t}\n-\n-\tdevinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |\n-\t\t\t\tRTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;\n-\tdevinfo->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_sec.c b/drivers/net/octeontx2/otx2_ethdev_sec.c\ndeleted file mode 100644\nindex 4d40184de4..0000000000\n--- a/drivers/net/octeontx2/otx2_ethdev_sec.c\n+++ /dev/null\n@@ -1,923 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#include <rte_cryptodev.h>\n-#include <rte_esp.h>\n-#include <rte_ethdev.h>\n-#include <rte_eventdev.h>\n-#include <rte_ip.h>\n-#include <rte_malloc.h>\n-#include <rte_memzone.h>\n-#include <rte_security.h>\n-#include <rte_security_driver.h>\n-#include <rte_udp.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_cryptodev_qp.h\"\n-#include \"otx2_ethdev.h\"\n-#include \"otx2_ethdev_sec.h\"\n-#include \"otx2_ipsec_fp.h\"\n-#include \"otx2_sec_idev.h\"\n-#include \"otx2_security.h\"\n-\n-#define ERR_STR_SZ 256\n-\n-struct eth_sec_tag_const {\n-\tRTE_STD_C11\n-\tunion {\n-\t\tstruct {\n-\t\t\tuint32_t rsvd_11_0 : 12;\n-\t\t\tuint32_t port : 8;\n-\t\t\tuint32_t event_type : 4;\n-\t\t\tuint32_t rsvd_31_24 : 8;\n-\t\t};\n-\t\tuint32_t u32;\n-\t};\n-};\n-\n-static struct rte_cryptodev_capabilities otx2_eth_sec_crypto_caps[] = {\n-\t{\t/* AES GCM */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\n-\t\t\t{.aead = {\n-\t\t\t\t.algo = RTE_CRYPTO_AEAD_AES_GCM,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t\t.aad_size = {\n-\t\t\t\t\t.min = 8,\n-\t\t\t\t\t.max = 12,\n-\t\t\t\t\t.increment = 4\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 12,\n-\t\t\t\t\t.max = 12,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* AES CBC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n-\t\t\t{.cipher = {\n-\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_CBC,\n-\t\t\t\t.block_size = 16,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 32,\n-\t\t\t\t\t.increment = 8\n-\t\t\t\t},\n-\t\t\t\t.iv_size = {\n-\t\t\t\t\t.min = 16,\n-\t\t\t\t\t.max = 16,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t}\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\t{\t/* SHA1 HMAC */\n-\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n-\t\t{.sym = {\n-\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n-\t\t\t{.auth = {\n-\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,\n-\t\t\t\t.block_size = 64,\n-\t\t\t\t.key_size = {\n-\t\t\t\t\t.min = 20,\n-\t\t\t\t\t.max = 64,\n-\t\t\t\t\t.increment = 1\n-\t\t\t\t},\n-\t\t\t\t.digest_size = {\n-\t\t\t\t\t.min = 12,\n-\t\t\t\t\t.max = 12,\n-\t\t\t\t\t.increment = 0\n-\t\t\t\t},\n-\t\t\t}, }\n-\t\t}, }\n-\t},\n-\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n-};\n-\n-static const struct rte_security_capability otx2_eth_sec_capabilities[] = {\n-\t{\t/* IPsec Inline Protocol ESP Tunnel Ingress */\n-\t\t.action = RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL,\n-\t\t.protocol = RTE_SECURITY_PROTOCOL_IPSEC,\n-\t\t.ipsec = {\n-\t\t\t.proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,\n-\t\t\t.mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,\n-\t\t\t.direction = RTE_SECURITY_IPSEC_SA_DIR_INGRESS,\n-\t\t\t.options = { 0 }\n-\t\t},\n-\t\t.crypto_capabilities = otx2_eth_sec_crypto_caps,\n-\t\t.ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA\n-\t},\n-\t{\t/* IPsec Inline Protocol ESP Tunnel Egress */\n-\t\t.action = RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL,\n-\t\t.protocol = RTE_SECURITY_PROTOCOL_IPSEC,\n-\t\t.ipsec = {\n-\t\t\t.proto = RTE_SECURITY_IPSEC_SA_PROTO_ESP,\n-\t\t\t.mode = RTE_SECURITY_IPSEC_SA_MODE_TUNNEL,\n-\t\t\t.direction = RTE_SECURITY_IPSEC_SA_DIR_EGRESS,\n-\t\t\t.options = { 0 }\n-\t\t},\n-\t\t.crypto_capabilities = otx2_eth_sec_crypto_caps,\n-\t\t.ol_flags = RTE_SECURITY_TX_OLOAD_NEED_MDATA\n-\t},\n-\t{\n-\t\t.action = RTE_SECURITY_ACTION_TYPE_NONE\n-\t}\n-};\n-\n-static void\n-lookup_mem_sa_tbl_clear(struct rte_eth_dev *eth_dev)\n-{\n-\tstatic const char name[] = OTX2_NIX_FASTPATH_LOOKUP_MEM;\n-\tuint16_t port = eth_dev->data->port_id;\n-\tconst struct rte_memzone *mz;\n-\tuint64_t **sa_tbl;\n-\tuint8_t *mem;\n-\n-\tmz = rte_memzone_lookup(name);\n-\tif (mz == NULL)\n-\t\treturn;\n-\n-\tmem = mz->addr;\n-\n-\tsa_tbl = (uint64_t **)RTE_PTR_ADD(mem, OTX2_NIX_SA_TBL_START);\n-\tif (sa_tbl[port] == NULL)\n-\t\treturn;\n-\n-\trte_free(sa_tbl[port]);\n-\tsa_tbl[port] = NULL;\n-}\n-\n-static int\n-lookup_mem_sa_index_update(struct rte_eth_dev *eth_dev, int spi, void *sa,\n-\t\t\t char *err_str)\n-{\n-\tstatic const char name[] = OTX2_NIX_FASTPATH_LOOKUP_MEM;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint16_t port = eth_dev->data->port_id;\n-\tconst struct rte_memzone *mz;\n-\tuint64_t **sa_tbl;\n-\tuint8_t *mem;\n-\n-\tmz = rte_memzone_lookup(name);\n-\tif (mz == NULL) {\n-\t\tsnprintf(err_str, ERR_STR_SZ,\n-\t\t\t \"Could not find fastpath lookup table\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tmem = mz->addr;\n-\n-\tsa_tbl = (uint64_t **)RTE_PTR_ADD(mem, OTX2_NIX_SA_TBL_START);\n-\n-\tif (sa_tbl[port] == NULL) {\n-\t\tsa_tbl[port] = rte_malloc(NULL, dev->ipsec_in_max_spi *\n-\t\t\t\t\t sizeof(uint64_t), 0);\n-\t}\n-\n-\tsa_tbl[port][spi] = (uint64_t)sa;\n-\n-\treturn 0;\n-}\n-\n-static inline void\n-in_sa_mz_name_get(char *name, int size, uint16_t port)\n-{\n-\tsnprintf(name, size, \"otx2_ipsec_in_sadb_%u\", port);\n-}\n-\n-static struct otx2_ipsec_fp_in_sa *\n-in_sa_get(uint16_t port, int sa_index)\n-{\n-\tchar name[RTE_MEMZONE_NAMESIZE];\n-\tstruct otx2_ipsec_fp_in_sa *sa;\n-\tconst struct rte_memzone *mz;\n-\n-\tin_sa_mz_name_get(name, RTE_MEMZONE_NAMESIZE, port);\n-\tmz = rte_memzone_lookup(name);\n-\tif (mz == NULL) {\n-\t\totx2_err(\"Could not get the memzone reserved for IN SA DB\");\n-\t\treturn NULL;\n-\t}\n-\n-\tsa = mz->addr;\n-\n-\treturn sa + sa_index;\n-}\n-\n-static int\n-ipsec_sa_const_set(struct rte_security_ipsec_xform *ipsec,\n-\t\t struct rte_crypto_sym_xform *xform,\n-\t\t struct otx2_sec_session_ipsec_ip *sess)\n-{\n-\tstruct rte_crypto_sym_xform *cipher_xform, *auth_xform;\n-\n-\tsess->partial_len = sizeof(struct rte_ipv4_hdr);\n-\n-\tif (ipsec->proto == RTE_SECURITY_IPSEC_SA_PROTO_ESP) {\n-\t\tsess->partial_len += sizeof(struct rte_esp_hdr);\n-\t\tsess->roundup_len = sizeof(struct rte_esp_tail);\n-\t} else if (ipsec->proto == RTE_SECURITY_IPSEC_SA_PROTO_AH) {\n-\t\tsess->partial_len += OTX2_SEC_AH_HDR_LEN;\n-\t} else {\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (ipsec->options.udp_encap)\n-\t\tsess->partial_len += sizeof(struct rte_udp_hdr);\n-\n-\tif (xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\tif (xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM) {\n-\t\t\tsess->partial_len += OTX2_SEC_AES_GCM_IV_LEN;\n-\t\t\tsess->partial_len += OTX2_SEC_AES_GCM_MAC_LEN;\n-\t\t\tsess->roundup_byte = OTX2_SEC_AES_GCM_ROUNDUP_BYTE_LEN;\n-\t\t}\n-\t\treturn 0;\n-\t}\n-\n-\tif (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_EGRESS) {\n-\t\tcipher_xform = xform;\n-\t\tauth_xform = xform->next;\n-\t} else if (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS) {\n-\t\tauth_xform = xform;\n-\t\tcipher_xform = xform->next;\n-\t} else {\n-\t\treturn -EINVAL;\n-\t}\n-\tif (cipher_xform->cipher.algo == RTE_CRYPTO_CIPHER_AES_CBC) {\n-\t\tsess->partial_len += OTX2_SEC_AES_CBC_IV_LEN;\n-\t\tsess->roundup_byte = OTX2_SEC_AES_CBC_ROUNDUP_BYTE_LEN;\n-\t} else {\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (auth_xform->auth.algo == RTE_CRYPTO_AUTH_SHA1_HMAC)\n-\t\tsess->partial_len += OTX2_SEC_SHA1_HMAC_LEN;\n-\telse\n-\t\treturn -EINVAL;\n-\n-\treturn 0;\n-}\n-\n-static int\n-hmac_init(struct otx2_ipsec_fp_sa_ctl *ctl, struct otx2_cpt_qp *qp,\n-\t const uint8_t *auth_key, int len, uint8_t *hmac_key)\n-{\n-\tstruct inst_data {\n-\t\tstruct otx2_cpt_res cpt_res;\n-\t\tuint8_t buffer[64];\n-\t} *md;\n-\n-\tvolatile struct otx2_cpt_res *res;\n-\tuint64_t timeout, lmt_status;\n-\tstruct otx2_cpt_inst_s inst;\n-\trte_iova_t md_iova;\n-\tint ret;\n-\n-\tmemset(&inst, 0, sizeof(struct otx2_cpt_inst_s));\n-\n-\tmd = rte_zmalloc(NULL, sizeof(struct inst_data), OTX2_CPT_RES_ALIGN);\n-\tif (md == NULL)\n-\t\treturn -ENOMEM;\n-\n-\tmemcpy(md->buffer, auth_key, len);\n-\n-\tmd_iova = rte_malloc_virt2iova(md);\n-\tif (md_iova == RTE_BAD_IOVA) {\n-\t\tret = -EINVAL;\n-\t\tgoto free_md;\n-\t}\n-\n-\tinst.res_addr = md_iova + offsetof(struct inst_data, cpt_res);\n-\tinst.opcode = OTX2_CPT_OP_WRITE_HMAC_IPAD_OPAD;\n-\tinst.param2 = ctl->auth_type;\n-\tinst.dlen = len;\n-\tinst.dptr = md_iova + offsetof(struct inst_data, buffer);\n-\tinst.rptr = inst.dptr;\n-\tinst.egrp = OTX2_CPT_EGRP_INLINE_IPSEC;\n-\n-\tmd->cpt_res.compcode = 0;\n-\tmd->cpt_res.uc_compcode = 0xff;\n-\n-\ttimeout = rte_get_timer_cycles() + 5 * rte_get_timer_hz();\n-\n-\trte_io_wmb();\n-\n-\tdo {\n-\t\totx2_lmt_mov(qp->lmtline, &inst, 2);\n-\t\tlmt_status = otx2_lmt_submit(qp->lf_nq_reg);\n-\t} while (lmt_status == 0);\n-\n-\tres = (volatile struct otx2_cpt_res *)&md->cpt_res;\n-\n-\t/* Wait until instruction completes or times out */\n-\twhile (res->uc_compcode == 0xff) {\n-\t\tif (rte_get_timer_cycles() > timeout)\n-\t\t\tbreak;\n-\t}\n-\n-\tif (res->u16[0] != OTX2_SEC_COMP_GOOD) {\n-\t\tret = -EIO;\n-\t\tgoto free_md;\n-\t}\n-\n-\t/* Retrieve the ipad and opad from rptr */\n-\tmemcpy(hmac_key, md->buffer, 48);\n-\n-\tret = 0;\n-\n-free_md:\n-\trte_free(md);\n-\treturn ret;\n-}\n-\n-static int\n-eth_sec_ipsec_out_sess_create(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_security_ipsec_xform *ipsec,\n-\t\t\t struct rte_crypto_sym_xform *crypto_xform,\n-\t\t\t struct rte_security_session *sec_sess)\n-{\n-\tstruct rte_crypto_sym_xform *auth_xform, *cipher_xform;\n-\tstruct otx2_sec_session_ipsec_ip *sess;\n-\tuint16_t port = eth_dev->data->port_id;\n-\tint cipher_key_len, auth_key_len, ret;\n-\tconst uint8_t *cipher_key, *auth_key;\n-\tstruct otx2_ipsec_fp_sa_ctl *ctl;\n-\tstruct otx2_ipsec_fp_out_sa *sa;\n-\tstruct otx2_sec_session *priv;\n-\tstruct otx2_cpt_inst_s inst;\n-\tstruct otx2_cpt_qp *qp;\n-\n-\tpriv = get_sec_session_private_data(sec_sess);\n-\tpriv->ipsec.dir = RTE_SECURITY_IPSEC_SA_DIR_EGRESS;\n-\tsess = &priv->ipsec.ip;\n-\n-\tsa = &sess->out_sa;\n-\tctl = &sa->ctl;\n-\tif (ctl->valid) {\n-\t\totx2_err(\"SA already registered\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tmemset(sess, 0, sizeof(struct otx2_sec_session_ipsec_ip));\n-\n-\tsess->seq = 1;\n-\n-\tret = ipsec_sa_const_set(ipsec, crypto_xform, sess);\n-\tif (ret < 0)\n-\t\treturn ret;\n-\n-\tif (crypto_xform->type == RTE_CRYPTO_SYM_XFORM_AEAD)\n-\t\tmemcpy(sa->nonce, &ipsec->salt, 4);\n-\n-\tif (ipsec->options.udp_encap == 1) {\n-\t\tsa->udp_src = 4500;\n-\t\tsa->udp_dst = 4500;\n-\t}\n-\n-\tif (ipsec->mode == RTE_SECURITY_IPSEC_SA_MODE_TUNNEL) {\n-\t\t/* Start ip id from 1 */\n-\t\tsess->ip_id = 1;\n-\n-\t\tif (ipsec->tunnel.type == RTE_SECURITY_IPSEC_TUNNEL_IPV4) {\n-\t\t\tmemcpy(&sa->ip_src, &ipsec->tunnel.ipv4.src_ip,\n-\t\t\t sizeof(struct in_addr));\n-\t\t\tmemcpy(&sa->ip_dst, &ipsec->tunnel.ipv4.dst_ip,\n-\t\t\t sizeof(struct in_addr));\n-\t\t} else {\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t} else {\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tcipher_xform = crypto_xform;\n-\tauth_xform = crypto_xform->next;\n-\n-\tcipher_key_len = 0;\n-\tauth_key_len = 0;\n-\tauth_key = NULL;\n-\n-\tif (crypto_xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\tcipher_key = crypto_xform->aead.key.data;\n-\t\tcipher_key_len = crypto_xform->aead.key.length;\n-\t} else {\n-\t\tcipher_key = cipher_xform->cipher.key.data;\n-\t\tcipher_key_len = cipher_xform->cipher.key.length;\n-\t\tauth_key = auth_xform->auth.key.data;\n-\t\tauth_key_len = auth_xform->auth.key.length;\n-\t}\n-\n-\tif (cipher_key_len != 0)\n-\t\tmemcpy(sa->cipher_key, cipher_key, cipher_key_len);\n-\telse\n-\t\treturn -EINVAL;\n-\n-\t/* Determine word 7 of CPT instruction */\n-\tinst.u64[7] = 0;\n-\tinst.egrp = OTX2_CPT_EGRP_INLINE_IPSEC;\n-\tinst.cptr = rte_mempool_virt2iova(sa);\n-\tsess->inst_w7 = inst.u64[7];\n-\n-\t/* Get CPT QP to be used for this SA */\n-\tret = otx2_sec_idev_tx_cpt_qp_get(port, &qp);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tsess->qp = qp;\n-\n-\tsess->cpt_lmtline = qp->lmtline;\n-\tsess->cpt_nq_reg = qp->lf_nq_reg;\n-\n-\t/* Populate control word */\n-\tret = ipsec_fp_sa_ctl_set(ipsec, crypto_xform, ctl);\n-\tif (ret)\n-\t\tgoto cpt_put;\n-\n-\tif (auth_key_len && auth_key) {\n-\t\tret = hmac_init(ctl, qp, auth_key, auth_key_len, sa->hmac_key);\n-\t\tif (ret)\n-\t\t\tgoto cpt_put;\n-\t}\n-\n-\trte_io_wmb();\n-\tctl->valid = 1;\n-\n-\treturn 0;\n-cpt_put:\n-\totx2_sec_idev_tx_cpt_qp_put(sess->qp);\n-\treturn ret;\n-}\n-\n-static int\n-eth_sec_ipsec_in_sess_create(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_security_ipsec_xform *ipsec,\n-\t\t\t struct rte_crypto_sym_xform *crypto_xform,\n-\t\t\t struct rte_security_session *sec_sess)\n-{\n-\tstruct rte_crypto_sym_xform *auth_xform, *cipher_xform;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_sec_session_ipsec_ip *sess;\n-\tuint16_t port = eth_dev->data->port_id;\n-\tint cipher_key_len, auth_key_len, ret;\n-\tconst uint8_t *cipher_key, *auth_key;\n-\tstruct otx2_ipsec_fp_sa_ctl *ctl;\n-\tstruct otx2_ipsec_fp_in_sa *sa;\n-\tstruct otx2_sec_session *priv;\n-\tchar err_str[ERR_STR_SZ];\n-\tstruct otx2_cpt_qp *qp;\n-\n-\tmemset(err_str, 0, ERR_STR_SZ);\n-\n-\tif (ipsec->spi >= dev->ipsec_in_max_spi) {\n-\t\totx2_err(\"SPI exceeds max supported\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tsa = in_sa_get(port, ipsec->spi);\n-\tif (sa == NULL)\n-\t\treturn -ENOMEM;\n-\n-\tctl = &sa->ctl;\n-\n-\tpriv = get_sec_session_private_data(sec_sess);\n-\tpriv->ipsec.dir = RTE_SECURITY_IPSEC_SA_DIR_INGRESS;\n-\tsess = &priv->ipsec.ip;\n-\n-\trte_spinlock_lock(&dev->ipsec_tbl_lock);\n-\n-\tif (ctl->valid) {\n-\t\tsnprintf(err_str, ERR_STR_SZ, \"SA already registered\");\n-\t\tret = -EEXIST;\n-\t\tgoto tbl_unlock;\n-\t}\n-\n-\tmemset(sa, 0, sizeof(struct otx2_ipsec_fp_in_sa));\n-\n-\tauth_xform = crypto_xform;\n-\tcipher_xform = crypto_xform->next;\n-\n-\tcipher_key_len = 0;\n-\tauth_key_len = 0;\n-\tauth_key = NULL;\n-\n-\tif (crypto_xform->type == RTE_CRYPTO_SYM_XFORM_AEAD) {\n-\t\tif (crypto_xform->aead.algo == RTE_CRYPTO_AEAD_AES_GCM)\n-\t\t\tmemcpy(sa->nonce, &ipsec->salt, 4);\n-\t\tcipher_key = crypto_xform->aead.key.data;\n-\t\tcipher_key_len = crypto_xform->aead.key.length;\n-\t} else {\n-\t\tcipher_key = cipher_xform->cipher.key.data;\n-\t\tcipher_key_len = cipher_xform->cipher.key.length;\n-\t\tauth_key = auth_xform->auth.key.data;\n-\t\tauth_key_len = auth_xform->auth.key.length;\n-\t}\n-\n-\tif (cipher_key_len != 0) {\n-\t\tmemcpy(sa->cipher_key, cipher_key, cipher_key_len);\n-\t} else {\n-\t\tsnprintf(err_str, ERR_STR_SZ, \"Invalid cipher key len\");\n-\t\tret = -EINVAL;\n-\t\tgoto sa_clear;\n-\t}\n-\n-\tsess->in_sa = sa;\n-\n-\tsa->userdata = priv->userdata;\n-\n-\tsa->replay_win_sz = ipsec->replay_win_sz;\n-\n-\tif (lookup_mem_sa_index_update(eth_dev, ipsec->spi, sa, err_str)) {\n-\t\tret = -EINVAL;\n-\t\tgoto sa_clear;\n-\t}\n-\n-\tret = ipsec_fp_sa_ctl_set(ipsec, crypto_xform, ctl);\n-\tif (ret) {\n-\t\tsnprintf(err_str, ERR_STR_SZ,\n-\t\t\t\"Could not set SA CTL word (err: %d)\", ret);\n-\t\tgoto sa_clear;\n-\t}\n-\n-\tif (auth_key_len && auth_key) {\n-\t\t/* Get a queue pair for HMAC init */\n-\t\tret = otx2_sec_idev_tx_cpt_qp_get(port, &qp);\n-\t\tif (ret) {\n-\t\t\tsnprintf(err_str, ERR_STR_SZ, \"Could not get CPT QP\");\n-\t\t\tgoto sa_clear;\n-\t\t}\n-\n-\t\tret = hmac_init(ctl, qp, auth_key, auth_key_len, sa->hmac_key);\n-\t\totx2_sec_idev_tx_cpt_qp_put(qp);\n-\t\tif (ret) {\n-\t\t\tsnprintf(err_str, ERR_STR_SZ, \"Could not put CPT QP\");\n-\t\t\tgoto sa_clear;\n-\t\t}\n-\t}\n-\n-\tif (sa->replay_win_sz) {\n-\t\tif (sa->replay_win_sz > OTX2_IPSEC_MAX_REPLAY_WIN_SZ) {\n-\t\t\tsnprintf(err_str, ERR_STR_SZ,\n-\t\t\t\t \"Replay window size is not supported\");\n-\t\t\tret = -ENOTSUP;\n-\t\t\tgoto sa_clear;\n-\t\t}\n-\t\tsa->replay = rte_zmalloc(NULL, sizeof(struct otx2_ipsec_replay),\n-\t\t\t\t0);\n-\t\tif (sa->replay == NULL) {\n-\t\t\tsnprintf(err_str, ERR_STR_SZ,\n-\t\t\t\t\"Could not allocate memory\");\n-\t\t\tret = -ENOMEM;\n-\t\t\tgoto sa_clear;\n-\t\t}\n-\n-\t\trte_spinlock_init(&sa->replay->lock);\n-\t\t/*\n-\t\t * Set window bottom to 1, base and top to size of\n-\t\t * window\n-\t\t */\n-\t\tsa->replay->winb = 1;\n-\t\tsa->replay->wint = sa->replay_win_sz;\n-\t\tsa->replay->base = sa->replay_win_sz;\n-\t\tsa->esn_low = 0;\n-\t\tsa->esn_hi = 0;\n-\t}\n-\n-\trte_io_wmb();\n-\tctl->valid = 1;\n-\n-\trte_spinlock_unlock(&dev->ipsec_tbl_lock);\n-\treturn 0;\n-\n-sa_clear:\n-\tmemset(sa, 0, sizeof(struct otx2_ipsec_fp_in_sa));\n-\n-tbl_unlock:\n-\trte_spinlock_unlock(&dev->ipsec_tbl_lock);\n-\n-\totx2_err(\"%s\", err_str);\n-\n-\treturn ret;\n-}\n-\n-static int\n-eth_sec_ipsec_sess_create(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_security_ipsec_xform *ipsec,\n-\t\t\t struct rte_crypto_sym_xform *crypto_xform,\n-\t\t\t struct rte_security_session *sess)\n-{\n-\tint ret;\n-\n-\tret = ipsec_fp_xform_verify(ipsec, crypto_xform);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tif (ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS)\n-\t\treturn eth_sec_ipsec_in_sess_create(eth_dev, ipsec,\n-\t\t\t\t\t\t crypto_xform, sess);\n-\telse\n-\t\treturn eth_sec_ipsec_out_sess_create(eth_dev, ipsec,\n-\t\t\t\t\t\t crypto_xform, sess);\n-}\n-\n-static int\n-otx2_eth_sec_session_create(void *device,\n-\t\t\t struct rte_security_session_conf *conf,\n-\t\t\t struct rte_security_session *sess,\n-\t\t\t struct rte_mempool *mempool)\n-{\n-\tstruct otx2_sec_session *priv;\n-\tint ret;\n-\n-\tif (conf->action_type != RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL)\n-\t\treturn -ENOTSUP;\n-\n-\tif (rte_mempool_get(mempool, (void **)&priv)) {\n-\t\totx2_err(\"Could not allocate security session private data\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tset_sec_session_private_data(sess, priv);\n-\n-\t/*\n-\t * Save userdata provided by the application. For ingress packets, this\n-\t * could be used to identify the SA.\n-\t */\n-\tpriv->userdata = conf->userdata;\n-\n-\tif (conf->protocol == RTE_SECURITY_PROTOCOL_IPSEC)\n-\t\tret = eth_sec_ipsec_sess_create(device, &conf->ipsec,\n-\t\t\t\t\t\tconf->crypto_xform,\n-\t\t\t\t\t\tsess);\n-\telse\n-\t\tret = -ENOTSUP;\n-\n-\tif (ret)\n-\t\tgoto mempool_put;\n-\n-\treturn 0;\n-\n-mempool_put:\n-\trte_mempool_put(mempool, priv);\n-\tset_sec_session_private_data(sess, NULL);\n-\treturn ret;\n-}\n-\n-static void\n-otx2_eth_sec_free_anti_replay(struct otx2_ipsec_fp_in_sa *sa)\n-{\n-\tif (sa != NULL) {\n-\t\tif (sa->replay_win_sz && sa->replay)\n-\t\t\trte_free(sa->replay);\n-\t}\n-}\n-\n-static int\n-otx2_eth_sec_session_destroy(void *device,\n-\t\t\t struct rte_security_session *sess)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(device);\n-\tstruct otx2_sec_session_ipsec_ip *sess_ip;\n-\tstruct otx2_ipsec_fp_in_sa *sa;\n-\tstruct otx2_sec_session *priv;\n-\tstruct rte_mempool *sess_mp;\n-\tint ret;\n-\n-\tpriv = get_sec_session_private_data(sess);\n-\tif (priv == NULL)\n-\t\treturn -EINVAL;\n-\n-\tsess_ip = &priv->ipsec.ip;\n-\n-\tif (priv->ipsec.dir == RTE_SECURITY_IPSEC_SA_DIR_INGRESS) {\n-\t\trte_spinlock_lock(&dev->ipsec_tbl_lock);\n-\t\tsa = sess_ip->in_sa;\n-\n-\t\t/* Release the anti replay window */\n-\t\totx2_eth_sec_free_anti_replay(sa);\n-\n-\t\t/* Clear SA table entry */\n-\t\tif (sa != NULL) {\n-\t\t\tsa->ctl.valid = 0;\n-\t\t\trte_io_wmb();\n-\t\t}\n-\n-\t\trte_spinlock_unlock(&dev->ipsec_tbl_lock);\n-\t}\n-\n-\t/* Release CPT LF used for this session */\n-\tif (sess_ip->qp != NULL) {\n-\t\tret = otx2_sec_idev_tx_cpt_qp_put(sess_ip->qp);\n-\t\tif (ret)\n-\t\t\treturn ret;\n-\t}\n-\n-\tsess_mp = rte_mempool_from_obj(priv);\n-\n-\tset_sec_session_private_data(sess, NULL);\n-\trte_mempool_put(sess_mp, priv);\n-\n-\treturn 0;\n-}\n-\n-static unsigned int\n-otx2_eth_sec_session_get_size(void *device __rte_unused)\n-{\n-\treturn sizeof(struct otx2_sec_session);\n-}\n-\n-static const struct rte_security_capability *\n-otx2_eth_sec_capabilities_get(void *device __rte_unused)\n-{\n-\treturn otx2_eth_sec_capabilities;\n-}\n-\n-static struct rte_security_ops otx2_eth_sec_ops = {\n-\t.session_create\t\t= otx2_eth_sec_session_create,\n-\t.session_destroy\t= otx2_eth_sec_session_destroy,\n-\t.session_get_size\t= otx2_eth_sec_session_get_size,\n-\t.capabilities_get\t= otx2_eth_sec_capabilities_get\n-};\n-\n-int\n-otx2_eth_sec_ctx_create(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct rte_security_ctx *ctx;\n-\tint ret;\n-\n-\tctx = rte_malloc(\"otx2_eth_sec_ctx\",\n-\t\t\t sizeof(struct rte_security_ctx), 0);\n-\tif (ctx == NULL)\n-\t\treturn -ENOMEM;\n-\n-\tret = otx2_sec_idev_cfg_init(eth_dev->data->port_id);\n-\tif (ret) {\n-\t\trte_free(ctx);\n-\t\treturn ret;\n-\t}\n-\n-\t/* Populate ctx */\n-\n-\tctx->device = eth_dev;\n-\tctx->ops = &otx2_eth_sec_ops;\n-\tctx->sess_cnt = 0;\n-\tctx->flags =\n-\t\t(RTE_SEC_CTX_F_FAST_SET_MDATA | RTE_SEC_CTX_F_FAST_GET_UDATA);\n-\n-\teth_dev->security_ctx = ctx;\n-\n-\treturn 0;\n-}\n-\n-void\n-otx2_eth_sec_ctx_destroy(struct rte_eth_dev *eth_dev)\n-{\n-\trte_free(eth_dev->security_ctx);\n-}\n-\n-static int\n-eth_sec_ipsec_cfg(struct rte_eth_dev *eth_dev, uint8_t tt)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint16_t port = eth_dev->data->port_id;\n-\tstruct nix_inline_ipsec_lf_cfg *req;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct eth_sec_tag_const tag_const;\n-\tchar name[RTE_MEMZONE_NAMESIZE];\n-\tconst struct rte_memzone *mz;\n-\n-\tin_sa_mz_name_get(name, RTE_MEMZONE_NAMESIZE, port);\n-\tmz = rte_memzone_lookup(name);\n-\tif (mz == NULL)\n-\t\treturn -EINVAL;\n-\n-\treq = otx2_mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox);\n-\treq->enable = 1;\n-\treq->sa_base_addr = mz->iova;\n-\n-\treq->ipsec_cfg0.tt = tt;\n-\n-\ttag_const.u32 = 0;\n-\ttag_const.event_type = RTE_EVENT_TYPE_ETHDEV;\n-\ttag_const.port = port;\n-\treq->ipsec_cfg0.tag_const = tag_const.u32;\n-\n-\treq->ipsec_cfg0.sa_pow2_size =\n-\t\t\trte_log2_u32(sizeof(struct otx2_ipsec_fp_in_sa));\n-\treq->ipsec_cfg0.lenm1_max = NIX_MAX_FRS - 1;\n-\n-\treq->ipsec_cfg1.sa_idx_w = rte_log2_u32(dev->ipsec_in_max_spi);\n-\treq->ipsec_cfg1.sa_idx_max = dev->ipsec_in_max_spi - 1;\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-int\n-otx2_eth_sec_update_tag_type(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_aq_enq_rsp *rsp;\n-\tstruct nix_aq_enq_req *aq;\n-\tint ret;\n-\n-\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\taq->qidx = 0; /* Read RQ:0 context */\n-\taq->ctype = NIX_AQ_CTYPE_RQ;\n-\taq->op = NIX_AQ_INSTOP_READ;\n-\n-\tret = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (ret < 0) {\n-\t\totx2_err(\"Could not read RQ context\");\n-\t\treturn ret;\n-\t}\n-\n-\t/* Update tag type */\n-\tret = eth_sec_ipsec_cfg(eth_dev, rsp->rq.sso_tt);\n-\tif (ret < 0)\n-\t\totx2_err(\"Could not update sec eth tag type\");\n-\n-\treturn ret;\n-}\n-\n-int\n-otx2_eth_sec_init(struct rte_eth_dev *eth_dev)\n-{\n-\tconst size_t sa_width = sizeof(struct otx2_ipsec_fp_in_sa);\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint16_t port = eth_dev->data->port_id;\n-\tchar name[RTE_MEMZONE_NAMESIZE];\n-\tconst struct rte_memzone *mz;\n-\tint mz_sz, ret;\n-\tuint16_t nb_sa;\n-\n-\tRTE_BUILD_BUG_ON(sa_width < 32 || sa_width > 512 ||\n-\t\t\t !RTE_IS_POWER_OF_2(sa_width));\n-\n-\tif (!(dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) &&\n-\t !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY))\n-\t\treturn 0;\n-\n-\tif (rte_security_dynfield_register() < 0)\n-\t\treturn -rte_errno;\n-\n-\tnb_sa = dev->ipsec_in_max_spi;\n-\tmz_sz = nb_sa * sa_width;\n-\tin_sa_mz_name_get(name, RTE_MEMZONE_NAMESIZE, port);\n-\tmz = rte_memzone_reserve_aligned(name, mz_sz, rte_socket_id(),\n-\t\t\t\t\t RTE_MEMZONE_IOVA_CONTIG, OTX2_ALIGN);\n-\n-\tif (mz == NULL) {\n-\t\totx2_err(\"Could not allocate inbound SA DB\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tmemset(mz->addr, 0, mz_sz);\n-\n-\tret = eth_sec_ipsec_cfg(eth_dev, SSO_TT_ORDERED);\n-\tif (ret < 0) {\n-\t\totx2_err(\"Could not configure inline IPsec\");\n-\t\tgoto sec_fini;\n-\t}\n-\n-\trte_spinlock_init(&dev->ipsec_tbl_lock);\n-\n-\treturn 0;\n-\n-sec_fini:\n-\totx2_err(\"Could not configure device for security\");\n-\totx2_eth_sec_fini(eth_dev);\n-\treturn ret;\n-}\n-\n-void\n-otx2_eth_sec_fini(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint16_t port = eth_dev->data->port_id;\n-\tchar name[RTE_MEMZONE_NAMESIZE];\n-\n-\tif (!(dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY) &&\n-\t !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY))\n-\t\treturn;\n-\n-\tlookup_mem_sa_tbl_clear(eth_dev);\n-\n-\tin_sa_mz_name_get(name, RTE_MEMZONE_NAMESIZE, port);\n-\trte_memzone_free(rte_memzone_lookup(name));\n-}\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_sec.h b/drivers/net/octeontx2/otx2_ethdev_sec.h\ndeleted file mode 100644\nindex 298b00bf89..0000000000\n--- a/drivers/net/octeontx2/otx2_ethdev_sec.h\n+++ /dev/null\n@@ -1,130 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_ETHDEV_SEC_H__\n-#define __OTX2_ETHDEV_SEC_H__\n-\n-#include <rte_ethdev.h>\n-\n-#include \"otx2_ipsec_fp.h\"\n-#include \"otx2_ipsec_po.h\"\n-\n-#define OTX2_CPT_RES_ALIGN\t\t16\n-#define OTX2_NIX_SEND_DESC_ALIGN\t16\n-#define OTX2_CPT_INST_SIZE\t\t64\n-\n-#define OTX2_CPT_EGRP_INLINE_IPSEC\t1\n-\n-#define OTX2_CPT_OP_INLINE_IPSEC_OUTB\t\t(0x40 | 0x25)\n-#define OTX2_CPT_OP_INLINE_IPSEC_INB\t\t(0x40 | 0x26)\n-#define OTX2_CPT_OP_WRITE_HMAC_IPAD_OPAD\t(0x40 | 0x27)\n-\n-#define OTX2_SEC_CPT_COMP_GOOD\t0x1\n-#define OTX2_SEC_UC_COMP_GOOD\t0x0\n-#define OTX2_SEC_COMP_GOOD\t(OTX2_SEC_UC_COMP_GOOD << 8 | \\\n-\t\t\t\t OTX2_SEC_CPT_COMP_GOOD)\n-\n-/* CPT Result */\n-struct otx2_cpt_res {\n-\tunion {\n-\t\tstruct {\n-\t\t\tuint64_t compcode:8;\n-\t\t\tuint64_t uc_compcode:8;\n-\t\t\tuint64_t doneint:1;\n-\t\t\tuint64_t reserved_17_63:47;\n-\t\t\tuint64_t reserved_64_127;\n-\t\t};\n-\t\tuint16_t u16[8];\n-\t};\n-};\n-\n-struct otx2_cpt_inst_s {\n-\tunion {\n-\t\tstruct {\n-\t\t\t/* W0 */\n-\t\t\tuint64_t nixtxl : 3;\n-\t\t\tuint64_t doneint : 1;\n-\t\t\tuint64_t nixtx_addr : 60;\n-\t\t\t/* W1 */\n-\t\t\tuint64_t res_addr : 64;\n-\t\t\t/* W2 */\n-\t\t\tuint64_t tag : 32;\n-\t\t\tuint64_t tt : 2;\n-\t\t\tuint64_t grp : 10;\n-\t\t\tuint64_t rsvd_175_172 : 4;\n-\t\t\tuint64_t rvu_pf_func : 16;\n-\t\t\t/* W3 */\n-\t\t\tuint64_t qord : 1;\n-\t\t\tuint64_t rsvd_194_193 : 2;\n-\t\t\tuint64_t wqe_ptr : 61;\n-\t\t\t/* W4 */\n-\t\t\tuint64_t dlen : 16;\n-\t\t\tuint64_t param2 : 16;\n-\t\t\tuint64_t param1 : 16;\n-\t\t\tuint64_t opcode : 16;\n-\t\t\t/* W5 */\n-\t\t\tuint64_t dptr : 64;\n-\t\t\t/* W6 */\n-\t\t\tuint64_t rptr : 64;\n-\t\t\t/* W7 */\n-\t\t\tuint64_t cptr : 61;\n-\t\t\tuint64_t egrp : 3;\n-\t\t};\n-\t\tuint64_t u64[8];\n-\t};\n-};\n-\n-/*\n- * Security session for inline IPsec protocol offload. This is private data of\n- * inline capable PMD.\n- */\n-struct otx2_sec_session_ipsec_ip {\n-\tRTE_STD_C11\n-\tunion {\n-\t\t/*\n-\t\t * Inbound SA would accessed by crypto block. And so the memory\n-\t\t * is allocated differently and shared with the h/w. Only\n-\t\t * holding a pointer to this memory in the session private\n-\t\t * space.\n-\t\t */\n-\t\tvoid *in_sa;\n-\t\t/* Outbound SA */\n-\t\tstruct otx2_ipsec_fp_out_sa out_sa;\n-\t};\n-\n-\t/* Address of CPT LMTLINE */\n-\tvoid *cpt_lmtline;\n-\t/* CPT LF enqueue register address */\n-\trte_iova_t cpt_nq_reg;\n-\n-\t/* Pre calculated lengths and data for a session */\n-\tuint8_t partial_len;\n-\tuint8_t roundup_len;\n-\tuint8_t roundup_byte;\n-\tuint16_t ip_id;\n-\tunion {\n-\t\tuint64_t esn;\n-\t\tstruct {\n-\t\t\tuint32_t seq;\n-\t\t\tuint32_t esn_hi;\n-\t\t};\n-\t};\n-\n-\tuint64_t inst_w7;\n-\n-\t/* CPT QP used by SA */\n-\tstruct otx2_cpt_qp *qp;\n-};\n-\n-int otx2_eth_sec_ctx_create(struct rte_eth_dev *eth_dev);\n-\n-void otx2_eth_sec_ctx_destroy(struct rte_eth_dev *eth_dev);\n-\n-int otx2_eth_sec_update_tag_type(struct rte_eth_dev *eth_dev);\n-\n-int otx2_eth_sec_init(struct rte_eth_dev *eth_dev);\n-\n-void otx2_eth_sec_fini(struct rte_eth_dev *eth_dev);\n-\n-#endif /* __OTX2_ETHDEV_SEC_H__ */\ndiff --git a/drivers/net/octeontx2/otx2_ethdev_sec_tx.h b/drivers/net/octeontx2/otx2_ethdev_sec_tx.h\ndeleted file mode 100644\nindex 021782009f..0000000000\n--- a/drivers/net/octeontx2/otx2_ethdev_sec_tx.h\n+++ /dev/null\n@@ -1,182 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2020 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_ETHDEV_SEC_TX_H__\n-#define __OTX2_ETHDEV_SEC_TX_H__\n-\n-#include <rte_security.h>\n-#include <rte_mbuf.h>\n-\n-#include \"otx2_ethdev_sec.h\"\n-#include \"otx2_security.h\"\n-\n-struct otx2_ipsec_fp_out_hdr {\n-\tuint32_t ip_id;\n-\tuint32_t seq;\n-\tuint8_t iv[16];\n-};\n-\n-static __rte_always_inline int32_t\n-otx2_ipsec_fp_out_rlen_get(struct otx2_sec_session_ipsec_ip *sess,\n-\t\t\t uint32_t plen)\n-{\n-\tuint32_t enc_payload_len;\n-\n-\tenc_payload_len = RTE_ALIGN_CEIL(plen + sess->roundup_len,\n-\t\t\tsess->roundup_byte);\n-\n-\treturn sess->partial_len + enc_payload_len;\n-}\n-\n-static __rte_always_inline void\n-otx2_ssogws_head_wait(uint64_t base);\n-\n-static __rte_always_inline int\n-otx2_sec_event_tx(uint64_t base, struct rte_event *ev, struct rte_mbuf *m,\n-\t\t const struct otx2_eth_txq *txq, const uint32_t offload_flags)\n-{\n-\tuint32_t dlen, rlen, desc_headroom, extend_head, extend_tail;\n-\tstruct otx2_sec_session_ipsec_ip *sess;\n-\tstruct otx2_ipsec_fp_out_hdr *hdr;\n-\tstruct otx2_ipsec_fp_out_sa *sa;\n-\tuint64_t data_addr, desc_addr;\n-\tstruct otx2_sec_session *priv;\n-\tstruct otx2_cpt_inst_s inst;\n-\tuint64_t lmt_status;\n-\tchar *data;\n-\n-\tstruct desc {\n-\t\tstruct otx2_cpt_res cpt_res __rte_aligned(OTX2_CPT_RES_ALIGN);\n-\t\tstruct nix_send_hdr_s nix_hdr\n-\t\t\t\t__rte_aligned(OTX2_NIX_SEND_DESC_ALIGN);\n-\t\tunion nix_send_sg_s nix_sg;\n-\t\tstruct nix_iova_s nix_iova;\n-\t} *sd;\n-\n-\tpriv = (struct otx2_sec_session *)(*rte_security_dynfield(m));\n-\tsess = &priv->ipsec.ip;\n-\tsa = &sess->out_sa;\n-\n-\tRTE_ASSERT(sess->cpt_lmtline != NULL);\n-\tRTE_ASSERT(!(offload_flags & NIX_TX_OFFLOAD_VLAN_QINQ_F));\n-\n-\tdlen = rte_pktmbuf_pkt_len(m) + sizeof(*hdr) - RTE_ETHER_HDR_LEN;\n-\trlen = otx2_ipsec_fp_out_rlen_get(sess, dlen - sizeof(*hdr));\n-\n-\tRTE_BUILD_BUG_ON(OTX2_CPT_RES_ALIGN % OTX2_NIX_SEND_DESC_ALIGN);\n-\tRTE_BUILD_BUG_ON(sizeof(sd->cpt_res) % OTX2_NIX_SEND_DESC_ALIGN);\n-\n-\textend_head = sizeof(*hdr);\n-\textend_tail = rlen - dlen;\n-\n-\tdesc_headroom = (OTX2_CPT_RES_ALIGN - 1) + sizeof(*sd);\n-\n-\tif (unlikely(!rte_pktmbuf_is_contiguous(m)) ||\n-\t unlikely(rte_pktmbuf_headroom(m) < extend_head + desc_headroom) ||\n-\t unlikely(rte_pktmbuf_tailroom(m) < extend_tail)) {\n-\t\tgoto drop;\n-\t}\n-\n-\t/*\n-\t * Extend mbuf data to point to the expected packet buffer for NIX.\n-\t * This includes the Ethernet header followed by the encrypted IPsec\n-\t * payload\n-\t */\n-\trte_pktmbuf_append(m, extend_tail);\n-\tdata = rte_pktmbuf_prepend(m, extend_head);\n-\tdata_addr = rte_pktmbuf_iova(m);\n-\n-\t/*\n-\t * Move the Ethernet header, to insert otx2_ipsec_fp_out_hdr prior\n-\t * to the IP header\n-\t */\n-\tmemcpy(data, data + sizeof(*hdr), RTE_ETHER_HDR_LEN);\n-\n-\thdr = (struct otx2_ipsec_fp_out_hdr *)(data + RTE_ETHER_HDR_LEN);\n-\n-\tif (sa->ctl.enc_type == OTX2_IPSEC_FP_SA_ENC_AES_GCM) {\n-\t\t/* AES-128-GCM */\n-\t\tmemcpy(hdr->iv, &sa->nonce, 4);\n-\t\tmemset(hdr->iv + 4, 0, 12); //TODO: make it random\n-\t} else {\n-\t\t/* AES-128-[CBC] + [SHA1] */\n-\t\tmemset(hdr->iv, 0, 16); //TODO: make it random\n-\t}\n-\n-\t/* Keep CPT result and NIX send descriptors in headroom */\n-\tsd = (void *)RTE_PTR_ALIGN(data - desc_headroom, OTX2_CPT_RES_ALIGN);\n-\tdesc_addr = data_addr - RTE_PTR_DIFF(data, sd);\n-\n-\t/* Prepare CPT instruction */\n-\n-\tinst.nixtx_addr = (desc_addr + offsetof(struct desc, nix_hdr)) >> 4;\n-\tinst.doneint = 0;\n-\tinst.nixtxl = 1;\n-\tinst.res_addr = desc_addr + offsetof(struct desc, cpt_res);\n-\tinst.u64[2] = 0;\n-\tinst.u64[3] = 0;\n-\tinst.wqe_ptr = desc_addr >> 3;\t/* FIXME: Handle errors */\n-\tinst.qord = 1;\n-\tinst.opcode = OTX2_CPT_OP_INLINE_IPSEC_OUTB;\n-\tinst.dlen = dlen;\n-\tinst.dptr = data_addr + RTE_ETHER_HDR_LEN;\n-\tinst.u64[7] = sess->inst_w7;\n-\n-\t/* First word contains 8 bit completion code & 8 bit uc comp code */\n-\tsd->cpt_res.u16[0] = 0;\n-\n-\t/* Prepare NIX send descriptors for output expected from CPT */\n-\n-\tsd->nix_hdr.w0.u = 0;\n-\tsd->nix_hdr.w1.u = 0;\n-\tsd->nix_hdr.w0.sq = txq->sq;\n-\tsd->nix_hdr.w0.sizem1 = 1;\n-\tsd->nix_hdr.w0.total = rte_pktmbuf_data_len(m);\n-\tsd->nix_hdr.w0.aura = npa_lf_aura_handle_to_aura(m->pool->pool_id);\n-\tif (offload_flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)\n-\t\tsd->nix_hdr.w0.df = otx2_nix_prefree_seg(m);\n-\n-\tsd->nix_sg.u = 0;\n-\tsd->nix_sg.subdc = NIX_SUBDC_SG;\n-\tsd->nix_sg.ld_type = NIX_SENDLDTYPE_LDD;\n-\tsd->nix_sg.segs = 1;\n-\tsd->nix_sg.seg1_size = rte_pktmbuf_data_len(m);\n-\n-\tsd->nix_iova.addr = rte_mbuf_data_iova(m);\n-\n-\t/* Mark mempool object as \"put\" since it is freed by NIX */\n-\tRTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);\n-\n-\tif (!ev->sched_type)\n-\t\totx2_ssogws_head_wait(base + SSOW_LF_GWS_TAG);\n-\n-\tinst.param1 = sess->esn_hi >> 16;\n-\tinst.param2 = sess->esn_hi & 0xffff;\n-\n-\thdr->seq = rte_cpu_to_be_32(sess->seq);\n-\thdr->ip_id = rte_cpu_to_be_32(sess->ip_id);\n-\n-\tsess->ip_id++;\n-\tsess->esn++;\n-\n-\trte_io_wmb();\n-\n-\tdo {\n-\t\totx2_lmt_mov(sess->cpt_lmtline, &inst, 2);\n-\t\tlmt_status = otx2_lmt_submit(sess->cpt_nq_reg);\n-\t} while (lmt_status == 0);\n-\n-\treturn 1;\n-\n-drop:\n-\tif (offload_flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n-\t\t/* Don't free if reference count > 1 */\n-\t\tif (rte_pktmbuf_prefree_seg(m) == NULL)\n-\t\t\treturn 0;\n-\t}\n-\trte_pktmbuf_free(m);\n-\treturn 0;\n-}\n-\n-#endif /* __OTX2_ETHDEV_SEC_TX_H__ */\ndiff --git a/drivers/net/octeontx2/otx2_flow.c b/drivers/net/octeontx2/otx2_flow.c\ndeleted file mode 100644\nindex 1d0fe4e950..0000000000\n--- a/drivers/net/octeontx2/otx2_flow.c\n+++ /dev/null\n@@ -1,1189 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_ethdev.h\"\n-#include \"otx2_ethdev_sec.h\"\n-#include \"otx2_flow.h\"\n-\n-enum flow_vtag_cfg_dir { VTAG_TX, VTAG_RX };\n-\n-int\n-otx2_flow_free_all_resources(struct otx2_eth_dev *hw)\n-{\n-\tstruct otx2_npc_flow_info *npc = &hw->npc_flow;\n-\tstruct otx2_mbox *mbox = hw->mbox;\n-\tstruct otx2_mcam_ents_info *info;\n-\tstruct rte_bitmap *bmap;\n-\tstruct rte_flow *flow;\n-\tint entry_count = 0;\n-\tint rc, idx;\n-\n-\tfor (idx = 0; idx < npc->flow_max_priority; idx++) {\n-\t\tinfo = &npc->flow_entry_info[idx];\n-\t\tentry_count += info->live_ent;\n-\t}\n-\n-\tif (entry_count == 0)\n-\t\treturn 0;\n-\n-\t/* Free all MCAM entries allocated */\n-\trc = otx2_flow_mcam_free_all_entries(mbox);\n-\n-\t/* Free any MCAM counters and delete flow list */\n-\tfor (idx = 0; idx < npc->flow_max_priority; idx++) {\n-\t\twhile ((flow = TAILQ_FIRST(&npc->flow_list[idx])) != NULL) {\n-\t\t\tif (flow->ctr_id != NPC_COUNTER_NONE)\n-\t\t\t\trc |= otx2_flow_mcam_free_counter(mbox,\n-\t\t\t\t\t\t\t flow->ctr_id);\n-\n-\t\t\tTAILQ_REMOVE(&npc->flow_list[idx], flow, next);\n-\t\t\trte_free(flow);\n-\t\t\tbmap = npc->live_entries[flow->priority];\n-\t\t\trte_bitmap_clear(bmap, flow->mcam_id);\n-\t\t}\n-\t\tinfo = &npc->flow_entry_info[idx];\n-\t\tinfo->free_ent = 0;\n-\t\tinfo->live_ent = 0;\n-\t}\n-\treturn rc;\n-}\n-\n-\n-static int\n-flow_program_npc(struct otx2_parse_state *pst, struct otx2_mbox *mbox,\n-\t\t struct otx2_npc_flow_info *flow_info)\n-{\n-\t/* This is non-LDATA part in search key */\n-\tuint64_t key_data[2] = {0ULL, 0ULL};\n-\tuint64_t key_mask[2] = {0ULL, 0ULL};\n-\tint intf = pst->flow->nix_intf;\n-\tint key_len, bit = 0, index;\n-\tint off, idx, data_off = 0;\n-\tuint8_t lid, mask, data;\n-\tuint16_t layer_info;\n-\tuint64_t lt, flags;\n-\n-\n-\t/* Skip till Layer A data start */\n-\twhile (bit < NPC_PARSE_KEX_S_LA_OFFSET) {\n-\t\tif (flow_info->keyx_supp_nmask[intf] & (1 << bit))\n-\t\t\tdata_off++;\n-\t\tbit++;\n-\t}\n-\n-\t/* Each bit represents 1 nibble */\n-\tdata_off *= 4;\n-\n-\tindex = 0;\n-\tfor (lid = 0; lid < NPC_MAX_LID; lid++) {\n-\t\t/* Offset in key */\n-\t\toff = NPC_PARSE_KEX_S_LID_OFFSET(lid);\n-\t\tlt = pst->lt[lid] & 0xf;\n-\t\tflags = pst->flags[lid] & 0xff;\n-\n-\t\t/* NPC_LAYER_KEX_S */\n-\t\tlayer_info = ((flow_info->keyx_supp_nmask[intf] >> off) & 0x7);\n-\n-\t\tif (layer_info) {\n-\t\t\tfor (idx = 0; idx <= 2 ; idx++) {\n-\t\t\t\tif (layer_info & (1 << idx)) {\n-\t\t\t\t\tif (idx == 2)\n-\t\t\t\t\t\tdata = lt;\n-\t\t\t\t\telse if (idx == 1)\n-\t\t\t\t\t\tdata = ((flags >> 4) & 0xf);\n-\t\t\t\t\telse\n-\t\t\t\t\t\tdata = (flags & 0xf);\n-\n-\t\t\t\t\tif (data_off >= 64) {\n-\t\t\t\t\t\tdata_off = 0;\n-\t\t\t\t\t\tindex++;\n-\t\t\t\t\t}\n-\t\t\t\t\tkey_data[index] |= ((uint64_t)data <<\n-\t\t\t\t\t\t\t data_off);\n-\t\t\t\t\tmask = 0xf;\n-\t\t\t\t\tif (lt == 0)\n-\t\t\t\t\t\tmask = 0;\n-\t\t\t\t\tkey_mask[index] |= ((uint64_t)mask <<\n-\t\t\t\t\t\t\t data_off);\n-\t\t\t\t\tdata_off += 4;\n-\t\t\t\t}\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\totx2_npc_dbg(\"Npc prog key data0: 0x%\" PRIx64 \", data1: 0x%\" PRIx64,\n-\t\t key_data[0], key_data[1]);\n-\n-\t/* Copy this into mcam string */\n-\tkey_len = (pst->npc->keyx_len[intf] + 7) / 8;\n-\totx2_npc_dbg(\"Key_len = %d\", key_len);\n-\tmemcpy(pst->flow->mcam_data, key_data, key_len);\n-\tmemcpy(pst->flow->mcam_mask, key_mask, key_len);\n-\n-\totx2_npc_dbg(\"Final flow data\");\n-\tfor (idx = 0; idx < OTX2_MAX_MCAM_WIDTH_DWORDS; idx++) {\n-\t\totx2_npc_dbg(\"data[%d]: 0x%\" PRIx64 \", mask[%d]: 0x%\" PRIx64,\n-\t\t\t idx, pst->flow->mcam_data[idx],\n-\t\t\t idx, pst->flow->mcam_mask[idx]);\n-\t}\n-\n-\t/*\n-\t * Now we have mcam data and mask formatted as\n-\t * [Key_len/4 nibbles][0 or 1 nibble hole][data]\n-\t * hole is present if key_len is odd number of nibbles.\n-\t * mcam data must be split into 64 bits + 48 bits segments\n-\t * for each back W0, W1.\n-\t */\n-\n-\treturn otx2_flow_mcam_alloc_and_write(pst->flow, mbox, pst, flow_info);\n-}\n-\n-static int\n-flow_parse_attr(struct rte_eth_dev *eth_dev,\n-\t\tconst struct rte_flow_attr *attr,\n-\t\tstruct rte_flow_error *error,\n-\t\tstruct rte_flow *flow)\n-{\n-\tstruct otx2_eth_dev *dev = eth_dev->data->dev_private;\n-\tconst char *errmsg = NULL;\n-\n-\tif (attr == NULL)\n-\t\terrmsg = \"Attribute can't be empty\";\n-\telse if (attr->group)\n-\t\terrmsg = \"Groups are not supported\";\n-\telse if (attr->priority >= dev->npc_flow.flow_max_priority)\n-\t\terrmsg = \"Priority should be with in specified range\";\n-\telse if ((!attr->egress && !attr->ingress) ||\n-\t\t (attr->egress && attr->ingress))\n-\t\terrmsg = \"Exactly one of ingress or egress must be set\";\n-\n-\tif (errmsg != NULL) {\n-\t\trte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ATTR,\n-\t\t\t\t attr, errmsg);\n-\t\treturn -ENOTSUP;\n-\t}\n-\n-\tif (attr->ingress)\n-\t\tflow->nix_intf = OTX2_INTF_RX;\n-\telse\n-\t\tflow->nix_intf = OTX2_INTF_TX;\n-\n-\tflow->priority = attr->priority;\n-\treturn 0;\n-}\n-\n-static inline int\n-flow_get_free_rss_grp(struct rte_bitmap *bmap,\n-\t\t uint32_t size, uint32_t *pos)\n-{\n-\tfor (*pos = 0; *pos < size; ++*pos) {\n-\t\tif (!rte_bitmap_get(bmap, *pos))\n-\t\t\tbreak;\n-\t}\n-\n-\treturn *pos < size ? 0 : -1;\n-}\n-\n-static int\n-flow_configure_rss_action(struct otx2_eth_dev *dev,\n-\t\t\t const struct rte_flow_action_rss *rss,\n-\t\t\t uint8_t *alg_idx, uint32_t *rss_grp,\n-\t\t\t int mcam_index)\n-{\n-\tstruct otx2_npc_flow_info *flow_info = &dev->npc_flow;\n-\tuint16_t reta[NIX_RSS_RETA_SIZE_MAX];\n-\tuint32_t flowkey_cfg, grp_aval, i;\n-\tuint16_t *ind_tbl = NULL;\n-\tuint8_t flowkey_algx;\n-\tint rc;\n-\n-\trc = flow_get_free_rss_grp(flow_info->rss_grp_entries,\n-\t\t\t\t flow_info->rss_grps, &grp_aval);\n-\t/* RSS group :0 is not usable for flow rss action */\n-\tif (rc < 0 || grp_aval == 0)\n-\t\treturn -ENOSPC;\n-\n-\t*rss_grp = grp_aval;\n-\n-\totx2_nix_rss_set_key(dev, (uint8_t *)(uintptr_t)rss->key,\n-\t\t\t rss->key_len);\n-\n-\t/* If queue count passed in the rss action is less than\n-\t * HW configured reta size, replicate rss action reta\n-\t * across HW reta table.\n-\t */\n-\tif (dev->rss_info.rss_size > rss->queue_num) {\n-\t\tind_tbl = reta;\n-\n-\t\tfor (i = 0; i < (dev->rss_info.rss_size / rss->queue_num); i++)\n-\t\t\tmemcpy(reta + i * rss->queue_num, rss->queue,\n-\t\t\t sizeof(uint16_t) * rss->queue_num);\n-\n-\t\ti = dev->rss_info.rss_size % rss->queue_num;\n-\t\tif (i)\n-\t\t\tmemcpy(&reta[dev->rss_info.rss_size] - i,\n-\t\t\t rss->queue, i * sizeof(uint16_t));\n-\t} else {\n-\t\tind_tbl = (uint16_t *)(uintptr_t)rss->queue;\n-\t}\n-\n-\trc = otx2_nix_rss_tbl_init(dev, *rss_grp, ind_tbl);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to init rss table rc = %d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\tflowkey_cfg = otx2_rss_ethdev_to_nix(dev, rss->types, rss->level);\n-\n-\trc = otx2_rss_set_hf(dev, flowkey_cfg, &flowkey_algx,\n-\t\t\t *rss_grp, mcam_index);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to set rss hash function rc = %d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\t*alg_idx = flowkey_algx;\n-\n-\trte_bitmap_set(flow_info->rss_grp_entries, *rss_grp);\n-\n-\treturn 0;\n-}\n-\n-\n-static int\n-flow_program_rss_action(struct rte_eth_dev *eth_dev,\n-\t\t\tconst struct rte_flow_action actions[],\n-\t\t\tstruct rte_flow *flow)\n-{\n-\tstruct otx2_eth_dev *dev = eth_dev->data->dev_private;\n-\tconst struct rte_flow_action_rss *rss;\n-\tuint32_t rss_grp;\n-\tuint8_t alg_idx;\n-\tint rc;\n-\n-\tfor (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {\n-\t\tif (actions->type == RTE_FLOW_ACTION_TYPE_RSS) {\n-\t\t\trss = (const struct rte_flow_action_rss *)actions->conf;\n-\n-\t\t\trc = flow_configure_rss_action(dev,\n-\t\t\t\t\t\t rss, &alg_idx, &rss_grp,\n-\t\t\t\t\t\t flow->mcam_id);\n-\t\t\tif (rc)\n-\t\t\t\treturn rc;\n-\n-\t\t\tflow->npc_action &= (~(0xfULL));\n-\t\t\tflow->npc_action |= NIX_RX_ACTIONOP_RSS;\n-\t\t\tflow->npc_action |=\n-\t\t\t\t((uint64_t)(alg_idx & NIX_RSS_ACT_ALG_MASK) <<\n-\t\t\t\t NIX_RSS_ACT_ALG_OFFSET) |\n-\t\t\t\t((uint64_t)(rss_grp & NIX_RSS_ACT_GRP_MASK) <<\n-\t\t\t\t NIX_RSS_ACT_GRP_OFFSET);\n-\t\t}\n-\t}\n-\treturn 0;\n-}\n-\n-static int\n-flow_free_rss_action(struct rte_eth_dev *eth_dev,\n-\t\t struct rte_flow *flow)\n-{\n-\tstruct otx2_eth_dev *dev = eth_dev->data->dev_private;\n-\tstruct otx2_npc_flow_info *npc = &dev->npc_flow;\n-\tuint32_t rss_grp;\n-\n-\tif (flow->npc_action & NIX_RX_ACTIONOP_RSS) {\n-\t\trss_grp = (flow->npc_action >> NIX_RSS_ACT_GRP_OFFSET) &\n-\t\t\tNIX_RSS_ACT_GRP_MASK;\n-\t\tif (rss_grp == 0 || rss_grp >= npc->rss_grps)\n-\t\t\treturn -EINVAL;\n-\n-\t\trte_bitmap_clear(npc->rss_grp_entries, rss_grp);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-flow_update_sec_tt(struct rte_eth_dev *eth_dev,\n-\t\t const struct rte_flow_action actions[])\n-{\n-\tint rc = 0;\n-\n-\tfor (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {\n-\t\tif (actions->type == RTE_FLOW_ACTION_TYPE_SECURITY) {\n-\t\t\trc = otx2_eth_sec_update_tag_type(eth_dev);\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static int\n-flow_parse_meta_items(__rte_unused struct otx2_parse_state *pst)\n-{\n-\totx2_npc_dbg(\"Meta Item\");\n-\treturn 0;\n-}\n-\n-/*\n- * Parse function of each layer:\n- * - Consume one or more patterns that are relevant.\n- * - Update parse_state\n- * - Set parse_state.pattern = last item consumed\n- * - Set appropriate error code/message when returning error.\n- */\n-typedef int (*flow_parse_stage_func_t)(struct otx2_parse_state *pst);\n-\n-static int\n-flow_parse_pattern(struct rte_eth_dev *dev,\n-\t\t const struct rte_flow_item pattern[],\n-\t\t struct rte_flow_error *error,\n-\t\t struct rte_flow *flow,\n-\t\t struct otx2_parse_state *pst)\n-{\n-\tflow_parse_stage_func_t parse_stage_funcs[] = {\n-\t\tflow_parse_meta_items,\n-\t\totx2_flow_parse_higig2_hdr,\n-\t\totx2_flow_parse_la,\n-\t\totx2_flow_parse_lb,\n-\t\totx2_flow_parse_lc,\n-\t\totx2_flow_parse_ld,\n-\t\totx2_flow_parse_le,\n-\t\totx2_flow_parse_lf,\n-\t\totx2_flow_parse_lg,\n-\t\totx2_flow_parse_lh,\n-\t};\n-\tstruct otx2_eth_dev *hw = dev->data->dev_private;\n-\tuint8_t layer = 0;\n-\tint key_offset;\n-\tint rc;\n-\n-\tif (pattern == NULL) {\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM_NUM, NULL,\n-\t\t\t\t \"pattern is NULL\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tmemset(pst, 0, sizeof(*pst));\n-\tpst->npc = &hw->npc_flow;\n-\tpst->error = error;\n-\tpst->flow = flow;\n-\n-\t/* Use integral byte offset */\n-\tkey_offset = pst->npc->keyx_len[flow->nix_intf];\n-\tkey_offset = (key_offset + 7) / 8;\n-\n-\t/* Location where LDATA would begin */\n-\tpst->mcam_data = (uint8_t *)flow->mcam_data;\n-\tpst->mcam_mask = (uint8_t *)flow->mcam_mask;\n-\n-\twhile (pattern->type != RTE_FLOW_ITEM_TYPE_END &&\n-\t layer < RTE_DIM(parse_stage_funcs)) {\n-\t\totx2_npc_dbg(\"Pattern type = %d\", pattern->type);\n-\n-\t\t/* Skip place-holders */\n-\t\tpattern = otx2_flow_skip_void_and_any_items(pattern);\n-\n-\t\tpst->pattern = pattern;\n-\t\totx2_npc_dbg(\"Is tunnel = %d, layer = %d\", pst->tunnel, layer);\n-\t\trc = parse_stage_funcs[layer](pst);\n-\t\tif (rc != 0)\n-\t\t\treturn -rte_errno;\n-\n-\t\tlayer++;\n-\n-\t\t/*\n-\t\t * Parse stage function sets pst->pattern to\n-\t\t * 1 past the last item it consumed.\n-\t\t */\n-\t\tpattern = pst->pattern;\n-\n-\t\tif (pst->terminate)\n-\t\t\tbreak;\n-\t}\n-\n-\t/* Skip trailing place-holders */\n-\tpattern = otx2_flow_skip_void_and_any_items(pattern);\n-\n-\t/* Are there more items than what we can handle? */\n-\tif (pattern->type != RTE_FLOW_ITEM_TYPE_END) {\n-\t\trte_flow_error_set(error, ENOTSUP,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, pattern,\n-\t\t\t\t \"unsupported item in the sequence\");\n-\t\treturn -ENOTSUP;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-flow_parse_rule(struct rte_eth_dev *dev,\n-\t\tconst struct rte_flow_attr *attr,\n-\t\tconst struct rte_flow_item pattern[],\n-\t\tconst struct rte_flow_action actions[],\n-\t\tstruct rte_flow_error *error,\n-\t\tstruct rte_flow *flow,\n-\t\tstruct otx2_parse_state *pst)\n-{\n-\tint err;\n-\n-\t/* Check attributes */\n-\terr = flow_parse_attr(dev, attr, error, flow);\n-\tif (err)\n-\t\treturn err;\n-\n-\t/* Check actions */\n-\terr = otx2_flow_parse_actions(dev, attr, actions, error, flow);\n-\tif (err)\n-\t\treturn err;\n-\n-\t/* Check pattern */\n-\terr = flow_parse_pattern(dev, pattern, error, flow, pst);\n-\tif (err)\n-\t\treturn err;\n-\n-\t/* Check for overlaps? */\n-\treturn 0;\n-}\n-\n-static int\n-otx2_flow_validate(struct rte_eth_dev *dev,\n-\t\t const struct rte_flow_attr *attr,\n-\t\t const struct rte_flow_item pattern[],\n-\t\t const struct rte_flow_action actions[],\n-\t\t struct rte_flow_error *error)\n-{\n-\tstruct otx2_parse_state parse_state;\n-\tstruct rte_flow flow;\n-\n-\tmemset(&flow, 0, sizeof(flow));\n-\treturn flow_parse_rule(dev, attr, pattern, actions, error, &flow,\n-\t\t\t &parse_state);\n-}\n-\n-static int\n-flow_program_vtag_action(struct rte_eth_dev *eth_dev,\n-\t\t\t const struct rte_flow_action actions[],\n-\t\t\t struct rte_flow *flow)\n-{\n-\tuint16_t vlan_id = 0, vlan_ethtype = RTE_ETHER_TYPE_VLAN;\n-\tstruct otx2_eth_dev *dev = eth_dev->data->dev_private;\n-\tunion {\n-\t\tuint64_t reg;\n-\t\tstruct nix_tx_vtag_action_s act;\n-\t} tx_vtag_action;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_vtag_config *vtag_cfg;\n-\tstruct nix_vtag_config_rsp *rsp;\n-\tbool vlan_insert_action = false;\n-\tuint64_t rx_vtag_action = 0;\n-\tuint8_t vlan_pcp = 0;\n-\tint rc;\n-\n-\tfor (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {\n-\t\tif (actions->type == RTE_FLOW_ACTION_TYPE_OF_POP_VLAN) {\n-\t\t\tif (dev->npc_flow.vtag_actions == 1) {\n-\t\t\t\tvtag_cfg =\n-\t\t\t\t\totx2_mbox_alloc_msg_nix_vtag_cfg(mbox);\n-\t\t\t\tvtag_cfg->cfg_type = VTAG_RX;\n-\t\t\t\tvtag_cfg->rx.strip_vtag = 1;\n-\t\t\t\t/* Always capture */\n-\t\t\t\tvtag_cfg->rx.capture_vtag = 1;\n-\t\t\t\tvtag_cfg->vtag_size = NIX_VTAGSIZE_T4;\n-\t\t\t\tvtag_cfg->rx.vtag_type = 0;\n-\n-\t\t\t\trc = otx2_mbox_process(mbox);\n-\t\t\t\tif (rc)\n-\t\t\t\t\treturn rc;\n-\t\t\t}\n-\n-\t\t\trx_vtag_action |= (NIX_RX_VTAGACTION_VTAG_VALID << 15);\n-\t\t\trx_vtag_action |= (NPC_LID_LB << 8);\n-\t\t\trx_vtag_action |= NIX_RX_VTAGACTION_VTAG0_RELPTR;\n-\t\t\tflow->vtag_action = rx_vtag_action;\n-\t\t} else if (actions->type ==\n-\t\t\t RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {\n-\t\t\tconst struct rte_flow_action_of_set_vlan_vid *vtag =\n-\t\t\t\t(const struct rte_flow_action_of_set_vlan_vid *)\n-\t\t\t\t\tactions->conf;\n-\t\t\tvlan_id = rte_be_to_cpu_16(vtag->vlan_vid);\n-\t\t\tif (vlan_id > 0xfff) {\n-\t\t\t\totx2_err(\"Invalid vlan_id for set vlan action\");\n-\t\t\t\treturn -EINVAL;\n-\t\t\t}\n-\t\t\tvlan_insert_action = true;\n-\t\t} else if (actions->type == RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) {\n-\t\t\tconst struct rte_flow_action_of_push_vlan *ethtype =\n-\t\t\t\t(const struct rte_flow_action_of_push_vlan *)\n-\t\t\t\t\tactions->conf;\n-\t\t\tvlan_ethtype = rte_be_to_cpu_16(ethtype->ethertype);\n-\t\t\tif (vlan_ethtype != RTE_ETHER_TYPE_VLAN &&\n-\t\t\t vlan_ethtype != RTE_ETHER_TYPE_QINQ) {\n-\t\t\t\totx2_err(\"Invalid ethtype specified for push\"\n-\t\t\t\t\t \" vlan action\");\n-\t\t\t\treturn -EINVAL;\n-\t\t\t}\n-\t\t\tvlan_insert_action = true;\n-\t\t} else if (actions->type ==\n-\t\t\t RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {\n-\t\t\tconst struct rte_flow_action_of_set_vlan_pcp *pcp =\n-\t\t\t\t(const struct rte_flow_action_of_set_vlan_pcp *)\n-\t\t\t\t\tactions->conf;\n-\t\t\tvlan_pcp = pcp->vlan_pcp;\n-\t\t\tif (vlan_pcp > 0x7) {\n-\t\t\t\totx2_err(\"Invalid PCP value for pcp action\");\n-\t\t\t\treturn -EINVAL;\n-\t\t\t}\n-\t\t\tvlan_insert_action = true;\n-\t\t}\n-\t}\n-\n-\tif (vlan_insert_action) {\n-\t\tvtag_cfg = otx2_mbox_alloc_msg_nix_vtag_cfg(mbox);\n-\t\tvtag_cfg->cfg_type = VTAG_TX;\n-\t\tvtag_cfg->vtag_size = NIX_VTAGSIZE_T4;\n-\t\tvtag_cfg->tx.vtag0 =\n-\t\t\t((vlan_ethtype << 16) | (vlan_pcp << 13) | vlan_id);\n-\t\tvtag_cfg->tx.cfg_vtag0 = 1;\n-\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\n-\t\ttx_vtag_action.reg = 0;\n-\t\ttx_vtag_action.act.vtag0_def = rsp->vtag0_idx;\n-\t\tif (tx_vtag_action.act.vtag0_def < 0) {\n-\t\t\totx2_err(\"Failed to config TX VTAG action\");\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\ttx_vtag_action.act.vtag0_lid = NPC_LID_LA;\n-\t\ttx_vtag_action.act.vtag0_op = NIX_TX_VTAGOP_INSERT;\n-\t\ttx_vtag_action.act.vtag0_relptr =\n-\t\t\tNIX_TX_VTAGACTION_VTAG0_RELPTR;\n-\t\tflow->vtag_action = tx_vtag_action.reg;\n-\t}\n-\treturn 0;\n-}\n-\n-static struct rte_flow *\n-otx2_flow_create(struct rte_eth_dev *dev,\n-\t\t const struct rte_flow_attr *attr,\n-\t\t const struct rte_flow_item pattern[],\n-\t\t const struct rte_flow_action actions[],\n-\t\t struct rte_flow_error *error)\n-{\n-\tstruct otx2_eth_dev *hw = dev->data->dev_private;\n-\tstruct otx2_parse_state parse_state;\n-\tstruct otx2_mbox *mbox = hw->mbox;\n-\tstruct rte_flow *flow, *flow_iter;\n-\tstruct otx2_flow_list *list;\n-\tint rc;\n-\n-\tflow = rte_zmalloc(\"otx2_rte_flow\", sizeof(*flow), 0);\n-\tif (flow == NULL) {\n-\t\trte_flow_error_set(error, ENOMEM,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t NULL,\n-\t\t\t\t \"Memory allocation failed\");\n-\t\treturn NULL;\n-\t}\n-\tmemset(flow, 0, sizeof(*flow));\n-\n-\trc = flow_parse_rule(dev, attr, pattern, actions, error, flow,\n-\t\t\t &parse_state);\n-\tif (rc != 0)\n-\t\tgoto err_exit;\n-\n-\trc = flow_program_vtag_action(dev, actions, flow);\n-\tif (rc != 0) {\n-\t\trte_flow_error_set(error, EIO,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t NULL,\n-\t\t\t\t \"Failed to program vlan action\");\n-\t\tgoto err_exit;\n-\t}\n-\n-\tparse_state.is_vf = otx2_dev_is_vf(hw);\n-\n-\trc = flow_program_npc(&parse_state, mbox, &hw->npc_flow);\n-\tif (rc != 0) {\n-\t\trte_flow_error_set(error, EIO,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t NULL,\n-\t\t\t\t \"Failed to insert filter\");\n-\t\tgoto err_exit;\n-\t}\n-\n-\trc = flow_program_rss_action(dev, actions, flow);\n-\tif (rc != 0) {\n-\t\trte_flow_error_set(error, EIO,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t NULL,\n-\t\t\t\t \"Failed to program rss action\");\n-\t\tgoto err_exit;\n-\t}\n-\n-\tif (hw->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {\n-\t\trc = flow_update_sec_tt(dev, actions);\n-\t\tif (rc != 0) {\n-\t\t\trte_flow_error_set(error, EIO,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t\t NULL,\n-\t\t\t\t\t \"Failed to update tt with sec act\");\n-\t\t\tgoto err_exit;\n-\t\t}\n-\t}\n-\n-\tlist = &hw->npc_flow.flow_list[flow->priority];\n-\t/* List in ascending order of mcam entries */\n-\tTAILQ_FOREACH(flow_iter, list, next) {\n-\t\tif (flow_iter->mcam_id > flow->mcam_id) {\n-\t\t\tTAILQ_INSERT_BEFORE(flow_iter, flow, next);\n-\t\t\treturn flow;\n-\t\t}\n-\t}\n-\n-\tTAILQ_INSERT_TAIL(list, flow, next);\n-\treturn flow;\n-\n-err_exit:\n-\trte_free(flow);\n-\treturn NULL;\n-}\n-\n-static int\n-otx2_flow_destroy(struct rte_eth_dev *dev,\n-\t\t struct rte_flow *flow,\n-\t\t struct rte_flow_error *error)\n-{\n-\tstruct otx2_eth_dev *hw = dev->data->dev_private;\n-\tstruct otx2_npc_flow_info *npc = &hw->npc_flow;\n-\tstruct otx2_mbox *mbox = hw->mbox;\n-\tstruct rte_bitmap *bmap;\n-\tuint16_t match_id;\n-\tint rc;\n-\n-\tmatch_id = (flow->npc_action >> NIX_RX_ACT_MATCH_OFFSET) &\n-\t\tNIX_RX_ACT_MATCH_MASK;\n-\n-\tif (match_id && match_id < OTX2_FLOW_ACTION_FLAG_DEFAULT) {\n-\t\tif (rte_atomic32_read(&npc->mark_actions) == 0)\n-\t\t\treturn -EINVAL;\n-\n-\t\t/* Clear mark offload flag if there are no more mark actions */\n-\t\tif (rte_atomic32_sub_return(&npc->mark_actions, 1) == 0) {\n-\t\t\thw->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;\n-\t\t\totx2_eth_set_rx_function(dev);\n-\t\t}\n-\t}\n-\n-\tif (flow->nix_intf == OTX2_INTF_RX && flow->vtag_action) {\n-\t\tnpc->vtag_actions--;\n-\t\tif (npc->vtag_actions == 0) {\n-\t\t\tif (hw->vlan_info.strip_on == 0) {\n-\t\t\t\thw->rx_offload_flags &=\n-\t\t\t\t\t~NIX_RX_OFFLOAD_VLAN_STRIP_F;\n-\t\t\t\totx2_eth_set_rx_function(dev);\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\trc = flow_free_rss_action(dev, flow);\n-\tif (rc != 0) {\n-\t\trte_flow_error_set(error, EIO,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t NULL,\n-\t\t\t\t \"Failed to free rss action\");\n-\t}\n-\n-\trc = otx2_flow_mcam_free_entry(mbox, flow->mcam_id);\n-\tif (rc != 0) {\n-\t\trte_flow_error_set(error, EIO,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t NULL,\n-\t\t\t\t \"Failed to destroy filter\");\n-\t}\n-\n-\tTAILQ_REMOVE(&npc->flow_list[flow->priority], flow, next);\n-\n-\tbmap = npc->live_entries[flow->priority];\n-\trte_bitmap_clear(bmap, flow->mcam_id);\n-\n-\trte_free(flow);\n-\treturn 0;\n-}\n-\n-static int\n-otx2_flow_flush(struct rte_eth_dev *dev,\n-\t\tstruct rte_flow_error *error)\n-{\n-\tstruct otx2_eth_dev *hw = dev->data->dev_private;\n-\tint rc;\n-\n-\trc = otx2_flow_free_all_resources(hw);\n-\tif (rc) {\n-\t\totx2_err(\"Error when deleting NPC MCAM entries \"\n-\t\t\t\t\", counters\");\n-\t\trte_flow_error_set(error, EIO,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t NULL,\n-\t\t\t\t \"Failed to flush filter\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_flow_isolate(struct rte_eth_dev *dev __rte_unused,\n-\t\t int enable __rte_unused,\n-\t\t struct rte_flow_error *error)\n-{\n-\t/*\n-\t * If we support, we need to un-install the default mcam\n-\t * entry for this port.\n-\t */\n-\n-\trte_flow_error_set(error, ENOTSUP,\n-\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t NULL,\n-\t\t\t \"Flow isolation not supported\");\n-\n-\treturn -rte_errno;\n-}\n-\n-static int\n-otx2_flow_query(struct rte_eth_dev *dev,\n-\t\tstruct rte_flow *flow,\n-\t\tconst struct rte_flow_action *action,\n-\t\tvoid *data,\n-\t\tstruct rte_flow_error *error)\n-{\n-\tstruct otx2_eth_dev *hw = dev->data->dev_private;\n-\tstruct rte_flow_query_count *query = data;\n-\tstruct otx2_mbox *mbox = hw->mbox;\n-\tconst char *errmsg = NULL;\n-\tint errcode = ENOTSUP;\n-\tint rc;\n-\n-\tif (action->type != RTE_FLOW_ACTION_TYPE_COUNT) {\n-\t\terrmsg = \"Only COUNT is supported in query\";\n-\t\tgoto err_exit;\n-\t}\n-\n-\tif (flow->ctr_id == NPC_COUNTER_NONE) {\n-\t\terrmsg = \"Counter is not available\";\n-\t\tgoto err_exit;\n-\t}\n-\n-\trc = otx2_flow_mcam_read_counter(mbox, flow->ctr_id, &query->hits);\n-\tif (rc != 0) {\n-\t\terrcode = EIO;\n-\t\terrmsg = \"Error reading flow counter\";\n-\t\tgoto err_exit;\n-\t}\n-\tquery->hits_set = 1;\n-\tquery->bytes_set = 0;\n-\n-\tif (query->reset)\n-\t\trc = otx2_flow_mcam_clear_counter(mbox, flow->ctr_id);\n-\tif (rc != 0) {\n-\t\terrcode = EIO;\n-\t\terrmsg = \"Error clearing flow counter\";\n-\t\tgoto err_exit;\n-\t}\n-\n-\treturn 0;\n-\n-err_exit:\n-\trte_flow_error_set(error, errcode,\n-\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t NULL,\n-\t\t\t errmsg);\n-\treturn -rte_errno;\n-}\n-\n-static int\n-otx2_flow_dev_dump(struct rte_eth_dev *dev,\n-\t\t struct rte_flow *flow, FILE *file,\n-\t\t struct rte_flow_error *error)\n-{\n-\tstruct otx2_eth_dev *hw = dev->data->dev_private;\n-\tstruct otx2_flow_list *list;\n-\tstruct rte_flow *flow_iter;\n-\tuint32_t max_prio, i;\n-\n-\tif (file == NULL) {\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n-\t\t\t\t NULL,\n-\t\t\t\t \"Invalid file\");\n-\t\treturn -EINVAL;\n-\t}\n-\tif (flow != NULL) {\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_HANDLE,\n-\t\t\t\t NULL,\n-\t\t\t\t \"Invalid argument\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tmax_prio = hw->npc_flow.flow_max_priority;\n-\n-\tfor (i = 0; i < max_prio; i++) {\n-\t\tlist = &hw->npc_flow.flow_list[i];\n-\n-\t\t/* List in ascending order of mcam entries */\n-\t\tTAILQ_FOREACH(flow_iter, list, next) {\n-\t\t\totx2_flow_dump(file, hw, flow_iter);\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-const struct rte_flow_ops otx2_flow_ops = {\n-\t.validate = otx2_flow_validate,\n-\t.create = otx2_flow_create,\n-\t.destroy = otx2_flow_destroy,\n-\t.flush = otx2_flow_flush,\n-\t.query = otx2_flow_query,\n-\t.isolate = otx2_flow_isolate,\n-\t.dev_dump = otx2_flow_dev_dump,\n-};\n-\n-static int\n-flow_supp_key_len(uint32_t supp_mask)\n-{\n-\tint nib_count = 0;\n-\twhile (supp_mask) {\n-\t\tnib_count++;\n-\t\tsupp_mask &= (supp_mask - 1);\n-\t}\n-\treturn nib_count * 4;\n-}\n-\n-/* Refer HRM register:\n- * NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG\n- * and\n- * NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG\n- **/\n-#define BYTESM1_SHIFT\t16\n-#define HDR_OFF_SHIFT\t8\n-static void\n-flow_update_kex_info(struct npc_xtract_info *xtract_info,\n-\t\t uint64_t val)\n-{\n-\txtract_info->len = ((val >> BYTESM1_SHIFT) & 0xf) + 1;\n-\txtract_info->hdr_off = (val >> HDR_OFF_SHIFT) & 0xff;\n-\txtract_info->key_off = val & 0x3f;\n-\txtract_info->enable = ((val >> 7) & 0x1);\n-\txtract_info->flags_enable = ((val >> 6) & 0x1);\n-}\n-\n-static void\n-flow_process_mkex_cfg(struct otx2_npc_flow_info *npc,\n-\t\t struct npc_get_kex_cfg_rsp *kex_rsp)\n-{\n-\tvolatile uint64_t (*q)[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT]\n-\t\t[NPC_MAX_LD];\n-\tstruct npc_xtract_info *x_info = NULL;\n-\tint lid, lt, ld, fl, ix;\n-\totx2_dxcfg_t *p;\n-\tuint64_t keyw;\n-\tuint64_t val;\n-\n-\tnpc->keyx_supp_nmask[NPC_MCAM_RX] =\n-\t\tkex_rsp->rx_keyx_cfg & 0x7fffffffULL;\n-\tnpc->keyx_supp_nmask[NPC_MCAM_TX] =\n-\t\tkex_rsp->tx_keyx_cfg & 0x7fffffffULL;\n-\tnpc->keyx_len[NPC_MCAM_RX] =\n-\t\tflow_supp_key_len(npc->keyx_supp_nmask[NPC_MCAM_RX]);\n-\tnpc->keyx_len[NPC_MCAM_TX] =\n-\t\tflow_supp_key_len(npc->keyx_supp_nmask[NPC_MCAM_TX]);\n-\n-\tkeyw = (kex_rsp->rx_keyx_cfg >> 32) & 0x7ULL;\n-\tnpc->keyw[NPC_MCAM_RX] = keyw;\n-\tkeyw = (kex_rsp->tx_keyx_cfg >> 32) & 0x7ULL;\n-\tnpc->keyw[NPC_MCAM_TX] = keyw;\n-\n-\t/* Update KEX_LD_FLAG */\n-\tfor (ix = 0; ix < NPC_MAX_INTF; ix++) {\n-\t\tfor (ld = 0; ld < NPC_MAX_LD; ld++) {\n-\t\t\tfor (fl = 0; fl < NPC_MAX_LFL; fl++) {\n-\t\t\t\tx_info =\n-\t\t\t\t &npc->prx_fxcfg[ix][ld][fl].xtract[0];\n-\t\t\t\tval = kex_rsp->intf_ld_flags[ix][ld][fl];\n-\t\t\t\tflow_update_kex_info(x_info, val);\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-\t/* Update LID, LT and LDATA cfg */\n-\tp = &npc->prx_dxcfg;\n-\tq = (volatile uint64_t (*)[][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD])\n-\t\t\t(&kex_rsp->intf_lid_lt_ld);\n-\tfor (ix = 0; ix < NPC_MAX_INTF; ix++) {\n-\t\tfor (lid = 0; lid < NPC_MAX_LID; lid++) {\n-\t\t\tfor (lt = 0; lt < NPC_MAX_LT; lt++) {\n-\t\t\t\tfor (ld = 0; ld < NPC_MAX_LD; ld++) {\n-\t\t\t\t\tx_info = &(*p)[ix][lid][lt].xtract[ld];\n-\t\t\t\t\tval = (*q)[ix][lid][lt][ld];\n-\t\t\t\t\tflow_update_kex_info(x_info, val);\n-\t\t\t\t}\n-\t\t\t}\n-\t\t}\n-\t}\n-\t/* Update LDATA Flags cfg */\n-\tnpc->prx_lfcfg[0].i = kex_rsp->kex_ld_flags[0];\n-\tnpc->prx_lfcfg[1].i = kex_rsp->kex_ld_flags[1];\n-}\n-\n-static struct otx2_idev_kex_cfg *\n-flow_intra_dev_kex_cfg(void)\n-{\n-\tstatic const char name[] = \"octeontx2_intra_device_kex_conf\";\n-\tstruct otx2_idev_kex_cfg *idev;\n-\tconst struct rte_memzone *mz;\n-\n-\tmz = rte_memzone_lookup(name);\n-\tif (mz)\n-\t\treturn mz->addr;\n-\n-\t/* Request for the first time */\n-\tmz = rte_memzone_reserve_aligned(name, sizeof(struct otx2_idev_kex_cfg),\n-\t\t\t\t\t SOCKET_ID_ANY, 0, OTX2_ALIGN);\n-\tif (mz) {\n-\t\tidev = mz->addr;\n-\t\trte_atomic16_set(&idev->kex_refcnt, 0);\n-\t\treturn idev;\n-\t}\n-\treturn NULL;\n-}\n-\n-static int\n-flow_fetch_kex_cfg(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_npc_flow_info *npc = &dev->npc_flow;\n-\tstruct npc_get_kex_cfg_rsp *kex_rsp;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tchar mkex_pfl_name[MKEX_NAME_LEN];\n-\tstruct otx2_idev_kex_cfg *idev;\n-\tint rc = 0;\n-\n-\tidev = flow_intra_dev_kex_cfg();\n-\tif (!idev)\n-\t\treturn -ENOMEM;\n-\n-\t/* Is kex_cfg read by any another driver? */\n-\tif (rte_atomic16_add_return(&idev->kex_refcnt, 1) == 1) {\n-\t\t/* Call mailbox to get key & data size */\n-\t\t(void)otx2_mbox_alloc_msg_npc_get_kex_cfg(mbox);\n-\t\totx2_mbox_msg_send(mbox, 0);\n-\t\trc = otx2_mbox_get_rsp(mbox, 0, (void *)&kex_rsp);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to fetch NPC keyx config\");\n-\t\t\tgoto done;\n-\t\t}\n-\t\tmemcpy(&idev->kex_cfg, kex_rsp,\n-\t\t sizeof(struct npc_get_kex_cfg_rsp));\n-\t}\n-\n-\totx2_mbox_memcpy(mkex_pfl_name,\n-\t\t\t idev->kex_cfg.mkex_pfl_name, MKEX_NAME_LEN);\n-\n-\tstrlcpy((char *)dev->mkex_pfl_name,\n-\t\tmkex_pfl_name, sizeof(dev->mkex_pfl_name));\n-\n-\tflow_process_mkex_cfg(npc, &idev->kex_cfg);\n-\n-done:\n-\treturn rc;\n-}\n-\n-#define OTX2_MCAM_TOT_ENTRIES_96XX (4096)\n-#define OTX2_MCAM_TOT_ENTRIES_98XX (16384)\n-\n-static int otx2_mcam_tot_entries(struct otx2_eth_dev *dev)\n-{\n-\tif (otx2_dev_is_98xx(dev))\n-\t\treturn OTX2_MCAM_TOT_ENTRIES_98XX;\n-\telse\n-\t\treturn OTX2_MCAM_TOT_ENTRIES_96XX;\n-}\n-\n-int\n-otx2_flow_init(struct otx2_eth_dev *hw)\n-{\n-\tuint8_t *mem = NULL, *nix_mem = NULL, *npc_mem = NULL;\n-\tstruct otx2_npc_flow_info *npc = &hw->npc_flow;\n-\tuint32_t bmap_sz, tot_mcam_entries = 0;\n-\tint rc = 0, idx;\n-\n-\trc = flow_fetch_kex_cfg(hw);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to fetch NPC keyx config from idev\");\n-\t\treturn rc;\n-\t}\n-\n-\trte_atomic32_init(&npc->mark_actions);\n-\tnpc->vtag_actions = 0;\n-\n-\ttot_mcam_entries = otx2_mcam_tot_entries(hw);\n-\tnpc->mcam_entries = tot_mcam_entries >> npc->keyw[NPC_MCAM_RX];\n-\t/* Free, free_rev, live and live_rev entries */\n-\tbmap_sz = rte_bitmap_get_memory_footprint(npc->mcam_entries);\n-\tmem = rte_zmalloc(NULL, 4 * bmap_sz * npc->flow_max_priority,\n-\t\t\t RTE_CACHE_LINE_SIZE);\n-\tif (mem == NULL) {\n-\t\totx2_err(\"Bmap alloc failed\");\n-\t\trc = -ENOMEM;\n-\t\treturn rc;\n-\t}\n-\n-\tnpc->flow_entry_info = rte_zmalloc(NULL, npc->flow_max_priority\n-\t\t\t\t\t * sizeof(struct otx2_mcam_ents_info),\n-\t\t\t\t\t 0);\n-\tif (npc->flow_entry_info == NULL) {\n-\t\totx2_err(\"flow_entry_info alloc failed\");\n-\t\trc = -ENOMEM;\n-\t\tgoto err;\n-\t}\n-\n-\tnpc->free_entries = rte_zmalloc(NULL, npc->flow_max_priority\n-\t\t\t\t\t* sizeof(struct rte_bitmap *),\n-\t\t\t\t\t0);\n-\tif (npc->free_entries == NULL) {\n-\t\totx2_err(\"free_entries alloc failed\");\n-\t\trc = -ENOMEM;\n-\t\tgoto err;\n-\t}\n-\n-\tnpc->free_entries_rev = rte_zmalloc(NULL, npc->flow_max_priority\n-\t\t\t\t\t* sizeof(struct rte_bitmap *),\n-\t\t\t\t\t0);\n-\tif (npc->free_entries_rev == NULL) {\n-\t\totx2_err(\"free_entries_rev alloc failed\");\n-\t\trc = -ENOMEM;\n-\t\tgoto err;\n-\t}\n-\n-\tnpc->live_entries = rte_zmalloc(NULL, npc->flow_max_priority\n-\t\t\t\t\t* sizeof(struct rte_bitmap *),\n-\t\t\t\t\t0);\n-\tif (npc->live_entries == NULL) {\n-\t\totx2_err(\"live_entries alloc failed\");\n-\t\trc = -ENOMEM;\n-\t\tgoto err;\n-\t}\n-\n-\tnpc->live_entries_rev = rte_zmalloc(NULL, npc->flow_max_priority\n-\t\t\t\t\t* sizeof(struct rte_bitmap *),\n-\t\t\t\t\t0);\n-\tif (npc->live_entries_rev == NULL) {\n-\t\totx2_err(\"live_entries_rev alloc failed\");\n-\t\trc = -ENOMEM;\n-\t\tgoto err;\n-\t}\n-\n-\tnpc->flow_list = rte_zmalloc(NULL, npc->flow_max_priority\n-\t\t\t\t\t* sizeof(struct otx2_flow_list),\n-\t\t\t\t\t0);\n-\tif (npc->flow_list == NULL) {\n-\t\totx2_err(\"flow_list alloc failed\");\n-\t\trc = -ENOMEM;\n-\t\tgoto err;\n-\t}\n-\n-\tnpc_mem = mem;\n-\tfor (idx = 0; idx < npc->flow_max_priority; idx++) {\n-\t\tTAILQ_INIT(&npc->flow_list[idx]);\n-\n-\t\tnpc->free_entries[idx] =\n-\t\t\trte_bitmap_init(npc->mcam_entries, mem, bmap_sz);\n-\t\tmem += bmap_sz;\n-\n-\t\tnpc->free_entries_rev[idx] =\n-\t\t\trte_bitmap_init(npc->mcam_entries, mem, bmap_sz);\n-\t\tmem += bmap_sz;\n-\n-\t\tnpc->live_entries[idx] =\n-\t\t\trte_bitmap_init(npc->mcam_entries, mem, bmap_sz);\n-\t\tmem += bmap_sz;\n-\n-\t\tnpc->live_entries_rev[idx] =\n-\t\t\trte_bitmap_init(npc->mcam_entries, mem, bmap_sz);\n-\t\tmem += bmap_sz;\n-\n-\t\tnpc->flow_entry_info[idx].free_ent = 0;\n-\t\tnpc->flow_entry_info[idx].live_ent = 0;\n-\t\tnpc->flow_entry_info[idx].max_id = 0;\n-\t\tnpc->flow_entry_info[idx].min_id = ~(0);\n-\t}\n-\n-\tnpc->rss_grps = NIX_RSS_GRPS;\n-\n-\tbmap_sz = rte_bitmap_get_memory_footprint(npc->rss_grps);\n-\tnix_mem = rte_zmalloc(NULL, bmap_sz, RTE_CACHE_LINE_SIZE);\n-\tif (nix_mem == NULL) {\n-\t\totx2_err(\"Bmap alloc failed\");\n-\t\trc = -ENOMEM;\n-\t\tgoto err;\n-\t}\n-\n-\tnpc->rss_grp_entries = rte_bitmap_init(npc->rss_grps, nix_mem, bmap_sz);\n-\n-\t/* Group 0 will be used for RSS,\n-\t * 1 -7 will be used for rte_flow RSS action\n-\t */\n-\trte_bitmap_set(npc->rss_grp_entries, 0);\n-\n-\treturn 0;\n-\n-err:\n-\tif (npc->flow_list)\n-\t\trte_free(npc->flow_list);\n-\tif (npc->live_entries_rev)\n-\t\trte_free(npc->live_entries_rev);\n-\tif (npc->live_entries)\n-\t\trte_free(npc->live_entries);\n-\tif (npc->free_entries_rev)\n-\t\trte_free(npc->free_entries_rev);\n-\tif (npc->free_entries)\n-\t\trte_free(npc->free_entries);\n-\tif (npc->flow_entry_info)\n-\t\trte_free(npc->flow_entry_info);\n-\tif (npc_mem)\n-\t\trte_free(npc_mem);\n-\treturn rc;\n-}\n-\n-int\n-otx2_flow_fini(struct otx2_eth_dev *hw)\n-{\n-\tstruct otx2_npc_flow_info *npc = &hw->npc_flow;\n-\tint rc;\n-\n-\trc = otx2_flow_free_all_resources(hw);\n-\tif (rc) {\n-\t\totx2_err(\"Error when deleting NPC MCAM entries, counters\");\n-\t\treturn rc;\n-\t}\n-\n-\tif (npc->flow_list)\n-\t\trte_free(npc->flow_list);\n-\tif (npc->live_entries_rev)\n-\t\trte_free(npc->live_entries_rev);\n-\tif (npc->live_entries)\n-\t\trte_free(npc->live_entries);\n-\tif (npc->free_entries_rev)\n-\t\trte_free(npc->free_entries_rev);\n-\tif (npc->free_entries)\n-\t\trte_free(npc->free_entries);\n-\tif (npc->flow_entry_info)\n-\t\trte_free(npc->flow_entry_info);\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/net/octeontx2/otx2_flow.h b/drivers/net/octeontx2/otx2_flow.h\ndeleted file mode 100644\nindex 790e6ef1e8..0000000000\n--- a/drivers/net/octeontx2/otx2_flow.h\n+++ /dev/null\n@@ -1,414 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_FLOW_H__\n-#define __OTX2_FLOW_H__\n-\n-#include <stdint.h>\n-\n-#include <rte_flow_driver.h>\n-#include <rte_malloc.h>\n-#include <rte_tailq.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_ethdev.h\"\n-#include \"otx2_mbox.h\"\n-\n-struct otx2_eth_dev;\n-\n-int otx2_flow_init(struct otx2_eth_dev *hw);\n-int otx2_flow_fini(struct otx2_eth_dev *hw);\n-extern const struct rte_flow_ops otx2_flow_ops;\n-\n-enum {\n-\tOTX2_INTF_RX = 0,\n-\tOTX2_INTF_TX = 1,\n-\tOTX2_INTF_MAX = 2,\n-};\n-\n-#define NPC_IH_LENGTH\t\t\t8\n-#define NPC_TPID_LENGTH\t\t\t2\n-#define NPC_HIGIG2_LENGTH\t\t16\n-#define NPC_MAX_RAW_ITEM_LEN\t\t16\n-#define NPC_COUNTER_NONE\t\t(-1)\n-/* 32 bytes from LDATA_CFG & 32 bytes from FLAGS_CFG */\n-#define NPC_MAX_EXTRACT_DATA_LEN\t(64)\n-#define NPC_LDATA_LFLAG_LEN\t\t(16)\n-#define NPC_MAX_KEY_NIBBLES\t\t(31)\n-/* Nibble offsets */\n-#define NPC_LAYER_KEYX_SZ\t\t(3)\n-#define NPC_PARSE_KEX_S_LA_OFFSET\t(7)\n-#define NPC_PARSE_KEX_S_LID_OFFSET(lid)\t\t\\\n-\t((((lid) - NPC_LID_LA) * NPC_LAYER_KEYX_SZ) \\\n-\t+ NPC_PARSE_KEX_S_LA_OFFSET)\n-\n-\n-/* supported flow actions flags */\n-#define OTX2_FLOW_ACT_MARK (1 << 0)\n-#define OTX2_FLOW_ACT_FLAG (1 << 1)\n-#define OTX2_FLOW_ACT_DROP (1 << 2)\n-#define OTX2_FLOW_ACT_QUEUE (1 << 3)\n-#define OTX2_FLOW_ACT_RSS (1 << 4)\n-#define OTX2_FLOW_ACT_DUP (1 << 5)\n-#define OTX2_FLOW_ACT_SEC (1 << 6)\n-#define OTX2_FLOW_ACT_COUNT (1 << 7)\n-#define OTX2_FLOW_ACT_PF (1 << 8)\n-#define OTX2_FLOW_ACT_VF (1 << 9)\n-#define OTX2_FLOW_ACT_VLAN_STRIP (1 << 10)\n-#define OTX2_FLOW_ACT_VLAN_INSERT (1 << 11)\n-#define OTX2_FLOW_ACT_VLAN_ETHTYPE_INSERT (1 << 12)\n-#define OTX2_FLOW_ACT_VLAN_PCP_INSERT (1 << 13)\n-\n-/* terminating actions */\n-#define OTX2_FLOW_ACT_TERM (OTX2_FLOW_ACT_DROP | \\\n-\t\t\t OTX2_FLOW_ACT_QUEUE | \\\n-\t\t\t OTX2_FLOW_ACT_RSS | \\\n-\t\t\t OTX2_FLOW_ACT_DUP | \\\n-\t\t\t OTX2_FLOW_ACT_SEC)\n-\n-/* This mark value indicates flag action */\n-#define OTX2_FLOW_FLAG_VAL (0xffff)\n-\n-#define NIX_RX_ACT_MATCH_OFFSET\t\t(40)\n-#define NIX_RX_ACT_MATCH_MASK\t\t(0xFFFF)\n-\n-#define NIX_RSS_ACT_GRP_OFFSET\t\t(20)\n-#define NIX_RSS_ACT_ALG_OFFSET\t\t(56)\n-#define NIX_RSS_ACT_GRP_MASK\t\t(0xFFFFF)\n-#define NIX_RSS_ACT_ALG_MASK\t\t(0x1F)\n-\n-/* PMD-specific definition of the opaque struct rte_flow */\n-#define OTX2_MAX_MCAM_WIDTH_DWORDS\t7\n-\n-enum npc_mcam_intf {\n-\tNPC_MCAM_RX,\n-\tNPC_MCAM_TX\n-};\n-\n-struct npc_xtract_info {\n-\t/* Length in bytes of pkt data extracted. len = 0\n-\t * indicates that extraction is disabled.\n-\t */\n-\tuint8_t len;\n-\tuint8_t hdr_off; /* Byte offset of proto hdr: extract_src */\n-\tuint8_t key_off; /* Byte offset in MCAM key where data is placed */\n-\tuint8_t enable; /* Extraction enabled or disabled */\n-\tuint8_t flags_enable; /* Flags extraction enabled */\n-};\n-\n-/* Information for a given {LAYER, LTYPE} */\n-struct npc_lid_lt_xtract_info {\n-\t/* Info derived from parser configuration */\n-\tuint16_t npc_proto; /* Network protocol identified */\n-\tuint8_t valid_flags_mask; /* Flags applicable */\n-\tuint8_t is_terminating:1; /* No more parsing */\n-\tstruct npc_xtract_info xtract[NPC_MAX_LD];\n-};\n-\n-union npc_kex_ldata_flags_cfg {\n-\tstruct {\n-\t#if defined(__BIG_ENDIAN_BITFIELD)\n-\t\tuint64_t rvsd_62_1\t: 61;\n-\t\tuint64_t lid\t\t: 3;\n-\t#else\n-\t\tuint64_t lid\t\t: 3;\n-\t\tuint64_t rvsd_62_1\t: 61;\n-\t#endif\n-\t} s;\n-\n-\tuint64_t i;\n-};\n-\n-typedef struct npc_lid_lt_xtract_info\n-\totx2_dxcfg_t[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT];\n-typedef struct npc_lid_lt_xtract_info\n-\totx2_fxcfg_t[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];\n-typedef union npc_kex_ldata_flags_cfg otx2_ld_flags_t[NPC_MAX_LD];\n-\n-\n-/* MBOX_MSG_NPC_GET_DATAX_CFG Response */\n-struct npc_get_datax_cfg {\n-\t/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */\n-\tunion npc_kex_ldata_flags_cfg ld_flags[NPC_MAX_LD];\n-\t/* Extract information indexed with [LID][LTYPE] */\n-\tstruct npc_lid_lt_xtract_info lid_lt_xtract[NPC_MAX_LID][NPC_MAX_LT];\n-\t/* Flags based extract indexed with [LDATA][FLAGS_LOWER_NIBBLE]\n-\t * Fields flags_ena_ld0, flags_ena_ld1 in\n-\t * struct npc_lid_lt_xtract_info indicate if this is applicable\n-\t * for a given {LAYER, LTYPE}\n-\t */\n-\tstruct npc_xtract_info flag_xtract[NPC_MAX_LD][NPC_MAX_LT];\n-};\n-\n-struct otx2_mcam_ents_info {\n-\t/* Current max & min values of mcam index */\n-\tuint32_t max_id;\n-\tuint32_t min_id;\n-\tuint32_t free_ent;\n-\tuint32_t live_ent;\n-};\n-\n-struct otx2_flow_dump_data {\n-\tuint8_t lid;\n-\tuint16_t ltype;\n-};\n-\n-struct rte_flow {\n-\tuint8_t nix_intf;\n-\tuint32_t mcam_id;\n-\tint32_t ctr_id;\n-\tuint32_t priority;\n-\t/* Contiguous match string */\n-\tuint64_t mcam_data[OTX2_MAX_MCAM_WIDTH_DWORDS];\n-\tuint64_t mcam_mask[OTX2_MAX_MCAM_WIDTH_DWORDS];\n-\tuint64_t npc_action;\n-\tuint64_t vtag_action;\n-\tstruct otx2_flow_dump_data dump_data[32];\n-\tuint16_t num_patterns;\n-\tTAILQ_ENTRY(rte_flow) next;\n-};\n-\n-TAILQ_HEAD(otx2_flow_list, rte_flow);\n-\n-/* Accessed from ethdev private - otx2_eth_dev */\n-struct otx2_npc_flow_info {\n-\trte_atomic32_t mark_actions;\n-\tuint32_t vtag_actions;\n-\tuint32_t keyx_supp_nmask[NPC_MAX_INTF];/* nibble mask */\n-\tuint32_t keyx_len[NPC_MAX_INTF];\t/* per intf key len in bits */\n-\tuint32_t datax_len[NPC_MAX_INTF];\t/* per intf data len in bits */\n-\tuint32_t keyw[NPC_MAX_INTF];\t\t/* max key + data len bits */\n-\tuint32_t mcam_entries;\t\t\t/* mcam entries supported */\n-\totx2_dxcfg_t prx_dxcfg;\t\t\t/* intf, lid, lt, extract */\n-\totx2_fxcfg_t prx_fxcfg;\t\t\t/* Flag extract */\n-\totx2_ld_flags_t prx_lfcfg;\t\t/* KEX LD_Flags CFG */\n-\t/* mcam entry info per priority level: both free & in-use */\n-\tstruct otx2_mcam_ents_info *flow_entry_info;\n-\t/* Bitmap of free preallocated entries in ascending index &\n-\t * descending priority\n-\t */\n-\tstruct rte_bitmap **free_entries;\n-\t/* Bitmap of free preallocated entries in descending index &\n-\t * ascending priority\n-\t */\n-\tstruct rte_bitmap **free_entries_rev;\n-\t/* Bitmap of live entries in ascending index & descending priority */\n-\tstruct rte_bitmap **live_entries;\n-\t/* Bitmap of live entries in descending index & ascending priority */\n-\tstruct rte_bitmap **live_entries_rev;\n-\t/* Priority bucket wise tail queue of all rte_flow resources */\n-\tstruct otx2_flow_list *flow_list;\n-\tuint32_t rss_grps; /* rss groups supported */\n-\tstruct rte_bitmap *rss_grp_entries;\n-\tuint16_t channel; /*rx channel */\n-\tuint16_t flow_prealloc_size;\n-\tuint16_t flow_max_priority;\n-\tuint16_t switch_header_type;\n-};\n-\n-struct otx2_parse_state {\n-\tstruct otx2_npc_flow_info *npc;\n-\tconst struct rte_flow_item *pattern;\n-\tconst struct rte_flow_item *last_pattern; /* Temp usage */\n-\tstruct rte_flow_error *error;\n-\tstruct rte_flow *flow;\n-\tuint8_t tunnel;\n-\tuint8_t terminate;\n-\tuint8_t layer_mask;\n-\tuint8_t lt[NPC_MAX_LID];\n-\tuint8_t flags[NPC_MAX_LID];\n-\tuint8_t *mcam_data; /* point to flow->mcam_data + key_len */\n-\tuint8_t *mcam_mask; /* point to flow->mcam_mask + key_len */\n-\tbool is_vf;\n-};\n-\n-struct otx2_flow_item_info {\n-\tconst void *def_mask; /* rte_flow default mask */\n-\tvoid *hw_mask; /* hardware supported mask */\n-\tint len; /* length of item */\n-\tconst void *spec; /* spec to use, NULL implies match any */\n-\tconst void *mask; /* mask to use */\n-\tuint8_t hw_hdr_len; /* Extra data len at each layer*/\n-};\n-\n-struct otx2_idev_kex_cfg {\n-\tstruct npc_get_kex_cfg_rsp kex_cfg;\n-\trte_atomic16_t kex_refcnt;\n-};\n-\n-enum npc_kpu_parser_flag {\n-\tNPC_F_NA = 0,\n-\tNPC_F_PKI,\n-\tNPC_F_PKI_VLAN,\n-\tNPC_F_PKI_ETAG,\n-\tNPC_F_PKI_ITAG,\n-\tNPC_F_PKI_MPLS,\n-\tNPC_F_PKI_NSH,\n-\tNPC_F_ETYPE_UNK,\n-\tNPC_F_ETHER_VLAN,\n-\tNPC_F_ETHER_ETAG,\n-\tNPC_F_ETHER_ITAG,\n-\tNPC_F_ETHER_MPLS,\n-\tNPC_F_ETHER_NSH,\n-\tNPC_F_STAG_CTAG,\n-\tNPC_F_STAG_CTAG_UNK,\n-\tNPC_F_STAG_STAG_CTAG,\n-\tNPC_F_STAG_STAG_STAG,\n-\tNPC_F_QINQ_CTAG,\n-\tNPC_F_QINQ_CTAG_UNK,\n-\tNPC_F_QINQ_QINQ_CTAG,\n-\tNPC_F_QINQ_QINQ_QINQ,\n-\tNPC_F_BTAG_ITAG,\n-\tNPC_F_BTAG_ITAG_STAG,\n-\tNPC_F_BTAG_ITAG_CTAG,\n-\tNPC_F_BTAG_ITAG_UNK,\n-\tNPC_F_ETAG_CTAG,\n-\tNPC_F_ETAG_BTAG_ITAG,\n-\tNPC_F_ETAG_STAG,\n-\tNPC_F_ETAG_QINQ,\n-\tNPC_F_ETAG_ITAG,\n-\tNPC_F_ETAG_ITAG_STAG,\n-\tNPC_F_ETAG_ITAG_CTAG,\n-\tNPC_F_ETAG_ITAG_UNK,\n-\tNPC_F_ITAG_STAG_CTAG,\n-\tNPC_F_ITAG_STAG,\n-\tNPC_F_ITAG_CTAG,\n-\tNPC_F_MPLS_4_LABELS,\n-\tNPC_F_MPLS_3_LABELS,\n-\tNPC_F_MPLS_2_LABELS,\n-\tNPC_F_IP_HAS_OPTIONS,\n-\tNPC_F_IP_IP_IN_IP,\n-\tNPC_F_IP_6TO4,\n-\tNPC_F_IP_MPLS_IN_IP,\n-\tNPC_F_IP_UNK_PROTO,\n-\tNPC_F_IP_IP_IN_IP_HAS_OPTIONS,\n-\tNPC_F_IP_6TO4_HAS_OPTIONS,\n-\tNPC_F_IP_MPLS_IN_IP_HAS_OPTIONS,\n-\tNPC_F_IP_UNK_PROTO_HAS_OPTIONS,\n-\tNPC_F_IP6_HAS_EXT,\n-\tNPC_F_IP6_TUN_IP6,\n-\tNPC_F_IP6_MPLS_IN_IP,\n-\tNPC_F_TCP_HAS_OPTIONS,\n-\tNPC_F_TCP_HTTP,\n-\tNPC_F_TCP_HTTPS,\n-\tNPC_F_TCP_PPTP,\n-\tNPC_F_TCP_UNK_PORT,\n-\tNPC_F_TCP_HTTP_HAS_OPTIONS,\n-\tNPC_F_TCP_HTTPS_HAS_OPTIONS,\n-\tNPC_F_TCP_PPTP_HAS_OPTIONS,\n-\tNPC_F_TCP_UNK_PORT_HAS_OPTIONS,\n-\tNPC_F_UDP_VXLAN,\n-\tNPC_F_UDP_VXLAN_NOVNI,\n-\tNPC_F_UDP_VXLAN_NOVNI_NSH,\n-\tNPC_F_UDP_VXLANGPE,\n-\tNPC_F_UDP_VXLANGPE_NSH,\n-\tNPC_F_UDP_VXLANGPE_MPLS,\n-\tNPC_F_UDP_VXLANGPE_NOVNI,\n-\tNPC_F_UDP_VXLANGPE_NOVNI_NSH,\n-\tNPC_F_UDP_VXLANGPE_NOVNI_MPLS,\n-\tNPC_F_UDP_VXLANGPE_UNK,\n-\tNPC_F_UDP_VXLANGPE_NONP,\n-\tNPC_F_UDP_GTP_GTPC,\n-\tNPC_F_UDP_GTP_GTPU_G_PDU,\n-\tNPC_F_UDP_GTP_GTPU_UNK,\n-\tNPC_F_UDP_UNK_PORT,\n-\tNPC_F_UDP_GENEVE,\n-\tNPC_F_UDP_GENEVE_OAM,\n-\tNPC_F_UDP_GENEVE_CRI_OPT,\n-\tNPC_F_UDP_GENEVE_OAM_CRI_OPT,\n-\tNPC_F_GRE_NVGRE,\n-\tNPC_F_GRE_HAS_SRE,\n-\tNPC_F_GRE_HAS_CSUM,\n-\tNPC_F_GRE_HAS_KEY,\n-\tNPC_F_GRE_HAS_SEQ,\n-\tNPC_F_GRE_HAS_CSUM_KEY,\n-\tNPC_F_GRE_HAS_CSUM_SEQ,\n-\tNPC_F_GRE_HAS_KEY_SEQ,\n-\tNPC_F_GRE_HAS_CSUM_KEY_SEQ,\n-\tNPC_F_GRE_HAS_ROUTE,\n-\tNPC_F_GRE_UNK_PROTO,\n-\tNPC_F_GRE_VER1,\n-\tNPC_F_GRE_VER1_HAS_SEQ,\n-\tNPC_F_GRE_VER1_HAS_ACK,\n-\tNPC_F_GRE_VER1_HAS_SEQ_ACK,\n-\tNPC_F_GRE_VER1_UNK_PROTO,\n-\tNPC_F_TU_ETHER_UNK,\n-\tNPC_F_TU_ETHER_CTAG,\n-\tNPC_F_TU_ETHER_CTAG_UNK,\n-\tNPC_F_TU_ETHER_STAG_CTAG,\n-\tNPC_F_TU_ETHER_STAG_CTAG_UNK,\n-\tNPC_F_TU_ETHER_STAG,\n-\tNPC_F_TU_ETHER_STAG_UNK,\n-\tNPC_F_TU_ETHER_QINQ_CTAG,\n-\tNPC_F_TU_ETHER_QINQ_CTAG_UNK,\n-\tNPC_F_TU_ETHER_QINQ,\n-\tNPC_F_TU_ETHER_QINQ_UNK,\n-\tNPC_F_LAST /* has to be the last item */\n-};\n-\n-\n-int otx2_flow_mcam_free_counter(struct otx2_mbox *mbox, uint16_t ctr_id);\n-\n-int otx2_flow_mcam_read_counter(struct otx2_mbox *mbox, uint32_t ctr_id,\n-\t\t\t\tuint64_t *count);\n-\n-int otx2_flow_mcam_clear_counter(struct otx2_mbox *mbox, uint32_t ctr_id);\n-\n-int otx2_flow_mcam_free_entry(struct otx2_mbox *mbox, uint32_t entry);\n-\n-int otx2_flow_mcam_free_all_entries(struct otx2_mbox *mbox);\n-\n-int otx2_flow_update_parse_state(struct otx2_parse_state *pst,\n-\t\t\t\t struct otx2_flow_item_info *info,\n-\t\t\t\t int lid, int lt, uint8_t flags);\n-\n-int otx2_flow_parse_item_basic(const struct rte_flow_item *item,\n-\t\t\t struct otx2_flow_item_info *info,\n-\t\t\t struct rte_flow_error *error);\n-\n-void otx2_flow_keyx_compress(uint64_t *data, uint32_t nibble_mask);\n-\n-int otx2_flow_mcam_alloc_and_write(struct rte_flow *flow,\n-\t\t\t\t struct otx2_mbox *mbox,\n-\t\t\t\t struct otx2_parse_state *pst,\n-\t\t\t\t struct otx2_npc_flow_info *flow_info);\n-\n-void otx2_flow_get_hw_supp_mask(struct otx2_parse_state *pst,\n-\t\t\t\tstruct otx2_flow_item_info *info,\n-\t\t\t\tint lid, int lt);\n-\n-const struct rte_flow_item *\n-otx2_flow_skip_void_and_any_items(const struct rte_flow_item *pattern);\n-\n-int otx2_flow_parse_lh(struct otx2_parse_state *pst);\n-\n-int otx2_flow_parse_lg(struct otx2_parse_state *pst);\n-\n-int otx2_flow_parse_lf(struct otx2_parse_state *pst);\n-\n-int otx2_flow_parse_le(struct otx2_parse_state *pst);\n-\n-int otx2_flow_parse_ld(struct otx2_parse_state *pst);\n-\n-int otx2_flow_parse_lc(struct otx2_parse_state *pst);\n-\n-int otx2_flow_parse_lb(struct otx2_parse_state *pst);\n-\n-int otx2_flow_parse_la(struct otx2_parse_state *pst);\n-\n-int otx2_flow_parse_higig2_hdr(struct otx2_parse_state *pst);\n-\n-int otx2_flow_parse_actions(struct rte_eth_dev *dev,\n-\t\t\t const struct rte_flow_attr *attr,\n-\t\t\t const struct rte_flow_action actions[],\n-\t\t\t struct rte_flow_error *error,\n-\t\t\t struct rte_flow *flow);\n-\n-int otx2_flow_free_all_resources(struct otx2_eth_dev *hw);\n-\n-int otx2_flow_parse_mpls(struct otx2_parse_state *pst, int lid);\n-\n-void otx2_flow_dump(FILE *file, struct otx2_eth_dev *hw,\n-\t\t struct rte_flow *flow);\n-#endif /* __OTX2_FLOW_H__ */\ndiff --git a/drivers/net/octeontx2/otx2_flow_ctrl.c b/drivers/net/octeontx2/otx2_flow_ctrl.c\ndeleted file mode 100644\nindex 071740de86..0000000000\n--- a/drivers/net/octeontx2/otx2_flow_ctrl.c\n+++ /dev/null\n@@ -1,252 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_ethdev.h\"\n-\n-int\n-otx2_nix_rxchan_bpid_cfg(struct rte_eth_dev *eth_dev, bool enb)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_fc_info *fc = &dev->fc_info;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_bp_cfg_req *req;\n-\tstruct nix_bp_cfg_rsp *rsp;\n-\tint rc;\n-\n-\tif (otx2_dev_is_sdp(dev))\n-\t\treturn 0;\n-\n-\tif (enb) {\n-\t\treq = otx2_mbox_alloc_msg_nix_bp_enable(mbox);\n-\t\treq->chan_base = 0;\n-\t\treq->chan_cnt = 1;\n-\t\treq->bpid_per_chan = 0;\n-\n-\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc || req->chan_cnt != rsp->chan_cnt) {\n-\t\t\totx2_err(\"Insufficient BPIDs, alloc=%u < req=%u rc=%d\",\n-\t\t\t\t rsp->chan_cnt, req->chan_cnt, rc);\n-\t\t\treturn rc;\n-\t\t}\n-\n-\t\tfc->bpid[0] = rsp->chan_bpid[0];\n-\t} else {\n-\t\treq = otx2_mbox_alloc_msg_nix_bp_disable(mbox);\n-\t\treq->chan_base = 0;\n-\t\treq->chan_cnt = 1;\n-\n-\t\trc = otx2_mbox_process(mbox);\n-\n-\t\tmemset(fc->bpid, 0, sizeof(uint16_t) * NIX_MAX_CHAN);\n-\t}\n-\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,\n-\t\t struct rte_eth_fc_conf *fc_conf)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct cgx_pause_frm_cfg *req, *rsp;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tint rc;\n-\n-\tif (otx2_dev_is_lbk(dev)) {\n-\t\tfc_conf->mode = RTE_ETH_FC_NONE;\n-\t\treturn 0;\n-\t}\n-\n-\treq = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(mbox);\n-\treq->set = 0;\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\tgoto done;\n-\n-\tif (rsp->rx_pause && rsp->tx_pause)\n-\t\tfc_conf->mode = RTE_ETH_FC_FULL;\n-\telse if (rsp->rx_pause)\n-\t\tfc_conf->mode = RTE_ETH_FC_RX_PAUSE;\n-\telse if (rsp->tx_pause)\n-\t\tfc_conf->mode = RTE_ETH_FC_TX_PAUSE;\n-\telse\n-\t\tfc_conf->mode = RTE_ETH_FC_NONE;\n-\n-done:\n-\treturn rc;\n-}\n-\n-static int\n-otx2_nix_cq_bp_cfg(struct rte_eth_dev *eth_dev, bool enb)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_fc_info *fc = &dev->fc_info;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_aq_enq_req *aq;\n-\tstruct otx2_eth_rxq *rxq;\n-\tint i, rc;\n-\n-\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n-\t\trxq = eth_dev->data->rx_queues[i];\n-\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!aq) {\n-\t\t\t/* The shared memory buffer can be full.\n-\t\t\t * flush it and retry\n-\t\t\t */\n-\t\t\totx2_mbox_msg_send(mbox, 0);\n-\t\t\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\t\t\tif (rc < 0)\n-\t\t\t\treturn rc;\n-\n-\t\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\t\tif (!aq)\n-\t\t\t\treturn -ENOMEM;\n-\t\t}\n-\t\taq->qidx = rxq->rq;\n-\t\taq->ctype = NIX_AQ_CTYPE_CQ;\n-\t\taq->op = NIX_AQ_INSTOP_WRITE;\n-\n-\t\tif (enb) {\n-\t\t\taq->cq.bpid = fc->bpid[0];\n-\t\t\taq->cq_mask.bpid = ~(aq->cq_mask.bpid);\n-\t\t\taq->cq.bp = rxq->cq_drop;\n-\t\t\taq->cq_mask.bp = ~(aq->cq_mask.bp);\n-\t\t}\n-\n-\t\taq->cq.bp_ena = !!enb;\n-\t\taq->cq_mask.bp_ena = ~(aq->cq_mask.bp_ena);\n-\t}\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\tif (rc < 0)\n-\t\treturn rc;\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_rx_fc_cfg(struct rte_eth_dev *eth_dev, bool enb)\n-{\n-\treturn otx2_nix_cq_bp_cfg(eth_dev, enb);\n-}\n-\n-int\n-otx2_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n-\t\t struct rte_eth_fc_conf *fc_conf)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_fc_info *fc = &dev->fc_info;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct cgx_pause_frm_cfg *req;\n-\tuint8_t tx_pause, rx_pause;\n-\tint rc = 0;\n-\n-\tif (otx2_dev_is_lbk(dev)) {\n-\t\totx2_info(\"No flow control support for LBK bound ethports\");\n-\t\treturn -ENOTSUP;\n-\t}\n-\n-\tif (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time ||\n-\t fc_conf->mac_ctrl_frame_fwd || fc_conf->autoneg) {\n-\t\totx2_info(\"Flowctrl parameter is not supported\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (fc_conf->mode == fc->mode)\n-\t\treturn 0;\n-\n-\trx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) ||\n-\t\t (fc_conf->mode == RTE_ETH_FC_RX_PAUSE);\n-\ttx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) ||\n-\t\t (fc_conf->mode == RTE_ETH_FC_TX_PAUSE);\n-\n-\t/* Check if TX pause frame is already enabled or not */\n-\tif (fc->tx_pause ^ tx_pause) {\n-\t\tif (otx2_dev_is_Ax(dev) && eth_dev->data->dev_started) {\n-\t\t\t/* on Ax, CQ should be in disabled state\n-\t\t\t * while setting flow control configuration.\n-\t\t\t */\n-\t\t\totx2_info(\"Stop the port=%d for setting flow control\\n\",\n-\t\t\t\t eth_dev->data->port_id);\n-\t\t\t\treturn 0;\n-\t\t}\n-\t\t/* TX pause frames, enable/disable flowctrl on RX side. */\n-\t\trc = otx2_nix_rx_fc_cfg(eth_dev, tx_pause);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\t}\n-\n-\treq = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(mbox);\n-\treq->set = 1;\n-\treq->rx_pause = rx_pause;\n-\treq->tx_pause = tx_pause;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tfc->tx_pause = tx_pause;\n-\tfc->rx_pause = rx_pause;\n-\tfc->mode = fc_conf->mode;\n-\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_fc_info *fc = &dev->fc_info;\n-\tstruct rte_eth_fc_conf fc_conf;\n-\n-\tif (otx2_dev_is_lbk(dev) || otx2_dev_is_sdp(dev))\n-\t\treturn 0;\n-\n-\tmemset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf));\n-\tfc_conf.mode = fc->mode;\n-\n-\t/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */\n-\tif (otx2_dev_is_Ax(dev) &&\n-\t (dev->npc_flow.switch_header_type != OTX2_PRIV_FLAGS_HIGIG) &&\n-\t (fc_conf.mode == RTE_ETH_FC_FULL || fc_conf.mode == RTE_ETH_FC_RX_PAUSE)) {\n-\t\tfc_conf.mode =\n-\t\t\t\t(fc_conf.mode == RTE_ETH_FC_FULL ||\n-\t\t\t\tfc_conf.mode == RTE_ETH_FC_TX_PAUSE) ?\n-\t\t\t\tRTE_ETH_FC_TX_PAUSE : RTE_ETH_FC_NONE;\n-\t}\n-\n-\treturn otx2_nix_flow_ctrl_set(eth_dev, &fc_conf);\n-}\n-\n-int\n-otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_fc_info *fc = &dev->fc_info;\n-\tstruct rte_eth_fc_conf fc_conf;\n-\tint rc;\n-\n-\tif (otx2_dev_is_lbk(dev) || otx2_dev_is_sdp(dev))\n-\t\treturn 0;\n-\n-\tmemset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf));\n-\t/* Both Rx & Tx flow ctrl get enabled(RTE_ETH_FC_FULL) in HW\n-\t * by AF driver, update those info in PMD structure.\n-\t */\n-\trc = otx2_nix_flow_ctrl_get(eth_dev, &fc_conf);\n-\tif (rc)\n-\t\tgoto exit;\n-\n-\tfc->mode = fc_conf.mode;\n-\tfc->rx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||\n-\t\t\t(fc_conf.mode == RTE_ETH_FC_RX_PAUSE);\n-\tfc->tx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||\n-\t\t\t(fc_conf.mode == RTE_ETH_FC_TX_PAUSE);\n-\n-exit:\n-\treturn rc;\n-}\ndiff --git a/drivers/net/octeontx2/otx2_flow_dump.c b/drivers/net/octeontx2/otx2_flow_dump.c\ndeleted file mode 100644\nindex 3f86071300..0000000000\n--- a/drivers/net/octeontx2/otx2_flow_dump.c\n+++ /dev/null\n@@ -1,595 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_ethdev.h\"\n-#include \"otx2_ethdev_sec.h\"\n-#include \"otx2_flow.h\"\n-\n-#define NPC_MAX_FIELD_NAME_SIZE 80\n-#define NPC_RX_ACTIONOP_MASK\t\tGENMASK(3, 0)\n-#define NPC_RX_ACTION_PFFUNC_MASK\tGENMASK(19, 4)\n-#define NPC_RX_ACTION_INDEX_MASK\tGENMASK(39, 20)\n-#define NPC_RX_ACTION_MATCH_MASK\tGENMASK(55, 40)\n-#define NPC_RX_ACTION_FLOWKEY_MASK\tGENMASK(60, 56)\n-\n-#define NPC_TX_ACTION_INDEX_MASK\tGENMASK(31, 12)\n-#define NPC_TX_ACTION_MATCH_MASK\tGENMASK(47, 32)\n-\n-#define NIX_RX_VTAGACT_VTAG0_RELPTR_MASK\tGENMASK(7, 0)\n-#define NIX_RX_VTAGACT_VTAG0_LID_MASK\t\tGENMASK(10, 8)\n-#define NIX_RX_VTAGACT_VTAG0_TYPE_MASK\t\tGENMASK(14, 12)\n-#define NIX_RX_VTAGACT_VTAG0_VALID_MASK\t\tBIT_ULL(15)\n-\n-#define NIX_RX_VTAGACT_VTAG1_RELPTR_MASK\tGENMASK(39, 32)\n-#define NIX_RX_VTAGACT_VTAG1_LID_MASK\t\tGENMASK(42, 40)\n-#define NIX_RX_VTAGACT_VTAG1_TYPE_MASK\t\tGENMASK(46, 44)\n-#define NIX_RX_VTAGACT_VTAG1_VALID_MASK\t\tBIT_ULL(47)\n-\n-#define NIX_TX_VTAGACT_VTAG0_RELPTR_MASK\tGENMASK(7, 0)\n-#define NIX_TX_VTAGACT_VTAG0_LID_MASK\t\tGENMASK(10, 8)\n-#define NIX_TX_VTAGACT_VTAG0_OP_MASK\t\tGENMASK(13, 12)\n-#define NIX_TX_VTAGACT_VTAG0_DEF_MASK\t\tGENMASK(25, 16)\n-\n-#define NIX_TX_VTAGACT_VTAG1_RELPTR_MASK\tGENMASK(39, 32)\n-#define NIX_TX_VTAGACT_VTAG1_LID_MASK\t\tGENMASK(42, 40)\n-#define NIX_TX_VTAGACT_VTAG1_OP_MASK\t\tGENMASK(45, 44)\n-#define NIX_TX_VTAGACT_VTAG1_DEF_MASK\t\tGENMASK(57, 48)\n-\n-struct npc_rx_parse_nibble_s {\n-\tuint16_t chan : 3;\n-\tuint16_t errlev : 1;\n-\tuint16_t errcode : 2;\n-\tuint16_t l2l3bm : 1;\n-\tuint16_t laflags : 2;\n-\tuint16_t latype : 1;\n-\tuint16_t lbflags : 2;\n-\tuint16_t lbtype : 1;\n-\tuint16_t lcflags : 2;\n-\tuint16_t lctype : 1;\n-\tuint16_t ldflags : 2;\n-\tuint16_t ldtype : 1;\n-\tuint16_t leflags : 2;\n-\tuint16_t letype : 1;\n-\tuint16_t lfflags : 2;\n-\tuint16_t lftype : 1;\n-\tuint16_t lgflags : 2;\n-\tuint16_t lgtype : 1;\n-\tuint16_t lhflags : 2;\n-\tuint16_t lhtype : 1;\n-} __rte_packed;\n-\n-const char *intf_str[] = {\n-\t\"NIX-RX\",\n-\t\"NIX-TX\",\n-};\n-\n-const char *ltype_str[NPC_MAX_LID][NPC_MAX_LT] = {\n-\t[NPC_LID_LA][0] = \"NONE\",\n-\t[NPC_LID_LA][NPC_LT_LA_ETHER] = \"LA_ETHER\",\n-\t[NPC_LID_LA][NPC_LT_LA_IH_NIX_ETHER] = \"LA_IH_NIX_ETHER\",\n-\t[NPC_LID_LA][NPC_LT_LA_HIGIG2_ETHER] = \"LA_HIGIG2_ETHER\",\n-\t[NPC_LID_LA][NPC_LT_LA_IH_NIX_HIGIG2_ETHER] = \"LA_IH_NIX_HIGIG2_ETHER\",\n-\t[NPC_LID_LB][0] = \"NONE\",\n-\t[NPC_LID_LB][NPC_LT_LB_CTAG] = \"LB_CTAG\",\n-\t[NPC_LID_LB][NPC_LT_LB_STAG_QINQ] = \"LB_STAG_QINQ\",\n-\t[NPC_LID_LB][NPC_LT_LB_ETAG] = \"LB_ETAG\",\n-\t[NPC_LID_LB][NPC_LT_LB_EXDSA] = \"LB_EXDSA\",\n-\t[NPC_LID_LB][NPC_LT_LB_VLAN_EXDSA] = \"LB_VLAN_EXDSA\",\n-\t[NPC_LID_LC][0] = \"NONE\",\n-\t[NPC_LID_LC][NPC_LT_LC_IP] = \"LC_IP\",\n-\t[NPC_LID_LC][NPC_LT_LC_IP6] = \"LC_IP6\",\n-\t[NPC_LID_LC][NPC_LT_LC_ARP] = \"LC_ARP\",\n-\t[NPC_LID_LC][NPC_LT_LC_IP6_EXT] = \"LC_IP6_EXT\",\n-\t[NPC_LID_LC][NPC_LT_LC_NGIO] = \"LC_NGIO\",\n-\t[NPC_LID_LD][0] = \"NONE\",\n-\t[NPC_LID_LD][NPC_LT_LD_ICMP] = \"LD_ICMP\",\n-\t[NPC_LID_LD][NPC_LT_LD_ICMP6] = \"LD_ICMP6\",\n-\t[NPC_LID_LD][NPC_LT_LD_UDP] = \"LD_UDP\",\n-\t[NPC_LID_LD][NPC_LT_LD_TCP] = \"LD_TCP\",\n-\t[NPC_LID_LD][NPC_LT_LD_SCTP] = \"LD_SCTP\",\n-\t[NPC_LID_LD][NPC_LT_LD_GRE] = \"LD_GRE\",\n-\t[NPC_LID_LD][NPC_LT_LD_NVGRE] = \"LD_NVGRE\",\n-\t[NPC_LID_LE][0] = \"NONE\",\n-\t[NPC_LID_LE][NPC_LT_LE_VXLAN] = \"LE_VXLAN\",\n-\t[NPC_LID_LE][NPC_LT_LE_ESP] = \"LE_ESP\",\n-\t[NPC_LID_LE][NPC_LT_LE_GTPC] = \"LE_GTPC\",\n-\t[NPC_LID_LE][NPC_LT_LE_GTPU] = \"LE_GTPU\",\n-\t[NPC_LID_LE][NPC_LT_LE_GENEVE] = \"LE_GENEVE\",\n-\t[NPC_LID_LE][NPC_LT_LE_VXLANGPE] = \"LE_VXLANGPE\",\n-\t[NPC_LID_LF][0] = \"NONE\",\n-\t[NPC_LID_LF][NPC_LT_LF_TU_ETHER] = \"LF_TU_ETHER\",\n-\t[NPC_LID_LG][0] = \"NONE\",\n-\t[NPC_LID_LG][NPC_LT_LG_TU_IP] = \"LG_TU_IP\",\n-\t[NPC_LID_LG][NPC_LT_LG_TU_IP6] = \"LG_TU_IP6\",\n-\t[NPC_LID_LH][0] = \"NONE\",\n-\t[NPC_LID_LH][NPC_LT_LH_TU_UDP] = \"LH_TU_UDP\",\n-\t[NPC_LID_LH][NPC_LT_LH_TU_TCP] = \"LH_TU_TCP\",\n-\t[NPC_LID_LH][NPC_LT_LH_TU_SCTP] = \"LH_TU_SCTP\",\n-\t[NPC_LID_LH][NPC_LT_LH_TU_ESP] = \"LH_TU_ESP\",\n-};\n-\n-static uint16_t\n-otx2_get_nibbles(struct rte_flow *flow, uint16_t size, uint32_t bit_offset)\n-{\n-\tuint32_t byte_index, noffset;\n-\tuint16_t data, mask;\n-\tuint8_t *bytes;\n-\n-\tbytes = (uint8_t *)flow->mcam_data;\n-\tmask = (1ULL << (size * 4)) - 1;\n-\tbyte_index = bit_offset / 8;\n-\tnoffset = bit_offset % 8;\n-\tdata = *(uint16_t *)&bytes[byte_index];\n-\tdata >>= noffset;\n-\tdata &= mask;\n-\n-\treturn data;\n-}\n-\n-static void\n-otx2_flow_print_parse_nibbles(FILE *file, struct rte_flow *flow,\n-\t\t\t uint64_t parse_nibbles)\n-{\n-\tstruct npc_rx_parse_nibble_s *rx_parse;\n-\tuint32_t data, offset = 0;\n-\n-\trx_parse = (struct npc_rx_parse_nibble_s *)&parse_nibbles;\n-\n-\tif (rx_parse->chan) {\n-\t\tdata = otx2_get_nibbles(flow, 3, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_CHAN:%#03X\\n\", data);\n-\t\toffset += 12;\n-\t}\n-\n-\tif (rx_parse->errlev) {\n-\t\tdata = otx2_get_nibbles(flow, 1, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_ERRLEV:%#X\\n\", data);\n-\t\toffset += 4;\n-\t}\n-\n-\tif (rx_parse->errcode) {\n-\t\tdata = otx2_get_nibbles(flow, 2, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_ERRCODE:%#02X\\n\", data);\n-\t\toffset += 8;\n-\t}\n-\n-\tif (rx_parse->l2l3bm) {\n-\t\tdata = otx2_get_nibbles(flow, 1, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_L2L3_BCAST:%#X\\n\", data);\n-\t\toffset += 4;\n-\t}\n-\n-\tif (rx_parse->latype) {\n-\t\tdata = otx2_get_nibbles(flow, 1, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LA_LTYPE:%s\\n\",\n-\t\t\tltype_str[NPC_LID_LA][data]);\n-\t\toffset += 4;\n-\t}\n-\n-\tif (rx_parse->laflags) {\n-\t\tdata = otx2_get_nibbles(flow, 2, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LA_FLAGS:%#02X\\n\", data);\n-\t\toffset += 8;\n-\t}\n-\n-\tif (rx_parse->lbtype) {\n-\t\tdata = otx2_get_nibbles(flow, 1, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LB_LTYPE:%s\\n\",\n-\t\t\tltype_str[NPC_LID_LB][data]);\n-\t\toffset += 4;\n-\t}\n-\n-\tif (rx_parse->lbflags) {\n-\t\tdata = otx2_get_nibbles(flow, 2, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LB_FLAGS:%#02X\\n\", data);\n-\t\toffset += 8;\n-\t}\n-\n-\tif (rx_parse->lctype) {\n-\t\tdata = otx2_get_nibbles(flow, 1, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LC_LTYPE:%s\\n\",\n-\t\t\tltype_str[NPC_LID_LC][data]);\n-\t\toffset += 4;\n-\t}\n-\n-\tif (rx_parse->lcflags) {\n-\t\tdata = otx2_get_nibbles(flow, 2, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LC_FLAGS:%#02X\\n\", data);\n-\t\toffset += 8;\n-\t}\n-\n-\tif (rx_parse->ldtype) {\n-\t\tdata = otx2_get_nibbles(flow, 1, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LD_LTYPE:%s\\n\",\n-\t\t\tltype_str[NPC_LID_LD][data]);\n-\t\toffset += 4;\n-\t}\n-\n-\tif (rx_parse->ldflags) {\n-\t\tdata = otx2_get_nibbles(flow, 2, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LD_FLAGS:%#02X\\n\", data);\n-\t\toffset += 8;\n-\t}\n-\n-\tif (rx_parse->letype) {\n-\t\tdata = otx2_get_nibbles(flow, 1, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LE_LTYPE:%s\\n\",\n-\t\t\tltype_str[NPC_LID_LE][data]);\n-\t\toffset += 4;\n-\t}\n-\n-\tif (rx_parse->leflags) {\n-\t\tdata = otx2_get_nibbles(flow, 2, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LE_FLAGS:%#02X\\n\", data);\n-\t\toffset += 8;\n-\t}\n-\n-\tif (rx_parse->lftype) {\n-\t\tdata = otx2_get_nibbles(flow, 1, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LF_LTYPE:%s\\n\",\n-\t\t\tltype_str[NPC_LID_LF][data]);\n-\t\toffset += 4;\n-\t}\n-\n-\tif (rx_parse->lfflags) {\n-\t\tdata = otx2_get_nibbles(flow, 2, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LF_FLAGS:%#02X\\n\", data);\n-\t\toffset += 8;\n-\t}\n-\n-\tif (rx_parse->lgtype) {\n-\t\tdata = otx2_get_nibbles(flow, 1, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LG_LTYPE:%s\\n\",\n-\t\t\tltype_str[NPC_LID_LG][data]);\n-\t\toffset += 4;\n-\t}\n-\n-\tif (rx_parse->lgflags) {\n-\t\tdata = otx2_get_nibbles(flow, 2, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LG_FLAGS:%#02X\\n\", data);\n-\t\toffset += 8;\n-\t}\n-\n-\tif (rx_parse->lhtype) {\n-\t\tdata = otx2_get_nibbles(flow, 1, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LH_LTYPE:%s\\n\",\n-\t\t\tltype_str[NPC_LID_LH][data]);\n-\t\toffset += 4;\n-\t}\n-\n-\tif (rx_parse->lhflags) {\n-\t\tdata = otx2_get_nibbles(flow, 2, offset);\n-\t\tfprintf(file, \"\\tNPC_PARSE_NIBBLE_LH_FLAGS:%#02X\\n\", data);\n-\t}\n-}\n-\n-static void\n-otx2_flow_print_xtractinfo(FILE *file, struct npc_xtract_info *lfinfo,\n-\t\t\t struct rte_flow *flow, int lid, int lt)\n-{\n-\tuint8_t *datastart, *maskstart;\n-\tint i;\n-\n-\tdatastart = (uint8_t *)&flow->mcam_data + lfinfo->key_off;\n-\tmaskstart = (uint8_t *)&flow->mcam_mask + lfinfo->key_off;\n-\n-\tfprintf(file, \"\\t%s, hdr offset:%#X, len:%#X, key offset:%#X, \",\n-\t\tltype_str[lid][lt], lfinfo->hdr_off,\n-\t\tlfinfo->len, lfinfo->key_off);\n-\n-\tfprintf(file, \"Data:0X\");\n-\tfor (i = lfinfo->len - 1; i >= 0; i--)\n-\t\tfprintf(file, \"%02X\", datastart[i]);\n-\n-\tfprintf(file, \", \");\n-\n-\tfprintf(file, \"Mask:0X\");\n-\n-\tfor (i = lfinfo->len - 1; i >= 0; i--)\n-\t\tfprintf(file, \"%02X\", maskstart[i]);\n-\n-\tfprintf(file, \"\\n\");\n-}\n-\n-static void\n-otx2_flow_print_item(FILE *file, struct otx2_eth_dev *hw,\n-\t\t struct npc_xtract_info *xinfo, struct rte_flow *flow,\n-\t\t int intf, int lid, int lt, int ld)\n-{\n-\tstruct otx2_npc_flow_info *npc_flow = &hw->npc_flow;\n-\tstruct npc_xtract_info *lflags_info;\n-\tint i, lf_cfg;\n-\n-\totx2_flow_print_xtractinfo(file, xinfo, flow, lid, lt);\n-\n-\tif (xinfo->flags_enable) {\n-\t\tlf_cfg = npc_flow->prx_lfcfg[ld].i;\n-\n-\t\tif (lf_cfg == lid) {\n-\t\t\tfor (i = 0; i < NPC_MAX_LFL; i++) {\n-\t\t\t\tlflags_info = npc_flow->prx_fxcfg[intf]\n-\t\t\t\t\t\t\t[ld][i].xtract;\n-\n-\t\t\t\totx2_flow_print_xtractinfo(file, lflags_info,\n-\t\t\t\t\t\t\t flow, lid, lt);\n-\t\t\t}\n-\t\t}\n-\t}\n-}\n-\n-static void\n-otx2_flow_dump_patterns(FILE *file, struct otx2_eth_dev *hw,\n-\t\t\tstruct rte_flow *flow)\n-{\n-\tstruct otx2_npc_flow_info *npc_flow = &hw->npc_flow;\n-\tstruct npc_lid_lt_xtract_info *lt_xinfo;\n-\tstruct npc_xtract_info *xinfo;\n-\tuint32_t intf, lid, ld, i;\n-\tuint64_t parse_nibbles;\n-\tuint16_t ltype;\n-\n-\tintf = flow->nix_intf;\n-\tparse_nibbles = npc_flow->keyx_supp_nmask[intf];\n-\totx2_flow_print_parse_nibbles(file, flow, parse_nibbles);\n-\n-\tfor (i = 0; i < flow->num_patterns; i++) {\n-\t\tlid = flow->dump_data[i].lid;\n-\t\tltype = flow->dump_data[i].ltype;\n-\t\tlt_xinfo = &npc_flow->prx_dxcfg[intf][lid][ltype];\n-\n-\t\tfor (ld = 0; ld < NPC_MAX_LD; ld++) {\n-\t\t\txinfo = <_xinfo->xtract[ld];\n-\t\t\tif (!xinfo->enable)\n-\t\t\t\tcontinue;\n-\t\t\totx2_flow_print_item(file, hw, xinfo, flow, intf, lid,\n-\t\t\t\t\t ltype, ld);\n-\t\t}\n-\t}\n-}\n-\n-static void\n-otx2_flow_dump_tx_action(FILE *file, uint64_t npc_action)\n-{\n-\tchar index_name[NPC_MAX_FIELD_NAME_SIZE] = \"Index:\";\n-\tuint32_t tx_op, index, match_id;\n-\n-\ttx_op = npc_action & NPC_RX_ACTIONOP_MASK;\n-\n-\tfprintf(file, \"\\tActionOp:\");\n-\n-\tswitch (tx_op) {\n-\tcase NIX_TX_ACTIONOP_DROP:\n-\t\tfprintf(file, \"NIX_TX_ACTIONOP_DROP (%lu)\\n\",\n-\t\t\t(uint64_t)NIX_RX_ACTIONOP_DROP);\n-\t\tbreak;\n-\tcase NIX_TX_ACTIONOP_UCAST_DEFAULT:\n-\t\tfprintf(file, \"NIX_TX_ACTIONOP_UCAST_DEFAULT (%lu)\\n\",\n-\t\t\t(uint64_t)NIX_TX_ACTIONOP_UCAST_DEFAULT);\n-\t\tbreak;\n-\tcase NIX_TX_ACTIONOP_UCAST_CHAN:\n-\t\tfprintf(file, \"NIX_TX_ACTIONOP_UCAST_DEFAULT (%lu)\\n\",\n-\t\t\t(uint64_t)NIX_TX_ACTIONOP_UCAST_CHAN);\n-\t\tstrncpy(index_name, \"Transmit Channel:\",\n-\t\t\tNPC_MAX_FIELD_NAME_SIZE);\n-\t\tbreak;\n-\tcase NIX_TX_ACTIONOP_MCAST:\n-\t\tfprintf(file, \"NIX_TX_ACTIONOP_MCAST (%lu)\\n\",\n-\t\t\t(uint64_t)NIX_TX_ACTIONOP_MCAST);\n-\t\tstrncpy(index_name, \"Multicast Table Index:\",\n-\t\t\tNPC_MAX_FIELD_NAME_SIZE);\n-\t\tbreak;\n-\tcase NIX_TX_ACTIONOP_DROP_VIOL:\n-\t\tfprintf(file, \"NIX_TX_ACTIONOP_DROP_VIOL (%lu)\\n\",\n-\t\t\t(uint64_t)NIX_TX_ACTIONOP_DROP_VIOL);\n-\t\tbreak;\n-\t}\n-\n-\tindex = ((npc_action & NPC_TX_ACTION_INDEX_MASK) >> 12) & 0xFFFFF;\n-\n-\tfprintf(file, \"\\t%s:%#05X\\n\", index_name, index);\n-\n-\tmatch_id = ((npc_action & NPC_TX_ACTION_MATCH_MASK) >> 32) & 0xFFFF;\n-\n-\tfprintf(file, \"\\tMatch Id:%#04X\\n\", match_id);\n-}\n-\n-static void\n-otx2_flow_dump_rx_action(FILE *file, uint64_t npc_action)\n-{\n-\tuint32_t rx_op, pf_func, index, match_id, flowkey_alg;\n-\tchar index_name[NPC_MAX_FIELD_NAME_SIZE] = \"Index:\";\n-\n-\trx_op = npc_action & NPC_RX_ACTIONOP_MASK;\n-\n-\tfprintf(file, \"\\tActionOp:\");\n-\n-\tswitch (rx_op) {\n-\tcase NIX_RX_ACTIONOP_DROP:\n-\t\tfprintf(file, \"NIX_RX_ACTIONOP_DROP (%lu)\\n\",\n-\t\t\t(uint64_t)NIX_RX_ACTIONOP_DROP);\n-\t\tbreak;\n-\tcase NIX_RX_ACTIONOP_UCAST:\n-\t\tfprintf(file, \"NIX_RX_ACTIONOP_UCAST (%lu)\\n\",\n-\t\t\t(uint64_t)NIX_RX_ACTIONOP_UCAST);\n-\t\tstrncpy(index_name, \"RQ Index\", NPC_MAX_FIELD_NAME_SIZE);\n-\t\tbreak;\n-\tcase NIX_RX_ACTIONOP_UCAST_IPSEC:\n-\t\tfprintf(file, \"NIX_RX_ACTIONOP_UCAST_IPSEC (%lu)\\n\",\n-\t\t\t(uint64_t)NIX_RX_ACTIONOP_UCAST_IPSEC);\n-\t\tstrncpy(index_name, \"RQ Index:\", NPC_MAX_FIELD_NAME_SIZE);\n-\t\tbreak;\n-\tcase NIX_RX_ACTIONOP_MCAST:\n-\t\tfprintf(file, \"NIX_RX_ACTIONOP_MCAST (%lu)\\n\",\n-\t\t\t(uint64_t)NIX_RX_ACTIONOP_MCAST);\n-\t\tstrncpy(index_name, \"Multicast/mirror table index\",\n-\t\t\tNPC_MAX_FIELD_NAME_SIZE);\n-\t\tbreak;\n-\tcase NIX_RX_ACTIONOP_RSS:\n-\t\tfprintf(file, \"NIX_RX_ACTIONOP_RSS (%lu)\\n\",\n-\t\t\t(uint64_t)NIX_RX_ACTIONOP_RSS);\n-\t\tstrncpy(index_name, \"RSS Group Index\",\n-\t\t\tNPC_MAX_FIELD_NAME_SIZE);\n-\t\tbreak;\n-\tcase NIX_RX_ACTIONOP_PF_FUNC_DROP:\n-\t\tfprintf(file, \"NIX_RX_ACTIONOP_PF_FUNC_DROP (%lu)\\n\",\n-\t\t\t(uint64_t)NIX_RX_ACTIONOP_PF_FUNC_DROP);\n-\t\tbreak;\n-\tcase NIX_RX_ACTIONOP_MIRROR:\n-\t\tfprintf(file, \"NIX_RX_ACTIONOP_MIRROR (%lu)\\n\",\n-\t\t\t(uint64_t)NIX_RX_ACTIONOP_MIRROR);\n-\t\tstrncpy(index_name, \"Multicast/mirror table index\",\n-\t\t\tNPC_MAX_FIELD_NAME_SIZE);\n-\t\tbreak;\n-\t}\n-\n-\tpf_func = ((npc_action & NPC_RX_ACTION_PFFUNC_MASK) >> 4) & 0xFFFF;\n-\n-\tfprintf(file, \"\\tPF_FUNC: %#04X\\n\", pf_func);\n-\n-\tindex = ((npc_action & NPC_RX_ACTION_INDEX_MASK) >> 20) & 0xFFFFF;\n-\n-\tfprintf(file, \"\\t%s:%#05X\\n\", index_name, index);\n-\n-\tmatch_id = ((npc_action & NPC_RX_ACTION_MATCH_MASK) >> 40) & 0xFFFF;\n-\n-\tfprintf(file, \"\\tMatch Id:%#04X\\n\", match_id);\n-\n-\tflowkey_alg = ((npc_action & NPC_RX_ACTION_FLOWKEY_MASK) >> 56) & 0x1F;\n-\n-\tfprintf(file, \"\\tFlow Key Alg:%#X\\n\", flowkey_alg);\n-}\n-\n-static void\n-otx2_flow_dump_parsed_action(FILE *file, uint64_t npc_action, bool is_rx)\n-{\n-\tif (is_rx) {\n-\t\tfprintf(file, \"NPC RX Action:%#016lX\\n\", npc_action);\n-\t\totx2_flow_dump_rx_action(file, npc_action);\n-\t} else {\n-\t\tfprintf(file, \"NPC TX Action:%#016lX\\n\", npc_action);\n-\t\totx2_flow_dump_tx_action(file, npc_action);\n-\t}\n-}\n-\n-static void\n-otx2_flow_dump_rx_vtag_action(FILE *file, uint64_t vtag_action)\n-{\n-\tuint32_t type, lid, relptr;\n-\n-\tif (vtag_action & NIX_RX_VTAGACT_VTAG0_VALID_MASK) {\n-\t\trelptr = vtag_action & NIX_RX_VTAGACT_VTAG0_RELPTR_MASK;\n-\t\tlid = ((vtag_action & NIX_RX_VTAGACT_VTAG0_LID_MASK) >> 8)\n-\t\t\t& 0x7;\n-\t\ttype = ((vtag_action & NIX_RX_VTAGACT_VTAG0_TYPE_MASK) >> 12)\n-\t\t\t& 0x7;\n-\n-\t\tfprintf(file, \"\\tVTAG0:relptr:%#X\\n\", relptr);\n-\t\tfprintf(file, \"\\tlid:%#X\\n\", lid);\n-\t\tfprintf(file, \"\\ttype:%#X\\n\", type);\n-\t}\n-\n-\tif (vtag_action & NIX_RX_VTAGACT_VTAG1_VALID_MASK) {\n-\t\trelptr = ((vtag_action & NIX_RX_VTAGACT_VTAG1_RELPTR_MASK)\n-\t\t\t >> 32) & 0xFF;\n-\t\tlid = ((vtag_action & NIX_RX_VTAGACT_VTAG1_LID_MASK) >> 40)\n-\t\t\t& 0x7;\n-\t\ttype = ((vtag_action & NIX_RX_VTAGACT_VTAG1_TYPE_MASK) >> 44)\n-\t\t\t& 0x7;\n-\n-\t\tfprintf(file, \"\\tVTAG1:relptr:%#X\\n\", relptr);\n-\t\tfprintf(file, \"\\tlid:%#X\\n\", lid);\n-\t\tfprintf(file, \"\\ttype:%#X\\n\", type);\n-\t}\n-}\n-\n-static void\n-otx2_get_vtag_opname(uint32_t op, char *opname, int len)\n-{\n-\tswitch (op) {\n-\tcase 0x0:\n-\t\tstrncpy(opname, \"NOP\", len - 1);\n-\t\tbreak;\n-\tcase 0x1:\n-\t\tstrncpy(opname, \"INSERT\", len - 1);\n-\t\tbreak;\n-\tcase 0x2:\n-\t\tstrncpy(opname, \"REPLACE\", len - 1);\n-\t\tbreak;\n-\t}\n-}\n-\n-static void\n-otx2_flow_dump_tx_vtag_action(FILE *file, uint64_t vtag_action)\n-{\n-\tuint32_t relptr, lid, op, vtag_def;\n-\tchar opname[10];\n-\n-\trelptr = vtag_action & NIX_TX_VTAGACT_VTAG0_RELPTR_MASK;\n-\tlid = ((vtag_action & NIX_TX_VTAGACT_VTAG0_LID_MASK) >> 8) & 0x7;\n-\top = ((vtag_action & NIX_TX_VTAGACT_VTAG0_OP_MASK) >> 12) & 0x3;\n-\tvtag_def = ((vtag_action & NIX_TX_VTAGACT_VTAG0_DEF_MASK) >> 16)\n-\t\t & 0x3FF;\n-\n-\totx2_get_vtag_opname(op, opname, sizeof(opname));\n-\n-\tfprintf(file, \"\\tVTAG0 relptr:%#X\\n\", relptr);\n-\tfprintf(file, \"\\tlid:%#X\\n\", lid);\n-\tfprintf(file, \"\\top:%s\\n\", opname);\n-\tfprintf(file, \"\\tvtag_def:%#X\\n\", vtag_def);\n-\n-\trelptr = ((vtag_action & NIX_TX_VTAGACT_VTAG1_RELPTR_MASK) >> 32)\n-\t\t & 0xFF;\n-\tlid = ((vtag_action & NIX_TX_VTAGACT_VTAG1_LID_MASK) >> 40) & 0x7;\n-\top = ((vtag_action & NIX_TX_VTAGACT_VTAG1_OP_MASK) >> 44) & 0x3;\n-\tvtag_def = ((vtag_action & NIX_TX_VTAGACT_VTAG1_DEF_MASK) >> 48)\n-\t\t & 0x3FF;\n-\n-\totx2_get_vtag_opname(op, opname, sizeof(opname));\n-\n-\tfprintf(file, \"\\tVTAG1:relptr:%#X\\n\", relptr);\n-\tfprintf(file, \"\\tlid:%#X\\n\", lid);\n-\tfprintf(file, \"\\top:%s\\n\", opname);\n-\tfprintf(file, \"\\tvtag_def:%#X\\n\", vtag_def);\n-}\n-\n-static void\n-otx2_flow_dump_vtag_action(FILE *file, uint64_t vtag_action, bool is_rx)\n-{\n-\tif (is_rx) {\n-\t\tfprintf(file, \"NPC RX VTAG Action:%#016lX\\n\", vtag_action);\n-\t\totx2_flow_dump_rx_vtag_action(file, vtag_action);\n-\t} else {\n-\t\tfprintf(file, \"NPC TX VTAG Action:%#016lX\\n\", vtag_action);\n-\t\totx2_flow_dump_tx_vtag_action(file, vtag_action);\n-\t}\n-}\n-\n-void\n-otx2_flow_dump(FILE *file, struct otx2_eth_dev *hw, struct rte_flow *flow)\n-{\n-\tbool is_rx = 0;\n-\tint i;\n-\n-\tfprintf(file, \"MCAM Index:%d\\n\", flow->mcam_id);\n-\tfprintf(file, \"Interface :%s (%d)\\n\", intf_str[flow->nix_intf],\n-\t\tflow->nix_intf);\n-\tfprintf(file, \"Priority :%d\\n\", flow->priority);\n-\n-\tif (flow->nix_intf == NIX_INTF_RX)\n-\t\tis_rx = 1;\n-\n-\totx2_flow_dump_parsed_action(file, flow->npc_action, is_rx);\n-\totx2_flow_dump_vtag_action(file, flow->vtag_action, is_rx);\n-\tfprintf(file, \"Patterns:\\n\");\n-\totx2_flow_dump_patterns(file, hw, flow);\n-\n-\tfprintf(file, \"MCAM Raw Data :\\n\");\n-\n-\tfor (i = 0; i < OTX2_MAX_MCAM_WIDTH_DWORDS; i++) {\n-\t\tfprintf(file, \"\\tDW%d :%016lX\\n\", i, flow->mcam_data[i]);\n-\t\tfprintf(file, \"\\tDW%d_Mask:%016lX\\n\", i, flow->mcam_mask[i]);\n-\t}\n-\n-\tfprintf(file, \"\\n\");\n-}\ndiff --git a/drivers/net/octeontx2/otx2_flow_parse.c b/drivers/net/octeontx2/otx2_flow_parse.c\ndeleted file mode 100644\nindex 91267bbb81..0000000000\n--- a/drivers/net/octeontx2/otx2_flow_parse.c\n+++ /dev/null\n@@ -1,1239 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_ethdev.h\"\n-#include \"otx2_flow.h\"\n-\n-const struct rte_flow_item *\n-otx2_flow_skip_void_and_any_items(const struct rte_flow_item *pattern)\n-{\n-\twhile ((pattern->type == RTE_FLOW_ITEM_TYPE_VOID) ||\n-\t (pattern->type == RTE_FLOW_ITEM_TYPE_ANY))\n-\t\tpattern++;\n-\n-\treturn pattern;\n-}\n-\n-/*\n- * Tunnel+ESP, Tunnel+ICMP4/6, Tunnel+TCP, Tunnel+UDP,\n- * Tunnel+SCTP\n- */\n-int\n-otx2_flow_parse_lh(struct otx2_parse_state *pst)\n-{\n-\tstruct otx2_flow_item_info info;\n-\tchar hw_mask[64];\n-\tint lid, lt;\n-\tint rc;\n-\n-\tif (!pst->tunnel)\n-\t\treturn 0;\n-\n-\tinfo.hw_mask = &hw_mask;\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n-\tinfo.hw_hdr_len = 0;\n-\tlid = NPC_LID_LH;\n-\n-\tswitch (pst->pattern->type) {\n-\tcase RTE_FLOW_ITEM_TYPE_UDP:\n-\t\tlt = NPC_LT_LH_TU_UDP;\n-\t\tinfo.def_mask = &rte_flow_item_udp_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_udp);\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_TCP:\n-\t\tlt = NPC_LT_LH_TU_TCP;\n-\t\tinfo.def_mask = &rte_flow_item_tcp_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_tcp);\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_SCTP:\n-\t\tlt = NPC_LT_LH_TU_SCTP;\n-\t\tinfo.def_mask = &rte_flow_item_sctp_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_sctp);\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_ESP:\n-\t\tlt = NPC_LT_LH_TU_ESP;\n-\t\tinfo.def_mask = &rte_flow_item_esp_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_esp);\n-\t\tbreak;\n-\tdefault:\n-\t\treturn 0;\n-\t}\n-\n-\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n-\trc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);\n-\tif (rc != 0)\n-\t\treturn rc;\n-\n-\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, 0);\n-}\n-\n-/* Tunnel+IPv4, Tunnel+IPv6 */\n-int\n-otx2_flow_parse_lg(struct otx2_parse_state *pst)\n-{\n-\tstruct otx2_flow_item_info info;\n-\tchar hw_mask[64];\n-\tint lid, lt;\n-\tint rc;\n-\n-\tif (!pst->tunnel)\n-\t\treturn 0;\n-\n-\tinfo.hw_mask = &hw_mask;\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n-\tinfo.hw_hdr_len = 0;\n-\tlid = NPC_LID_LG;\n-\n-\tif (pst->pattern->type == RTE_FLOW_ITEM_TYPE_IPV4) {\n-\t\tlt = NPC_LT_LG_TU_IP;\n-\t\tinfo.def_mask = &rte_flow_item_ipv4_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_ipv4);\n-\t} else if (pst->pattern->type == RTE_FLOW_ITEM_TYPE_IPV6) {\n-\t\tlt = NPC_LT_LG_TU_IP6;\n-\t\tinfo.def_mask = &rte_flow_item_ipv6_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_ipv6);\n-\t} else {\n-\t\t/* There is no tunneled IP header */\n-\t\treturn 0;\n-\t}\n-\n-\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n-\trc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);\n-\tif (rc != 0)\n-\t\treturn rc;\n-\n-\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, 0);\n-}\n-\n-/* Tunnel+Ether */\n-int\n-otx2_flow_parse_lf(struct otx2_parse_state *pst)\n-{\n-\tconst struct rte_flow_item *pattern, *last_pattern;\n-\tstruct rte_flow_item_eth hw_mask;\n-\tstruct otx2_flow_item_info info;\n-\tint lid, lt, lflags;\n-\tint nr_vlans = 0;\n-\tint rc;\n-\n-\t/* We hit this layer if there is a tunneling protocol */\n-\tif (!pst->tunnel)\n-\t\treturn 0;\n-\n-\tif (pst->pattern->type != RTE_FLOW_ITEM_TYPE_ETH)\n-\t\treturn 0;\n-\n-\tlid = NPC_LID_LF;\n-\tlt = NPC_LT_LF_TU_ETHER;\n-\tlflags = 0;\n-\n-\tinfo.def_mask = &rte_flow_item_vlan_mask;\n-\t/* No match support for vlan tags */\n-\tinfo.hw_mask = NULL;\n-\tinfo.len = sizeof(struct rte_flow_item_vlan);\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n-\tinfo.hw_hdr_len = 0;\n-\n-\t/* Look ahead and find out any VLAN tags. These can be\n-\t * detected but no data matching is available.\n-\t */\n-\tlast_pattern = pst->pattern;\n-\tpattern = pst->pattern + 1;\n-\tpattern = otx2_flow_skip_void_and_any_items(pattern);\n-\twhile (pattern->type == RTE_FLOW_ITEM_TYPE_VLAN) {\n-\t\tnr_vlans++;\n-\t\trc = otx2_flow_parse_item_basic(pattern, &info, pst->error);\n-\t\tif (rc != 0)\n-\t\t\treturn rc;\n-\t\tlast_pattern = pattern;\n-\t\tpattern++;\n-\t\tpattern = otx2_flow_skip_void_and_any_items(pattern);\n-\t}\n-\totx2_npc_dbg(\"Nr_vlans = %d\", nr_vlans);\n-\tswitch (nr_vlans) {\n-\tcase 0:\n-\t\tbreak;\n-\tcase 1:\n-\t\tlflags = NPC_F_TU_ETHER_CTAG;\n-\t\tbreak;\n-\tcase 2:\n-\t\tlflags = NPC_F_TU_ETHER_STAG_CTAG;\n-\t\tbreak;\n-\tdefault:\n-\t\trte_flow_error_set(pst->error, ENOTSUP,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t last_pattern,\n-\t\t\t\t \"more than 2 vlans with tunneled Ethernet \"\n-\t\t\t\t \"not supported\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\tinfo.def_mask = &rte_flow_item_eth_mask;\n-\tinfo.hw_mask = &hw_mask;\n-\tinfo.len = sizeof(struct rte_flow_item_eth);\n-\tinfo.hw_hdr_len = 0;\n-\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n-\n-\trc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);\n-\tif (rc != 0)\n-\t\treturn rc;\n-\n-\tpst->pattern = last_pattern;\n-\n-\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, lflags);\n-}\n-\n-int\n-otx2_flow_parse_le(struct otx2_parse_state *pst)\n-{\n-\t/*\n-\t * We are positioned at UDP. Scan ahead and look for\n-\t * UDP encapsulated tunnel protocols. If available,\n-\t * parse them. In that case handle this:\n-\t *\t- RTE spec assumes we point to tunnel header.\n-\t *\t- NPC parser provides offset from UDP header.\n-\t */\n-\n-\t/*\n-\t * Note: Add support to GENEVE, VXLAN_GPE when we\n-\t * upgrade DPDK\n-\t *\n-\t * Note: Better to split flags into two nibbles:\n-\t *\t- Higher nibble can have flags\n-\t *\t- Lower nibble to further enumerate protocols\n-\t *\t and have flags based extraction\n-\t */\n-\tconst struct rte_flow_item *pattern = pst->pattern;\n-\tstruct otx2_flow_item_info info;\n-\tint lid, lt, lflags;\n-\tchar hw_mask[64];\n-\tint rc;\n-\n-\tif (pst->tunnel)\n-\t\treturn 0;\n-\n-\tif (pst->pattern->type == RTE_FLOW_ITEM_TYPE_MPLS)\n-\t\treturn otx2_flow_parse_mpls(pst, NPC_LID_LE);\n-\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n-\tinfo.hw_mask = NULL;\n-\tinfo.def_mask = NULL;\n-\tinfo.len = 0;\n-\tinfo.hw_hdr_len = 0;\n-\tlid = NPC_LID_LE;\n-\tlflags = 0;\n-\n-\t/* Ensure we are not matching anything in UDP */\n-\trc = otx2_flow_parse_item_basic(pattern, &info, pst->error);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tinfo.hw_mask = &hw_mask;\n-\tpattern = otx2_flow_skip_void_and_any_items(pattern);\n-\totx2_npc_dbg(\"Pattern->type = %d\", pattern->type);\n-\tswitch (pattern->type) {\n-\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n-\t\tlflags = NPC_F_UDP_VXLAN;\n-\t\tinfo.def_mask = &rte_flow_item_vxlan_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_vxlan);\n-\t\tlt = NPC_LT_LE_VXLAN;\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_ESP:\n-\t\tlt = NPC_LT_LE_ESP;\n-\t\tinfo.def_mask = &rte_flow_item_esp_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_esp);\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_GTPC:\n-\t\tlflags = NPC_F_UDP_GTP_GTPC;\n-\t\tinfo.def_mask = &rte_flow_item_gtp_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_gtp);\n-\t\tlt = NPC_LT_LE_GTPC;\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_GTPU:\n-\t\tlflags = NPC_F_UDP_GTP_GTPU_G_PDU;\n-\t\tinfo.def_mask = &rte_flow_item_gtp_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_gtp);\n-\t\tlt = NPC_LT_LE_GTPU;\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_GENEVE:\n-\t\tlflags = NPC_F_UDP_GENEVE;\n-\t\tinfo.def_mask = &rte_flow_item_geneve_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_geneve);\n-\t\tlt = NPC_LT_LE_GENEVE;\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_VXLAN_GPE:\n-\t\tlflags = NPC_F_UDP_VXLANGPE;\n-\t\tinfo.def_mask = &rte_flow_item_vxlan_gpe_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_vxlan_gpe);\n-\t\tlt = NPC_LT_LE_VXLANGPE;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn 0;\n-\t}\n-\n-\tpst->tunnel = 1;\n-\n-\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n-\trc = otx2_flow_parse_item_basic(pattern, &info, pst->error);\n-\tif (rc != 0)\n-\t\treturn rc;\n-\n-\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, lflags);\n-}\n-\n-static int\n-flow_parse_mpls_label_stack(struct otx2_parse_state *pst, int *flag)\n-{\n-\tint nr_labels = 0;\n-\tconst struct rte_flow_item *pattern = pst->pattern;\n-\tstruct otx2_flow_item_info info;\n-\tint rc;\n-\tuint8_t flag_list[] = {0, NPC_F_MPLS_2_LABELS,\n-\t\tNPC_F_MPLS_3_LABELS, NPC_F_MPLS_4_LABELS};\n-\n-\t/*\n-\t * pst->pattern points to first MPLS label. We only check\n-\t * that subsequent labels do not have anything to match.\n-\t */\n-\tinfo.def_mask = &rte_flow_item_mpls_mask;\n-\tinfo.hw_mask = NULL;\n-\tinfo.len = sizeof(struct rte_flow_item_mpls);\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n-\tinfo.hw_hdr_len = 0;\n-\n-\twhile (pattern->type == RTE_FLOW_ITEM_TYPE_MPLS) {\n-\t\tnr_labels++;\n-\n-\t\t/* Basic validation of 2nd/3rd/4th mpls item */\n-\t\tif (nr_labels > 1) {\n-\t\t\trc = otx2_flow_parse_item_basic(pattern, &info,\n-\t\t\t\t\t\t\tpst->error);\n-\t\t\tif (rc != 0)\n-\t\t\t\treturn rc;\n-\t\t}\n-\t\tpst->last_pattern = pattern;\n-\t\tpattern++;\n-\t\tpattern = otx2_flow_skip_void_and_any_items(pattern);\n-\t}\n-\n-\tif (nr_labels > 4) {\n-\t\trte_flow_error_set(pst->error, ENOTSUP,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t pst->last_pattern,\n-\t\t\t\t \"more than 4 mpls labels not supported\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\t*flag = flag_list[nr_labels - 1];\n-\treturn 0;\n-}\n-\n-int\n-otx2_flow_parse_mpls(struct otx2_parse_state *pst, int lid)\n-{\n-\t/* Find number of MPLS labels */\n-\tstruct rte_flow_item_mpls hw_mask;\n-\tstruct otx2_flow_item_info info;\n-\tint lt, lflags;\n-\tint rc;\n-\n-\tlflags = 0;\n-\n-\tif (lid == NPC_LID_LC)\n-\t\tlt = NPC_LT_LC_MPLS;\n-\telse if (lid == NPC_LID_LD)\n-\t\tlt = NPC_LT_LD_TU_MPLS_IN_IP;\n-\telse\n-\t\tlt = NPC_LT_LE_TU_MPLS_IN_UDP;\n-\n-\t/* Prepare for parsing the first item */\n-\tinfo.def_mask = &rte_flow_item_mpls_mask;\n-\tinfo.hw_mask = &hw_mask;\n-\tinfo.len = sizeof(struct rte_flow_item_mpls);\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n-\tinfo.hw_hdr_len = 0;\n-\n-\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n-\trc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);\n-\tif (rc != 0)\n-\t\treturn rc;\n-\n-\t/*\n-\t * Parse for more labels.\n-\t * This sets lflags and pst->last_pattern correctly.\n-\t */\n-\trc = flow_parse_mpls_label_stack(pst, &lflags);\n-\tif (rc != 0)\n-\t\treturn rc;\n-\n-\tpst->tunnel = 1;\n-\tpst->pattern = pst->last_pattern;\n-\n-\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, lflags);\n-}\n-\n-/*\n- * ICMP, ICMP6, UDP, TCP, SCTP, VXLAN, GRE, NVGRE,\n- * GTP, GTPC, GTPU, ESP\n- *\n- * Note: UDP tunnel protocols are identified by flags.\n- * LPTR for these protocol still points to UDP\n- * header. Need flag based extraction to support\n- * this.\n- */\n-int\n-otx2_flow_parse_ld(struct otx2_parse_state *pst)\n-{\n-\tchar hw_mask[NPC_MAX_EXTRACT_DATA_LEN];\n-\tuint32_t gre_key_mask = 0xffffffff;\n-\tstruct otx2_flow_item_info info;\n-\tint lid, lt, lflags;\n-\tint rc;\n-\n-\tif (pst->tunnel) {\n-\t\t/* We have already parsed MPLS or IPv4/v6 followed\n-\t\t * by MPLS or IPv4/v6. Subsequent TCP/UDP etc\n-\t\t * would be parsed as tunneled versions. Skip\n-\t\t * this layer, except for tunneled MPLS. If LC is\n-\t\t * MPLS, we have anyway skipped all stacked MPLS\n-\t\t * labels.\n-\t\t */\n-\t\tif (pst->pattern->type == RTE_FLOW_ITEM_TYPE_MPLS)\n-\t\t\treturn otx2_flow_parse_mpls(pst, NPC_LID_LD);\n-\t\treturn 0;\n-\t}\n-\tinfo.hw_mask = &hw_mask;\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n-\tinfo.def_mask = NULL;\n-\tinfo.len = 0;\n-\tinfo.hw_hdr_len = 0;\n-\n-\tlid = NPC_LID_LD;\n-\tlflags = 0;\n-\n-\totx2_npc_dbg(\"Pst->pattern->type = %d\", pst->pattern->type);\n-\tswitch (pst->pattern->type) {\n-\tcase RTE_FLOW_ITEM_TYPE_ICMP:\n-\t\tif (pst->lt[NPC_LID_LC] == NPC_LT_LC_IP6)\n-\t\t\tlt = NPC_LT_LD_ICMP6;\n-\t\telse\n-\t\t\tlt = NPC_LT_LD_ICMP;\n-\t\tinfo.def_mask = &rte_flow_item_icmp_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_icmp);\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_UDP:\n-\t\tlt = NPC_LT_LD_UDP;\n-\t\tinfo.def_mask = &rte_flow_item_udp_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_udp);\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_TCP:\n-\t\tlt = NPC_LT_LD_TCP;\n-\t\tinfo.def_mask = &rte_flow_item_tcp_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_tcp);\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_SCTP:\n-\t\tlt = NPC_LT_LD_SCTP;\n-\t\tinfo.def_mask = &rte_flow_item_sctp_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_sctp);\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_GRE:\n-\t\tlt = NPC_LT_LD_GRE;\n-\t\tinfo.def_mask = &rte_flow_item_gre_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_gre);\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_GRE_KEY:\n-\t\tlt = NPC_LT_LD_GRE;\n-\t\tinfo.def_mask = &gre_key_mask;\n-\t\tinfo.len = sizeof(gre_key_mask);\n-\t\tinfo.hw_hdr_len = 4;\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_NVGRE:\n-\t\tlt = NPC_LT_LD_NVGRE;\n-\t\tlflags = NPC_F_GRE_NVGRE;\n-\t\tinfo.def_mask = &rte_flow_item_nvgre_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_nvgre);\n-\t\t/* Further IP/Ethernet are parsed as tunneled */\n-\t\tpst->tunnel = 1;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn 0;\n-\t}\n-\n-\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n-\trc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);\n-\tif (rc != 0)\n-\t\treturn rc;\n-\n-\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, lflags);\n-}\n-\n-static inline void\n-flow_check_lc_ip_tunnel(struct otx2_parse_state *pst)\n-{\n-\tconst struct rte_flow_item *pattern = pst->pattern + 1;\n-\n-\tpattern = otx2_flow_skip_void_and_any_items(pattern);\n-\tif (pattern->type == RTE_FLOW_ITEM_TYPE_MPLS ||\n-\t pattern->type == RTE_FLOW_ITEM_TYPE_IPV4 ||\n-\t pattern->type == RTE_FLOW_ITEM_TYPE_IPV6)\n-\t\tpst->tunnel = 1;\n-}\n-\n-static int\n-otx2_flow_raw_item_prepare(const struct rte_flow_item_raw *raw_spec,\n-\t\t\t const struct rte_flow_item_raw *raw_mask,\n-\t\t\t struct otx2_flow_item_info *info,\n-\t\t\t uint8_t *spec_buf, uint8_t *mask_buf)\n-{\n-\tuint32_t custom_hdr_size = 0;\n-\n-\tmemset(spec_buf, 0, NPC_MAX_RAW_ITEM_LEN);\n-\tmemset(mask_buf, 0, NPC_MAX_RAW_ITEM_LEN);\n-\tcustom_hdr_size = raw_spec->offset + raw_spec->length;\n-\n-\tmemcpy(spec_buf + raw_spec->offset, raw_spec->pattern,\n-\t raw_spec->length);\n-\n-\tif (raw_mask->pattern) {\n-\t\tmemcpy(mask_buf + raw_spec->offset, raw_mask->pattern,\n-\t\t raw_spec->length);\n-\t} else {\n-\t\tmemset(mask_buf + raw_spec->offset, 0xFF, raw_spec->length);\n-\t}\n-\n-\tinfo->len = custom_hdr_size;\n-\tinfo->spec = spec_buf;\n-\tinfo->mask = mask_buf;\n-\n-\treturn 0;\n-}\n-\n-/* Outer IPv4, Outer IPv6, MPLS, ARP */\n-int\n-otx2_flow_parse_lc(struct otx2_parse_state *pst)\n-{\n-\tuint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];\n-\tuint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];\n-\tuint8_t hw_mask[NPC_MAX_EXTRACT_DATA_LEN];\n-\tconst struct rte_flow_item_raw *raw_spec;\n-\tstruct otx2_flow_item_info info;\n-\tint lid, lt, len;\n-\tint rc;\n-\n-\tif (pst->pattern->type == RTE_FLOW_ITEM_TYPE_MPLS)\n-\t\treturn otx2_flow_parse_mpls(pst, NPC_LID_LC);\n-\n-\tinfo.hw_mask = &hw_mask;\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n-\tinfo.hw_hdr_len = 0;\n-\tlid = NPC_LID_LC;\n-\n-\tswitch (pst->pattern->type) {\n-\tcase RTE_FLOW_ITEM_TYPE_IPV4:\n-\t\tlt = NPC_LT_LC_IP;\n-\t\tinfo.def_mask = &rte_flow_item_ipv4_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_ipv4);\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_IPV6:\n-\t\tlid = NPC_LID_LC;\n-\t\tlt = NPC_LT_LC_IP6;\n-\t\tinfo.def_mask = &rte_flow_item_ipv6_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_ipv6);\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4:\n-\t\tlt = NPC_LT_LC_ARP;\n-\t\tinfo.def_mask = &rte_flow_item_arp_eth_ipv4_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_arp_eth_ipv4);\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_IPV6_EXT:\n-\t\tlid = NPC_LID_LC;\n-\t\tlt = NPC_LT_LC_IP6_EXT;\n-\t\tinfo.def_mask = &rte_flow_item_ipv6_ext_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_ipv6_ext);\n-\t\tinfo.hw_hdr_len = 40;\n-\t\tbreak;\n-\tcase RTE_FLOW_ITEM_TYPE_RAW:\n-\t\traw_spec = pst->pattern->spec;\n-\t\tif (!raw_spec->relative)\n-\t\t\treturn 0;\n-\n-\t\tlen = raw_spec->length + raw_spec->offset;\n-\t\tif (len > NPC_MAX_RAW_ITEM_LEN) {\n-\t\t\trte_flow_error_set(pst->error, EINVAL,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, NULL,\n-\t\t\t\t\t \"Spec length too big\");\n-\t\t\treturn -rte_errno;\n-\t\t}\n-\n-\t\totx2_flow_raw_item_prepare((const struct rte_flow_item_raw *)\n-\t\t\t\t\t pst->pattern->spec,\n-\t\t\t\t\t (const struct rte_flow_item_raw *)\n-\t\t\t\t\t pst->pattern->mask, &info,\n-\t\t\t\t\t raw_spec_buf, raw_mask_buf);\n-\n-\t\tlid = NPC_LID_LC;\n-\t\tlt = NPC_LT_LC_NGIO;\n-\t\tinfo.hw_mask = &hw_mask;\n-\t\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n-\t\tbreak;\n-\tdefault:\n-\t\t/* No match at this layer */\n-\t\treturn 0;\n-\t}\n-\n-\t/* Identify if IP tunnels MPLS or IPv4/v6 */\n-\tflow_check_lc_ip_tunnel(pst);\n-\n-\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n-\trc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);\n-\tif (rc != 0)\n-\t\treturn rc;\n-\n-\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, 0);\n-}\n-\n-/* VLAN, ETAG */\n-int\n-otx2_flow_parse_lb(struct otx2_parse_state *pst)\n-{\n-\tconst struct rte_flow_item *pattern = pst->pattern;\n-\tuint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];\n-\tuint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];\n-\tconst struct rte_flow_item *last_pattern;\n-\tconst struct rte_flow_item_raw *raw_spec;\n-\tchar hw_mask[NPC_MAX_EXTRACT_DATA_LEN];\n-\tstruct otx2_flow_item_info info;\n-\tint lid, lt, lflags, len;\n-\tint nr_vlans = 0;\n-\tint rc;\n-\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n-\tinfo.hw_hdr_len = NPC_TPID_LENGTH;\n-\n-\tlid = NPC_LID_LB;\n-\tlflags = 0;\n-\tlast_pattern = pattern;\n-\n-\tif (pst->pattern->type == RTE_FLOW_ITEM_TYPE_VLAN) {\n-\t\t/* RTE vlan is either 802.1q or 802.1ad,\n-\t\t * this maps to either CTAG/STAG. We need to decide\n-\t\t * based on number of VLANS present. Matching is\n-\t\t * supported on first tag only.\n-\t\t */\n-\t\tinfo.def_mask = &rte_flow_item_vlan_mask;\n-\t\tinfo.hw_mask = NULL;\n-\t\tinfo.len = sizeof(struct rte_flow_item_vlan);\n-\n-\t\tpattern = pst->pattern;\n-\t\twhile (pattern->type == RTE_FLOW_ITEM_TYPE_VLAN) {\n-\t\t\tnr_vlans++;\n-\n-\t\t\t/* Basic validation of 2nd/3rd vlan item */\n-\t\t\tif (nr_vlans > 1) {\n-\t\t\t\totx2_npc_dbg(\"Vlans = %d\", nr_vlans);\n-\t\t\t\trc = otx2_flow_parse_item_basic(pattern, &info,\n-\t\t\t\t\t\t\t\tpst->error);\n-\t\t\t\tif (rc != 0)\n-\t\t\t\t\treturn rc;\n-\t\t\t}\n-\t\t\tlast_pattern = pattern;\n-\t\t\tpattern++;\n-\t\t\tpattern = otx2_flow_skip_void_and_any_items(pattern);\n-\t\t}\n-\n-\t\tswitch (nr_vlans) {\n-\t\tcase 1:\n-\t\t\tlt = NPC_LT_LB_CTAG;\n-\t\t\tbreak;\n-\t\tcase 2:\n-\t\t\tlt = NPC_LT_LB_STAG_QINQ;\n-\t\t\tlflags = NPC_F_STAG_CTAG;\n-\t\t\tbreak;\n-\t\tcase 3:\n-\t\t\tlt = NPC_LT_LB_STAG_QINQ;\n-\t\t\tlflags = NPC_F_STAG_STAG_CTAG;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\trte_flow_error_set(pst->error, ENOTSUP,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t\t last_pattern,\n-\t\t\t\t\t \"more than 3 vlans not supported\");\n-\t\t\treturn -rte_errno;\n-\t\t}\n-\t} else if (pst->pattern->type == RTE_FLOW_ITEM_TYPE_E_TAG) {\n-\t\t/* we can support ETAG and match a subsequent CTAG\n-\t\t * without any matching support.\n-\t\t */\n-\t\tlt = NPC_LT_LB_ETAG;\n-\t\tlflags = 0;\n-\n-\t\tlast_pattern = pst->pattern;\n-\t\tpattern = otx2_flow_skip_void_and_any_items(pst->pattern + 1);\n-\t\tif (pattern->type == RTE_FLOW_ITEM_TYPE_VLAN) {\n-\t\t\tinfo.def_mask = &rte_flow_item_vlan_mask;\n-\t\t\t/* set supported mask to NULL for vlan tag */\n-\t\t\tinfo.hw_mask = NULL;\n-\t\t\tinfo.len = sizeof(struct rte_flow_item_vlan);\n-\t\t\trc = otx2_flow_parse_item_basic(pattern, &info,\n-\t\t\t\t\t\t\tpst->error);\n-\t\t\tif (rc != 0)\n-\t\t\t\treturn rc;\n-\n-\t\t\tlflags = NPC_F_ETAG_CTAG;\n-\t\t\tlast_pattern = pattern;\n-\t\t}\n-\n-\t\tinfo.def_mask = &rte_flow_item_e_tag_mask;\n-\t\tinfo.len = sizeof(struct rte_flow_item_e_tag);\n-\t} else if (pst->pattern->type == RTE_FLOW_ITEM_TYPE_RAW) {\n-\t\traw_spec = pst->pattern->spec;\n-\t\tif (raw_spec->relative)\n-\t\t\treturn 0;\n-\t\tlen = raw_spec->length + raw_spec->offset;\n-\t\tif (len > NPC_MAX_RAW_ITEM_LEN) {\n-\t\t\trte_flow_error_set(pst->error, EINVAL,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, NULL,\n-\t\t\t\t\t \"Spec length too big\");\n-\t\t\treturn -rte_errno;\n-\t\t}\n-\n-\t\tif (pst->npc->switch_header_type ==\n-\t\t OTX2_PRIV_FLAGS_VLAN_EXDSA) {\n-\t\t\tlt = NPC_LT_LB_VLAN_EXDSA;\n-\t\t} else if (pst->npc->switch_header_type ==\n-\t\t\t OTX2_PRIV_FLAGS_EXDSA) {\n-\t\t\tlt = NPC_LT_LB_EXDSA;\n-\t\t} else {\n-\t\t\trte_flow_error_set(pst->error, ENOTSUP,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, NULL,\n-\t\t\t\t\t \"exdsa or vlan_exdsa not enabled on\"\n-\t\t\t\t\t \" port\");\n-\t\t\treturn -rte_errno;\n-\t\t}\n-\n-\t\totx2_flow_raw_item_prepare((const struct rte_flow_item_raw *)\n-\t\t\t\t\t pst->pattern->spec,\n-\t\t\t\t\t (const struct rte_flow_item_raw *)\n-\t\t\t\t\t pst->pattern->mask, &info,\n-\t\t\t\t\t raw_spec_buf, raw_mask_buf);\n-\n-\t\tinfo.hw_hdr_len = 0;\n-\t} else {\n-\t\treturn 0;\n-\t}\n-\n-\tinfo.hw_mask = &hw_mask;\n-\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n-\n-\trc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);\n-\tif (rc != 0)\n-\t\treturn rc;\n-\n-\t/* Point pattern to last item consumed */\n-\tpst->pattern = last_pattern;\n-\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, lflags);\n-}\n-\n-\n-int\n-otx2_flow_parse_la(struct otx2_parse_state *pst)\n-{\n-\tstruct rte_flow_item_eth hw_mask;\n-\tstruct otx2_flow_item_info info;\n-\tint lid, lt;\n-\tint rc;\n-\n-\t/* Identify the pattern type into lid, lt */\n-\tif (pst->pattern->type != RTE_FLOW_ITEM_TYPE_ETH)\n-\t\treturn 0;\n-\n-\tlid = NPC_LID_LA;\n-\tlt = NPC_LT_LA_ETHER;\n-\tinfo.hw_hdr_len = 0;\n-\n-\tif (pst->flow->nix_intf == NIX_INTF_TX) {\n-\t\tlt = NPC_LT_LA_IH_NIX_ETHER;\n-\t\tinfo.hw_hdr_len = NPC_IH_LENGTH;\n-\t\tif (pst->npc->switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {\n-\t\t\tlt = NPC_LT_LA_IH_NIX_HIGIG2_ETHER;\n-\t\t\tinfo.hw_hdr_len += NPC_HIGIG2_LENGTH;\n-\t\t}\n-\t} else {\n-\t\tif (pst->npc->switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {\n-\t\t\tlt = NPC_LT_LA_HIGIG2_ETHER;\n-\t\t\tinfo.hw_hdr_len = NPC_HIGIG2_LENGTH;\n-\t\t}\n-\t}\n-\n-\t/* Prepare for parsing the item */\n-\tinfo.def_mask = &rte_flow_item_eth_mask;\n-\tinfo.hw_mask = &hw_mask;\n-\tinfo.len = sizeof(struct rte_flow_item_eth);\n-\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n-\n-\t/* Basic validation of item parameters */\n-\trc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\t/* Update pst if not validate only? clash check? */\n-\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, 0);\n-}\n-\n-int\n-otx2_flow_parse_higig2_hdr(struct otx2_parse_state *pst)\n-{\n-\tstruct rte_flow_item_higig2_hdr hw_mask;\n-\tstruct otx2_flow_item_info info;\n-\tint lid, lt;\n-\tint rc;\n-\n-\t/* Identify the pattern type into lid, lt */\n-\tif (pst->pattern->type != RTE_FLOW_ITEM_TYPE_HIGIG2)\n-\t\treturn 0;\n-\n-\tlid = NPC_LID_LA;\n-\tlt = NPC_LT_LA_HIGIG2_ETHER;\n-\tinfo.hw_hdr_len = 0;\n-\n-\tif (pst->flow->nix_intf == NIX_INTF_TX) {\n-\t\tlt = NPC_LT_LA_IH_NIX_HIGIG2_ETHER;\n-\t\tinfo.hw_hdr_len = NPC_IH_LENGTH;\n-\t}\n-\n-\t/* Prepare for parsing the item */\n-\tinfo.def_mask = &rte_flow_item_higig2_hdr_mask;\n-\tinfo.hw_mask = &hw_mask;\n-\tinfo.len = sizeof(struct rte_flow_item_higig2_hdr);\n-\totx2_flow_get_hw_supp_mask(pst, &info, lid, lt);\n-\tinfo.spec = NULL;\n-\tinfo.mask = NULL;\n-\n-\t/* Basic validation of item parameters */\n-\trc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\t/* Update pst if not validate only? clash check? */\n-\treturn otx2_flow_update_parse_state(pst, &info, lid, lt, 0);\n-}\n-\n-static int\n-parse_rss_action(struct rte_eth_dev *dev,\n-\t\t const struct rte_flow_attr *attr,\n-\t\t const struct rte_flow_action *act,\n-\t\t struct rte_flow_error *error)\n-{\n-\tstruct otx2_eth_dev *hw = dev->data->dev_private;\n-\tstruct otx2_rss_info *rss_info = &hw->rss_info;\n-\tconst struct rte_flow_action_rss *rss;\n-\tuint32_t i;\n-\n-\trss = (const struct rte_flow_action_rss *)act->conf;\n-\n-\t/* Not supported */\n-\tif (attr->egress) {\n-\t\treturn rte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,\n-\t\t\t\t\t attr, \"No support of RSS in egress\");\n-\t}\n-\n-\tif (dev->data->dev_conf.rxmode.mq_mode != RTE_ETH_MQ_RX_RSS)\n-\t\treturn rte_flow_error_set(error, ENOTSUP,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION,\n-\t\t\t\t\t act, \"multi-queue mode is disabled\");\n-\n-\t/* Parse RSS related parameters from configuration */\n-\tif (!rss || !rss->queue_num)\n-\t\treturn rte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION,\n-\t\t\t\t\t act, \"no valid queues\");\n-\n-\tif (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT)\n-\t\treturn rte_flow_error_set(error, ENOTSUP,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, act,\n-\t\t\t\t\t \"non-default RSS hash functions\"\n-\t\t\t\t\t \" are not supported\");\n-\n-\tif (rss->key_len && rss->key_len > RTE_DIM(rss_info->key))\n-\t\treturn rte_flow_error_set(error, ENOTSUP,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION, act,\n-\t\t\t\t\t \"RSS hash key too large\");\n-\n-\tif (rss->queue_num > rss_info->rss_size)\n-\t\treturn rte_flow_error_set\n-\t\t\t(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,\n-\t\t\t \"too many queues for RSS context\");\n-\n-\tfor (i = 0; i < rss->queue_num; i++) {\n-\t\tif (rss->queue[i] >= dev->data->nb_rx_queues)\n-\t\t\treturn rte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ACTION,\n-\t\t\t\t\t\t act,\n-\t\t\t\t\t\t \"queue id > max number\"\n-\t\t\t\t\t\t \" of queues\");\n-\t}\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_flow_parse_actions(struct rte_eth_dev *dev,\n-\t\t\tconst struct rte_flow_attr *attr,\n-\t\t\tconst struct rte_flow_action actions[],\n-\t\t\tstruct rte_flow_error *error,\n-\t\t\tstruct rte_flow *flow)\n-{\n-\tstruct otx2_eth_dev *hw = dev->data->dev_private;\n-\tstruct otx2_npc_flow_info *npc = &hw->npc_flow;\n-\tconst struct rte_flow_action_mark *act_mark;\n-\tconst struct rte_flow_action_queue *act_q;\n-\tconst struct rte_flow_action_vf *vf_act;\n-\tuint16_t pf_func, vf_id, port_id, pf_id;\n-\tchar if_name[RTE_ETH_NAME_MAX_LEN];\n-\tbool vlan_insert_action = false;\n-\tstruct rte_eth_dev *eth_dev;\n-\tconst char *errmsg = NULL;\n-\tint sel_act, req_act = 0;\n-\tint errcode = 0;\n-\tint mark = 0;\n-\tint rq = 0;\n-\n-\t/* Initialize actions */\n-\tflow->ctr_id = NPC_COUNTER_NONE;\n-\tpf_func = otx2_pfvf_func(hw->pf, hw->vf);\n-\n-\tfor (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {\n-\t\totx2_npc_dbg(\"Action type = %d\", actions->type);\n-\n-\t\tswitch (actions->type) {\n-\t\tcase RTE_FLOW_ACTION_TYPE_VOID:\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ACTION_TYPE_MARK:\n-\t\t\tact_mark =\n-\t\t\t (const struct rte_flow_action_mark *)actions->conf;\n-\n-\t\t\t/* We have only 16 bits. Use highest val for flag */\n-\t\t\tif (act_mark->id > (OTX2_FLOW_FLAG_VAL - 2)) {\n-\t\t\t\terrmsg = \"mark value must be < 0xfffe\";\n-\t\t\t\terrcode = ENOTSUP;\n-\t\t\t\tgoto err_exit;\n-\t\t\t}\n-\t\t\tmark = act_mark->id + 1;\n-\t\t\treq_act |= OTX2_FLOW_ACT_MARK;\n-\t\t\trte_atomic32_inc(&npc->mark_actions);\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ACTION_TYPE_FLAG:\n-\t\t\tmark = OTX2_FLOW_FLAG_VAL;\n-\t\t\treq_act |= OTX2_FLOW_ACT_FLAG;\n-\t\t\trte_atomic32_inc(&npc->mark_actions);\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ACTION_TYPE_COUNT:\n-\t\t\t/* Indicates, need a counter */\n-\t\t\tflow->ctr_id = 1;\n-\t\t\treq_act |= OTX2_FLOW_ACT_COUNT;\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ACTION_TYPE_DROP:\n-\t\t\treq_act |= OTX2_FLOW_ACT_DROP;\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ACTION_TYPE_PF:\n-\t\t\treq_act |= OTX2_FLOW_ACT_PF;\n-\t\t\tpf_func &= (0xfc00);\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ACTION_TYPE_VF:\n-\t\t\tvf_act = (const struct rte_flow_action_vf *)\n-\t\t\t\tactions->conf;\n-\t\t\treq_act |= OTX2_FLOW_ACT_VF;\n-\t\t\tif (vf_act->original == 0) {\n-\t\t\t\tvf_id = vf_act->id & RVU_PFVF_FUNC_MASK;\n-\t\t\t\tif (vf_id >= hw->maxvf) {\n-\t\t\t\t\terrmsg = \"invalid vf specified\";\n-\t\t\t\t\terrcode = EINVAL;\n-\t\t\t\t\tgoto err_exit;\n-\t\t\t\t}\n-\t\t\t\tpf_func &= (0xfc00);\n-\t\t\t\tpf_func = (pf_func | (vf_id + 1));\n-\t\t\t}\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ACTION_TYPE_PORT_ID:\n-\t\tcase RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR:\n-\t\t\tif (actions->type == RTE_FLOW_ACTION_TYPE_PORT_ID) {\n-\t\t\t\tconst struct rte_flow_action_port_id *port_act;\n-\n-\t\t\t\tport_act = actions->conf;\n-\t\t\t\tport_id = port_act->id;\n-\t\t\t} else {\n-\t\t\t\tconst struct rte_flow_action_ethdev *ethdev_act;\n-\n-\t\t\t\tethdev_act = actions->conf;\n-\t\t\t\tport_id = ethdev_act->port_id;\n-\t\t\t}\n-\t\t\tif (rte_eth_dev_get_name_by_port(port_id, if_name)) {\n-\t\t\t\terrmsg = \"Name not found for output port id\";\n-\t\t\t\terrcode = EINVAL;\n-\t\t\t\tgoto err_exit;\n-\t\t\t}\n-\t\t\teth_dev = rte_eth_dev_allocated(if_name);\n-\t\t\tif (!eth_dev) {\n-\t\t\t\terrmsg = \"eth_dev not found for output port id\";\n-\t\t\t\terrcode = EINVAL;\n-\t\t\t\tgoto err_exit;\n-\t\t\t}\n-\t\t\tif (!otx2_ethdev_is_same_driver(eth_dev)) {\n-\t\t\t\terrmsg = \"Output port id unsupported type\";\n-\t\t\t\terrcode = ENOTSUP;\n-\t\t\t\tgoto err_exit;\n-\t\t\t}\n-\t\t\tif (!otx2_dev_is_vf(otx2_eth_pmd_priv(eth_dev))) {\n-\t\t\t\terrmsg = \"Output port should be VF\";\n-\t\t\t\terrcode = ENOTSUP;\n-\t\t\t\tgoto err_exit;\n-\t\t\t}\n-\t\t\tvf_id = otx2_eth_pmd_priv(eth_dev)->vf;\n-\t\t\tif (vf_id >= hw->maxvf) {\n-\t\t\t\terrmsg = \"Invalid vf for output port\";\n-\t\t\t\terrcode = EINVAL;\n-\t\t\t\tgoto err_exit;\n-\t\t\t}\n-\t\t\tpf_id = otx2_eth_pmd_priv(eth_dev)->pf;\n-\t\t\tif (pf_id != hw->pf) {\n-\t\t\t\terrmsg = \"Output port unsupported PF\";\n-\t\t\t\terrcode = ENOTSUP;\n-\t\t\t\tgoto err_exit;\n-\t\t\t}\n-\t\t\tpf_func &= (0xfc00);\n-\t\t\tpf_func = (pf_func | (vf_id + 1));\n-\t\t\treq_act |= OTX2_FLOW_ACT_VF;\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ACTION_TYPE_QUEUE:\n-\t\t\t/* Applicable only to ingress flow */\n-\t\t\tact_q = (const struct rte_flow_action_queue *)\n-\t\t\t\tactions->conf;\n-\t\t\trq = act_q->index;\n-\t\t\tif (rq >= dev->data->nb_rx_queues) {\n-\t\t\t\terrmsg = \"invalid queue index\";\n-\t\t\t\terrcode = EINVAL;\n-\t\t\t\tgoto err_exit;\n-\t\t\t}\n-\t\t\treq_act |= OTX2_FLOW_ACT_QUEUE;\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ACTION_TYPE_RSS:\n-\t\t\terrcode = parse_rss_action(dev,\tattr, actions, error);\n-\t\t\tif (errcode)\n-\t\t\t\treturn -rte_errno;\n-\n-\t\t\treq_act |= OTX2_FLOW_ACT_RSS;\n-\t\t\tbreak;\n-\n-\t\tcase RTE_FLOW_ACTION_TYPE_SECURITY:\n-\t\t\t/* Assumes user has already configured security\n-\t\t\t * session for this flow. Associated conf is\n-\t\t\t * opaque. When RTE security is implemented for otx2,\n-\t\t\t * we need to verify that for specified security\n-\t\t\t * session:\n-\t\t\t * action_type ==\n-\t\t\t * RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL &&\n-\t\t\t * session_protocol ==\n-\t\t\t * RTE_SECURITY_PROTOCOL_IPSEC\n-\t\t\t *\n-\t\t\t * RSS is not supported with inline ipsec. Get the\n-\t\t\t * rq from associated conf, or make\n-\t\t\t * RTE_FLOW_ACTION_TYPE_QUEUE compulsory with this\n-\t\t\t * action.\n-\t\t\t * Currently, rq = 0 is assumed.\n-\t\t\t */\n-\t\t\treq_act |= OTX2_FLOW_ACT_SEC;\n-\t\t\trq = 0;\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:\n-\t\t\treq_act |= OTX2_FLOW_ACT_VLAN_INSERT;\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:\n-\t\t\treq_act |= OTX2_FLOW_ACT_VLAN_STRIP;\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:\n-\t\t\treq_act |= OTX2_FLOW_ACT_VLAN_ETHTYPE_INSERT;\n-\t\t\tbreak;\n-\t\tcase RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:\n-\t\t\treq_act |= OTX2_FLOW_ACT_VLAN_PCP_INSERT;\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\terrmsg = \"Unsupported action specified\";\n-\t\t\terrcode = ENOTSUP;\n-\t\t\tgoto err_exit;\n-\t\t}\n-\t}\n-\n-\tif (req_act &\n-\t (OTX2_FLOW_ACT_VLAN_INSERT | OTX2_FLOW_ACT_VLAN_ETHTYPE_INSERT |\n-\t OTX2_FLOW_ACT_VLAN_PCP_INSERT))\n-\t\tvlan_insert_action = true;\n-\n-\tif ((req_act &\n-\t (OTX2_FLOW_ACT_VLAN_INSERT | OTX2_FLOW_ACT_VLAN_ETHTYPE_INSERT |\n-\t OTX2_FLOW_ACT_VLAN_PCP_INSERT)) ==\n-\t OTX2_FLOW_ACT_VLAN_PCP_INSERT) {\n-\t\terrmsg = \" PCP insert action can't be supported alone\";\n-\t\terrcode = ENOTSUP;\n-\t\tgoto err_exit;\n-\t}\n-\n-\t/* Both STRIP and INSERT actions are not supported */\n-\tif (vlan_insert_action && (req_act & OTX2_FLOW_ACT_VLAN_STRIP)) {\n-\t\terrmsg = \"Both VLAN insert and strip actions not supported\"\n-\t\t\t\" together\";\n-\t\terrcode = ENOTSUP;\n-\t\tgoto err_exit;\n-\t}\n-\n-\t/* Check if actions specified are compatible */\n-\tif (attr->egress) {\n-\t\tif (req_act & OTX2_FLOW_ACT_VLAN_STRIP) {\n-\t\t\terrmsg = \"VLAN pop action is not supported on Egress\";\n-\t\t\terrcode = ENOTSUP;\n-\t\t\tgoto err_exit;\n-\t\t}\n-\n-\t\tif (req_act & OTX2_FLOW_ACT_DROP) {\n-\t\t\tflow->npc_action = NIX_TX_ACTIONOP_DROP;\n-\t\t} else if ((req_act & OTX2_FLOW_ACT_COUNT) ||\n-\t\t\t vlan_insert_action) {\n-\t\t\tflow->npc_action = NIX_TX_ACTIONOP_UCAST_DEFAULT;\n-\t\t} else {\n-\t\t\terrmsg = \"Unsupported action for egress\";\n-\t\t\terrcode = EINVAL;\n-\t\t\tgoto err_exit;\n-\t\t}\n-\t\tgoto set_pf_func;\n-\t}\n-\n-\t/* We have already verified the attr, this is ingress.\n-\t * - Exactly one terminating action is supported\n-\t * - Exactly one of MARK or FLAG is supported\n-\t * - If terminating action is DROP, only count is valid.\n-\t */\n-\tsel_act = req_act & OTX2_FLOW_ACT_TERM;\n-\tif ((sel_act & (sel_act - 1)) != 0) {\n-\t\terrmsg = \"Only one terminating action supported\";\n-\t\terrcode = EINVAL;\n-\t\tgoto err_exit;\n-\t}\n-\n-\tif (req_act & OTX2_FLOW_ACT_DROP) {\n-\t\tsel_act = req_act & ~OTX2_FLOW_ACT_COUNT;\n-\t\tif ((sel_act & (sel_act - 1)) != 0) {\n-\t\t\terrmsg = \"Only COUNT action is supported \"\n-\t\t\t\t\"with DROP ingress action\";\n-\t\t\terrcode = ENOTSUP;\n-\t\t\tgoto err_exit;\n-\t\t}\n-\t}\n-\n-\tif ((req_act & (OTX2_FLOW_ACT_FLAG | OTX2_FLOW_ACT_MARK))\n-\t == (OTX2_FLOW_ACT_FLAG | OTX2_FLOW_ACT_MARK)) {\n-\t\terrmsg = \"Only one of FLAG or MARK action is supported\";\n-\t\terrcode = ENOTSUP;\n-\t\tgoto err_exit;\n-\t}\n-\n-\tif (vlan_insert_action) {\n-\t\terrmsg = \"VLAN push/Insert action is not supported on Ingress\";\n-\t\terrcode = ENOTSUP;\n-\t\tgoto err_exit;\n-\t}\n-\n-\tif (req_act & OTX2_FLOW_ACT_VLAN_STRIP)\n-\t\tnpc->vtag_actions++;\n-\n-\t/* Only VLAN action is provided */\n-\tif (req_act == OTX2_FLOW_ACT_VLAN_STRIP)\n-\t\tflow->npc_action = NIX_RX_ACTIONOP_UCAST;\n-\t/* Set NIX_RX_ACTIONOP */\n-\telse if (req_act & (OTX2_FLOW_ACT_PF | OTX2_FLOW_ACT_VF)) {\n-\t\tflow->npc_action = NIX_RX_ACTIONOP_UCAST;\n-\t\tif (req_act & OTX2_FLOW_ACT_QUEUE)\n-\t\t\tflow->npc_action |= (uint64_t)rq << 20;\n-\t} else if (req_act & OTX2_FLOW_ACT_DROP) {\n-\t\tflow->npc_action = NIX_RX_ACTIONOP_DROP;\n-\t} else if (req_act & OTX2_FLOW_ACT_QUEUE) {\n-\t\tflow->npc_action = NIX_RX_ACTIONOP_UCAST;\n-\t\tflow->npc_action |= (uint64_t)rq << 20;\n-\t} else if (req_act & OTX2_FLOW_ACT_RSS) {\n-\t\t/* When user added a rule for rss, first we will add the\n-\t\t *rule in MCAM and then update the action, once if we have\n-\t\t *FLOW_KEY_ALG index. So, till we update the action with\n-\t\t *flow_key_alg index, set the action to drop.\n-\t\t */\n-\t\tif (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS)\n-\t\t\tflow->npc_action = NIX_RX_ACTIONOP_DROP;\n-\t\telse\n-\t\t\tflow->npc_action = NIX_RX_ACTIONOP_UCAST;\n-\t} else if (req_act & OTX2_FLOW_ACT_SEC) {\n-\t\tflow->npc_action = NIX_RX_ACTIONOP_UCAST_IPSEC;\n-\t\tflow->npc_action |= (uint64_t)rq << 20;\n-\t} else if (req_act & (OTX2_FLOW_ACT_FLAG | OTX2_FLOW_ACT_MARK)) {\n-\t\tflow->npc_action = NIX_RX_ACTIONOP_UCAST;\n-\t} else if (req_act & OTX2_FLOW_ACT_COUNT) {\n-\t\t/* Keep OTX2_FLOW_ACT_COUNT always at the end\n-\t\t * This is default action, when user specify only\n-\t\t * COUNT ACTION\n-\t\t */\n-\t\tflow->npc_action = NIX_RX_ACTIONOP_UCAST;\n-\t} else {\n-\t\t/* Should never reach here */\n-\t\terrmsg = \"Invalid action specified\";\n-\t\terrcode = EINVAL;\n-\t\tgoto err_exit;\n-\t}\n-\n-\tif (mark)\n-\t\tflow->npc_action |= (uint64_t)mark << 40;\n-\n-\tif (rte_atomic32_read(&npc->mark_actions) == 1) {\n-\t\thw->rx_offload_flags |=\n-\t\t\tNIX_RX_OFFLOAD_MARK_UPDATE_F;\n-\t\totx2_eth_set_rx_function(dev);\n-\t}\n-\n-\tif (npc->vtag_actions == 1) {\n-\t\thw->rx_offload_flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;\n-\t\totx2_eth_set_rx_function(dev);\n-\t}\n-\n-set_pf_func:\n-\t/* Ideally AF must ensure that correct pf_func is set */\n-\tif (attr->egress)\n-\t\tflow->npc_action |= (uint64_t)pf_func << 48;\n-\telse\n-\t\tflow->npc_action |= (uint64_t)pf_func << 4;\n-\n-\treturn 0;\n-\n-err_exit:\n-\trte_flow_error_set(error, errcode,\n-\t\t\t RTE_FLOW_ERROR_TYPE_ACTION_NUM, NULL,\n-\t\t\t errmsg);\n-\treturn -rte_errno;\n-}\ndiff --git a/drivers/net/octeontx2/otx2_flow_utils.c b/drivers/net/octeontx2/otx2_flow_utils.c\ndeleted file mode 100644\nindex 35f7d0f4bc..0000000000\n--- a/drivers/net/octeontx2/otx2_flow_utils.c\n+++ /dev/null\n@@ -1,969 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_ethdev.h\"\n-#include \"otx2_flow.h\"\n-\n-static int\n-flow_mcam_alloc_counter(struct otx2_mbox *mbox, uint16_t *ctr)\n-{\n-\tstruct npc_mcam_alloc_counter_req *req;\n-\tstruct npc_mcam_alloc_counter_rsp *rsp;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_npc_mcam_alloc_counter(mbox);\n-\treq->count = 1;\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_get_rsp(mbox, 0, (void *)&rsp);\n-\n-\t*ctr = rsp->cntr_list[0];\n-\treturn rc;\n-}\n-\n-int\n-otx2_flow_mcam_free_counter(struct otx2_mbox *mbox, uint16_t ctr_id)\n-{\n-\tstruct npc_mcam_oper_counter_req *req;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_npc_mcam_free_counter(mbox);\n-\treq->cntr = ctr_id;\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_get_rsp(mbox, 0, NULL);\n-\n-\treturn rc;\n-}\n-\n-int\n-otx2_flow_mcam_read_counter(struct otx2_mbox *mbox, uint32_t ctr_id,\n-\t\t\t uint64_t *count)\n-{\n-\tstruct npc_mcam_oper_counter_req *req;\n-\tstruct npc_mcam_oper_counter_rsp *rsp;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_npc_mcam_counter_stats(mbox);\n-\treq->cntr = ctr_id;\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_get_rsp(mbox, 0, (void *)&rsp);\n-\n-\t*count = rsp->stat;\n-\treturn rc;\n-}\n-\n-int\n-otx2_flow_mcam_clear_counter(struct otx2_mbox *mbox, uint32_t ctr_id)\n-{\n-\tstruct npc_mcam_oper_counter_req *req;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_npc_mcam_clear_counter(mbox);\n-\treq->cntr = ctr_id;\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_get_rsp(mbox, 0, NULL);\n-\n-\treturn rc;\n-}\n-\n-int\n-otx2_flow_mcam_free_entry(struct otx2_mbox *mbox, uint32_t entry)\n-{\n-\tstruct npc_mcam_free_entry_req *req;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_npc_mcam_free_entry(mbox);\n-\treq->entry = entry;\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_get_rsp(mbox, 0, NULL);\n-\n-\treturn rc;\n-}\n-\n-int\n-otx2_flow_mcam_free_all_entries(struct otx2_mbox *mbox)\n-{\n-\tstruct npc_mcam_free_entry_req *req;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_npc_mcam_free_entry(mbox);\n-\treq->all = 1;\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_get_rsp(mbox, 0, NULL);\n-\n-\treturn rc;\n-}\n-\n-static void\n-flow_prep_mcam_ldata(uint8_t *ptr, const uint8_t *data, int len)\n-{\n-\tint idx;\n-\n-\tfor (idx = 0; idx < len; idx++)\n-\t\tptr[idx] = data[len - 1 - idx];\n-}\n-\n-static int\n-flow_check_copysz(size_t size, size_t len)\n-{\n-\tif (len <= size)\n-\t\treturn len;\n-\treturn -1;\n-}\n-\n-static inline int\n-flow_mem_is_zero(const void *mem, int len)\n-{\n-\tconst char *m = mem;\n-\tint i;\n-\n-\tfor (i = 0; i < len; i++) {\n-\t\tif (m[i] != 0)\n-\t\t\treturn 0;\n-\t}\n-\treturn 1;\n-}\n-\n-static void\n-flow_set_hw_mask(struct otx2_flow_item_info *info,\n-\t\t struct npc_xtract_info *xinfo,\n-\t\t char *hw_mask)\n-{\n-\tint max_off, offset;\n-\tint j;\n-\n-\tif (xinfo->enable == 0)\n-\t\treturn;\n-\n-\tif (xinfo->hdr_off < info->hw_hdr_len)\n-\t\treturn;\n-\n-\tmax_off = xinfo->hdr_off + xinfo->len - info->hw_hdr_len;\n-\n-\tif (max_off > info->len)\n-\t\tmax_off = info->len;\n-\n-\toffset = xinfo->hdr_off - info->hw_hdr_len;\n-\tfor (j = offset; j < max_off; j++)\n-\t\thw_mask[j] = 0xff;\n-}\n-\n-void\n-otx2_flow_get_hw_supp_mask(struct otx2_parse_state *pst,\n-\t\t\t struct otx2_flow_item_info *info, int lid, int lt)\n-{\n-\tstruct npc_xtract_info *xinfo, *lfinfo;\n-\tchar *hw_mask = info->hw_mask;\n-\tint lf_cfg;\n-\tint i, j;\n-\tint intf;\n-\n-\tintf = pst->flow->nix_intf;\n-\txinfo = pst->npc->prx_dxcfg[intf][lid][lt].xtract;\n-\tmemset(hw_mask, 0, info->len);\n-\n-\tfor (i = 0; i < NPC_MAX_LD; i++) {\n-\t\tflow_set_hw_mask(info, &xinfo[i], hw_mask);\n-\t}\n-\n-\tfor (i = 0; i < NPC_MAX_LD; i++) {\n-\n-\t\tif (xinfo[i].flags_enable == 0)\n-\t\t\tcontinue;\n-\n-\t\tlf_cfg = pst->npc->prx_lfcfg[i].i;\n-\t\tif (lf_cfg == lid) {\n-\t\t\tfor (j = 0; j < NPC_MAX_LFL; j++) {\n-\t\t\t\tlfinfo = pst->npc->prx_fxcfg[intf]\n-\t\t\t\t\t[i][j].xtract;\n-\t\t\t\tflow_set_hw_mask(info, &lfinfo[0], hw_mask);\n-\t\t\t}\n-\t\t}\n-\t}\n-}\n-\n-static int\n-flow_update_extraction_data(struct otx2_parse_state *pst,\n-\t\t\t struct otx2_flow_item_info *info,\n-\t\t\t struct npc_xtract_info *xinfo)\n-{\n-\tuint8_t int_info_mask[NPC_MAX_EXTRACT_DATA_LEN];\n-\tuint8_t int_info[NPC_MAX_EXTRACT_DATA_LEN];\n-\tstruct npc_xtract_info *x;\n-\tint k, idx, hdr_off;\n-\tint len = 0;\n-\n-\tx = xinfo;\n-\tlen = x->len;\n-\thdr_off = x->hdr_off;\n-\n-\tif (hdr_off < info->hw_hdr_len)\n-\t\treturn 0;\n-\n-\tif (x->enable == 0)\n-\t\treturn 0;\n-\n-\totx2_npc_dbg(\"x->hdr_off = %d, len = %d, info->len = %d,\"\n-\t\t \"x->key_off = %d\", x->hdr_off, len, info->len,\n-\t\t x->key_off);\n-\n-\thdr_off -= info->hw_hdr_len;\n-\n-\tif (hdr_off + len > info->len)\n-\t\tlen = info->len - hdr_off;\n-\n-\t/* Check for over-write of previous layer */\n-\tif (!flow_mem_is_zero(pst->mcam_mask + x->key_off,\n-\t\t\t len)) {\n-\t\t/* Cannot support this data match */\n-\t\trte_flow_error_set(pst->error, ENOTSUP,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t pst->pattern,\n-\t\t\t\t \"Extraction unsupported\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\tlen = flow_check_copysz((OTX2_MAX_MCAM_WIDTH_DWORDS * 8)\n-\t\t\t\t- x->key_off,\n-\t\t\t\tlen);\n-\tif (len < 0) {\n-\t\trte_flow_error_set(pst->error, ENOTSUP,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t pst->pattern,\n-\t\t\t\t \"Internal Error\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\t/* Need to reverse complete structure so that dest addr is at\n-\t * MSB so as to program the MCAM using mcam_data & mcam_mask\n-\t * arrays\n-\t */\n-\tflow_prep_mcam_ldata(int_info,\n-\t\t\t (const uint8_t *)info->spec + hdr_off,\n-\t\t\t x->len);\n-\tflow_prep_mcam_ldata(int_info_mask,\n-\t\t\t (const uint8_t *)info->mask + hdr_off,\n-\t\t\t x->len);\n-\n-\totx2_npc_dbg(\"Spec: \");\n-\tfor (k = 0; k < info->len; k++)\n-\t\totx2_npc_dbg(\"0x%.2x \",\n-\t\t\t ((const uint8_t *)info->spec)[k]);\n-\n-\totx2_npc_dbg(\"Int_info: \");\n-\tfor (k = 0; k < info->len; k++)\n-\t\totx2_npc_dbg(\"0x%.2x \", int_info[k]);\n-\n-\tmemcpy(pst->mcam_mask + x->key_off, int_info_mask, len);\n-\tmemcpy(pst->mcam_data + x->key_off, int_info, len);\n-\n-\totx2_npc_dbg(\"Parse state mcam data & mask\");\n-\tfor (idx = 0; idx < len ; idx++)\n-\t\totx2_npc_dbg(\"data[%d]: 0x%x, mask[%d]: 0x%x\", idx,\n-\t\t\t *(pst->mcam_data + idx + x->key_off), idx,\n-\t\t\t *(pst->mcam_mask + idx + x->key_off));\n-\treturn 0;\n-}\n-\n-int\n-otx2_flow_update_parse_state(struct otx2_parse_state *pst,\n-\t\t\t struct otx2_flow_item_info *info, int lid, int lt,\n-\t\t\t uint8_t flags)\n-{\n-\tstruct npc_lid_lt_xtract_info *xinfo;\n-\tstruct otx2_flow_dump_data *dump;\n-\tstruct npc_xtract_info *lfinfo;\n-\tint intf, lf_cfg;\n-\tint i, j, rc = 0;\n-\n-\totx2_npc_dbg(\"Parse state function info mask total %s\",\n-\t\t (const uint8_t *)info->mask);\n-\n-\tpst->layer_mask |= lid;\n-\tpst->lt[lid] = lt;\n-\tpst->flags[lid] = flags;\n-\n-\tintf = pst->flow->nix_intf;\n-\txinfo = &pst->npc->prx_dxcfg[intf][lid][lt];\n-\totx2_npc_dbg(\"Is_terminating = %d\", xinfo->is_terminating);\n-\tif (xinfo->is_terminating)\n-\t\tpst->terminate = 1;\n-\n-\tif (info->spec == NULL) {\n-\t\totx2_npc_dbg(\"Info spec NULL\");\n-\t\tgoto done;\n-\t}\n-\n-\tfor (i = 0; i < NPC_MAX_LD; i++) {\n-\t\trc = flow_update_extraction_data(pst, info, &xinfo->xtract[i]);\n-\t\tif (rc != 0)\n-\t\t\treturn rc;\n-\t}\n-\n-\tfor (i = 0; i < NPC_MAX_LD; i++) {\n-\t\tif (xinfo->xtract[i].flags_enable == 0)\n-\t\t\tcontinue;\n-\n-\t\tlf_cfg = pst->npc->prx_lfcfg[i].i;\n-\t\tif (lf_cfg == lid) {\n-\t\t\tfor (j = 0; j < NPC_MAX_LFL; j++) {\n-\t\t\t\tlfinfo = pst->npc->prx_fxcfg[intf]\n-\t\t\t\t\t[i][j].xtract;\n-\t\t\t\trc = flow_update_extraction_data(pst, info,\n-\t\t\t\t\t\t\t\t &lfinfo[0]);\n-\t\t\t\tif (rc != 0)\n-\t\t\t\t\treturn rc;\n-\n-\t\t\t\tif (lfinfo[0].enable)\n-\t\t\t\t\tpst->flags[lid] = j;\n-\t\t\t}\n-\t\t}\n-\t}\n-\n-done:\n-\tdump = &pst->flow->dump_data[pst->flow->num_patterns++];\n-\tdump->lid = lid;\n-\tdump->ltype = lt;\n-\t/* Next pattern to parse by subsequent layers */\n-\tpst->pattern++;\n-\treturn 0;\n-}\n-\n-static inline int\n-flow_range_is_valid(const char *spec, const char *last, const char *mask,\n-\t\t int len)\n-{\n-\t/* Mask must be zero or equal to spec as we do not support\n-\t * non-contiguous ranges.\n-\t */\n-\twhile (len--) {\n-\t\tif (last[len] &&\n-\t\t (spec[len] & mask[len]) != (last[len] & mask[len]))\n-\t\t\treturn 0; /* False */\n-\t}\n-\treturn 1;\n-}\n-\n-\n-static inline int\n-flow_mask_is_supported(const char *mask, const char *hw_mask, int len)\n-{\n-\t/*\n-\t * If no hw_mask, assume nothing is supported.\n-\t * mask is never NULL\n-\t */\n-\tif (hw_mask == NULL)\n-\t\treturn flow_mem_is_zero(mask, len);\n-\n-\twhile (len--) {\n-\t\tif ((mask[len] | hw_mask[len]) != hw_mask[len])\n-\t\t\treturn 0; /* False */\n-\t}\n-\treturn 1;\n-}\n-\n-int\n-otx2_flow_parse_item_basic(const struct rte_flow_item *item,\n-\t\t\t struct otx2_flow_item_info *info,\n-\t\t\t struct rte_flow_error *error)\n-{\n-\t/* Item must not be NULL */\n-\tif (item == NULL) {\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, NULL,\n-\t\t\t\t \"Item is NULL\");\n-\t\treturn -rte_errno;\n-\t}\n-\t/* If spec is NULL, both mask and last must be NULL, this\n-\t * makes it to match ANY value (eq to mask = 0).\n-\t * Setting either mask or last without spec is an error\n-\t */\n-\tif (item->spec == NULL) {\n-\t\tif (item->last == NULL && item->mask == NULL) {\n-\t\t\tinfo->spec = NULL;\n-\t\t\treturn 0;\n-\t\t}\n-\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n-\t\t\t\t \"mask or last set without spec\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\t/* We have valid spec */\n-\tif (item->type != RTE_FLOW_ITEM_TYPE_RAW)\n-\t\tinfo->spec = item->spec;\n-\n-\t/* If mask is not set, use default mask, err if default mask is\n-\t * also NULL.\n-\t */\n-\tif (item->mask == NULL) {\n-\t\totx2_npc_dbg(\"Item mask null, using default mask\");\n-\t\tif (info->def_mask == NULL) {\n-\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n-\t\t\t\t\t \"No mask or default mask given\");\n-\t\t\treturn -rte_errno;\n-\t\t}\n-\t\tinfo->mask = info->def_mask;\n-\t} else {\n-\t\tif (item->type != RTE_FLOW_ITEM_TYPE_RAW)\n-\t\t\tinfo->mask = item->mask;\n-\t}\n-\n-\t/* mask specified must be subset of hw supported mask\n-\t * mask | hw_mask == hw_mask\n-\t */\n-\tif (!flow_mask_is_supported(info->mask, info->hw_mask, info->len)) {\n-\t\trte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,\n-\t\t\t\t item, \"Unsupported field in the mask\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\t/* Now we have spec and mask. OTX2 does not support non-contiguous\n-\t * range. We should have either:\n-\t * - spec & mask == last & mask or,\n-\t * - last == 0 or,\n-\t * - last == NULL\n-\t */\n-\tif (item->last != NULL && !flow_mem_is_zero(item->last, info->len)) {\n-\t\tif (!flow_range_is_valid(item->spec, item->last, info->mask,\n-\t\t\t\t\t info->len)) {\n-\t\t\trte_flow_error_set(error, EINVAL,\n-\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, item,\n-\t\t\t\t\t \"Unsupported range for match\");\n-\t\t\treturn -rte_errno;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-void\n-otx2_flow_keyx_compress(uint64_t *data, uint32_t nibble_mask)\n-{\n-\tuint64_t cdata[2] = {0ULL, 0ULL}, nibble;\n-\tint i, j = 0;\n-\n-\tfor (i = 0; i < NPC_MAX_KEY_NIBBLES; i++) {\n-\t\tif (nibble_mask & (1 << i)) {\n-\t\t\tnibble = (data[i / 16] >> ((i & 0xf) * 4)) & 0xf;\n-\t\t\tcdata[j / 16] |= (nibble << ((j & 0xf) * 4));\n-\t\t\tj += 1;\n-\t\t}\n-\t}\n-\n-\tdata[0] = cdata[0];\n-\tdata[1] = cdata[1];\n-}\n-\n-static int\n-flow_first_set_bit(uint64_t slab)\n-{\n-\tint num = 0;\n-\n-\tif ((slab & 0xffffffff) == 0) {\n-\t\tnum += 32;\n-\t\tslab >>= 32;\n-\t}\n-\tif ((slab & 0xffff) == 0) {\n-\t\tnum += 16;\n-\t\tslab >>= 16;\n-\t}\n-\tif ((slab & 0xff) == 0) {\n-\t\tnum += 8;\n-\t\tslab >>= 8;\n-\t}\n-\tif ((slab & 0xf) == 0) {\n-\t\tnum += 4;\n-\t\tslab >>= 4;\n-\t}\n-\tif ((slab & 0x3) == 0) {\n-\t\tnum += 2;\n-\t\tslab >>= 2;\n-\t}\n-\tif ((slab & 0x1) == 0)\n-\t\tnum += 1;\n-\n-\treturn num;\n-}\n-\n-static int\n-flow_shift_lv_ent(struct otx2_mbox *mbox, struct rte_flow *flow,\n-\t\t struct otx2_npc_flow_info *flow_info,\n-\t\t uint32_t old_ent, uint32_t new_ent)\n-{\n-\tstruct npc_mcam_shift_entry_req *req;\n-\tstruct npc_mcam_shift_entry_rsp *rsp;\n-\tstruct otx2_flow_list *list;\n-\tstruct rte_flow *flow_iter;\n-\tint rc = 0;\n-\n-\totx2_npc_dbg(\"Old ent:%u new ent:%u priority:%u\", old_ent, new_ent,\n-\t\t flow->priority);\n-\n-\tlist = &flow_info->flow_list[flow->priority];\n-\n-\t/* Old entry is disabled & it's contents are moved to new_entry,\n-\t * new entry is enabled finally.\n-\t */\n-\treq = otx2_mbox_alloc_msg_npc_mcam_shift_entry(mbox);\n-\treq->curr_entry[0] = old_ent;\n-\treq->new_entry[0] = new_ent;\n-\treq->shift_count = 1;\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_get_rsp(mbox, 0, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\t/* Remove old node from list */\n-\tTAILQ_FOREACH(flow_iter, list, next) {\n-\t\tif (flow_iter->mcam_id == old_ent)\n-\t\t\tTAILQ_REMOVE(list, flow_iter, next);\n-\t}\n-\n-\t/* Insert node with new mcam id at right place */\n-\tTAILQ_FOREACH(flow_iter, list, next) {\n-\t\tif (flow_iter->mcam_id > new_ent)\n-\t\t\tTAILQ_INSERT_BEFORE(flow_iter, flow, next);\n-\t}\n-\treturn rc;\n-}\n-\n-/* Exchange all required entries with a given priority level */\n-static int\n-flow_shift_ent(struct otx2_mbox *mbox, struct rte_flow *flow,\n-\t struct otx2_npc_flow_info *flow_info,\n-\t struct npc_mcam_alloc_entry_rsp *rsp, int dir, int prio_lvl)\n-{\n-\tstruct rte_bitmap *fr_bmp, *fr_bmp_rev, *lv_bmp, *lv_bmp_rev, *bmp;\n-\tuint32_t e_fr = 0, e_lv = 0, e, e_id = 0, mcam_entries;\n-\tuint64_t fr_bit_pos = 0, lv_bit_pos = 0, bit_pos = 0;\n-\t/* Bit position within the slab */\n-\tuint32_t sl_fr_bit_off = 0, sl_lv_bit_off = 0;\n-\t/* Overall bit position of the start of slab */\n-\t/* free & live entry index */\n-\tint rc_fr = 0, rc_lv = 0, rc = 0, idx = 0;\n-\tstruct otx2_mcam_ents_info *ent_info;\n-\t/* free & live bitmap slab */\n-\tuint64_t sl_fr = 0, sl_lv = 0, *sl;\n-\n-\tfr_bmp = flow_info->free_entries[prio_lvl];\n-\tfr_bmp_rev = flow_info->free_entries_rev[prio_lvl];\n-\tlv_bmp = flow_info->live_entries[prio_lvl];\n-\tlv_bmp_rev = flow_info->live_entries_rev[prio_lvl];\n-\tent_info = &flow_info->flow_entry_info[prio_lvl];\n-\tmcam_entries = flow_info->mcam_entries;\n-\n-\n-\t/* New entries allocated are always contiguous, but older entries\n-\t * already in free/live bitmap can be non-contiguous: so return\n-\t * shifted entries should be in non-contiguous format.\n-\t */\n-\twhile (idx <= rsp->count) {\n-\t\tif (!sl_fr && !sl_lv) {\n-\t\t\t/* Lower index elements to be exchanged */\n-\t\t\tif (dir < 0) {\n-\t\t\t\trc_fr = rte_bitmap_scan(fr_bmp, &e_fr, &sl_fr);\n-\t\t\t\trc_lv = rte_bitmap_scan(lv_bmp, &e_lv, &sl_lv);\n-\t\t\t\totx2_npc_dbg(\"Fwd slab rc fr %u rc lv %u \"\n-\t\t\t\t\t \"e_fr %u e_lv %u\", rc_fr, rc_lv,\n-\t\t\t\t\t e_fr, e_lv);\n-\t\t\t} else {\n-\t\t\t\trc_fr = rte_bitmap_scan(fr_bmp_rev,\n-\t\t\t\t\t\t\t&sl_fr_bit_off,\n-\t\t\t\t\t\t\t&sl_fr);\n-\t\t\t\trc_lv = rte_bitmap_scan(lv_bmp_rev,\n-\t\t\t\t\t\t\t&sl_lv_bit_off,\n-\t\t\t\t\t\t\t&sl_lv);\n-\n-\t\t\t\totx2_npc_dbg(\"Rev slab rc fr %u rc lv %u \"\n-\t\t\t\t\t \"e_fr %u e_lv %u\", rc_fr, rc_lv,\n-\t\t\t\t\t e_fr, e_lv);\n-\t\t\t}\n-\t\t}\n-\n-\t\tif (rc_fr) {\n-\t\t\tfr_bit_pos = flow_first_set_bit(sl_fr);\n-\t\t\te_fr = sl_fr_bit_off + fr_bit_pos;\n-\t\t\totx2_npc_dbg(\"Fr_bit_pos 0x%\" PRIx64, fr_bit_pos);\n-\t\t} else {\n-\t\t\te_fr = ~(0);\n-\t\t}\n-\n-\t\tif (rc_lv) {\n-\t\t\tlv_bit_pos = flow_first_set_bit(sl_lv);\n-\t\t\te_lv = sl_lv_bit_off + lv_bit_pos;\n-\t\t\totx2_npc_dbg(\"Lv_bit_pos 0x%\" PRIx64, lv_bit_pos);\n-\t\t} else {\n-\t\t\te_lv = ~(0);\n-\t\t}\n-\n-\t\t/* First entry is from free_bmap */\n-\t\tif (e_fr < e_lv) {\n-\t\t\tbmp = fr_bmp;\n-\t\t\te = e_fr;\n-\t\t\tsl = &sl_fr;\n-\t\t\tbit_pos = fr_bit_pos;\n-\t\t\tif (dir > 0)\n-\t\t\t\te_id = mcam_entries - e - 1;\n-\t\t\telse\n-\t\t\t\te_id = e;\n-\t\t\totx2_npc_dbg(\"Fr e %u e_id %u\", e, e_id);\n-\t\t} else {\n-\t\t\tbmp = lv_bmp;\n-\t\t\te = e_lv;\n-\t\t\tsl = &sl_lv;\n-\t\t\tbit_pos = lv_bit_pos;\n-\t\t\tif (dir > 0)\n-\t\t\t\te_id = mcam_entries - e - 1;\n-\t\t\telse\n-\t\t\t\te_id = e;\n-\n-\t\t\totx2_npc_dbg(\"Lv e %u e_id %u\", e, e_id);\n-\t\t\tif (idx < rsp->count)\n-\t\t\t\trc =\n-\t\t\t\t flow_shift_lv_ent(mbox, flow,\n-\t\t\t\t\t\t flow_info, e_id,\n-\t\t\t\t\t\t rsp->entry + idx);\n-\t\t}\n-\n-\t\trte_bitmap_clear(bmp, e);\n-\t\trte_bitmap_set(bmp, rsp->entry + idx);\n-\t\t/* Update entry list, use non-contiguous\n-\t\t * list now.\n-\t\t */\n-\t\trsp->entry_list[idx] = e_id;\n-\t\t*sl &= ~(1 << bit_pos);\n-\n-\t\t/* Update min & max entry identifiers in current\n-\t\t * priority level.\n-\t\t */\n-\t\tif (dir < 0) {\n-\t\t\tent_info->max_id = rsp->entry + idx;\n-\t\t\tent_info->min_id = e_id;\n-\t\t} else {\n-\t\t\tent_info->max_id = e_id;\n-\t\t\tent_info->min_id = rsp->entry;\n-\t\t}\n-\n-\t\tidx++;\n-\t}\n-\treturn rc;\n-}\n-\n-/* Validate if newly allocated entries lie in the correct priority zone\n- * since NPC_MCAM_LOWER_PRIO & NPC_MCAM_HIGHER_PRIO don't ensure zone accuracy.\n- * If not properly aligned, shift entries to do so\n- */\n-static int\n-flow_validate_and_shift_prio_ent(struct otx2_mbox *mbox, struct rte_flow *flow,\n-\t\t\t\t struct otx2_npc_flow_info *flow_info,\n-\t\t\t\t struct npc_mcam_alloc_entry_rsp *rsp,\n-\t\t\t\t int req_prio)\n-{\n-\tint prio_idx = 0, rc = 0, needs_shift = 0, idx, prio = flow->priority;\n-\tstruct otx2_mcam_ents_info *info = flow_info->flow_entry_info;\n-\tint dir = (req_prio == NPC_MCAM_HIGHER_PRIO) ? 1 : -1;\n-\tuint32_t tot_ent = 0;\n-\n-\totx2_npc_dbg(\"Dir %d, priority = %d\", dir, prio);\n-\n-\tif (dir < 0)\n-\t\tprio_idx = flow_info->flow_max_priority - 1;\n-\n-\t/* Only live entries needs to be shifted, free entries can just be\n-\t * moved by bits manipulation.\n-\t */\n-\n-\t/* For dir = -1(NPC_MCAM_LOWER_PRIO), when shifting,\n-\t * NPC_MAX_PREALLOC_ENT are exchanged with adjoining higher priority\n-\t * level entries(lower indexes).\n-\t *\n-\t * For dir = +1(NPC_MCAM_HIGHER_PRIO), during shift,\n-\t * NPC_MAX_PREALLOC_ENT are exchanged with adjoining lower priority\n-\t * level entries(higher indexes) with highest indexes.\n-\t */\n-\tdo {\n-\t\ttot_ent = info[prio_idx].free_ent + info[prio_idx].live_ent;\n-\n-\t\tif (dir < 0 && prio_idx != prio &&\n-\t\t rsp->entry > info[prio_idx].max_id && tot_ent) {\n-\t\t\totx2_npc_dbg(\"Rsp entry %u prio idx %u \"\n-\t\t\t\t \"max id %u\", rsp->entry, prio_idx,\n-\t\t\t\t info[prio_idx].max_id);\n-\n-\t\t\tneeds_shift = 1;\n-\t\t} else if ((dir > 0) && (prio_idx != prio) &&\n-\t\t (rsp->entry < info[prio_idx].min_id) && tot_ent) {\n-\t\t\totx2_npc_dbg(\"Rsp entry %u prio idx %u \"\n-\t\t\t\t \"min id %u\", rsp->entry, prio_idx,\n-\t\t\t\t info[prio_idx].min_id);\n-\t\t\tneeds_shift = 1;\n-\t\t}\n-\n-\t\totx2_npc_dbg(\"Needs_shift = %d\", needs_shift);\n-\t\tif (needs_shift) {\n-\t\t\tneeds_shift = 0;\n-\t\t\trc = flow_shift_ent(mbox, flow, flow_info, rsp, dir,\n-\t\t\t\t\t prio_idx);\n-\t\t} else {\n-\t\t\tfor (idx = 0; idx < rsp->count; idx++)\n-\t\t\t\trsp->entry_list[idx] = rsp->entry + idx;\n-\t\t}\n-\t} while ((prio_idx != prio) && (prio_idx += dir));\n-\n-\treturn rc;\n-}\n-\n-static int\n-flow_find_ref_entry(struct otx2_npc_flow_info *flow_info, int *prio,\n-\t\t int prio_lvl)\n-{\n-\tstruct otx2_mcam_ents_info *info = flow_info->flow_entry_info;\n-\tint step = 1;\n-\n-\twhile (step < flow_info->flow_max_priority) {\n-\t\tif (((prio_lvl + step) < flow_info->flow_max_priority) &&\n-\t\t info[prio_lvl + step].live_ent) {\n-\t\t\t*prio = NPC_MCAM_HIGHER_PRIO;\n-\t\t\treturn info[prio_lvl + step].min_id;\n-\t\t}\n-\n-\t\tif (((prio_lvl - step) >= 0) &&\n-\t\t info[prio_lvl - step].live_ent) {\n-\t\t\totx2_npc_dbg(\"Prio_lvl %u live %u\", prio_lvl - step,\n-\t\t\t\t info[prio_lvl - step].live_ent);\n-\t\t\t*prio = NPC_MCAM_LOWER_PRIO;\n-\t\t\treturn info[prio_lvl - step].max_id;\n-\t\t}\n-\t\tstep++;\n-\t}\n-\t*prio = NPC_MCAM_ANY_PRIO;\n-\treturn 0;\n-}\n-\n-static int\n-flow_fill_entry_cache(struct otx2_mbox *mbox, struct rte_flow *flow,\n-\t\t struct otx2_npc_flow_info *flow_info, uint32_t *free_ent)\n-{\n-\tstruct rte_bitmap *free_bmp, *free_bmp_rev, *live_bmp, *live_bmp_rev;\n-\tstruct npc_mcam_alloc_entry_rsp rsp_local;\n-\tstruct npc_mcam_alloc_entry_rsp *rsp_cmd;\n-\tstruct npc_mcam_alloc_entry_req *req;\n-\tstruct npc_mcam_alloc_entry_rsp *rsp;\n-\tstruct otx2_mcam_ents_info *info;\n-\tuint16_t ref_ent, idx;\n-\tint rc, prio;\n-\n-\tinfo = &flow_info->flow_entry_info[flow->priority];\n-\tfree_bmp = flow_info->free_entries[flow->priority];\n-\tfree_bmp_rev = flow_info->free_entries_rev[flow->priority];\n-\tlive_bmp = flow_info->live_entries[flow->priority];\n-\tlive_bmp_rev = flow_info->live_entries_rev[flow->priority];\n-\n-\tref_ent = flow_find_ref_entry(flow_info, &prio, flow->priority);\n-\n-\treq = otx2_mbox_alloc_msg_npc_mcam_alloc_entry(mbox);\n-\treq->contig = 1;\n-\treq->count = flow_info->flow_prealloc_size;\n-\treq->priority = prio;\n-\treq->ref_entry = ref_ent;\n-\n-\totx2_npc_dbg(\"Fill cache ref entry %u prio %u\", ref_ent, prio);\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_get_rsp(mbox, 0, (void *)&rsp_cmd);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\trsp = &rsp_local;\n-\tmemcpy(rsp, rsp_cmd, sizeof(*rsp));\n-\n-\totx2_npc_dbg(\"Alloc entry %u count %u , prio = %d\", rsp->entry,\n-\t\t rsp->count, prio);\n-\n-\t/* Non-first ent cache fill */\n-\tif (prio != NPC_MCAM_ANY_PRIO) {\n-\t\tflow_validate_and_shift_prio_ent(mbox, flow, flow_info, rsp,\n-\t\t\t\t\t\t prio);\n-\t} else {\n-\t\t/* Copy into response entry list */\n-\t\tfor (idx = 0; idx < rsp->count; idx++)\n-\t\t\trsp->entry_list[idx] = rsp->entry + idx;\n-\t}\n-\n-\totx2_npc_dbg(\"Fill entry cache rsp count %u\", rsp->count);\n-\t/* Update free entries, reverse free entries list,\n-\t * min & max entry ids.\n-\t */\n-\tfor (idx = 0; idx < rsp->count; idx++) {\n-\t\tif (unlikely(rsp->entry_list[idx] < info->min_id))\n-\t\t\tinfo->min_id = rsp->entry_list[idx];\n-\n-\t\tif (unlikely(rsp->entry_list[idx] > info->max_id))\n-\t\t\tinfo->max_id = rsp->entry_list[idx];\n-\n-\t\t/* Skip entry to be returned, not to be part of free\n-\t\t * list.\n-\t\t */\n-\t\tif (prio == NPC_MCAM_HIGHER_PRIO) {\n-\t\t\tif (unlikely(idx == (rsp->count - 1))) {\n-\t\t\t\t*free_ent = rsp->entry_list[idx];\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\t\t} else {\n-\t\t\tif (unlikely(!idx)) {\n-\t\t\t\t*free_ent = rsp->entry_list[idx];\n-\t\t\t\tcontinue;\n-\t\t\t}\n-\t\t}\n-\t\tinfo->free_ent++;\n-\t\trte_bitmap_set(free_bmp, rsp->entry_list[idx]);\n-\t\trte_bitmap_set(free_bmp_rev, flow_info->mcam_entries -\n-\t\t\t rsp->entry_list[idx] - 1);\n-\n-\t\totx2_npc_dbg(\"Final rsp entry %u rsp entry rev %u\",\n-\t\t\t rsp->entry_list[idx],\n-\t\tflow_info->mcam_entries - rsp->entry_list[idx] - 1);\n-\t}\n-\n-\totx2_npc_dbg(\"Cache free entry %u, rev = %u\", *free_ent,\n-\t\t flow_info->mcam_entries - *free_ent - 1);\n-\tinfo->live_ent++;\n-\trte_bitmap_set(live_bmp, *free_ent);\n-\trte_bitmap_set(live_bmp_rev, flow_info->mcam_entries - *free_ent - 1);\n-\n-\treturn 0;\n-}\n-\n-static int\n-flow_check_preallocated_entry_cache(struct otx2_mbox *mbox,\n-\t\t\t\t struct rte_flow *flow,\n-\t\t\t\t struct otx2_npc_flow_info *flow_info)\n-{\n-\tstruct rte_bitmap *free, *free_rev, *live, *live_rev;\n-\tuint32_t pos = 0, free_ent = 0, mcam_entries;\n-\tstruct otx2_mcam_ents_info *info;\n-\tuint64_t slab = 0;\n-\tint rc;\n-\n-\totx2_npc_dbg(\"Flow priority %u\", flow->priority);\n-\n-\tinfo = &flow_info->flow_entry_info[flow->priority];\n-\n-\tfree_rev = flow_info->free_entries_rev[flow->priority];\n-\tfree = flow_info->free_entries[flow->priority];\n-\tlive_rev = flow_info->live_entries_rev[flow->priority];\n-\tlive = flow_info->live_entries[flow->priority];\n-\tmcam_entries = flow_info->mcam_entries;\n-\n-\tif (info->free_ent) {\n-\t\trc = rte_bitmap_scan(free, &pos, &slab);\n-\t\tif (rc) {\n-\t\t\t/* Get free_ent from free entry bitmap */\n-\t\t\tfree_ent = pos + __builtin_ctzll(slab);\n-\t\t\totx2_npc_dbg(\"Allocated from cache entry %u\", free_ent);\n-\t\t\t/* Remove from free bitmaps and add to live ones */\n-\t\t\trte_bitmap_clear(free, free_ent);\n-\t\t\trte_bitmap_set(live, free_ent);\n-\t\t\trte_bitmap_clear(free_rev,\n-\t\t\t\t\t mcam_entries - free_ent - 1);\n-\t\t\trte_bitmap_set(live_rev,\n-\t\t\t\t mcam_entries - free_ent - 1);\n-\n-\t\t\tinfo->free_ent--;\n-\t\t\tinfo->live_ent++;\n-\t\t\treturn free_ent;\n-\t\t}\n-\n-\t\totx2_npc_dbg(\"No free entry:its a mess\");\n-\t\treturn -1;\n-\t}\n-\n-\trc = flow_fill_entry_cache(mbox, flow, flow_info, &free_ent);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\treturn free_ent;\n-}\n-\n-int\n-otx2_flow_mcam_alloc_and_write(struct rte_flow *flow, struct otx2_mbox *mbox,\n-\t\t\t struct otx2_parse_state *pst,\n-\t\t\t struct otx2_npc_flow_info *flow_info)\n-{\n-\tint use_ctr = (flow->ctr_id == NPC_COUNTER_NONE ? 0 : 1);\n-\tstruct npc_mcam_read_base_rule_rsp *base_rule_rsp;\n-\tstruct npc_mcam_write_entry_req *req;\n-\tstruct mcam_entry *base_entry;\n-\tstruct mbox_msghdr *rsp;\n-\tuint16_t ctr = ~(0);\n-\tint rc, idx;\n-\tint entry;\n-\n-\tif (use_ctr) {\n-\t\trc = flow_mcam_alloc_counter(mbox, &ctr);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\t}\n-\n-\tentry = flow_check_preallocated_entry_cache(mbox, flow, flow_info);\n-\tif (entry < 0) {\n-\t\totx2_err(\"Prealloc failed\");\n-\t\totx2_flow_mcam_free_counter(mbox, ctr);\n-\t\treturn NPC_MCAM_ALLOC_FAILED;\n-\t}\n-\n-\tif (pst->is_vf) {\n-\t\t(void)otx2_mbox_alloc_msg_npc_read_base_steer_rule(mbox);\n-\t\trc = otx2_mbox_process_msg(mbox, (void *)&base_rule_rsp);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to fetch VF's base MCAM entry\");\n-\t\t\treturn rc;\n-\t\t}\n-\t\tbase_entry = &base_rule_rsp->entry_data;\n-\t\tfor (idx = 0; idx < OTX2_MAX_MCAM_WIDTH_DWORDS; idx++) {\n-\t\t\tflow->mcam_data[idx] |= base_entry->kw[idx];\n-\t\t\tflow->mcam_mask[idx] |= base_entry->kw_mask[idx];\n-\t\t}\n-\t}\n-\n-\treq = otx2_mbox_alloc_msg_npc_mcam_write_entry(mbox);\n-\treq->set_cntr = use_ctr;\n-\treq->cntr = ctr;\n-\treq->entry = entry;\n-\totx2_npc_dbg(\"Alloc & write entry %u\", entry);\n-\n-\treq->intf =\n-\t\t(flow->nix_intf == OTX2_INTF_RX) ? NPC_MCAM_RX : NPC_MCAM_TX;\n-\treq->enable_entry = 1;\n-\treq->entry_data.action = flow->npc_action;\n-\treq->entry_data.vtag_action = flow->vtag_action;\n-\n-\tfor (idx = 0; idx < OTX2_MAX_MCAM_WIDTH_DWORDS; idx++) {\n-\t\treq->entry_data.kw[idx] = flow->mcam_data[idx];\n-\t\treq->entry_data.kw_mask[idx] = flow->mcam_mask[idx];\n-\t}\n-\n-\tif (flow->nix_intf == OTX2_INTF_RX) {\n-\t\treq->entry_data.kw[0] |= flow_info->channel;\n-\t\treq->entry_data.kw_mask[0] |= (BIT_ULL(12) - 1);\n-\t} else {\n-\t\tuint16_t pf_func = (flow->npc_action >> 48) & 0xffff;\n-\n-\t\tpf_func = htons(pf_func);\n-\t\treq->entry_data.kw[0] |= ((uint64_t)pf_func << 32);\n-\t\treq->entry_data.kw_mask[0] |= ((uint64_t)0xffff << 32);\n-\t}\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_get_rsp(mbox, 0, (void *)&rsp);\n-\tif (rc != 0)\n-\t\treturn rc;\n-\n-\tflow->mcam_id = entry;\n-\tif (use_ctr)\n-\t\tflow->ctr_id = ctr;\n-\treturn 0;\n-}\ndiff --git a/drivers/net/octeontx2/otx2_link.c b/drivers/net/octeontx2/otx2_link.c\ndeleted file mode 100644\nindex 8f5d0eed92..0000000000\n--- a/drivers/net/octeontx2/otx2_link.c\n+++ /dev/null\n@@ -1,287 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_common.h>\n-#include <ethdev_pci.h>\n-\n-#include \"otx2_ethdev.h\"\n-\n-void\n-otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set)\n-{\n-\tif (set)\n-\t\tdev->flags |= OTX2_LINK_CFG_IN_PROGRESS_F;\n-\telse\n-\t\tdev->flags &= ~OTX2_LINK_CFG_IN_PROGRESS_F;\n-\n-\trte_wmb();\n-}\n-\n-static inline int\n-nix_wait_for_link_cfg(struct otx2_eth_dev *dev)\n-{\n-\tuint16_t wait = 1000;\n-\n-\tdo {\n-\t\trte_rmb();\n-\t\tif (!(dev->flags & OTX2_LINK_CFG_IN_PROGRESS_F))\n-\t\t\tbreak;\n-\t\twait--;\n-\t\trte_delay_ms(1);\n-\t} while (wait);\n-\n-\treturn wait ? 0 : -1;\n-}\n-\n-static void\n-nix_link_status_print(struct rte_eth_dev *eth_dev, struct rte_eth_link *link)\n-{\n-\tif (link && link->link_status)\n-\t\totx2_info(\"Port %d: Link Up - speed %u Mbps - %s\",\n-\t\t\t (int)(eth_dev->data->port_id),\n-\t\t\t (uint32_t)link->link_speed,\n-\t\t\t link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX ?\n-\t\t\t \"full-duplex\" : \"half-duplex\");\n-\telse\n-\t\totx2_info(\"Port %d: Link Down\", (int)(eth_dev->data->port_id));\n-}\n-\n-void\n-otx2_eth_dev_link_status_get(struct otx2_dev *dev,\n-\t\t\t struct cgx_link_user_info *link)\n-{\n-\tstruct otx2_eth_dev *otx2_dev = (struct otx2_eth_dev *)dev;\n-\tstruct rte_eth_link eth_link;\n-\tstruct rte_eth_dev *eth_dev;\n-\n-\tif (!link || !dev)\n-\t\treturn;\n-\n-\teth_dev = otx2_dev->eth_dev;\n-\tif (!eth_dev)\n-\t\treturn;\n-\n-\trte_eth_linkstatus_get(eth_dev, ð_link);\n-\n-\tlink->link_up = eth_link.link_status;\n-\tlink->speed = eth_link.link_speed;\n-\tlink->an = eth_link.link_autoneg;\n-\tlink->full_duplex = eth_link.link_duplex;\n-}\n-\n-void\n-otx2_eth_dev_link_status_update(struct otx2_dev *dev,\n-\t\t\t\tstruct cgx_link_user_info *link)\n-{\n-\tstruct otx2_eth_dev *otx2_dev = (struct otx2_eth_dev *)dev;\n-\tstruct rte_eth_link eth_link;\n-\tstruct rte_eth_dev *eth_dev;\n-\n-\tif (!link || !dev)\n-\t\treturn;\n-\n-\teth_dev = otx2_dev->eth_dev;\n-\tif (!eth_dev || !eth_dev->data->dev_conf.intr_conf.lsc)\n-\t\treturn;\n-\n-\tif (nix_wait_for_link_cfg(otx2_dev)) {\n-\t\totx2_err(\"Timeout waiting for link_cfg to complete\");\n-\t\treturn;\n-\t}\n-\n-\teth_link.link_status = link->link_up;\n-\teth_link.link_speed = link->speed;\n-\teth_link.link_autoneg = RTE_ETH_LINK_AUTONEG;\n-\teth_link.link_duplex = link->full_duplex;\n-\n-\totx2_dev->speed = link->speed;\n-\totx2_dev->duplex = link->full_duplex;\n-\n-\t/* Print link info */\n-\tnix_link_status_print(eth_dev, ð_link);\n-\n-\t/* Update link info */\n-\trte_eth_linkstatus_set(eth_dev, ð_link);\n-\n-\t/* Set the flag and execute application callbacks */\n-\trte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL);\n-}\n-\n-static int\n-lbk_link_update(struct rte_eth_link *link)\n-{\n-\tlink->link_status = RTE_ETH_LINK_UP;\n-\tlink->link_speed = RTE_ETH_SPEED_NUM_100G;\n-\tlink->link_autoneg = RTE_ETH_LINK_FIXED;\n-\tlink->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;\n-\treturn 0;\n-}\n-\n-static int\n-cgx_link_update(struct otx2_eth_dev *dev, struct rte_eth_link *link)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct cgx_link_info_msg *rsp;\n-\tint rc;\n-\totx2_mbox_alloc_msg_cgx_get_linkinfo(mbox);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tlink->link_status = rsp->link_info.link_up;\n-\tlink->link_speed = rsp->link_info.speed;\n-\tlink->link_autoneg = RTE_ETH_LINK_AUTONEG;\n-\n-\tif (rsp->link_info.full_duplex)\n-\t\tlink->link_duplex = rsp->link_info.full_duplex;\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct rte_eth_link link;\n-\tint rc;\n-\n-\tRTE_SET_USED(wait_to_complete);\n-\tmemset(&link, 0, sizeof(struct rte_eth_link));\n-\n-\tif (!eth_dev->data->dev_started || otx2_dev_is_sdp(dev))\n-\t\treturn 0;\n-\n-\tif (otx2_dev_is_lbk(dev))\n-\t\trc = lbk_link_update(&link);\n-\telse\n-\t\trc = cgx_link_update(dev, &link);\n-\n-\tif (rc)\n-\t\treturn rc;\n-\n-\treturn rte_eth_linkstatus_set(eth_dev, &link);\n-}\n-\n-static int\n-nix_dev_set_link_state(struct rte_eth_dev *eth_dev, uint8_t enable)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct cgx_set_link_state_msg *req;\n-\n-\treq = otx2_mbox_alloc_msg_cgx_set_link_state(mbox);\n-\treq->enable = enable;\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-int\n-otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint rc, i;\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev))\n-\t\treturn -ENOTSUP;\n-\n-\trc = nix_dev_set_link_state(eth_dev, 1);\n-\tif (rc)\n-\t\tgoto done;\n-\n-\t/* Start tx queues */\n-\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++)\n-\t\totx2_nix_tx_queue_start(eth_dev, i);\n-\n-done:\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint i;\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev))\n-\t\treturn -ENOTSUP;\n-\n-\t/* Stop tx queues */\n-\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++)\n-\t\totx2_nix_tx_queue_stop(eth_dev, i);\n-\n-\treturn nix_dev_set_link_state(eth_dev, 0);\n-}\n-\n-static int\n-cgx_change_mode(struct otx2_eth_dev *dev, struct cgx_set_link_mode_args *cfg)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct cgx_set_link_mode_req *req;\n-\n-\treq = otx2_mbox_alloc_msg_cgx_set_link_mode(mbox);\n-\treq->args.speed = cfg->speed;\n-\treq->args.duplex = cfg->duplex;\n-\treq->args.an = cfg->an;\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-#define SPEED_NONE 0\n-static inline uint32_t\n-nix_parse_link_speeds(struct otx2_eth_dev *dev, uint32_t link_speeds)\n-{\n-\tuint32_t link_speed = SPEED_NONE;\n-\n-\t/* 50G and 100G to be supported for board version C0 and above */\n-\tif (!otx2_dev_is_Ax(dev)) {\n-\t\tif (link_speeds & RTE_ETH_LINK_SPEED_100G)\n-\t\t\tlink_speed = 100000;\n-\t\tif (link_speeds & RTE_ETH_LINK_SPEED_50G)\n-\t\t\tlink_speed = 50000;\n-\t}\n-\tif (link_speeds & RTE_ETH_LINK_SPEED_40G)\n-\t\tlink_speed = 40000;\n-\tif (link_speeds & RTE_ETH_LINK_SPEED_25G)\n-\t\tlink_speed = 25000;\n-\tif (link_speeds & RTE_ETH_LINK_SPEED_20G)\n-\t\tlink_speed = 20000;\n-\tif (link_speeds & RTE_ETH_LINK_SPEED_10G)\n-\t\tlink_speed = 10000;\n-\tif (link_speeds & RTE_ETH_LINK_SPEED_5G)\n-\t\tlink_speed = 5000;\n-\tif (link_speeds & RTE_ETH_LINK_SPEED_1G)\n-\t\tlink_speed = 1000;\n-\n-\treturn link_speed;\n-}\n-\n-static inline uint8_t\n-nix_parse_eth_link_duplex(uint32_t link_speeds)\n-{\n-\tif ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) ||\n-\t\t\t(link_speeds & RTE_ETH_LINK_SPEED_100M_HD))\n-\t\treturn RTE_ETH_LINK_HALF_DUPLEX;\n-\telse\n-\t\treturn RTE_ETH_LINK_FULL_DUPLEX;\n-}\n-\n-int\n-otx2_apply_link_speed(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct rte_eth_conf *conf = ð_dev->data->dev_conf;\n-\tstruct cgx_set_link_mode_args cfg;\n-\n-\t/* If VF/SDP/LBK, link attributes cannot be changed */\n-\tif (otx2_dev_is_vf_or_sdp(dev) || otx2_dev_is_lbk(dev))\n-\t\treturn 0;\n-\n-\tmemset(&cfg, 0, sizeof(struct cgx_set_link_mode_args));\n-\tcfg.speed = nix_parse_link_speeds(dev, conf->link_speeds);\n-\tif (cfg.speed != SPEED_NONE && cfg.speed != dev->speed) {\n-\t\tcfg.duplex = nix_parse_eth_link_duplex(conf->link_speeds);\n-\t\tcfg.an = (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) == 0;\n-\n-\t\treturn cgx_change_mode(dev, &cfg);\n-\t}\n-\treturn 0;\n-}\ndiff --git a/drivers/net/octeontx2/otx2_lookup.c b/drivers/net/octeontx2/otx2_lookup.c\ndeleted file mode 100644\nindex 5fa9ae1396..0000000000\n--- a/drivers/net/octeontx2/otx2_lookup.c\n+++ /dev/null\n@@ -1,352 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_common.h>\n-#include <rte_memzone.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_ethdev.h\"\n-\n-/* NIX_RX_PARSE_S's ERRCODE + ERRLEV (12 bits) */\n-#define ERRCODE_ERRLEN_WIDTH\t\t12\n-#define ERR_ARRAY_SZ\t\t\t((BIT(ERRCODE_ERRLEN_WIDTH)) *\\\n-\t\t\t\t\tsizeof(uint32_t))\n-\n-#define SA_TBL_SZ\t\t\t(RTE_MAX_ETHPORTS * sizeof(uint64_t))\n-#define LOOKUP_ARRAY_SZ\t\t\t(PTYPE_ARRAY_SZ + ERR_ARRAY_SZ +\\\n-\t\t\t\t\tSA_TBL_SZ)\n-\n-const uint32_t *\n-otx2_nix_supported_ptypes_get(struct rte_eth_dev *eth_dev)\n-{\n-\tRTE_SET_USED(eth_dev);\n-\n-\tstatic const uint32_t ptypes[] = {\n-\t\tRTE_PTYPE_L2_ETHER_QINQ, /* LB */\n-\t\tRTE_PTYPE_L2_ETHER_VLAN, /* LB */\n-\t\tRTE_PTYPE_L2_ETHER_TIMESYNC, /* LB */\n-\t\tRTE_PTYPE_L2_ETHER_ARP,\t /* LC */\n-\t\tRTE_PTYPE_L2_ETHER_NSH,\t /* LC */\n-\t\tRTE_PTYPE_L2_ETHER_FCOE, /* LC */\n-\t\tRTE_PTYPE_L2_ETHER_MPLS, /* LC */\n-\t\tRTE_PTYPE_L3_IPV4,\t /* LC */\n-\t\tRTE_PTYPE_L3_IPV4_EXT,\t /* LC */\n-\t\tRTE_PTYPE_L3_IPV6,\t /* LC */\n-\t\tRTE_PTYPE_L3_IPV6_EXT,\t /* LC */\n-\t\tRTE_PTYPE_L4_TCP,\t /* LD */\n-\t\tRTE_PTYPE_L4_UDP,\t /* LD */\n-\t\tRTE_PTYPE_L4_SCTP,\t /* LD */\n-\t\tRTE_PTYPE_L4_ICMP,\t /* LD */\n-\t\tRTE_PTYPE_L4_IGMP,\t /* LD */\n-\t\tRTE_PTYPE_TUNNEL_GRE,\t /* LD */\n-\t\tRTE_PTYPE_TUNNEL_ESP,\t /* LD */\n-\t\tRTE_PTYPE_TUNNEL_NVGRE, /* LD */\n-\t\tRTE_PTYPE_TUNNEL_VXLAN, /* LE */\n-\t\tRTE_PTYPE_TUNNEL_GENEVE, /* LE */\n-\t\tRTE_PTYPE_TUNNEL_GTPC,\t /* LE */\n-\t\tRTE_PTYPE_TUNNEL_GTPU,\t /* LE */\n-\t\tRTE_PTYPE_TUNNEL_VXLAN_GPE, /* LE */\n-\t\tRTE_PTYPE_TUNNEL_MPLS_IN_GRE, /* LE */\n-\t\tRTE_PTYPE_TUNNEL_MPLS_IN_UDP, /* LE */\n-\t\tRTE_PTYPE_INNER_L2_ETHER,/* LF */\n-\t\tRTE_PTYPE_INNER_L3_IPV4, /* LG */\n-\t\tRTE_PTYPE_INNER_L3_IPV6, /* LG */\n-\t\tRTE_PTYPE_INNER_L4_TCP,\t /* LH */\n-\t\tRTE_PTYPE_INNER_L4_UDP, /* LH */\n-\t\tRTE_PTYPE_INNER_L4_SCTP, /* LH */\n-\t\tRTE_PTYPE_INNER_L4_ICMP, /* LH */\n-\t\tRTE_PTYPE_UNKNOWN,\n-\t};\n-\n-\treturn ptypes;\n-}\n-\n-int\n-otx2_nix_ptypes_set(struct rte_eth_dev *eth_dev, uint32_t ptype_mask)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tif (ptype_mask) {\n-\t\tdev->rx_offload_flags |= NIX_RX_OFFLOAD_PTYPE_F;\n-\t\tdev->ptype_disable = 0;\n-\t} else {\n-\t\tdev->rx_offload_flags &= ~NIX_RX_OFFLOAD_PTYPE_F;\n-\t\tdev->ptype_disable = 1;\n-\t}\n-\n-\totx2_eth_set_rx_function(eth_dev);\n-\n-\treturn 0;\n-}\n-\n-/*\n- * +------------------ +------------------ +\n- * | | IL4 | IL3| IL2 | TU | L4 | L3 | L2 |\n- * +-------------------+-------------------+\n- *\n- * +-------------------+------------------ +\n- * | | LH | LG | LF | LE | LD | LC | LB |\n- * +-------------------+-------------------+\n- *\n- * ptype [LE - LD - LC - LB] = TU - L4 - L3 - T2\n- * ptype_tunnel[LH - LG - LF] = IL4 - IL3 - IL2 - TU\n- *\n- */\n-static void\n-nix_create_non_tunnel_ptype_array(uint16_t *ptype)\n-{\n-\tuint8_t lb, lc, ld, le;\n-\tuint16_t val;\n-\tuint32_t idx;\n-\n-\tfor (idx = 0; idx < PTYPE_NON_TUNNEL_ARRAY_SZ; idx++) {\n-\t\tlb = idx & 0xF;\n-\t\tlc = (idx & 0xF0) >> 4;\n-\t\tld = (idx & 0xF00) >> 8;\n-\t\tle = (idx & 0xF000) >> 12;\n-\t\tval = RTE_PTYPE_UNKNOWN;\n-\n-\t\tswitch (lb) {\n-\t\tcase NPC_LT_LB_STAG_QINQ:\n-\t\t\tval |= RTE_PTYPE_L2_ETHER_QINQ;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LB_CTAG:\n-\t\t\tval |= RTE_PTYPE_L2_ETHER_VLAN;\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\tswitch (lc) {\n-\t\tcase NPC_LT_LC_ARP:\n-\t\t\tval |= RTE_PTYPE_L2_ETHER_ARP;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LC_NSH:\n-\t\t\tval |= RTE_PTYPE_L2_ETHER_NSH;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LC_FCOE:\n-\t\t\tval |= RTE_PTYPE_L2_ETHER_FCOE;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LC_MPLS:\n-\t\t\tval |= RTE_PTYPE_L2_ETHER_MPLS;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LC_IP:\n-\t\t\tval |= RTE_PTYPE_L3_IPV4;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LC_IP_OPT:\n-\t\t\tval |= RTE_PTYPE_L3_IPV4_EXT;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LC_IP6:\n-\t\t\tval |= RTE_PTYPE_L3_IPV6;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LC_IP6_EXT:\n-\t\t\tval |= RTE_PTYPE_L3_IPV6_EXT;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LC_PTP:\n-\t\t\tval |= RTE_PTYPE_L2_ETHER_TIMESYNC;\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\tswitch (ld) {\n-\t\tcase NPC_LT_LD_TCP:\n-\t\t\tval |= RTE_PTYPE_L4_TCP;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LD_UDP:\n-\t\t\tval |= RTE_PTYPE_L4_UDP;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LD_SCTP:\n-\t\t\tval |= RTE_PTYPE_L4_SCTP;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LD_ICMP:\n-\t\tcase NPC_LT_LD_ICMP6:\n-\t\t\tval |= RTE_PTYPE_L4_ICMP;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LD_IGMP:\n-\t\t\tval |= RTE_PTYPE_L4_IGMP;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LD_GRE:\n-\t\t\tval |= RTE_PTYPE_TUNNEL_GRE;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LD_NVGRE:\n-\t\t\tval |= RTE_PTYPE_TUNNEL_NVGRE;\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\tswitch (le) {\n-\t\tcase NPC_LT_LE_VXLAN:\n-\t\t\tval |= RTE_PTYPE_TUNNEL_VXLAN;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LE_ESP:\n-\t\t\tval |= RTE_PTYPE_TUNNEL_ESP;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LE_VXLANGPE:\n-\t\t\tval |= RTE_PTYPE_TUNNEL_VXLAN_GPE;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LE_GENEVE:\n-\t\t\tval |= RTE_PTYPE_TUNNEL_GENEVE;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LE_GTPC:\n-\t\t\tval |= RTE_PTYPE_TUNNEL_GTPC;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LE_GTPU:\n-\t\t\tval |= RTE_PTYPE_TUNNEL_GTPU;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LE_TU_MPLS_IN_GRE:\n-\t\t\tval |= RTE_PTYPE_TUNNEL_MPLS_IN_GRE;\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LE_TU_MPLS_IN_UDP:\n-\t\t\tval |= RTE_PTYPE_TUNNEL_MPLS_IN_UDP;\n-\t\t\tbreak;\n-\t\t}\n-\t\tptype[idx] = val;\n-\t}\n-}\n-\n-#define TU_SHIFT(x) ((x) >> PTYPE_NON_TUNNEL_WIDTH)\n-static void\n-nix_create_tunnel_ptype_array(uint16_t *ptype)\n-{\n-\tuint8_t lf, lg, lh;\n-\tuint16_t val;\n-\tuint32_t idx;\n-\n-\t/* Skip non tunnel ptype array memory */\n-\tptype = ptype + PTYPE_NON_TUNNEL_ARRAY_SZ;\n-\n-\tfor (idx = 0; idx < PTYPE_TUNNEL_ARRAY_SZ; idx++) {\n-\t\tlf = idx & 0xF;\n-\t\tlg = (idx & 0xF0) >> 4;\n-\t\tlh = (idx & 0xF00) >> 8;\n-\t\tval = RTE_PTYPE_UNKNOWN;\n-\n-\t\tswitch (lf) {\n-\t\tcase NPC_LT_LF_TU_ETHER:\n-\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L2_ETHER);\n-\t\t\tbreak;\n-\t\t}\n-\t\tswitch (lg) {\n-\t\tcase NPC_LT_LG_TU_IP:\n-\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L3_IPV4);\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LG_TU_IP6:\n-\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L3_IPV6);\n-\t\t\tbreak;\n-\t\t}\n-\t\tswitch (lh) {\n-\t\tcase NPC_LT_LH_TU_TCP:\n-\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L4_TCP);\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LH_TU_UDP:\n-\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L4_UDP);\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LH_TU_SCTP:\n-\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L4_SCTP);\n-\t\t\tbreak;\n-\t\tcase NPC_LT_LH_TU_ICMP:\n-\t\tcase NPC_LT_LH_TU_ICMP6:\n-\t\t\tval |= TU_SHIFT(RTE_PTYPE_INNER_L4_ICMP);\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\tptype[idx] = val;\n-\t}\n-}\n-\n-static void\n-nix_create_rx_ol_flags_array(void *mem)\n-{\n-\tuint16_t idx, errcode, errlev;\n-\tuint32_t val, *ol_flags;\n-\n-\t/* Skip ptype array memory */\n-\tol_flags = (uint32_t *)((uint8_t *)mem + PTYPE_ARRAY_SZ);\n-\n-\tfor (idx = 0; idx < BIT(ERRCODE_ERRLEN_WIDTH); idx++) {\n-\t\terrlev = idx & 0xf;\n-\t\terrcode = (idx & 0xff0) >> 4;\n-\n-\t\tval = RTE_MBUF_F_RX_IP_CKSUM_UNKNOWN;\n-\t\tval |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN;\n-\t\tval |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_UNKNOWN;\n-\n-\t\tswitch (errlev) {\n-\t\tcase NPC_ERRLEV_RE:\n-\t\t\t/* Mark all errors as BAD checksum errors\n-\t\t\t * including Outer L2 length mismatch error\n-\t\t\t */\n-\t\t\tif (errcode) {\n-\t\t\t\tval |= RTE_MBUF_F_RX_IP_CKSUM_BAD;\n-\t\t\t\tval |= RTE_MBUF_F_RX_L4_CKSUM_BAD;\n-\t\t\t} else {\n-\t\t\t\tval |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;\n-\t\t\t\tval |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase NPC_ERRLEV_LC:\n-\t\t\tif (errcode == NPC_EC_OIP4_CSUM ||\n-\t\t\t errcode == NPC_EC_IP_FRAG_OFFSET_1) {\n-\t\t\t\tval |= RTE_MBUF_F_RX_IP_CKSUM_BAD;\n-\t\t\t\tval |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;\n-\t\t\t} else {\n-\t\t\t\tval |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase NPC_ERRLEV_LG:\n-\t\t\tif (errcode == NPC_EC_IIP4_CSUM)\n-\t\t\t\tval |= RTE_MBUF_F_RX_IP_CKSUM_BAD;\n-\t\t\telse\n-\t\t\t\tval |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;\n-\t\t\tbreak;\n-\t\tcase NPC_ERRLEV_NIX:\n-\t\t\tif (errcode == NIX_RX_PERRCODE_OL4_CHK ||\n-\t\t\t errcode == NIX_RX_PERRCODE_OL4_LEN ||\n-\t\t\t errcode == NIX_RX_PERRCODE_OL4_PORT) {\n-\t\t\t\tval |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;\n-\t\t\t\tval |= RTE_MBUF_F_RX_L4_CKSUM_BAD;\n-\t\t\t\tval |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;\n-\t\t\t} else if (errcode == NIX_RX_PERRCODE_IL4_CHK ||\n-\t\t\t\t errcode == NIX_RX_PERRCODE_IL4_LEN ||\n-\t\t\t\t errcode == NIX_RX_PERRCODE_IL4_PORT) {\n-\t\t\t\tval |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;\n-\t\t\t\tval |= RTE_MBUF_F_RX_L4_CKSUM_BAD;\n-\t\t\t} else if (errcode == NIX_RX_PERRCODE_IL3_LEN ||\n-\t\t\t\t errcode == NIX_RX_PERRCODE_OL3_LEN) {\n-\t\t\t\tval |= RTE_MBUF_F_RX_IP_CKSUM_BAD;\n-\t\t\t} else {\n-\t\t\t\tval |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;\n-\t\t\t\tval |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\t}\n-\t\tol_flags[idx] = val;\n-\t}\n-}\n-\n-void *\n-otx2_nix_fastpath_lookup_mem_get(void)\n-{\n-\tconst char name[] = OTX2_NIX_FASTPATH_LOOKUP_MEM;\n-\tconst struct rte_memzone *mz;\n-\tvoid *mem;\n-\n-\t/* SA_TBL starts after PTYPE_ARRAY & ERR_ARRAY */\n-\tRTE_BUILD_BUG_ON(OTX2_NIX_SA_TBL_START != (PTYPE_ARRAY_SZ +\n-\t\t\t\t\t\t ERR_ARRAY_SZ));\n-\n-\tmz = rte_memzone_lookup(name);\n-\tif (mz != NULL)\n-\t\treturn mz->addr;\n-\n-\t/* Request for the first time */\n-\tmz = rte_memzone_reserve_aligned(name, LOOKUP_ARRAY_SZ,\n-\t\t\t\t\t SOCKET_ID_ANY, 0, OTX2_ALIGN);\n-\tif (mz != NULL) {\n-\t\tmem = mz->addr;\n-\t\t/* Form the ptype array lookup memory */\n-\t\tnix_create_non_tunnel_ptype_array(mem);\n-\t\tnix_create_tunnel_ptype_array(mem);\n-\t\t/* Form the rx ol_flags based on errcode */\n-\t\tnix_create_rx_ol_flags_array(mem);\n-\t\treturn mem;\n-\t}\n-\treturn NULL;\n-}\ndiff --git a/drivers/net/octeontx2/otx2_mac.c b/drivers/net/octeontx2/otx2_mac.c\ndeleted file mode 100644\nindex 49a700ca1d..0000000000\n--- a/drivers/net/octeontx2/otx2_mac.c\n+++ /dev/null\n@@ -1,151 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_common.h>\n-\n-#include \"otx2_dev.h\"\n-#include \"otx2_ethdev.h\"\n-\n-int\n-otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct cgx_mac_addr_set_or_get *req;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tint rc;\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev))\n-\t\treturn -ENOTSUP;\n-\n-\tif (otx2_dev_active_vfs(dev))\n-\t\treturn -ENOTSUP;\n-\n-\treq = otx2_mbox_alloc_msg_cgx_mac_addr_set(mbox);\n-\totx2_mbox_memcpy(req->mac_addr, addr->addr_bytes, RTE_ETHER_ADDR_LEN);\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\totx2_err(\"Failed to set mac address in CGX, rc=%d\", rc);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev)\n-{\n-\tstruct cgx_max_dmac_entries_get_rsp *rsp;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tint rc;\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev))\n-\t\treturn 0;\n-\n-\totx2_mbox_alloc_msg_cgx_mac_max_entries_get(mbox);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\treturn rsp->max_dmac_filters;\n-}\n-\n-int\n-otx2_nix_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr,\n-\t\t uint32_t index __rte_unused, uint32_t pool __rte_unused)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct cgx_mac_addr_add_req *req;\n-\tstruct cgx_mac_addr_add_rsp *rsp;\n-\tint rc;\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev))\n-\t\treturn -ENOTSUP;\n-\n-\tif (otx2_dev_active_vfs(dev))\n-\t\treturn -ENOTSUP;\n-\n-\treq = otx2_mbox_alloc_msg_cgx_mac_addr_add(mbox);\n-\totx2_mbox_memcpy(req->mac_addr, addr->addr_bytes, RTE_ETHER_ADDR_LEN);\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to add mac address, rc=%d\", rc);\n-\t\tgoto done;\n-\t}\n-\n-\t/* Enable promiscuous mode at NIX level */\n-\totx2_nix_promisc_config(eth_dev, 1);\n-\tdev->dmac_filter_enable = true;\n-\teth_dev->data->promiscuous = 0;\n-\n-done:\n-\treturn rc;\n-}\n-\n-void\n-otx2_nix_mac_addr_del(struct rte_eth_dev *eth_dev, uint32_t index)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct cgx_mac_addr_del_req *req;\n-\tint rc;\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev))\n-\t\treturn;\n-\n-\treq = otx2_mbox_alloc_msg_cgx_mac_addr_del(mbox);\n-\treq->index = index;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\totx2_err(\"Failed to delete mac address, rc=%d\", rc);\n-}\n-\n-int\n-otx2_nix_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_set_mac_addr *req;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_nix_set_mac_addr(mbox);\n-\totx2_mbox_memcpy(req->mac_addr, addr->addr_bytes, RTE_ETHER_ADDR_LEN);\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to set mac address, rc=%d\", rc);\n-\t\tgoto done;\n-\t}\n-\n-\totx2_mbox_memcpy(dev->mac_addr, addr->addr_bytes, RTE_ETHER_ADDR_LEN);\n-\n-\t/* Install the same entry into CGX DMAC filter table too. */\n-\totx2_cgx_mac_addr_set(eth_dev, addr);\n-\n-done:\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_mac_addr_get(struct rte_eth_dev *eth_dev, uint8_t *addr)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_get_mac_addr_rsp *rsp;\n-\tint rc;\n-\n-\totx2_mbox_alloc_msg_nix_get_mac_addr(mbox);\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_get_rsp(mbox, 0, (void *)&rsp);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to get mac address, rc=%d\", rc);\n-\t\tgoto done;\n-\t}\n-\n-\totx2_mbox_memcpy(addr, rsp->mac_addr, RTE_ETHER_ADDR_LEN);\n-\n-done:\n-\treturn rc;\n-}\ndiff --git a/drivers/net/octeontx2/otx2_mcast.c b/drivers/net/octeontx2/otx2_mcast.c\ndeleted file mode 100644\nindex b9c63ad3bc..0000000000\n--- a/drivers/net/octeontx2/otx2_mcast.c\n+++ /dev/null\n@@ -1,339 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_ethdev.h\"\n-\n-static int\n-nix_mc_addr_list_free(struct otx2_eth_dev *dev, uint32_t entry_count)\n-{\n-\tstruct npc_mcam_free_entry_req *req;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct mcast_entry *entry;\n-\tint rc = 0;\n-\n-\tif (entry_count == 0)\n-\t\tgoto exit;\n-\n-\tTAILQ_FOREACH(entry, &dev->mc_fltr_tbl, next) {\n-\t\treq = otx2_mbox_alloc_msg_npc_mcam_free_entry(mbox);\n-\t\treq->entry = entry->mcam_index;\n-\n-\t\trc = otx2_mbox_process_msg(mbox, NULL);\n-\t\tif (rc < 0)\n-\t\t\tgoto exit;\n-\n-\t\tTAILQ_REMOVE(&dev->mc_fltr_tbl, entry, next);\n-\t\trte_free(entry);\n-\t\tentry_count--;\n-\n-\t\tif (entry_count == 0)\n-\t\t\tbreak;\n-\t}\n-\n-\tif (entry == NULL)\n-\t\tdev->mc_tbl_set = false;\n-\n-exit:\n-\treturn rc;\n-}\n-\n-static int\n-nix_hw_update_mc_addr_list(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_npc_flow_info *npc = &dev->npc_flow;\n-\tvolatile uint8_t *key_data, *key_mask;\n-\tstruct npc_mcam_write_entry_req *req;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct npc_xtract_info *x_info;\n-\tuint64_t mcam_data, mcam_mask;\n-\tstruct mcast_entry *entry;\n-\totx2_dxcfg_t *ld_cfg;\n-\tuint8_t *mac_addr;\n-\tuint64_t action;\n-\tint idx, rc = 0;\n-\n-\tld_cfg = &npc->prx_dxcfg;\n-\t/* Get ETH layer profile info for populating mcam entries */\n-\tx_info = &(*ld_cfg)[NPC_MCAM_RX][NPC_LID_LA][NPC_LT_LA_ETHER].xtract[0];\n-\n-\tTAILQ_FOREACH(entry, &dev->mc_fltr_tbl, next) {\n-\t\treq = otx2_mbox_alloc_msg_npc_mcam_write_entry(mbox);\n-\t\tif (req == NULL) {\n-\t\t\t/* The mbox memory buffer can be full.\n-\t\t\t * Flush it and retry\n-\t\t\t */\n-\t\t\totx2_mbox_msg_send(mbox, 0);\n-\t\t\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\t\t\tif (rc < 0)\n-\t\t\t\tgoto exit;\n-\n-\t\t\treq = otx2_mbox_alloc_msg_npc_mcam_write_entry(mbox);\n-\t\t\tif (req == NULL) {\n-\t\t\t\trc = -ENOMEM;\n-\t\t\t\tgoto exit;\n-\t\t\t}\n-\t\t}\n-\t\treq->entry = entry->mcam_index;\n-\t\treq->intf = NPC_MCAM_RX;\n-\t\treq->enable_entry = 1;\n-\n-\t\t/* Channel base extracted to KW0[11:0] */\n-\t\treq->entry_data.kw[0] = dev->rx_chan_base;\n-\t\treq->entry_data.kw_mask[0] = RTE_LEN2MASK(12, uint64_t);\n-\n-\t\t/* Update mcam address */\n-\t\tkey_data = (volatile uint8_t *)req->entry_data.kw;\n-\t\tkey_mask = (volatile uint8_t *)req->entry_data.kw_mask;\n-\n-\t\tmcam_data = 0ull;\n-\t\tmcam_mask = RTE_LEN2MASK(48, uint64_t);\n-\t\tmac_addr = &entry->mcast_mac.addr_bytes[0];\n-\t\tfor (idx = RTE_ETHER_ADDR_LEN - 1; idx >= 0; idx--)\n-\t\t\tmcam_data |= ((uint64_t)*mac_addr++) << (8 * idx);\n-\n-\t\totx2_mbox_memcpy(key_data + x_info->key_off,\n-\t\t\t\t &mcam_data, x_info->len);\n-\t\totx2_mbox_memcpy(key_mask + x_info->key_off,\n-\t\t\t\t &mcam_mask, x_info->len);\n-\n-\t\taction = NIX_RX_ACTIONOP_UCAST;\n-\n-\t\tif (eth_dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {\n-\t\t\taction = NIX_RX_ACTIONOP_RSS;\n-\t\t\taction |= (uint64_t)(dev->rss_info.alg_idx) << 56;\n-\t\t}\n-\n-\t\taction |= ((uint64_t)otx2_pfvf_func(dev->pf, dev->vf)) << 4;\n-\t\treq->entry_data.action = action;\n-\t}\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\n-exit:\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_mc_addr_list_install(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct npc_mcam_alloc_entry_req *req;\n-\tstruct npc_mcam_alloc_entry_rsp *rsp;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tuint32_t entry_count = 0, idx = 0;\n-\tstruct mcast_entry *entry;\n-\tint rc = 0;\n-\n-\tif (!dev->mc_tbl_set)\n-\t\treturn 0;\n-\n-\tTAILQ_FOREACH(entry, &dev->mc_fltr_tbl, next)\n-\t\tentry_count++;\n-\n-\treq = otx2_mbox_alloc_msg_npc_mcam_alloc_entry(mbox);\n-\treq->priority = NPC_MCAM_ANY_PRIO;\n-\treq->count = entry_count;\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc || rsp->count < entry_count) {\n-\t\totx2_err(\"Failed to allocate required mcam entries\");\n-\t\tgoto exit;\n-\t}\n-\n-\tTAILQ_FOREACH(entry, &dev->mc_fltr_tbl, next)\n-\t\tentry->mcam_index = rsp->entry_list[idx];\n-\n-\trc = nix_hw_update_mc_addr_list(eth_dev);\n-\n-exit:\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_mc_addr_list_uninstall(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct npc_mcam_free_entry_req *req;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct mcast_entry *entry;\n-\tint rc = 0;\n-\n-\tif (!dev->mc_tbl_set)\n-\t\treturn 0;\n-\n-\tTAILQ_FOREACH(entry, &dev->mc_fltr_tbl, next) {\n-\t\treq = otx2_mbox_alloc_msg_npc_mcam_free_entry(mbox);\n-\t\tif (req == NULL) {\n-\t\t\totx2_mbox_msg_send(mbox, 0);\n-\t\t\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\t\t\tif (rc < 0)\n-\t\t\t\tgoto exit;\n-\n-\t\t\treq = otx2_mbox_alloc_msg_npc_mcam_free_entry(mbox);\n-\t\t\tif (req == NULL) {\n-\t\t\t\trc = -ENOMEM;\n-\t\t\t\tgoto exit;\n-\t\t\t}\n-\t\t}\n-\t\treq->entry = entry->mcam_index;\n-\t}\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\n-exit:\n-\treturn rc;\n-}\n-\n-static int\n-nix_setup_mc_addr_list(struct otx2_eth_dev *dev,\n-\t\t struct rte_ether_addr *mc_addr_set)\n-{\n-\tstruct npc_mcam_ena_dis_entry_req *req;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct mcast_entry *entry;\n-\tuint32_t idx = 0;\n-\tint rc = 0;\n-\n-\t/* Populate PMD's mcast list with given mcast mac addresses and\n-\t * disable all mcam entries pertaining to the mcast list.\n-\t */\n-\tTAILQ_FOREACH(entry, &dev->mc_fltr_tbl, next) {\n-\t\trte_memcpy(&entry->mcast_mac, &mc_addr_set[idx++],\n-\t\t\t RTE_ETHER_ADDR_LEN);\n-\n-\t\treq = otx2_mbox_alloc_msg_npc_mcam_dis_entry(mbox);\n-\t\tif (req == NULL) {\n-\t\t\totx2_mbox_msg_send(mbox, 0);\n-\t\t\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\t\t\tif (rc < 0)\n-\t\t\t\tgoto exit;\n-\n-\t\t\treq = otx2_mbox_alloc_msg_npc_mcam_dis_entry(mbox);\n-\t\t\tif (req == NULL) {\n-\t\t\t\trc = -ENOMEM;\n-\t\t\t\tgoto exit;\n-\t\t\t}\n-\t\t}\n-\t\treq->entry = entry->mcam_index;\n-\t}\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\n-exit:\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_set_mc_addr_list(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_ether_addr *mc_addr_set,\n-\t\t\t uint32_t nb_mc_addr)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct npc_mcam_alloc_entry_req *req;\n-\tstruct npc_mcam_alloc_entry_rsp *rsp;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tuint32_t idx, priv_count = 0;\n-\tstruct mcast_entry *entry;\n-\tint rc = 0;\n-\n-\tif (otx2_dev_is_vf(dev))\n-\t\treturn -ENOTSUP;\n-\n-\tTAILQ_FOREACH(entry, &dev->mc_fltr_tbl, next)\n-\t\tpriv_count++;\n-\n-\tif (nb_mc_addr == 0 || mc_addr_set == NULL) {\n-\t\t/* Free existing list if new list is null */\n-\t\tnb_mc_addr = priv_count;\n-\t\tgoto exit;\n-\t}\n-\n-\tfor (idx = 0; idx < nb_mc_addr; idx++) {\n-\t\tif (!rte_is_multicast_ether_addr(&mc_addr_set[idx]))\n-\t\t\treturn -EINVAL;\n-\t}\n-\n-\t/* New list is bigger than the existing list,\n-\t * allocate mcam entries for the extra entries.\n-\t */\n-\tif (nb_mc_addr > priv_count) {\n-\t\treq = otx2_mbox_alloc_msg_npc_mcam_alloc_entry(mbox);\n-\t\treq->priority = NPC_MCAM_ANY_PRIO;\n-\t\treq->count = nb_mc_addr - priv_count;\n-\n-\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc || (rsp->count + priv_count < nb_mc_addr)) {\n-\t\t\totx2_err(\"Failed to allocate required entries\");\n-\t\t\tnb_mc_addr = priv_count;\n-\t\t\tgoto exit;\n-\t\t}\n-\n-\t\t/* Append new mcam entries to the existing mc list */\n-\t\tfor (idx = 0; idx < rsp->count; idx++) {\n-\t\t\tentry = rte_zmalloc(\"otx2_nix_mc_entry\",\n-\t\t\t\t\t sizeof(struct mcast_entry), 0);\n-\t\t\tif (!entry) {\n-\t\t\t\totx2_err(\"Failed to allocate memory\");\n-\t\t\t\tnb_mc_addr = priv_count;\n-\t\t\t\trc = -ENOMEM;\n-\t\t\t\tgoto exit;\n-\t\t\t}\n-\t\t\tentry->mcam_index = rsp->entry_list[idx];\n-\t\t\tTAILQ_INSERT_HEAD(&dev->mc_fltr_tbl, entry, next);\n-\t\t}\n-\t} else {\n-\t\t/* Free the extra mcam entries if the new list is smaller\n-\t\t * than exiting list.\n-\t\t */\n-\t\tnix_mc_addr_list_free(dev, priv_count - nb_mc_addr);\n-\t}\n-\n-\n-\t/* Now mc_fltr_tbl has the required number of mcam entries,\n-\t * Traverse through it and add new multicast filter table entries.\n-\t */\n-\trc = nix_setup_mc_addr_list(dev, mc_addr_set);\n-\tif (rc < 0)\n-\t\tgoto exit;\n-\n-\trc = nix_hw_update_mc_addr_list(eth_dev);\n-\tif (rc < 0)\n-\t\tgoto exit;\n-\n-\tdev->mc_tbl_set = true;\n-\n-\treturn 0;\n-\n-exit:\n-\tnix_mc_addr_list_free(dev, nb_mc_addr);\n-\treturn rc;\n-}\n-\n-void\n-otx2_nix_mc_filter_init(struct otx2_eth_dev *dev)\n-{\n-\tif (otx2_dev_is_vf(dev))\n-\t\treturn;\n-\n-\tTAILQ_INIT(&dev->mc_fltr_tbl);\n-}\n-\n-void\n-otx2_nix_mc_filter_fini(struct otx2_eth_dev *dev)\n-{\n-\tstruct mcast_entry *entry;\n-\tuint32_t count = 0;\n-\n-\tif (otx2_dev_is_vf(dev))\n-\t\treturn;\n-\n-\tTAILQ_FOREACH(entry, &dev->mc_fltr_tbl, next)\n-\t\tcount++;\n-\n-\tnix_mc_addr_list_free(dev, count);\n-}\ndiff --git a/drivers/net/octeontx2/otx2_ptp.c b/drivers/net/octeontx2/otx2_ptp.c\ndeleted file mode 100644\nindex abb2130587..0000000000\n--- a/drivers/net/octeontx2/otx2_ptp.c\n+++ /dev/null\n@@ -1,450 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <ethdev_driver.h>\n-\n-#include \"otx2_ethdev.h\"\n-\n-#define PTP_FREQ_ADJUST (1 << 9)\n-\n-/* Function to enable ptp config for VFs */\n-void\n-otx2_nix_ptp_enable_vf(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tif (otx2_nix_recalc_mtu(eth_dev))\n-\t\totx2_err(\"Failed to set MTU size for ptp\");\n-\n-\tdev->scalar_ena = true;\n-\tdev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;\n-\n-\t/* Setting up the function pointers as per new offload flags */\n-\totx2_eth_set_rx_function(eth_dev);\n-\totx2_eth_set_tx_function(eth_dev);\n-}\n-\n-static uint16_t\n-nix_eth_ptp_vf_burst(void *queue, struct rte_mbuf **mbufs, uint16_t pkts)\n-{\n-\tstruct otx2_eth_rxq *rxq = queue;\n-\tstruct rte_eth_dev *eth_dev;\n-\n-\tRTE_SET_USED(mbufs);\n-\tRTE_SET_USED(pkts);\n-\n-\teth_dev = rxq->eth_dev;\n-\totx2_nix_ptp_enable_vf(eth_dev);\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_read_raw_clock(struct otx2_eth_dev *dev, uint64_t *clock, uint64_t *tsc,\n-\t\t uint8_t is_pmu)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct ptp_req *req;\n-\tstruct ptp_rsp *rsp;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_ptp_op(mbox);\n-\treq->op = PTP_OP_GET_CLOCK;\n-\treq->is_pmu = is_pmu;\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\tgoto fail;\n-\n-\tif (clock)\n-\t\t*clock = rsp->clk;\n-\tif (tsc)\n-\t\t*tsc = rsp->tsc;\n-\n-fail:\n-\treturn rc;\n-}\n-\n-/* This function calculates two parameters \"clk_freq_mult\" and\n- * \"clk_delta\" which is useful in deriving PTP HI clock from\n- * timestamp counter (tsc) value.\n- */\n-int\n-otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev)\n-{\n-\tuint64_t ticks_base = 0, ticks = 0, tsc = 0, t_freq;\n-\tint rc, val;\n-\n-\t/* Calculating the frequency at which PTP HI clock is running */\n-\trc = nix_read_raw_clock(dev, &ticks_base, &tsc, false);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to read the raw clock value: %d\", rc);\n-\t\tgoto fail;\n-\t}\n-\n-\trte_delay_ms(100);\n-\n-\trc = nix_read_raw_clock(dev, &ticks, &tsc, false);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to read the raw clock value: %d\", rc);\n-\t\tgoto fail;\n-\t}\n-\n-\tt_freq = (ticks - ticks_base) * 10;\n-\n-\t/* Calculating the freq multiplier viz the ratio between the\n-\t * frequency at which PTP HI clock works and tsc clock runs\n-\t */\n-\tdev->clk_freq_mult =\n-\t\t(double)pow(10, floor(log10(t_freq))) / rte_get_timer_hz();\n-\n-\tval = false;\n-#ifdef RTE_ARM_EAL_RDTSC_USE_PMU\n-\tval = true;\n-#endif\n-\trc = nix_read_raw_clock(dev, &ticks, &tsc, val);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to read the raw clock value: %d\", rc);\n-\t\tgoto fail;\n-\t}\n-\n-\t/* Calculating delta between PTP HI clock and tsc */\n-\tdev->clk_delta = ((uint64_t)(ticks / dev->clk_freq_mult) - tsc);\n-\n-fail:\n-\treturn rc;\n-}\n-\n-static void\n-nix_start_timecounters(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tmemset(&dev->systime_tc, 0, sizeof(struct rte_timecounter));\n-\tmemset(&dev->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));\n-\tmemset(&dev->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));\n-\n-\tdev->systime_tc.cc_mask = OTX2_CYCLECOUNTER_MASK;\n-\tdev->rx_tstamp_tc.cc_mask = OTX2_CYCLECOUNTER_MASK;\n-\tdev->tx_tstamp_tc.cc_mask = OTX2_CYCLECOUNTER_MASK;\n-}\n-\n-static int\n-nix_ptp_config(struct rte_eth_dev *eth_dev, int en)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tuint8_t rc = -EINVAL;\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev) || otx2_dev_is_lbk(dev))\n-\t\treturn rc;\n-\n-\tif (en) {\n-\t\t/* Enable time stamping of sent PTP packets. */\n-\t\totx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(mbox);\n-\t\trc = otx2_mbox_process(mbox);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"MBOX ptp tx conf enable failed: err %d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t\t/* Enable time stamping of received PTP packets. */\n-\t\totx2_mbox_alloc_msg_cgx_ptp_rx_enable(mbox);\n-\t} else {\n-\t\t/* Disable time stamping of sent PTP packets. */\n-\t\totx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(mbox);\n-\t\trc = otx2_mbox_process(mbox);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"MBOX ptp tx conf disable failed: err %d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t\t/* Disable time stamping of received PTP packets. */\n-\t\totx2_mbox_alloc_msg_cgx_ptp_rx_disable(mbox);\n-\t}\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-int\n-otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en)\n-{\n-\tstruct otx2_eth_dev *otx2_dev = (struct otx2_eth_dev *)dev;\n-\tstruct rte_eth_dev *eth_dev;\n-\tint i;\n-\n-\tif (!dev)\n-\t\treturn -EINVAL;\n-\n-\teth_dev = otx2_dev->eth_dev;\n-\tif (!eth_dev)\n-\t\treturn -EINVAL;\n-\n-\totx2_dev->ptp_en = ptp_en;\n-\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n-\t\tstruct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[i];\n-\t\trxq->mbuf_initializer =\n-\t\t\totx2_nix_rxq_mbuf_setup(otx2_dev,\n-\t\t\t\t\t\teth_dev->data->port_id);\n-\t}\n-\tif (otx2_dev_is_vf(otx2_dev) && !(otx2_dev_is_sdp(otx2_dev)) &&\n-\t !(otx2_dev_is_lbk(otx2_dev))) {\n-\t\t/* In case of VF, setting of MTU cant be done directly in this\n-\t\t * function as this is running as part of MBOX request(PF->VF)\n-\t\t * and MTU setting also requires MBOX message to be\n-\t\t * sent(VF->PF)\n-\t\t */\n-\t\teth_dev->rx_pkt_burst = nix_eth_ptp_vf_burst;\n-\t\trte_mb();\n-\t}\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint i, rc = 0;\n-\n-\t/* If we are VF/SDP/LBK, ptp cannot not be enabled */\n-\tif (otx2_dev_is_vf_or_sdp(dev) || otx2_dev_is_lbk(dev)) {\n-\t\totx2_info(\"PTP cannot be enabled in case of VF/SDP/LBK\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (otx2_ethdev_is_ptp_en(dev)) {\n-\t\totx2_info(\"PTP mode is already enabled\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)) {\n-\t\totx2_err(\"Ptype offload is disabled, it should be enabled\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {\n-\t\totx2_err(\"Both PTP and switch header enabled\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Allocating a iova address for tx tstamp */\n-\tconst struct rte_memzone *ts;\n-\tts = rte_eth_dma_zone_reserve(eth_dev, \"otx2_ts\",\n-\t\t\t\t 0, OTX2_ALIGN, OTX2_ALIGN,\n-\t\t\t\t dev->node);\n-\tif (ts == NULL) {\n-\t\totx2_err(\"Failed to allocate mem for tx tstamp addr\");\n-\t\treturn -ENOMEM;\n-\t}\n-\n-\tdev->tstamp.tx_tstamp_iova = ts->iova;\n-\tdev->tstamp.tx_tstamp = ts->addr;\n-\n-\trc = rte_mbuf_dyn_rx_timestamp_register(\n-\t\t\t&dev->tstamp.tstamp_dynfield_offset,\n-\t\t\t&dev->tstamp.rx_tstamp_dynflag);\n-\tif (rc != 0) {\n-\t\totx2_err(\"Failed to register Rx timestamp field/flag\");\n-\t\treturn -rte_errno;\n-\t}\n-\n-\t/* System time should be already on by default */\n-\tnix_start_timecounters(eth_dev);\n-\n-\tdev->rx_offloads |= RTE_ETH_RX_OFFLOAD_TIMESTAMP;\n-\tdev->rx_offload_flags |= NIX_RX_OFFLOAD_TSTAMP_F;\n-\tdev->tx_offload_flags |= NIX_TX_OFFLOAD_TSTAMP_F;\n-\n-\trc = nix_ptp_config(eth_dev, 1);\n-\tif (!rc) {\n-\t\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n-\t\t\tstruct otx2_eth_txq *txq = eth_dev->data->tx_queues[i];\n-\t\t\totx2_nix_form_default_desc(txq);\n-\t\t}\n-\n-\t\t/* Setting up the function pointers as per new offload flags */\n-\t\totx2_eth_set_rx_function(eth_dev);\n-\t\totx2_eth_set_tx_function(eth_dev);\n-\t}\n-\n-\trc = otx2_nix_recalc_mtu(eth_dev);\n-\tif (rc)\n-\t\totx2_err(\"Failed to set MTU size for ptp\");\n-\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_timesync_disable(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint i, rc = 0;\n-\n-\tif (!otx2_ethdev_is_ptp_en(dev)) {\n-\t\totx2_nix_dbg(\"PTP mode is disabled\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (otx2_dev_is_vf_or_sdp(dev) || otx2_dev_is_lbk(dev))\n-\t\treturn -EINVAL;\n-\n-\tdev->rx_offloads &= ~RTE_ETH_RX_OFFLOAD_TIMESTAMP;\n-\tdev->rx_offload_flags &= ~NIX_RX_OFFLOAD_TSTAMP_F;\n-\tdev->tx_offload_flags &= ~NIX_TX_OFFLOAD_TSTAMP_F;\n-\n-\trc = nix_ptp_config(eth_dev, 0);\n-\tif (!rc) {\n-\t\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n-\t\t\tstruct otx2_eth_txq *txq = eth_dev->data->tx_queues[i];\n-\t\t\totx2_nix_form_default_desc(txq);\n-\t\t}\n-\n-\t\t/* Setting up the function pointers as per new offload flags */\n-\t\totx2_eth_set_rx_function(eth_dev);\n-\t\totx2_eth_set_tx_function(eth_dev);\n-\t}\n-\n-\trc = otx2_nix_recalc_mtu(eth_dev);\n-\tif (rc)\n-\t\totx2_err(\"Failed to set MTU size for ptp\");\n-\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev,\n-\t\t\t\t struct timespec *timestamp,\n-\t\t\t\t uint32_t __rte_unused flags)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_timesync_info *tstamp = &dev->tstamp;\n-\tuint64_t ns;\n-\n-\tif (!tstamp->rx_ready)\n-\t\treturn -EINVAL;\n-\n-\tns = rte_timecounter_update(&dev->rx_tstamp_tc, tstamp->rx_tstamp);\n-\t*timestamp = rte_ns_to_timespec(ns);\n-\ttstamp->rx_ready = 0;\n-\n-\totx2_nix_dbg(\"rx timestamp: %\"PRIu64\" sec: %\"PRIu64\" nsec %\"PRIu64\"\",\n-\t\t (uint64_t)tstamp->rx_tstamp, (uint64_t)timestamp->tv_sec,\n-\t\t (uint64_t)timestamp->tv_nsec);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev,\n-\t\t\t\t struct timespec *timestamp)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_timesync_info *tstamp = &dev->tstamp;\n-\tuint64_t ns;\n-\n-\tif (*tstamp->tx_tstamp == 0)\n-\t\treturn -EINVAL;\n-\n-\tns = rte_timecounter_update(&dev->tx_tstamp_tc, *tstamp->tx_tstamp);\n-\t*timestamp = rte_ns_to_timespec(ns);\n-\n-\totx2_nix_dbg(\"tx timestamp: %\"PRIu64\" sec: %\"PRIu64\" nsec %\"PRIu64\"\",\n-\t\t *tstamp->tx_tstamp, (uint64_t)timestamp->tv_sec,\n-\t\t (uint64_t)timestamp->tv_nsec);\n-\n-\t*tstamp->tx_tstamp = 0;\n-\trte_wmb();\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct ptp_req *req;\n-\tstruct ptp_rsp *rsp;\n-\tint rc;\n-\n-\t/* Adjust the frequent to make tics increments in 10^9 tics per sec */\n-\tif (delta < PTP_FREQ_ADJUST && delta > -PTP_FREQ_ADJUST) {\n-\t\treq = otx2_mbox_alloc_msg_ptp_op(mbox);\n-\t\treq->op = PTP_OP_ADJFINE;\n-\t\treq->scaled_ppm = delta;\n-\n-\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\t\t/* Since the frequency of PTP comp register is tuned, delta and\n-\t\t * freq mult calculation for deriving PTP_HI from timestamp\n-\t\t * counter should be done again.\n-\t\t */\n-\t\trc = otx2_nix_raw_clock_tsc_conv(dev);\n-\t\tif (rc)\n-\t\t\totx2_err(\"Failed to calculate delta and freq mult\");\n-\t}\n-\tdev->systime_tc.nsec += delta;\n-\tdev->rx_tstamp_tc.nsec += delta;\n-\tdev->tx_tstamp_tc.nsec += delta;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_timesync_write_time(struct rte_eth_dev *eth_dev,\n-\t\t\t const struct timespec *ts)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint64_t ns;\n-\n-\tns = rte_timespec_to_ns(ts);\n-\t/* Set the time counters to a new value. */\n-\tdev->systime_tc.nsec = ns;\n-\tdev->rx_tstamp_tc.nsec = ns;\n-\tdev->tx_tstamp_tc.nsec = ns;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev, struct timespec *ts)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct ptp_req *req;\n-\tstruct ptp_rsp *rsp;\n-\tuint64_t ns;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_ptp_op(mbox);\n-\treq->op = PTP_OP_GET_CLOCK;\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tns = rte_timecounter_update(&dev->systime_tc, rsp->clk);\n-\t*ts = rte_ns_to_timespec(ns);\n-\n-\totx2_nix_dbg(\"PTP time read: %\"PRIu64\" .%09\"PRIu64\"\",\n-\t\t (uint64_t)ts->tv_sec, (uint64_t)ts->tv_nsec);\n-\n-\treturn 0;\n-}\n-\n-\n-int\n-otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\t/* This API returns the raw PTP HI clock value. Since LFs doesn't\n-\t * have direct access to PTP registers and it requires mbox msg\n-\t * to AF for this value. In fastpath reading this value for every\n-\t * packet (which involes mbox call) becomes very expensive, hence\n-\t * we should be able to derive PTP HI clock value from tsc by\n-\t * using freq_mult and clk_delta calculated during configure stage.\n-\t */\n-\t*clock = (rte_get_tsc_cycles() + dev->clk_delta) * dev->clk_freq_mult;\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/net/octeontx2/otx2_rss.c b/drivers/net/octeontx2/otx2_rss.c\ndeleted file mode 100644\nindex 68cef1caa3..0000000000\n--- a/drivers/net/octeontx2/otx2_rss.c\n+++ /dev/null\n@@ -1,427 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include \"otx2_ethdev.h\"\n-\n-int\n-otx2_nix_rss_tbl_init(struct otx2_eth_dev *dev,\n-\t\t uint8_t group, uint16_t *ind_tbl)\n-{\n-\tstruct otx2_rss_info *rss = &dev->rss_info;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_aq_enq_req *req;\n-\tint rc, idx;\n-\n-\tfor (idx = 0; idx < rss->rss_size; idx++) {\n-\t\treq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!req) {\n-\t\t\t/* The shared memory buffer can be full.\n-\t\t\t * Flush it and retry\n-\t\t\t */\n-\t\t\totx2_mbox_msg_send(mbox, 0);\n-\t\t\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\t\t\tif (rc < 0)\n-\t\t\t\treturn rc;\n-\n-\t\t\treq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\t\tif (!req)\n-\t\t\t\treturn -ENOMEM;\n-\t\t}\n-\t\treq->rss.rq = ind_tbl[idx];\n-\t\t/* Fill AQ info */\n-\t\treq->qidx = (group * rss->rss_size) + idx;\n-\t\treq->ctype = NIX_AQ_CTYPE_RSS;\n-\t\treq->op = NIX_AQ_INSTOP_INIT;\n-\n-\t\tif (!dev->lock_rx_ctx)\n-\t\t\tcontinue;\n-\n-\t\treq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\tif (!req) {\n-\t\t\t/* The shared memory buffer can be full.\n-\t\t\t * Flush it and retry\n-\t\t\t */\n-\t\t\totx2_mbox_msg_send(mbox, 0);\n-\t\t\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\t\t\tif (rc < 0)\n-\t\t\t\treturn rc;\n-\n-\t\t\treq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\t\tif (!req)\n-\t\t\t\treturn -ENOMEM;\n-\t\t}\n-\t\treq->rss.rq = ind_tbl[idx];\n-\t\t/* Fill AQ info */\n-\t\treq->qidx = (group * rss->rss_size) + idx;\n-\t\treq->ctype = NIX_AQ_CTYPE_RSS;\n-\t\treq->op = NIX_AQ_INSTOP_LOCK;\n-\t}\n-\n-\totx2_mbox_msg_send(mbox, 0);\n-\trc = otx2_mbox_wait_for_rsp(mbox, 0);\n-\tif (rc < 0)\n-\t\treturn rc;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_dev_reta_update(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n-\t\t\t uint16_t reta_size)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_rss_info *rss = &dev->rss_info;\n-\tint rc, i, j;\n-\tint idx = 0;\n-\n-\trc = -EINVAL;\n-\tif (reta_size != dev->rss_info.rss_size) {\n-\t\totx2_err(\"Size of hash lookup table configured \"\n-\t\t\"(%d) doesn't match the number hardware can supported \"\n-\t\t\"(%d)\", reta_size, dev->rss_info.rss_size);\n-\t\tgoto fail;\n-\t}\n-\n-\t/* Copy RETA table */\n-\tfor (i = 0; i < (dev->rss_info.rss_size / RTE_ETH_RETA_GROUP_SIZE); i++) {\n-\t\tfor (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) {\n-\t\t\tif ((reta_conf[i].mask >> j) & 0x01)\n-\t\t\t\trss->ind_tbl[idx] = reta_conf[i].reta[j];\n-\t\t\tidx++;\n-\t\t}\n-\t}\n-\n-\treturn otx2_nix_rss_tbl_init(dev, 0, dev->rss_info.ind_tbl);\n-\n-fail:\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_dev_reta_query(struct rte_eth_dev *eth_dev,\n-\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n-\t\t\tuint16_t reta_size)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_rss_info *rss = &dev->rss_info;\n-\tint rc, i, j;\n-\n-\trc = -EINVAL;\n-\n-\tif (reta_size != dev->rss_info.rss_size) {\n-\t\totx2_err(\"Size of hash lookup table configured \"\n-\t\t\t\"(%d) doesn't match the number hardware can supported \"\n-\t\t\t\"(%d)\", reta_size, dev->rss_info.rss_size);\n-\t\tgoto fail;\n-\t}\n-\n-\t/* Copy RETA table */\n-\tfor (i = 0; i < (dev->rss_info.rss_size / RTE_ETH_RETA_GROUP_SIZE); i++) {\n-\t\tfor (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++)\n-\t\t\tif ((reta_conf[i].mask >> j) & 0x01)\n-\t\t\t\treta_conf[i].reta[j] = rss->ind_tbl[j];\n-\t}\n-\n-\treturn 0;\n-\n-fail:\n-\treturn rc;\n-}\n-\n-void\n-otx2_nix_rss_set_key(struct otx2_eth_dev *dev, uint8_t *key,\n-\t\t uint32_t key_len)\n-{\n-\tconst uint8_t default_key[NIX_HASH_KEY_SIZE] = {\n-\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,\n-\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,\n-\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,\n-\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,\n-\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD,\n-\t\t0xFE, 0xED, 0x0B, 0xAD, 0xFE, 0xED, 0x0B, 0xAD\n-\t};\n-\tstruct otx2_rss_info *rss = &dev->rss_info;\n-\tuint64_t *keyptr;\n-\tuint64_t val;\n-\tuint32_t idx;\n-\n-\tif (key == NULL || key == 0) {\n-\t\tkeyptr = (uint64_t *)(uintptr_t)default_key;\n-\t\tkey_len = NIX_HASH_KEY_SIZE;\n-\t\tmemset(rss->key, 0, key_len);\n-\t} else {\n-\t\tmemcpy(rss->key, key, key_len);\n-\t\tkeyptr = (uint64_t *)rss->key;\n-\t}\n-\n-\tfor (idx = 0; idx < (key_len >> 3); idx++) {\n-\t\tval = rte_cpu_to_be_64(*keyptr);\n-\t\totx2_write64(val, dev->base + NIX_LF_RX_SECRETX(idx));\n-\t\tkeyptr++;\n-\t}\n-}\n-\n-static void\n-rss_get_key(struct otx2_eth_dev *dev, uint8_t *key)\n-{\n-\tuint64_t *keyptr = (uint64_t *)key;\n-\tuint64_t val;\n-\tint idx;\n-\n-\tfor (idx = 0; idx < (NIX_HASH_KEY_SIZE >> 3); idx++) {\n-\t\tval = otx2_read64(dev->base + NIX_LF_RX_SECRETX(idx));\n-\t\t*keyptr = rte_be_to_cpu_64(val);\n-\t\tkeyptr++;\n-\t}\n-}\n-\n-#define RSS_IPV4_ENABLE ( \\\n-\t\t\t RTE_ETH_RSS_IPV4 | \\\n-\t\t\t RTE_ETH_RSS_FRAG_IPV4 | \\\n-\t\t\t RTE_ETH_RSS_NONFRAG_IPV4_UDP | \\\n-\t\t\t RTE_ETH_RSS_NONFRAG_IPV4_TCP | \\\n-\t\t\t RTE_ETH_RSS_NONFRAG_IPV4_SCTP)\n-\n-#define RSS_IPV6_ENABLE ( \\\n-\t\t\t RTE_ETH_RSS_IPV6 | \\\n-\t\t\t RTE_ETH_RSS_FRAG_IPV6 | \\\n-\t\t\t RTE_ETH_RSS_NONFRAG_IPV6_UDP | \\\n-\t\t\t RTE_ETH_RSS_NONFRAG_IPV6_TCP | \\\n-\t\t\t RTE_ETH_RSS_NONFRAG_IPV6_SCTP)\n-\n-#define RSS_IPV6_EX_ENABLE ( \\\n-\t\t\t RTE_ETH_RSS_IPV6_EX | \\\n-\t\t\t RTE_ETH_RSS_IPV6_TCP_EX | \\\n-\t\t\t RTE_ETH_RSS_IPV6_UDP_EX)\n-\n-#define RSS_MAX_LEVELS 3\n-\n-#define RSS_IPV4_INDEX 0\n-#define RSS_IPV6_INDEX 1\n-#define RSS_TCP_INDEX 2\n-#define RSS_UDP_INDEX 3\n-#define RSS_SCTP_INDEX 4\n-#define RSS_DMAC_INDEX 5\n-\n-uint32_t\n-otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev, uint64_t ethdev_rss,\n-\t\t uint8_t rss_level)\n-{\n-\tuint32_t flow_key_type[RSS_MAX_LEVELS][6] = {\n-\t\t{\n-\t\t\tFLOW_KEY_TYPE_IPV4, FLOW_KEY_TYPE_IPV6,\n-\t\t\tFLOW_KEY_TYPE_TCP, FLOW_KEY_TYPE_UDP,\n-\t\t\tFLOW_KEY_TYPE_SCTP, FLOW_KEY_TYPE_ETH_DMAC\n-\t\t},\n-\t\t{\n-\t\t\tFLOW_KEY_TYPE_INNR_IPV4, FLOW_KEY_TYPE_INNR_IPV6,\n-\t\t\tFLOW_KEY_TYPE_INNR_TCP, FLOW_KEY_TYPE_INNR_UDP,\n-\t\t\tFLOW_KEY_TYPE_INNR_SCTP, FLOW_KEY_TYPE_INNR_ETH_DMAC\n-\t\t},\n-\t\t{\n-\t\t\tFLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_INNR_IPV4,\n-\t\t\tFLOW_KEY_TYPE_IPV6 | FLOW_KEY_TYPE_INNR_IPV6,\n-\t\t\tFLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_INNR_TCP,\n-\t\t\tFLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_INNR_UDP,\n-\t\t\tFLOW_KEY_TYPE_SCTP | FLOW_KEY_TYPE_INNR_SCTP,\n-\t\t\tFLOW_KEY_TYPE_ETH_DMAC | FLOW_KEY_TYPE_INNR_ETH_DMAC\n-\t\t}\n-\t};\n-\tuint32_t flowkey_cfg = 0;\n-\n-\tdev->rss_info.nix_rss = ethdev_rss;\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_L2_PAYLOAD &&\n-\t dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B) {\n-\t\tflowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;\n-\t}\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_C_VLAN)\n-\t\tflowkey_cfg |= FLOW_KEY_TYPE_VLAN;\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_L3_SRC_ONLY)\n-\t\tflowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_L3_DST_ONLY)\n-\t\tflowkey_cfg |= FLOW_KEY_TYPE_L3_DST;\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_L4_SRC_ONLY)\n-\t\tflowkey_cfg |= FLOW_KEY_TYPE_L4_SRC;\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_L4_DST_ONLY)\n-\t\tflowkey_cfg |= FLOW_KEY_TYPE_L4_DST;\n-\n-\tif (ethdev_rss & RSS_IPV4_ENABLE)\n-\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_IPV4_INDEX];\n-\n-\tif (ethdev_rss & RSS_IPV6_ENABLE)\n-\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_IPV6_INDEX];\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_TCP)\n-\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_TCP_INDEX];\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_UDP)\n-\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_UDP_INDEX];\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_SCTP)\n-\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_SCTP_INDEX];\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_L2_PAYLOAD)\n-\t\tflowkey_cfg |= flow_key_type[rss_level][RSS_DMAC_INDEX];\n-\n-\tif (ethdev_rss & RSS_IPV6_EX_ENABLE)\n-\t\tflowkey_cfg |= FLOW_KEY_TYPE_IPV6_EXT;\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_PORT)\n-\t\tflowkey_cfg |= FLOW_KEY_TYPE_PORT;\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_NVGRE)\n-\t\tflowkey_cfg |= FLOW_KEY_TYPE_NVGRE;\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_VXLAN)\n-\t\tflowkey_cfg |= FLOW_KEY_TYPE_VXLAN;\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_GENEVE)\n-\t\tflowkey_cfg |= FLOW_KEY_TYPE_GENEVE;\n-\n-\tif (ethdev_rss & RTE_ETH_RSS_GTPU)\n-\t\tflowkey_cfg |= FLOW_KEY_TYPE_GTPU;\n-\n-\treturn flowkey_cfg;\n-}\n-\n-int\n-otx2_rss_set_hf(struct otx2_eth_dev *dev, uint32_t flowkey_cfg,\n-\t\tuint8_t *alg_idx, uint8_t group, int mcam_index)\n-{\n-\tstruct nix_rss_flowkey_cfg_rsp *rss_rsp;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_rss_flowkey_cfg *cfg;\n-\tint rc;\n-\n-\trc = -EINVAL;\n-\n-\tdev->rss_info.flowkey_cfg = flowkey_cfg;\n-\n-\tcfg = otx2_mbox_alloc_msg_nix_rss_flowkey_cfg(mbox);\n-\n-\tcfg->flowkey_cfg = flowkey_cfg;\n-\tcfg->mcam_index = mcam_index; /* -1 indicates default group */\n-\tcfg->group = group; /* 0 is default group */\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rss_rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tif (alg_idx)\n-\t\t*alg_idx = rss_rsp->alg_idx;\n-\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_rss_hash_update(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_rss_conf *rss_conf)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint8_t rss_hash_level;\n-\tuint32_t flowkey_cfg;\n-\tuint8_t alg_idx;\n-\tint rc;\n-\n-\trc = -EINVAL;\n-\n-\tif (rss_conf->rss_key && rss_conf->rss_key_len != NIX_HASH_KEY_SIZE) {\n-\t\totx2_err(\"Hash key size mismatch %d vs %d\",\n-\t\t\t rss_conf->rss_key_len, NIX_HASH_KEY_SIZE);\n-\t\tgoto fail;\n-\t}\n-\n-\tif (rss_conf->rss_key)\n-\t\totx2_nix_rss_set_key(dev, rss_conf->rss_key,\n-\t\t\t\t (uint32_t)rss_conf->rss_key_len);\n-\n-\trss_hash_level = RTE_ETH_RSS_LEVEL(rss_conf->rss_hf);\n-\tif (rss_hash_level)\n-\t\trss_hash_level -= 1;\n-\tflowkey_cfg =\n-\t\totx2_rss_ethdev_to_nix(dev, rss_conf->rss_hf, rss_hash_level);\n-\n-\trc = otx2_rss_set_hf(dev, flowkey_cfg, &alg_idx,\n-\t\t\t NIX_DEFAULT_RSS_CTX_GROUP,\n-\t\t\t NIX_DEFAULT_RSS_MCAM_IDX);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to set RSS hash function rc=%d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\tdev->rss_info.alg_idx = alg_idx;\n-\n-fail:\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_rss_hash_conf_get(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_rss_conf *rss_conf)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tif (rss_conf->rss_key)\n-\t\trss_get_key(dev, rss_conf->rss_key);\n-\n-\trss_conf->rss_key_len = NIX_HASH_KEY_SIZE;\n-\trss_conf->rss_hf = dev->rss_info.nix_rss;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_rss_config(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint32_t idx, qcnt = eth_dev->data->nb_rx_queues;\n-\tuint8_t rss_hash_level;\n-\tuint32_t flowkey_cfg;\n-\tuint64_t rss_hf;\n-\tuint8_t alg_idx;\n-\tint rc;\n-\n-\t/* Skip further configuration if selected mode is not RSS */\n-\tif (eth_dev->data->dev_conf.rxmode.mq_mode != RTE_ETH_MQ_RX_RSS || !qcnt)\n-\t\treturn 0;\n-\n-\t/* Update default RSS key and cfg */\n-\totx2_nix_rss_set_key(dev, NULL, 0);\n-\n-\t/* Update default RSS RETA */\n-\tfor (idx = 0; idx < dev->rss_info.rss_size; idx++)\n-\t\tdev->rss_info.ind_tbl[idx] = idx % qcnt;\n-\n-\t/* Init RSS table context */\n-\trc = otx2_nix_rss_tbl_init(dev, 0, dev->rss_info.ind_tbl);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to init RSS table rc=%d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\trss_hf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;\n-\trss_hash_level = RTE_ETH_RSS_LEVEL(rss_hf);\n-\tif (rss_hash_level)\n-\t\trss_hash_level -= 1;\n-\tflowkey_cfg = otx2_rss_ethdev_to_nix(dev, rss_hf, rss_hash_level);\n-\n-\trc = otx2_rss_set_hf(dev, flowkey_cfg, &alg_idx,\n-\t\t\t NIX_DEFAULT_RSS_CTX_GROUP,\n-\t\t\t NIX_DEFAULT_RSS_MCAM_IDX);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to set RSS hash function rc=%d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\tdev->rss_info.alg_idx = alg_idx;\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/net/octeontx2/otx2_rx.c b/drivers/net/octeontx2/otx2_rx.c\ndeleted file mode 100644\nindex 5ee1aed786..0000000000\n--- a/drivers/net/octeontx2/otx2_rx.c\n+++ /dev/null\n@@ -1,430 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_vect.h>\n-\n-#include \"otx2_ethdev.h\"\n-#include \"otx2_rx.h\"\n-\n-#define NIX_DESCS_PER_LOOP\t4\n-#define CQE_CAST(x)\t\t((struct nix_cqe_hdr_s *)(x))\n-#define CQE_SZ(x)\t\t((x) * NIX_CQ_ENTRY_SZ)\n-\n-static inline uint16_t\n-nix_rx_nb_pkts(struct otx2_eth_rxq *rxq, const uint64_t wdata,\n-\t const uint16_t pkts, const uint32_t qmask)\n-{\n-\tuint32_t available = rxq->available;\n-\n-\t/* Update the available count if cached value is not enough */\n-\tif (unlikely(available < pkts)) {\n-\t\tuint64_t reg, head, tail;\n-\n-\t\t/* Use LDADDA version to avoid reorder */\n-\t\treg = otx2_atomic64_add_sync(wdata, rxq->cq_status);\n-\t\t/* CQ_OP_STATUS operation error */\n-\t\tif (reg & BIT_ULL(CQ_OP_STAT_OP_ERR) ||\n-\t\t reg & BIT_ULL(CQ_OP_STAT_CQ_ERR))\n-\t\t\treturn 0;\n-\n-\t\ttail = reg & 0xFFFFF;\n-\t\thead = (reg >> 20) & 0xFFFFF;\n-\t\tif (tail < head)\n-\t\t\tavailable = tail - head + qmask + 1;\n-\t\telse\n-\t\t\tavailable = tail - head;\n-\n-\t\trxq->available = available;\n-\t}\n-\n-\treturn RTE_MIN(pkts, available);\n-}\n-\n-static __rte_always_inline uint16_t\n-nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n-\t uint16_t pkts, const uint16_t flags)\n-{\n-\tstruct otx2_eth_rxq *rxq = rx_queue;\n-\tconst uint64_t mbuf_init = rxq->mbuf_initializer;\n-\tconst void *lookup_mem = rxq->lookup_mem;\n-\tconst uint64_t data_off = rxq->data_off;\n-\tconst uintptr_t desc = rxq->desc;\n-\tconst uint64_t wdata = rxq->wdata;\n-\tconst uint32_t qmask = rxq->qmask;\n-\tuint16_t packets = 0, nb_pkts;\n-\tuint32_t head = rxq->head;\n-\tstruct nix_cqe_hdr_s *cq;\n-\tstruct rte_mbuf *mbuf;\n-\n-\tnb_pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);\n-\n-\twhile (packets < nb_pkts) {\n-\t\t/* Prefetch N desc ahead */\n-\t\trte_prefetch_non_temporal((void *)(desc +\n-\t\t\t\t\t(CQE_SZ((head + 2) & qmask))));\n-\t\tcq = (struct nix_cqe_hdr_s *)(desc + CQE_SZ(head));\n-\n-\t\tmbuf = nix_get_mbuf_from_cqe(cq, data_off);\n-\n-\t\totx2_nix_cqe_to_mbuf(cq, cq->tag, mbuf, lookup_mem, mbuf_init,\n-\t\t\t\t flags);\n-\t\totx2_nix_mbuf_to_tstamp(mbuf, rxq->tstamp, flags,\n-\t\t\t\t(uint64_t *)((uint8_t *)mbuf + data_off));\n-\t\trx_pkts[packets++] = mbuf;\n-\t\totx2_prefetch_store_keep(mbuf);\n-\t\thead++;\n-\t\thead &= qmask;\n-\t}\n-\n-\trxq->head = head;\n-\trxq->available -= nb_pkts;\n-\n-\t/* Free all the CQs that we've processed */\n-\totx2_write64((wdata | nb_pkts), rxq->cq_door);\n-\n-\treturn nb_pkts;\n-}\n-\n-#if defined(RTE_ARCH_ARM64)\n-\n-static __rte_always_inline uint64_t\n-nix_vlan_update(const uint64_t w2, uint64_t ol_flags, uint8x16_t *f)\n-{\n-\tif (w2 & BIT_ULL(21) /* vtag0_gone */) {\n-\t\tol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;\n-\t\t*f = vsetq_lane_u16((uint16_t)(w2 >> 32), *f, 5);\n-\t}\n-\n-\treturn ol_flags;\n-}\n-\n-static __rte_always_inline uint64_t\n-nix_qinq_update(const uint64_t w2, uint64_t ol_flags, struct rte_mbuf *mbuf)\n-{\n-\tif (w2 & BIT_ULL(23) /* vtag1_gone */) {\n-\t\tol_flags |= RTE_MBUF_F_RX_QINQ | RTE_MBUF_F_RX_QINQ_STRIPPED;\n-\t\tmbuf->vlan_tci_outer = (uint16_t)(w2 >> 48);\n-\t}\n-\n-\treturn ol_flags;\n-}\n-\n-static __rte_always_inline uint16_t\n-nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n-\t\t uint16_t pkts, const uint16_t flags)\n-{\n-\tstruct otx2_eth_rxq *rxq = rx_queue; uint16_t packets = 0;\n-\tuint64x2_t cq0_w8, cq1_w8, cq2_w8, cq3_w8, mbuf01, mbuf23;\n-\tconst uint64_t mbuf_initializer = rxq->mbuf_initializer;\n-\tconst uint64x2_t data_off = vdupq_n_u64(rxq->data_off);\n-\tuint64_t ol_flags0, ol_flags1, ol_flags2, ol_flags3;\n-\tuint64x2_t rearm0 = vdupq_n_u64(mbuf_initializer);\n-\tuint64x2_t rearm1 = vdupq_n_u64(mbuf_initializer);\n-\tuint64x2_t rearm2 = vdupq_n_u64(mbuf_initializer);\n-\tuint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer);\n-\tstruct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;\n-\tconst uint16_t *lookup_mem = rxq->lookup_mem;\n-\tconst uint32_t qmask = rxq->qmask;\n-\tconst uint64_t wdata = rxq->wdata;\n-\tconst uintptr_t desc = rxq->desc;\n-\tuint8x16_t f0, f1, f2, f3;\n-\tuint32_t head = rxq->head;\n-\tuint16_t pkts_left;\n-\n-\tpkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);\n-\tpkts_left = pkts & (NIX_DESCS_PER_LOOP - 1);\n-\n-\t/* Packets has to be floor-aligned to NIX_DESCS_PER_LOOP */\n-\tpkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);\n-\n-\twhile (packets < pkts) {\n-\t\t/* Exit loop if head is about to wrap and become unaligned */\n-\t\tif (((head + NIX_DESCS_PER_LOOP - 1) & qmask) <\n-\t\t\t\tNIX_DESCS_PER_LOOP) {\n-\t\t\tpkts_left += (pkts - packets);\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\tconst uintptr_t cq0 = desc + CQE_SZ(head);\n-\n-\t\t/* Prefetch N desc ahead */\n-\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(8)));\n-\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(9)));\n-\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(10)));\n-\t\trte_prefetch_non_temporal((void *)(cq0 + CQE_SZ(11)));\n-\n-\t\t/* Get NIX_RX_SG_S for size and buffer pointer */\n-\t\tcq0_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(0) + 64));\n-\t\tcq1_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(1) + 64));\n-\t\tcq2_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(2) + 64));\n-\t\tcq3_w8 = vld1q_u64((uint64_t *)(cq0 + CQE_SZ(3) + 64));\n-\n-\t\t/* Extract mbuf from NIX_RX_SG_S */\n-\t\tmbuf01 = vzip2q_u64(cq0_w8, cq1_w8);\n-\t\tmbuf23 = vzip2q_u64(cq2_w8, cq3_w8);\n-\t\tmbuf01 = vqsubq_u64(mbuf01, data_off);\n-\t\tmbuf23 = vqsubq_u64(mbuf23, data_off);\n-\n-\t\t/* Move mbufs to scalar registers for future use */\n-\t\tmbuf0 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 0);\n-\t\tmbuf1 = (struct rte_mbuf *)vgetq_lane_u64(mbuf01, 1);\n-\t\tmbuf2 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 0);\n-\t\tmbuf3 = (struct rte_mbuf *)vgetq_lane_u64(mbuf23, 1);\n-\n-\t\t/* Mask to get packet len from NIX_RX_SG_S */\n-\t\tconst uint8x16_t shuf_msk = {\n-\t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n-\t\t\t0xFF, 0xFF, /* pkt_type set as unknown */\n-\t\t\t0, 1, /* octet 1~0, low 16 bits pkt_len */\n-\t\t\t0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */\n-\t\t\t0, 1, /* octet 1~0, 16 bits data_len */\n-\t\t\t0xFF, 0xFF,\n-\t\t\t0xFF, 0xFF, 0xFF, 0xFF\n-\t\t\t};\n-\n-\t\t/* Form the rx_descriptor_fields1 with pkt_len and data_len */\n-\t\tf0 = vqtbl1q_u8(cq0_w8, shuf_msk);\n-\t\tf1 = vqtbl1q_u8(cq1_w8, shuf_msk);\n-\t\tf2 = vqtbl1q_u8(cq2_w8, shuf_msk);\n-\t\tf3 = vqtbl1q_u8(cq3_w8, shuf_msk);\n-\n-\t\t/* Load CQE word0 and word 1 */\n-\t\tuint64_t cq0_w0 = ((uint64_t *)(cq0 + CQE_SZ(0)))[0];\n-\t\tuint64_t cq0_w1 = ((uint64_t *)(cq0 + CQE_SZ(0)))[1];\n-\t\tuint64_t cq1_w0 = ((uint64_t *)(cq0 + CQE_SZ(1)))[0];\n-\t\tuint64_t cq1_w1 = ((uint64_t *)(cq0 + CQE_SZ(1)))[1];\n-\t\tuint64_t cq2_w0 = ((uint64_t *)(cq0 + CQE_SZ(2)))[0];\n-\t\tuint64_t cq2_w1 = ((uint64_t *)(cq0 + CQE_SZ(2)))[1];\n-\t\tuint64_t cq3_w0 = ((uint64_t *)(cq0 + CQE_SZ(3)))[0];\n-\t\tuint64_t cq3_w1 = ((uint64_t *)(cq0 + CQE_SZ(3)))[1];\n-\n-\t\tif (flags & NIX_RX_OFFLOAD_RSS_F) {\n-\t\t\t/* Fill rss in the rx_descriptor_fields1 */\n-\t\t\tf0 = vsetq_lane_u32(cq0_w0, f0, 3);\n-\t\t\tf1 = vsetq_lane_u32(cq1_w0, f1, 3);\n-\t\t\tf2 = vsetq_lane_u32(cq2_w0, f2, 3);\n-\t\t\tf3 = vsetq_lane_u32(cq3_w0, f3, 3);\n-\t\t\tol_flags0 = RTE_MBUF_F_RX_RSS_HASH;\n-\t\t\tol_flags1 = RTE_MBUF_F_RX_RSS_HASH;\n-\t\t\tol_flags2 = RTE_MBUF_F_RX_RSS_HASH;\n-\t\t\tol_flags3 = RTE_MBUF_F_RX_RSS_HASH;\n-\t\t} else {\n-\t\t\tol_flags0 = 0; ol_flags1 = 0;\n-\t\t\tol_flags2 = 0; ol_flags3 = 0;\n-\t\t}\n-\n-\t\tif (flags & NIX_RX_OFFLOAD_PTYPE_F) {\n-\t\t\t/* Fill packet_type in the rx_descriptor_fields1 */\n-\t\t\tf0 = vsetq_lane_u32(nix_ptype_get(lookup_mem, cq0_w1),\n-\t\t\t\t\t f0, 0);\n-\t\t\tf1 = vsetq_lane_u32(nix_ptype_get(lookup_mem, cq1_w1),\n-\t\t\t\t\t f1, 0);\n-\t\t\tf2 = vsetq_lane_u32(nix_ptype_get(lookup_mem, cq2_w1),\n-\t\t\t\t\t f2, 0);\n-\t\t\tf3 = vsetq_lane_u32(nix_ptype_get(lookup_mem, cq3_w1),\n-\t\t\t\t\t f3, 0);\n-\t\t}\n-\n-\t\tif (flags & NIX_RX_OFFLOAD_CHECKSUM_F) {\n-\t\t\tol_flags0 |= nix_rx_olflags_get(lookup_mem, cq0_w1);\n-\t\t\tol_flags1 |= nix_rx_olflags_get(lookup_mem, cq1_w1);\n-\t\t\tol_flags2 |= nix_rx_olflags_get(lookup_mem, cq2_w1);\n-\t\t\tol_flags3 |= nix_rx_olflags_get(lookup_mem, cq3_w1);\n-\t\t}\n-\n-\t\tif (flags & NIX_RX_OFFLOAD_VLAN_STRIP_F) {\n-\t\t\tuint64_t cq0_w2 = *(uint64_t *)(cq0 + CQE_SZ(0) + 16);\n-\t\t\tuint64_t cq1_w2 = *(uint64_t *)(cq0 + CQE_SZ(1) + 16);\n-\t\t\tuint64_t cq2_w2 = *(uint64_t *)(cq0 + CQE_SZ(2) + 16);\n-\t\t\tuint64_t cq3_w2 = *(uint64_t *)(cq0 + CQE_SZ(3) + 16);\n-\n-\t\t\tol_flags0 = nix_vlan_update(cq0_w2, ol_flags0, &f0);\n-\t\t\tol_flags1 = nix_vlan_update(cq1_w2, ol_flags1, &f1);\n-\t\t\tol_flags2 = nix_vlan_update(cq2_w2, ol_flags2, &f2);\n-\t\t\tol_flags3 = nix_vlan_update(cq3_w2, ol_flags3, &f3);\n-\n-\t\t\tol_flags0 = nix_qinq_update(cq0_w2, ol_flags0, mbuf0);\n-\t\t\tol_flags1 = nix_qinq_update(cq1_w2, ol_flags1, mbuf1);\n-\t\t\tol_flags2 = nix_qinq_update(cq2_w2, ol_flags2, mbuf2);\n-\t\t\tol_flags3 = nix_qinq_update(cq3_w2, ol_flags3, mbuf3);\n-\t\t}\n-\n-\t\tif (flags & NIX_RX_OFFLOAD_MARK_UPDATE_F) {\n-\t\t\tol_flags0 = nix_update_match_id(*(uint16_t *)\n-\t\t\t\t (cq0 + CQE_SZ(0) + 38), ol_flags0, mbuf0);\n-\t\t\tol_flags1 = nix_update_match_id(*(uint16_t *)\n-\t\t\t\t (cq0 + CQE_SZ(1) + 38), ol_flags1, mbuf1);\n-\t\t\tol_flags2 = nix_update_match_id(*(uint16_t *)\n-\t\t\t\t (cq0 + CQE_SZ(2) + 38), ol_flags2, mbuf2);\n-\t\t\tol_flags3 = nix_update_match_id(*(uint16_t *)\n-\t\t\t\t (cq0 + CQE_SZ(3) + 38), ol_flags3, mbuf3);\n-\t\t}\n-\n-\t\t/* Form rearm_data with ol_flags */\n-\t\trearm0 = vsetq_lane_u64(ol_flags0, rearm0, 1);\n-\t\trearm1 = vsetq_lane_u64(ol_flags1, rearm1, 1);\n-\t\trearm2 = vsetq_lane_u64(ol_flags2, rearm2, 1);\n-\t\trearm3 = vsetq_lane_u64(ol_flags3, rearm3, 1);\n-\n-\t\t/* Update rx_descriptor_fields1 */\n-\t\tvst1q_u64((uint64_t *)mbuf0->rx_descriptor_fields1, f0);\n-\t\tvst1q_u64((uint64_t *)mbuf1->rx_descriptor_fields1, f1);\n-\t\tvst1q_u64((uint64_t *)mbuf2->rx_descriptor_fields1, f2);\n-\t\tvst1q_u64((uint64_t *)mbuf3->rx_descriptor_fields1, f3);\n-\n-\t\t/* Update rearm_data */\n-\t\tvst1q_u64((uint64_t *)mbuf0->rearm_data, rearm0);\n-\t\tvst1q_u64((uint64_t *)mbuf1->rearm_data, rearm1);\n-\t\tvst1q_u64((uint64_t *)mbuf2->rearm_data, rearm2);\n-\t\tvst1q_u64((uint64_t *)mbuf3->rearm_data, rearm3);\n-\n-\t\t/* Update that no more segments */\n-\t\tmbuf0->next = NULL;\n-\t\tmbuf1->next = NULL;\n-\t\tmbuf2->next = NULL;\n-\t\tmbuf3->next = NULL;\n-\n-\t\t/* Store the mbufs to rx_pkts */\n-\t\tvst1q_u64((uint64_t *)&rx_pkts[packets], mbuf01);\n-\t\tvst1q_u64((uint64_t *)&rx_pkts[packets + 2], mbuf23);\n-\n-\t\t/* Prefetch mbufs */\n-\t\totx2_prefetch_store_keep(mbuf0);\n-\t\totx2_prefetch_store_keep(mbuf1);\n-\t\totx2_prefetch_store_keep(mbuf2);\n-\t\totx2_prefetch_store_keep(mbuf3);\n-\n-\t\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n-\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf0->pool, (void **)&mbuf0, 1, 1);\n-\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf1->pool, (void **)&mbuf1, 1, 1);\n-\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf2->pool, (void **)&mbuf2, 1, 1);\n-\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf3->pool, (void **)&mbuf3, 1, 1);\n-\n-\t\t/* Advance head pointer and packets */\n-\t\thead += NIX_DESCS_PER_LOOP; head &= qmask;\n-\t\tpackets += NIX_DESCS_PER_LOOP;\n-\t}\n-\n-\trxq->head = head;\n-\trxq->available -= packets;\n-\n-\trte_io_wmb();\n-\t/* Free all the CQs that we've processed */\n-\totx2_write64((rxq->wdata | packets), rxq->cq_door);\n-\n-\tif (unlikely(pkts_left))\n-\t\tpackets += nix_recv_pkts(rx_queue, &rx_pkts[packets],\n-\t\t\t\t\t pkts_left, flags);\n-\n-\treturn packets;\n-}\n-\n-#else\n-\n-static inline uint16_t\n-nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,\n-\t\t uint16_t pkts, const uint16_t flags)\n-{\n-\tRTE_SET_USED(rx_queue);\n-\tRTE_SET_USED(rx_pkts);\n-\tRTE_SET_USED(pkts);\n-\tRTE_SET_USED(flags);\n-\n-\treturn 0;\n-}\n-\n-#endif\n-\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t \\\n-static uint16_t __rte_noinline\t__rte_hot\t\t\t\t\t \\\n-otx2_nix_recv_pkts_ ## name(void *rx_queue,\t\t\t\t \\\n-\t\t\tstruct rte_mbuf **rx_pkts, uint16_t pkts)\t \\\n-{\t\t\t\t\t\t\t\t\t \\\n-\treturn nix_recv_pkts(rx_queue, rx_pkts, pkts, (flags));\t\t \\\n-}\t\t\t\t\t\t\t\t\t \\\n-\t\t\t\t\t\t\t\t\t \\\n-static uint16_t __rte_noinline\t__rte_hot\t\t\t\t\t \\\n-otx2_nix_recv_pkts_mseg_ ## name(void *rx_queue,\t\t\t \\\n-\t\t\tstruct rte_mbuf **rx_pkts, uint16_t pkts)\t \\\n-{\t\t\t\t\t\t\t\t\t \\\n-\treturn nix_recv_pkts(rx_queue, rx_pkts, pkts,\t\t\t \\\n-\t\t\t (flags) | NIX_RX_MULTI_SEG_F);\t\t \\\n-}\t\t\t\t\t\t\t\t\t \\\n-\t\t\t\t\t\t\t\t\t \\\n-static uint16_t __rte_noinline\t__rte_hot\t\t\t\t\t \\\n-otx2_nix_recv_pkts_vec_ ## name(void *rx_queue,\t\t\t\t \\\n-\t\t\tstruct rte_mbuf **rx_pkts, uint16_t pkts)\t \\\n-{\t\t\t\t\t\t\t\t\t \\\n-\t/* TSTMP is not supported by vector */\t\t\t\t \\\n-\tif ((flags) & NIX_RX_OFFLOAD_TSTAMP_F)\t\t\t\t \\\n-\t\treturn 0;\t\t\t\t\t\t \\\n-\treturn nix_recv_pkts_vector(rx_queue, rx_pkts, pkts, (flags));\t \\\n-}\t\t\t\t\t\t\t\t\t \\\n-\n-NIX_RX_FASTPATH_MODES\n-#undef R\n-\n-static inline void\n-pick_rx_func(struct rte_eth_dev *eth_dev,\n-\t const eth_rx_burst_t rx_burst[2][2][2][2][2][2][2])\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\t/* [SEC] [TSTMP] [MARK] [VLAN] [CKSUM] [PTYPE] [RSS] */\n-\teth_dev->rx_pkt_burst = rx_burst\n-\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_SECURITY_F)]\n-\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F)]\n-\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_MARK_UPDATE_F)]\n-\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_VLAN_STRIP_F)]\n-\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_CHECKSUM_F)]\n-\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_PTYPE_F)]\n-\t\t[!!(dev->rx_offload_flags & NIX_RX_OFFLOAD_RSS_F)];\n-}\n-\n-void\n-otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tconst eth_rx_burst_t nix_eth_rx_burst[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t[f6][f5][f4][f3][f2][f1][f0] = otx2_nix_recv_pkts_ ## name,\n-\n-NIX_RX_FASTPATH_MODES\n-#undef R\n-\t};\n-\n-\tconst eth_rx_burst_t nix_eth_rx_burst_mseg[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t[f6][f5][f4][f3][f2][f1][f0] = otx2_nix_recv_pkts_mseg_ ## name,\n-\n-NIX_RX_FASTPATH_MODES\n-#undef R\n-\t};\n-\n-\tconst eth_rx_burst_t nix_eth_rx_vec_burst[2][2][2][2][2][2][2] = {\n-#define R(name, f6, f5, f4, f3, f2, f1, f0, flags)\t\t\t\\\n-\t[f6][f5][f4][f3][f2][f1][f0] = otx2_nix_recv_pkts_vec_ ## name,\n-\n-NIX_RX_FASTPATH_MODES\n-#undef R\n-\t};\n-\n-\t/* For PTP enabled, scalar rx function should be chosen as most of the\n-\t * PTP apps are implemented to rx burst 1 pkt.\n-\t */\n-\tif (dev->scalar_ena || dev->rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)\n-\t\tpick_rx_func(eth_dev, nix_eth_rx_burst);\n-\telse\n-\t\tpick_rx_func(eth_dev, nix_eth_rx_vec_burst);\n-\n-\tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER)\n-\t\tpick_rx_func(eth_dev, nix_eth_rx_burst_mseg);\n-\n-\t/* Copy multi seg version with no offload for tear down sequence */\n-\tif (rte_eal_process_type() == RTE_PROC_PRIMARY)\n-\t\tdev->rx_pkt_burst_no_offload =\n-\t\t\tnix_eth_rx_burst_mseg[0][0][0][0][0][0][0];\n-\trte_mb();\n-}\ndiff --git a/drivers/net/octeontx2/otx2_rx.h b/drivers/net/octeontx2/otx2_rx.h\ndeleted file mode 100644\nindex 98406244e2..0000000000\n--- a/drivers/net/octeontx2/otx2_rx.h\n+++ /dev/null\n@@ -1,583 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_RX_H__\n-#define __OTX2_RX_H__\n-\n-#include <rte_ether.h>\n-\n-#include \"otx2_common.h\"\n-#include \"otx2_ethdev_sec.h\"\n-#include \"otx2_ipsec_anti_replay.h\"\n-#include \"otx2_ipsec_fp.h\"\n-\n-/* Default mark value used when none is provided. */\n-#define OTX2_FLOW_ACTION_FLAG_DEFAULT\t0xffff\n-\n-#define PTYPE_NON_TUNNEL_WIDTH\t\t16\n-#define PTYPE_TUNNEL_WIDTH\t\t12\n-#define PTYPE_NON_TUNNEL_ARRAY_SZ\tBIT(PTYPE_NON_TUNNEL_WIDTH)\n-#define PTYPE_TUNNEL_ARRAY_SZ\t\tBIT(PTYPE_TUNNEL_WIDTH)\n-#define PTYPE_ARRAY_SZ\t\t\t((PTYPE_NON_TUNNEL_ARRAY_SZ +\\\n-\t\t\t\t\t PTYPE_TUNNEL_ARRAY_SZ) *\\\n-\t\t\t\t\t sizeof(uint16_t))\n-\n-#define NIX_RX_OFFLOAD_NONE (0)\n-#define NIX_RX_OFFLOAD_RSS_F BIT(0)\n-#define NIX_RX_OFFLOAD_PTYPE_F BIT(1)\n-#define NIX_RX_OFFLOAD_CHECKSUM_F BIT(2)\n-#define NIX_RX_OFFLOAD_VLAN_STRIP_F BIT(3)\n-#define NIX_RX_OFFLOAD_MARK_UPDATE_F BIT(4)\n-#define NIX_RX_OFFLOAD_TSTAMP_F BIT(5)\n-#define NIX_RX_OFFLOAD_SECURITY_F BIT(6)\n-\n-/* Flags to control cqe_to_mbuf conversion function.\n- * Defining it from backwards to denote its been\n- * not used as offload flags to pick function\n- */\n-#define NIX_RX_MULTI_SEG_F BIT(15)\n-#define NIX_TIMESYNC_RX_OFFSET\t\t8\n-\n-/* Inline IPsec offsets */\n-\n-/* nix_cqe_hdr_s + nix_rx_parse_s + nix_rx_sg_s + nix_iova_s */\n-#define INLINE_CPT_RESULT_OFFSET\t80\n-\n-struct otx2_timesync_info {\n-\tuint64_t\trx_tstamp;\n-\trte_iova_t\ttx_tstamp_iova;\n-\tuint64_t\t*tx_tstamp;\n-\tuint64_t\trx_tstamp_dynflag;\n-\tint\t\ttstamp_dynfield_offset;\n-\tuint8_t\t\ttx_ready;\n-\tuint8_t\t\trx_ready;\n-} __rte_cache_aligned;\n-\n-union mbuf_initializer {\n-\tstruct {\n-\t\tuint16_t data_off;\n-\t\tuint16_t refcnt;\n-\t\tuint16_t nb_segs;\n-\t\tuint16_t port;\n-\t} fields;\n-\tuint64_t value;\n-};\n-\n-static inline rte_mbuf_timestamp_t *\n-otx2_timestamp_dynfield(struct rte_mbuf *mbuf,\n-\t\tstruct otx2_timesync_info *info)\n-{\n-\treturn RTE_MBUF_DYNFIELD(mbuf,\n-\t\tinfo->tstamp_dynfield_offset, rte_mbuf_timestamp_t *);\n-}\n-\n-static __rte_always_inline void\n-otx2_nix_mbuf_to_tstamp(struct rte_mbuf *mbuf,\n-\t\t\tstruct otx2_timesync_info *tstamp, const uint16_t flag,\n-\t\t\tuint64_t *tstamp_ptr)\n-{\n-\tif ((flag & NIX_RX_OFFLOAD_TSTAMP_F) &&\n-\t (mbuf->data_off == RTE_PKTMBUF_HEADROOM +\n-\t NIX_TIMESYNC_RX_OFFSET)) {\n-\n-\t\tmbuf->pkt_len -= NIX_TIMESYNC_RX_OFFSET;\n-\n-\t\t/* Reading the rx timestamp inserted by CGX, viz at\n-\t\t * starting of the packet data.\n-\t\t */\n-\t\t*otx2_timestamp_dynfield(mbuf, tstamp) =\n-\t\t\t\trte_be_to_cpu_64(*tstamp_ptr);\n-\t\t/* RTE_MBUF_F_RX_IEEE1588_TMST flag needs to be set only in case\n-\t\t * PTP packets are received.\n-\t\t */\n-\t\tif (mbuf->packet_type == RTE_PTYPE_L2_ETHER_TIMESYNC) {\n-\t\t\ttstamp->rx_tstamp =\n-\t\t\t\t\t*otx2_timestamp_dynfield(mbuf, tstamp);\n-\t\t\ttstamp->rx_ready = 1;\n-\t\t\tmbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP |\n-\t\t\t\tRTE_MBUF_F_RX_IEEE1588_TMST |\n-\t\t\t\ttstamp->rx_tstamp_dynflag;\n-\t\t}\n-\t}\n-}\n-\n-static __rte_always_inline uint64_t\n-nix_clear_data_off(uint64_t oldval)\n-{\n-\tunion mbuf_initializer mbuf_init = { .value = oldval };\n-\n-\tmbuf_init.fields.data_off = 0;\n-\treturn mbuf_init.value;\n-}\n-\n-static __rte_always_inline struct rte_mbuf *\n-nix_get_mbuf_from_cqe(void *cq, const uint64_t data_off)\n-{\n-\trte_iova_t buff;\n-\n-\t/* Skip CQE, NIX_RX_PARSE_S and SG HDR(9 DWORDs) and peek buff addr */\n-\tbuff = *((rte_iova_t *)((uint64_t *)cq + 9));\n-\treturn (struct rte_mbuf *)(buff - data_off);\n-}\n-\n-\n-static __rte_always_inline uint32_t\n-nix_ptype_get(const void * const lookup_mem, const uint64_t in)\n-{\n-\tconst uint16_t * const ptype = lookup_mem;\n-\tconst uint16_t lh_lg_lf = (in & 0xFFF0000000000000) >> 52;\n-\tconst uint16_t tu_l2 = ptype[(in & 0x000FFFF000000000) >> 36];\n-\tconst uint16_t il4_tu = ptype[PTYPE_NON_TUNNEL_ARRAY_SZ + lh_lg_lf];\n-\n-\treturn (il4_tu << PTYPE_NON_TUNNEL_WIDTH) | tu_l2;\n-}\n-\n-static __rte_always_inline uint32_t\n-nix_rx_olflags_get(const void * const lookup_mem, const uint64_t in)\n-{\n-\tconst uint32_t * const ol_flags = (const uint32_t *)\n-\t\t\t((const uint8_t *)lookup_mem + PTYPE_ARRAY_SZ);\n-\n-\treturn ol_flags[(in & 0xfff00000) >> 20];\n-}\n-\n-static inline uint64_t\n-nix_update_match_id(const uint16_t match_id, uint64_t ol_flags,\n-\t\t struct rte_mbuf *mbuf)\n-{\n-\t/* There is no separate bit to check match_id\n-\t * is valid or not? and no flag to identify it is an\n-\t * RTE_FLOW_ACTION_TYPE_FLAG vs RTE_FLOW_ACTION_TYPE_MARK\n-\t * action. The former case addressed through 0 being invalid\n-\t * value and inc/dec match_id pair when MARK is activated.\n-\t * The later case addressed through defining\n-\t * OTX2_FLOW_MARK_DEFAULT as value for\n-\t * RTE_FLOW_ACTION_TYPE_MARK.\n-\t * This would translate to not use\n-\t * OTX2_FLOW_ACTION_FLAG_DEFAULT - 1 and\n-\t * OTX2_FLOW_ACTION_FLAG_DEFAULT for match_id.\n-\t * i.e valid mark_id's are from\n-\t * 0 to OTX2_FLOW_ACTION_FLAG_DEFAULT - 2\n-\t */\n-\tif (likely(match_id)) {\n-\t\tol_flags |= RTE_MBUF_F_RX_FDIR;\n-\t\tif (match_id != OTX2_FLOW_ACTION_FLAG_DEFAULT) {\n-\t\t\tol_flags |= RTE_MBUF_F_RX_FDIR_ID;\n-\t\t\tmbuf->hash.fdir.hi = match_id - 1;\n-\t\t}\n-\t}\n-\n-\treturn ol_flags;\n-}\n-\n-static __rte_always_inline void\n-nix_cqe_xtract_mseg(const struct nix_rx_parse_s *rx,\n-\t\t struct rte_mbuf *mbuf, uint64_t rearm)\n-{\n-\tconst rte_iova_t *iova_list;\n-\tstruct rte_mbuf *head;\n-\tconst rte_iova_t *eol;\n-\tuint8_t nb_segs;\n-\tuint64_t sg;\n-\n-\tsg = *(const uint64_t *)(rx + 1);\n-\tnb_segs = (sg >> 48) & 0x3;\n-\tmbuf->nb_segs = nb_segs;\n-\tmbuf->data_len = sg & 0xFFFF;\n-\tsg = sg >> 16;\n-\n-\teol = ((const rte_iova_t *)(rx + 1) + ((rx->desc_sizem1 + 1) << 1));\n-\t/* Skip SG_S and first IOVA*/\n-\tiova_list = ((const rte_iova_t *)(rx + 1)) + 2;\n-\tnb_segs--;\n-\n-\trearm = rearm & ~0xFFFF;\n-\n-\thead = mbuf;\n-\twhile (nb_segs) {\n-\t\tmbuf->next = ((struct rte_mbuf *)*iova_list) - 1;\n-\t\tmbuf = mbuf->next;\n-\n-\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);\n-\n-\t\tmbuf->data_len = sg & 0xFFFF;\n-\t\tsg = sg >> 16;\n-\t\t*(uint64_t *)(&mbuf->rearm_data) = rearm;\n-\t\tnb_segs--;\n-\t\tiova_list++;\n-\n-\t\tif (!nb_segs && (iova_list + 1 < eol)) {\n-\t\t\tsg = *(const uint64_t *)(iova_list);\n-\t\t\tnb_segs = (sg >> 48) & 0x3;\n-\t\t\thead->nb_segs += nb_segs;\n-\t\t\tiova_list = (const rte_iova_t *)(iova_list + 1);\n-\t\t}\n-\t}\n-\tmbuf->next = NULL;\n-}\n-\n-static __rte_always_inline uint16_t\n-nix_rx_sec_cptres_get(const void *cq)\n-{\n-\tvolatile const struct otx2_cpt_res *res;\n-\n-\tres = (volatile const struct otx2_cpt_res *)((const char *)cq +\n-\t\t\tINLINE_CPT_RESULT_OFFSET);\n-\n-\treturn res->u16[0];\n-}\n-\n-static __rte_always_inline void *\n-nix_rx_sec_sa_get(const void * const lookup_mem, int spi, uint16_t port)\n-{\n-\tconst uint64_t *const *sa_tbl = (const uint64_t * const *)\n-\t\t\t((const uint8_t *)lookup_mem + OTX2_NIX_SA_TBL_START);\n-\n-\treturn (void *)sa_tbl[port][spi];\n-}\n-\n-static __rte_always_inline uint64_t\n-nix_rx_sec_mbuf_update(const struct nix_rx_parse_s *rx,\n-\t\t const struct nix_cqe_hdr_s *cq, struct rte_mbuf *m,\n-\t\t const void * const lookup_mem)\n-{\n-\tuint8_t *l2_ptr, *l3_ptr, *l2_ptr_actual, *l3_ptr_actual;\n-\tstruct otx2_ipsec_fp_in_sa *sa;\n-\tuint16_t m_len, l2_len, ip_len;\n-\tstruct rte_ipv6_hdr *ip6h;\n-\tstruct rte_ipv4_hdr *iph;\n-\tuint16_t *ether_type;\n-\tuint32_t spi;\n-\tint i;\n-\n-\tif (unlikely(nix_rx_sec_cptres_get(cq) != OTX2_SEC_COMP_GOOD))\n-\t\treturn RTE_MBUF_F_RX_SEC_OFFLOAD | RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;\n-\n-\t/* 20 bits of tag would have the SPI */\n-\tspi = cq->tag & 0xFFFFF;\n-\n-\tsa = nix_rx_sec_sa_get(lookup_mem, spi, m->port);\n-\t*rte_security_dynfield(m) = sa->udata64;\n-\n-\tl2_ptr = rte_pktmbuf_mtod(m, uint8_t *);\n-\tl2_len = rx->lcptr - rx->laptr;\n-\tl3_ptr = RTE_PTR_ADD(l2_ptr, l2_len);\n-\n-\tif (sa->replay_win_sz) {\n-\t\tif (cpt_ipsec_ip_antireplay_check(sa, l3_ptr) < 0)\n-\t\t\treturn RTE_MBUF_F_RX_SEC_OFFLOAD | RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED;\n-\t}\n-\n-\tl2_ptr_actual = RTE_PTR_ADD(l2_ptr,\n-\t\t\t\t sizeof(struct otx2_ipsec_fp_res_hdr));\n-\tl3_ptr_actual = RTE_PTR_ADD(l3_ptr,\n-\t\t\t\t sizeof(struct otx2_ipsec_fp_res_hdr));\n-\n-\tfor (i = l2_len - RTE_ETHER_TYPE_LEN - 1; i >= 0; i--)\n-\t\tl2_ptr_actual[i] = l2_ptr[i];\n-\n-\tm->data_off += sizeof(struct otx2_ipsec_fp_res_hdr);\n-\n-\tether_type = RTE_PTR_SUB(l3_ptr_actual, RTE_ETHER_TYPE_LEN);\n-\n-\tiph = (struct rte_ipv4_hdr *)l3_ptr_actual;\n-\tif ((iph->version_ihl >> 4) == 4) {\n-\t\tip_len = rte_be_to_cpu_16(iph->total_length);\n-\t\t*ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV4);\n-\t} else {\n-\t\tip6h = (struct rte_ipv6_hdr *)iph;\n-\t\tip_len = rte_be_to_cpu_16(ip6h->payload_len);\n-\t\t*ether_type = rte_cpu_to_be_16(RTE_ETHER_TYPE_IPV6);\n-\t}\n-\n-\tm_len = ip_len + l2_len;\n-\tm->data_len = m_len;\n-\tm->pkt_len = m_len;\n-\treturn RTE_MBUF_F_RX_SEC_OFFLOAD;\n-}\n-\n-static __rte_always_inline void\n-otx2_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,\n-\t\t struct rte_mbuf *mbuf, const void *lookup_mem,\n-\t\t const uint64_t val, const uint16_t flag)\n-{\n-\tconst struct nix_rx_parse_s *rx =\n-\t\t (const struct nix_rx_parse_s *)((const uint64_t *)cq + 1);\n-\tconst uint64_t w1 = *(const uint64_t *)rx;\n-\tconst uint16_t len = rx->pkt_lenm1 + 1;\n-\tuint64_t ol_flags = 0;\n-\n-\t/* Mark mempool obj as \"get\" as it is alloc'ed by NIX */\n-\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);\n-\n-\tif (flag & NIX_RX_OFFLOAD_PTYPE_F)\n-\t\tmbuf->packet_type = nix_ptype_get(lookup_mem, w1);\n-\telse\n-\t\tmbuf->packet_type = 0;\n-\n-\tif (flag & NIX_RX_OFFLOAD_RSS_F) {\n-\t\tmbuf->hash.rss = tag;\n-\t\tol_flags |= RTE_MBUF_F_RX_RSS_HASH;\n-\t}\n-\n-\tif (flag & NIX_RX_OFFLOAD_CHECKSUM_F)\n-\t\tol_flags |= nix_rx_olflags_get(lookup_mem, w1);\n-\n-\tif (flag & NIX_RX_OFFLOAD_VLAN_STRIP_F) {\n-\t\tif (rx->vtag0_gone) {\n-\t\t\tol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;\n-\t\t\tmbuf->vlan_tci = rx->vtag0_tci;\n-\t\t}\n-\t\tif (rx->vtag1_gone) {\n-\t\t\tol_flags |= RTE_MBUF_F_RX_QINQ | RTE_MBUF_F_RX_QINQ_STRIPPED;\n-\t\t\tmbuf->vlan_tci_outer = rx->vtag1_tci;\n-\t\t}\n-\t}\n-\n-\tif (flag & NIX_RX_OFFLOAD_MARK_UPDATE_F)\n-\t\tol_flags = nix_update_match_id(rx->match_id, ol_flags, mbuf);\n-\n-\tif ((flag & NIX_RX_OFFLOAD_SECURITY_F) &&\n-\t cq->cqe_type == NIX_XQE_TYPE_RX_IPSECH) {\n-\t\t*(uint64_t *)(&mbuf->rearm_data) = val;\n-\t\tol_flags |= nix_rx_sec_mbuf_update(rx, cq, mbuf, lookup_mem);\n-\t\tmbuf->ol_flags = ol_flags;\n-\t\treturn;\n-\t}\n-\n-\tmbuf->ol_flags = ol_flags;\n-\t*(uint64_t *)(&mbuf->rearm_data) = val;\n-\tmbuf->pkt_len = len;\n-\n-\tif (flag & NIX_RX_MULTI_SEG_F) {\n-\t\tnix_cqe_xtract_mseg(rx, mbuf, val);\n-\t} else {\n-\t\tmbuf->data_len = len;\n-\t\tmbuf->next = NULL;\n-\t}\n-}\n-\n-#define CKSUM_F NIX_RX_OFFLOAD_CHECKSUM_F\n-#define PTYPE_F NIX_RX_OFFLOAD_PTYPE_F\n-#define RSS_F\tNIX_RX_OFFLOAD_RSS_F\n-#define RX_VLAN_F NIX_RX_OFFLOAD_VLAN_STRIP_F\n-#define MARK_F NIX_RX_OFFLOAD_MARK_UPDATE_F\n-#define TS_F\tNIX_RX_OFFLOAD_TSTAMP_F\n-#define RX_SEC_F NIX_RX_OFFLOAD_SECURITY_F\n-\n-/* [SEC] [TSMP] [MARK] [VLAN] [CKSUM] [PTYPE] [RSS] */\n-#define NIX_RX_FASTPATH_MODES\t\t\t\t\t\t \\\n-R(no_offload,\t\t\t0, 0, 0, 0, 0, 0, 0, NIX_RX_OFFLOAD_NONE) \\\n-R(rss,\t\t\t\t0, 0, 0, 0, 0, 0, 1, RSS_F)\t\t \\\n-R(ptype,\t\t\t0, 0, 0, 0, 0, 1, 0, PTYPE_F)\t\t \\\n-R(ptype_rss,\t\t\t0, 0, 0, 0, 0, 1, 1, PTYPE_F | RSS_F)\t \\\n-R(cksum,\t\t\t0, 0, 0, 0, 1, 0, 0, CKSUM_F)\t\t \\\n-R(cksum_rss,\t\t\t0, 0, 0, 0, 1, 0, 1, CKSUM_F | RSS_F)\t \\\n-R(cksum_ptype,\t\t\t0, 0, 0, 0, 1, 1, 0, CKSUM_F | PTYPE_F)\t \\\n-R(cksum_ptype_rss,\t\t0, 0, 0, 0, 1, 1, 1, CKSUM_F | PTYPE_F | RSS_F)\\\n-R(vlan,\t\t\t\t0, 0, 0, 1, 0, 0, 0, RX_VLAN_F)\t\t \\\n-R(vlan_rss,\t\t\t0, 0, 0, 1, 0, 0, 1, RX_VLAN_F | RSS_F)\t \\\n-R(vlan_ptype,\t\t\t0, 0, 0, 1, 0, 1, 0, RX_VLAN_F | PTYPE_F) \\\n-R(vlan_ptype_rss,\t\t0, 0, 0, 1, 0, 1, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | PTYPE_F | RSS_F)\t\t\t \\\n-R(vlan_cksum,\t\t\t0, 0, 0, 1, 1, 0, 0, RX_VLAN_F | CKSUM_F) \\\n-R(vlan_cksum_rss,\t\t0, 0, 0, 1, 1, 0, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | CKSUM_F | RSS_F)\t\t\t \\\n-R(vlan_cksum_ptype,\t\t0, 0, 0, 1, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_VLAN_F | CKSUM_F | PTYPE_F)\t\t\t \\\n-R(vlan_cksum_ptype_rss,\t\t0, 0, 0, 1, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F)\t\t \\\n-R(mark,\t\t\t\t0, 0, 1, 0, 0, 0, 0, MARK_F)\t\t \\\n-R(mark_rss,\t\t\t0, 0, 1, 0, 0, 0, 1, MARK_F | RSS_F)\t \\\n-R(mark_ptype,\t\t\t0, 0, 1, 0, 0, 1, 0, MARK_F | PTYPE_F)\t \\\n-R(mark_ptype_rss,\t\t0, 0, 1, 0, 0, 1, 1, MARK_F | PTYPE_F | RSS_F) \\\n-R(mark_cksum,\t\t\t0, 0, 1, 0, 1, 0, 0, MARK_F | CKSUM_F)\t \\\n-R(mark_cksum_rss,\t\t0, 0, 1, 0, 1, 0, 1, MARK_F | CKSUM_F | RSS_F) \\\n-R(mark_cksum_ptype,\t\t0, 0, 1, 0, 1, 1, 0,\t\t\t \\\n-\t\t\tMARK_F | CKSUM_F | PTYPE_F)\t\t\t \\\n-R(mark_cksum_ptype_rss,\t\t0, 0, 1, 0, 1, 1, 1,\t\t\t \\\n-\t\t\tMARK_F | CKSUM_F | PTYPE_F | RSS_F)\t\t \\\n-R(mark_vlan,\t\t\t0, 0, 1, 1, 0, 0, 0, MARK_F | RX_VLAN_F) \\\n-R(mark_vlan_rss,\t\t0, 0, 1, 1, 0, 0, 1,\t\t\t \\\n-\t\t\tMARK_F | RX_VLAN_F | RSS_F)\t\t\t \\\n-R(mark_vlan_ptype,\t\t0, 0, 1, 1, 0, 1, 0,\t\t\t \\\n-\t\t\tMARK_F | RX_VLAN_F | PTYPE_F)\t\t\t \\\n-R(mark_vlan_ptype_rss,\t\t0, 0, 1, 1, 0, 1, 1,\t\t\t \\\n-\t\t\tMARK_F | RX_VLAN_F | PTYPE_F | RSS_F)\t\t \\\n-R(mark_vlan_cksum,\t\t0, 0, 1, 1, 1, 0, 0,\t\t\t \\\n-\t\t\tMARK_F | RX_VLAN_F | CKSUM_F)\t\t\t \\\n-R(mark_vlan_cksum_rss,\t\t0, 0, 1, 1, 1, 0, 1,\t\t\t \\\n-\t\t\tMARK_F | RX_VLAN_F | CKSUM_F | RSS_F)\t\t \\\n-R(mark_vlan_cksum_ptype,\t0, 0, 1, 1, 1, 1, 0,\t\t\t \\\n-\t\t\tMARK_F | RX_VLAN_F | CKSUM_F | PTYPE_F)\t\t \\\n-R(mark_vlan_cksum_ptype_rss,\t0, 0, 1, 1, 1, 1, 1,\t\t\t \\\n-\t\t\tMARK_F | RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F)\t \\\n-R(ts,\t\t\t\t0, 1, 0, 0, 0, 0, 0, TS_F)\t\t \\\n-R(ts_rss,\t\t\t0, 1, 0, 0, 0, 0, 1, TS_F | RSS_F)\t \\\n-R(ts_ptype,\t\t\t0, 1, 0, 0, 0, 1, 0, TS_F | PTYPE_F)\t \\\n-R(ts_ptype_rss,\t\t\t0, 1, 0, 0, 0, 1, 1, TS_F | PTYPE_F | RSS_F) \\\n-R(ts_cksum,\t\t\t0, 1, 0, 0, 1, 0, 0, TS_F | CKSUM_F)\t \\\n-R(ts_cksum_rss,\t\t\t0, 1, 0, 0, 1, 0, 1, TS_F | CKSUM_F | RSS_F) \\\n-R(ts_cksum_ptype,\t\t0, 1, 0, 0, 1, 1, 0, TS_F | CKSUM_F | PTYPE_F) \\\n-R(ts_cksum_ptype_rss,\t\t0, 1, 0, 0, 1, 1, 1,\t\t\t \\\n-\t\t\tTS_F | CKSUM_F | PTYPE_F | RSS_F)\t\t \\\n-R(ts_vlan,\t\t\t0, 1, 0, 1, 0, 0, 0, TS_F | RX_VLAN_F)\t \\\n-R(ts_vlan_rss,\t\t\t0, 1, 0, 1, 0, 0, 1, TS_F | RX_VLAN_F | RSS_F) \\\n-R(ts_vlan_ptype,\t\t0, 1, 0, 1, 0, 1, 0,\t\t\t \\\n-\t\t\tTS_F | RX_VLAN_F | PTYPE_F)\t\t\t \\\n-R(ts_vlan_ptype_rss,\t\t0, 1, 0, 1, 0, 1, 1,\t\t\t \\\n-\t\t\tTS_F | RX_VLAN_F | PTYPE_F | RSS_F)\t\t \\\n-R(ts_vlan_cksum,\t\t0, 1, 0, 1, 1, 0, 0,\t\t\t \\\n-\t\t\tTS_F | RX_VLAN_F | CKSUM_F)\t\t\t \\\n-R(ts_vlan_cksum_rss,\t\t0, 1, 0, 1, 1, 0, 1,\t\t\t \\\n-\t\t\tMARK_F | RX_VLAN_F | CKSUM_F | RSS_F)\t\t \\\n-R(ts_vlan_cksum_ptype,\t\t0, 1, 0, 1, 1, 1, 0,\t\t\t \\\n-\t\t\tTS_F | RX_VLAN_F | CKSUM_F | PTYPE_F)\t\t \\\n-R(ts_vlan_cksum_ptype_rss,\t0, 1, 0, 1, 1, 1, 1,\t\t\t \\\n-\t\t\tTS_F | RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F)\t \\\n-R(ts_mark,\t\t\t0, 1, 1, 0, 0, 0, 0, TS_F | MARK_F)\t \\\n-R(ts_mark_rss,\t\t\t0, 1, 1, 0, 0, 0, 1, TS_F | MARK_F | RSS_F) \\\n-R(ts_mark_ptype,\t\t0, 1, 1, 0, 0, 1, 0, TS_F | MARK_F | PTYPE_F) \\\n-R(ts_mark_ptype_rss,\t\t0, 1, 1, 0, 0, 1, 1,\t\t\t \\\n-\t\t\tTS_F | MARK_F | PTYPE_F | RSS_F)\t\t \\\n-R(ts_mark_cksum,\t\t0, 1, 1, 0, 1, 0, 0, TS_F | MARK_F | CKSUM_F) \\\n-R(ts_mark_cksum_rss,\t\t0, 1, 1, 0, 1, 0, 1,\t\t\t \\\n-\t\t\tTS_F | MARK_F | CKSUM_F | RSS_F)\t\t \\\n-R(ts_mark_cksum_ptype,\t\t0, 1, 1, 0, 1, 1, 0,\t\t\t \\\n-\t\t\tTS_F | MARK_F | CKSUM_F | PTYPE_F)\t\t \\\n-R(ts_mark_cksum_ptype_rss,\t0, 1, 1, 0, 1, 1, 1,\t\t\t \\\n-\t\t\tTS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)\t \\\n-R(ts_mark_vlan,\t\t\t0, 1, 1, 1, 0, 0, 0, TS_F | MARK_F | RX_VLAN_F)\\\n-R(ts_mark_vlan_rss,\t\t0, 1, 1, 1, 0, 0, 1,\t\t\t \\\n-\t\t\tTS_F | MARK_F | RX_VLAN_F | RSS_F)\t\t \\\n-R(ts_mark_vlan_ptype,\t\t0, 1, 1, 1, 0, 1, 0,\t\t\t \\\n-\t\t\tTS_F | MARK_F | RX_VLAN_F | PTYPE_F)\t\t \\\n-R(ts_mark_vlan_ptype_rss,\t0, 1, 1, 1, 0, 1, 1,\t\t\t \\\n-\t\t\tTS_F | MARK_F | RX_VLAN_F | PTYPE_F | RSS_F)\t \\\n-R(ts_mark_vlan_cksum_ptype,\t0, 1, 1, 1, 1, 1, 0,\t\t\t \\\n-\t\t\tTS_F | MARK_F | RX_VLAN_F | CKSUM_F | PTYPE_F)\t \\\n-R(ts_mark_vlan_cksum_ptype_rss,\t0, 1, 1, 1, 1, 1, 1,\t\t\t \\\n-\t\t\tTS_F | MARK_F | RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F) \\\n-R(sec,\t\t\t\t1, 0, 0, 0, 0, 0, 0, RX_SEC_F)\t\t \\\n-R(sec_rss,\t\t\t1, 0, 0, 0, 0, 0, 1, RX_SEC_F | RSS_F)\t \\\n-R(sec_ptype,\t\t\t1, 0, 0, 0, 0, 1, 0, RX_SEC_F | PTYPE_F) \\\n-R(sec_ptype_rss,\t\t1, 0, 0, 0, 0, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | PTYPE_F | RSS_F)\t\t\t \\\n-R(sec_cksum,\t\t\t1, 0, 0, 0, 1, 0, 0, RX_SEC_F | CKSUM_F) \\\n-R(sec_cksum_rss,\t\t1, 0, 0, 0, 1, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | CKSUM_F | RSS_F)\t\t\t \\\n-R(sec_cksum_ptype,\t\t1, 0, 0, 0, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | CKSUM_F | PTYPE_F)\t\t\t \\\n-R(sec_cksum_ptype_rss,\t\t1, 0, 0, 0, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | CKSUM_F | PTYPE_F | RSS_F)\t\t \\\n-R(sec_vlan,\t\t\t1, 0, 0, 1, 0, 0, 0, RX_SEC_F | RX_VLAN_F) \\\n-R(sec_vlan_rss,\t\t\t1, 0, 0, 1, 0, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | RX_VLAN_F | RSS_F)\t\t\t \\\n-R(sec_vlan_ptype,\t\t1, 0, 0, 1, 0, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | RX_VLAN_F | PTYPE_F)\t\t\t \\\n-R(sec_vlan_ptype_rss,\t\t1, 0, 0, 1, 0, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | RX_VLAN_F | PTYPE_F | RSS_F)\t\t \\\n-R(sec_vlan_cksum,\t\t1, 0, 0, 1, 1, 0, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | RX_VLAN_F | CKSUM_F)\t\t\t \\\n-R(sec_vlan_cksum_rss,\t\t1, 0, 0, 1, 1, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | RX_VLAN_F | CKSUM_F | RSS_F)\t\t \\\n-R(sec_vlan_cksum_ptype,\t\t1, 0, 0, 1, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | RX_VLAN_F | CKSUM_F | PTYPE_F)\t \\\n-R(sec_vlan_cksum_ptype_rss,\t1, 0, 0, 1, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | RX_VLAN_F | CKSUM_F | PTYPE_F | RSS_F) \\\n-R(sec_mark,\t\t\t1, 0, 1, 0, 0, 0, 0, RX_SEC_F | MARK_F)\t \\\n-R(sec_mark_rss,\t\t\t1, 0, 1, 0, 0, 0, 1, RX_SEC_F | MARK_F | RSS_F)\\\n-R(sec_mark_ptype,\t\t1, 0, 1, 0, 0, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | PTYPE_F)\t\t\t \\\n-R(sec_mark_ptype_rss,\t\t1, 0, 1, 0, 0, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | PTYPE_F | RSS_F)\t\t \\\n-R(sec_mark_cksum,\t\t1, 0, 1, 0, 1, 0, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | CKSUM_F)\t\t\t \\\n-R(sec_mark_cksum_rss,\t\t1, 0, 1, 0, 1, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | CKSUM_F | RSS_F)\t\t \\\n-R(sec_mark_cksum_ptype,\t\t1, 0, 1, 0, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | CKSUM_F | PTYPE_F)\t\t \\\n-R(sec_mark_cksum_ptype_rss,\t1, 0, 1, 0, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F)\t \\\n-R(sec_mark_vlan,\t\t1, 0, 1, 1, 0, 0, 0, RX_SEC_F | RX_VLAN_F) \\\n-R(sec_mark_vlan_rss,\t\t1, 0, 1, 1, 0, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | RX_VLAN_F | RSS_F)\t\t \\\n-R(sec_mark_vlan_ptype,\t\t1, 0, 1, 1, 0, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | RX_VLAN_F | PTYPE_F)\t \\\n-R(sec_mark_vlan_ptype_rss,\t1, 0, 1, 1, 0, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | RX_VLAN_F | PTYPE_F | RSS_F) \\\n-R(sec_mark_vlan_cksum,\t\t1, 0, 1, 1, 1, 0, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | RX_VLAN_F | CKSUM_F)\t \\\n-R(sec_mark_vlan_cksum_rss,\t1, 0, 1, 1, 1, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | RX_VLAN_F | CKSUM_F | RSS_F) \\\n-R(sec_mark_vlan_cksum_ptype,\t1, 0, 1, 1, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | RX_VLAN_F | CKSUM_F | PTYPE_F) \\\n-R(sec_mark_vlan_cksum_ptype_rss,\t\t\t\t\t \\\n-\t\t\t\t1, 0, 1, 1, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | MARK_F | RX_VLAN_F | CKSUM_F | PTYPE_F | \\\n-\t\t\tRSS_F)\t\t\t\t\t\t \\\n-R(sec_ts,\t\t\t1, 1, 0, 0, 0, 0, 0, RX_SEC_F | TS_F)\t \\\n-R(sec_ts_rss,\t\t\t1, 1, 0, 0, 0, 0, 1, RX_SEC_F | TS_F | RSS_F) \\\n-R(sec_ts_ptype,\t\t\t1, 1, 0, 0, 0, 1, 0, RX_SEC_F | TS_F | PTYPE_F)\\\n-R(sec_ts_ptype_rss,\t\t1, 1, 0, 0, 0, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | PTYPE_F | RSS_F)\t\t \\\n-R(sec_ts_cksum,\t\t\t1, 1, 0, 0, 1, 0, 0, RX_SEC_F | TS_F | CKSUM_F)\\\n-R(sec_ts_cksum_rss,\t\t1, 1, 0, 0, 1, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | CKSUM_F | RSS_F)\t\t \\\n-R(sec_ts_cksum_ptype,\t\t1, 1, 0, 0, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | CKSUM_F | PTYPE_F)\t\t\t \\\n-R(sec_ts_cksum_ptype_rss,\t1, 1, 0, 0, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | CKSUM_F | PTYPE_F | RSS_F)\t \\\n-R(sec_ts_vlan,\t\t\t1, 1, 0, 1, 0, 0, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | RX_VLAN_F)\t\t\t \\\n-R(sec_ts_vlan_rss,\t\t1, 1, 0, 1, 0, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | RX_VLAN_F | RSS_F)\t\t \\\n-R(sec_ts_vlan_ptype,\t\t1, 1, 0, 1, 0, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | RX_VLAN_F | PTYPE_F)\t\t \\\n-R(sec_ts_vlan_ptype_rss,\t1, 1, 0, 1, 0, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | RX_VLAN_F | PTYPE_F | RSS_F)\t \\\n-R(sec_ts_vlan_cksum,\t\t1, 1, 0, 1, 1, 0, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | RX_VLAN_F | CKSUM_F)\t\t \\\n-R(sec_ts_vlan_cksum_rss,\t1, 1, 0, 1, 1, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | RX_VLAN_F | CKSUM_F | RSS_F)\t \\\n-R(sec_ts_vlan_cksum_ptype,\t1, 1, 0, 1, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | RX_VLAN_F | CKSUM_F | PTYPE_F) \\\n-R(sec_ts_vlan_cksum_ptype_rss,\t1, 1, 0, 1, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | RX_VLAN_F | CKSUM_F | PTYPE_F | \\\n-\t\t\tRSS_F)\t\t\t\t\t\t \\\n-R(sec_ts_mark,\t\t\t1, 1, 1, 0, 0, 0, 0, RX_SEC_F | TS_F | MARK_F) \\\n-R(sec_ts_mark_rss,\t\t1, 1, 1, 0, 0, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | RSS_F)\t\t \\\n-R(sec_ts_mark_ptype,\t\t1, 1, 1, 0, 0, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | PTYPE_F)\t\t \\\n-R(sec_ts_mark_ptype_rss,\t1, 1, 1, 0, 0, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | PTYPE_F | RSS_F)\t \\\n-R(sec_ts_mark_cksum,\t\t1, 1, 1, 0, 1, 0, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | CKSUM_F)\t\t \\\n-R(sec_ts_mark_cksum_rss,\t1, 1, 1, 0, 1, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | CKSUM_F | RSS_F)\t \\\n-R(sec_ts_mark_cksum_ptype,\t1, 1, 1, 0, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | CKSUM_F | PTYPE_F)\t \\\n-R(sec_ts_mark_cksum_ptype_rss,\t1, 1, 1, 0, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | CKSUM_F | PTYPE_F | RSS_F) \\\n-R(sec_ts_mark_vlan,\t\t1, 1, 1, 1, 0, 0, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | RX_VLAN_F)\t\t \\\n-R(sec_ts_mark_vlan_rss,\t\t1, 1, 1, 1, 0, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | RX_VLAN_F | RSS_F)\t\t\t \\\n-R(sec_ts_mark_vlan_ptype,\t1, 1, 1, 1, 0, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | RX_VLAN_F | PTYPE_F)\t \\\n-R(sec_ts_mark_vlan_ptype_rss,\t1, 1, 1, 1, 0, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | RX_VLAN_F | PTYPE_F | RSS_F)\\\n-R(sec_ts_mark_vlan_cksum,\t1, 1, 1, 1, 1, 0, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | RX_VLAN_F | CKSUM_F)\t \\\n-R(sec_ts_mark_vlan_cksum_rss,\t1, 1, 1, 1, 1, 0, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | RX_VLAN_F | CKSUM_F | RSS_F)\\\n-R(sec_ts_mark_vlan_cksum_ptype,\t1, 1, 1, 1, 1, 1, 0,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | RX_VLAN_F | CKSUM_F | \\\n-\t\t\tPTYPE_F)\t\t\t\t\t \\\n-R(sec_ts_mark_vlan_cksum_ptype_rss,\t\t\t\t\t \\\n-\t\t\t\t1, 1, 1, 1, 1, 1, 1,\t\t\t \\\n-\t\t\tRX_SEC_F | TS_F | MARK_F | RX_VLAN_F | CKSUM_F | \\\n-\t\t\tPTYPE_F | RSS_F)\n-#endif /* __OTX2_RX_H__ */\ndiff --git a/drivers/net/octeontx2/otx2_stats.c b/drivers/net/octeontx2/otx2_stats.c\ndeleted file mode 100644\nindex 3adf21608c..0000000000\n--- a/drivers/net/octeontx2/otx2_stats.c\n+++ /dev/null\n@@ -1,397 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <inttypes.h>\n-\n-#include \"otx2_ethdev.h\"\n-\n-struct otx2_nix_xstats_name {\n-\tchar name[RTE_ETH_XSTATS_NAME_SIZE];\n-\tuint32_t offset;\n-};\n-\n-static const struct otx2_nix_xstats_name nix_tx_xstats[] = {\n-\t{\"tx_ucast\", NIX_STAT_LF_TX_TX_UCAST},\n-\t{\"tx_bcast\", NIX_STAT_LF_TX_TX_BCAST},\n-\t{\"tx_mcast\", NIX_STAT_LF_TX_TX_MCAST},\n-\t{\"tx_drop\", NIX_STAT_LF_TX_TX_DROP},\n-\t{\"tx_octs\", NIX_STAT_LF_TX_TX_OCTS},\n-};\n-\n-static const struct otx2_nix_xstats_name nix_rx_xstats[] = {\n-\t{\"rx_octs\", NIX_STAT_LF_RX_RX_OCTS},\n-\t{\"rx_ucast\", NIX_STAT_LF_RX_RX_UCAST},\n-\t{\"rx_bcast\", NIX_STAT_LF_RX_RX_BCAST},\n-\t{\"rx_mcast\", NIX_STAT_LF_RX_RX_MCAST},\n-\t{\"rx_drop\", NIX_STAT_LF_RX_RX_DROP},\n-\t{\"rx_drop_octs\", NIX_STAT_LF_RX_RX_DROP_OCTS},\n-\t{\"rx_fcs\", NIX_STAT_LF_RX_RX_FCS},\n-\t{\"rx_err\", NIX_STAT_LF_RX_RX_ERR},\n-\t{\"rx_drp_bcast\", NIX_STAT_LF_RX_RX_DRP_BCAST},\n-\t{\"rx_drp_mcast\", NIX_STAT_LF_RX_RX_DRP_MCAST},\n-\t{\"rx_drp_l3bcast\", NIX_STAT_LF_RX_RX_DRP_L3BCAST},\n-\t{\"rx_drp_l3mcast\", NIX_STAT_LF_RX_RX_DRP_L3MCAST},\n-};\n-\n-static const struct otx2_nix_xstats_name nix_q_xstats[] = {\n-\t{\"rq_op_re_pkts\", NIX_LF_RQ_OP_RE_PKTS},\n-};\n-\n-#define OTX2_NIX_NUM_RX_XSTATS RTE_DIM(nix_rx_xstats)\n-#define OTX2_NIX_NUM_TX_XSTATS RTE_DIM(nix_tx_xstats)\n-#define OTX2_NIX_NUM_QUEUE_XSTATS RTE_DIM(nix_q_xstats)\n-\n-#define OTX2_NIX_NUM_XSTATS_REG (OTX2_NIX_NUM_RX_XSTATS + \\\n-\t\tOTX2_NIX_NUM_TX_XSTATS + OTX2_NIX_NUM_QUEUE_XSTATS)\n-\n-int\n-otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,\n-\t\t struct rte_eth_stats *stats)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint64_t reg, val;\n-\tuint32_t qidx, i;\n-\tint64_t *addr;\n-\n-\tstats->opackets = otx2_read64(dev->base +\n-\t\t\tNIX_LF_TX_STATX(NIX_STAT_LF_TX_TX_UCAST));\n-\tstats->opackets += otx2_read64(dev->base +\n-\t\t\tNIX_LF_TX_STATX(NIX_STAT_LF_TX_TX_MCAST));\n-\tstats->opackets += otx2_read64(dev->base +\n-\t\t\tNIX_LF_TX_STATX(NIX_STAT_LF_TX_TX_BCAST));\n-\tstats->oerrors = otx2_read64(dev->base +\n-\t\t\tNIX_LF_TX_STATX(NIX_STAT_LF_TX_TX_DROP));\n-\tstats->obytes = otx2_read64(dev->base +\n-\t\t\tNIX_LF_TX_STATX(NIX_STAT_LF_TX_TX_OCTS));\n-\n-\tstats->ipackets = otx2_read64(dev->base +\n-\t\t\tNIX_LF_RX_STATX(NIX_STAT_LF_RX_RX_UCAST));\n-\tstats->ipackets += otx2_read64(dev->base +\n-\t\t\tNIX_LF_RX_STATX(NIX_STAT_LF_RX_RX_MCAST));\n-\tstats->ipackets += otx2_read64(dev->base +\n-\t\t\tNIX_LF_RX_STATX(NIX_STAT_LF_RX_RX_BCAST));\n-\tstats->imissed = otx2_read64(dev->base +\n-\t\t\tNIX_LF_RX_STATX(NIX_STAT_LF_RX_RX_DROP));\n-\tstats->ibytes = otx2_read64(dev->base +\n-\t\t\tNIX_LF_RX_STATX(NIX_STAT_LF_RX_RX_OCTS));\n-\tstats->ierrors = otx2_read64(dev->base +\n-\t\t\tNIX_LF_RX_STATX(NIX_STAT_LF_RX_RX_ERR));\n-\n-\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) {\n-\t\tif (dev->txmap[i] & (1U << 31)) {\n-\t\t\tqidx = dev->txmap[i] & 0xFFFF;\n-\t\t\treg = (((uint64_t)qidx) << 32);\n-\n-\t\t\taddr = (int64_t *)(dev->base + NIX_LF_SQ_OP_PKTS);\n-\t\t\tval = otx2_atomic64_add_nosync(reg, addr);\n-\t\t\tif (val & OP_ERR)\n-\t\t\t\tval = 0;\n-\t\t\tstats->q_opackets[i] = val;\n-\n-\t\t\taddr = (int64_t *)(dev->base + NIX_LF_SQ_OP_OCTS);\n-\t\t\tval = otx2_atomic64_add_nosync(reg, addr);\n-\t\t\tif (val & OP_ERR)\n-\t\t\t\tval = 0;\n-\t\t\tstats->q_obytes[i] = val;\n-\n-\t\t\taddr = (int64_t *)(dev->base + NIX_LF_SQ_OP_DROP_PKTS);\n-\t\t\tval = otx2_atomic64_add_nosync(reg, addr);\n-\t\t\tif (val & OP_ERR)\n-\t\t\t\tval = 0;\n-\t\t\tstats->q_errors[i] = val;\n-\t\t}\n-\t}\n-\n-\tfor (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) {\n-\t\tif (dev->rxmap[i] & (1U << 31)) {\n-\t\t\tqidx = dev->rxmap[i] & 0xFFFF;\n-\t\t\treg = (((uint64_t)qidx) << 32);\n-\n-\t\t\taddr = (int64_t *)(dev->base + NIX_LF_RQ_OP_PKTS);\n-\t\t\tval = otx2_atomic64_add_nosync(reg, addr);\n-\t\t\tif (val & OP_ERR)\n-\t\t\t\tval = 0;\n-\t\t\tstats->q_ipackets[i] = val;\n-\n-\t\t\taddr = (int64_t *)(dev->base + NIX_LF_RQ_OP_OCTS);\n-\t\t\tval = otx2_atomic64_add_nosync(reg, addr);\n-\t\t\tif (val & OP_ERR)\n-\t\t\t\tval = 0;\n-\t\t\tstats->q_ibytes[i] = val;\n-\n-\t\t\taddr = (int64_t *)(dev->base + NIX_LF_RQ_OP_DROP_PKTS);\n-\t\t\tval = otx2_atomic64_add_nosync(reg, addr);\n-\t\t\tif (val & OP_ERR)\n-\t\t\t\tval = 0;\n-\t\t\tstats->q_errors[i] += val;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_dev_stats_reset(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\n-\tif (otx2_mbox_alloc_msg_nix_stats_rst(mbox) == NULL)\n-\t\treturn -ENOMEM;\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-int\n-otx2_nix_queue_stats_mapping(struct rte_eth_dev *eth_dev, uint16_t queue_id,\n-\t\t\t uint8_t stat_idx, uint8_t is_rx)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tif (is_rx)\n-\t\tdev->rxmap[stat_idx] = ((1U << 31) | queue_id);\n-\telse\n-\t\tdev->txmap[stat_idx] = ((1U << 31) | queue_id);\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_xstats_get(struct rte_eth_dev *eth_dev,\n-\t\t struct rte_eth_xstat *xstats,\n-\t\t unsigned int n)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tunsigned int i, count = 0;\n-\tuint64_t reg, val;\n-\n-\tif (n < OTX2_NIX_NUM_XSTATS_REG)\n-\t\treturn OTX2_NIX_NUM_XSTATS_REG;\n-\n-\tif (xstats == NULL)\n-\t\treturn 0;\n-\n-\tfor (i = 0; i < OTX2_NIX_NUM_TX_XSTATS; i++) {\n-\t\txstats[count].value = otx2_read64(dev->base +\n-\t\tNIX_LF_TX_STATX(nix_tx_xstats[i].offset));\n-\t\txstats[count].id = count;\n-\t\tcount++;\n-\t}\n-\n-\tfor (i = 0; i < OTX2_NIX_NUM_RX_XSTATS; i++) {\n-\t\txstats[count].value = otx2_read64(dev->base +\n-\t\tNIX_LF_RX_STATX(nix_rx_xstats[i].offset));\n-\t\txstats[count].id = count;\n-\t\tcount++;\n-\t}\n-\n-\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n-\t\treg = (((uint64_t)i) << 32);\n-\t\tval = otx2_atomic64_add_nosync(reg, (int64_t *)(dev->base +\n-\t\t\t\t\t nix_q_xstats[0].offset));\n-\t\tif (val & OP_ERR)\n-\t\t\tval = 0;\n-\t\txstats[count].value += val;\n-\t}\n-\txstats[count].id = count;\n-\tcount++;\n-\n-\treturn count;\n-}\n-\n-int\n-otx2_nix_xstats_get_names(struct rte_eth_dev *eth_dev,\n-\t\t\t struct rte_eth_xstat_name *xstats_names,\n-\t\t\t unsigned int limit)\n-{\n-\tunsigned int i, count = 0;\n-\n-\tRTE_SET_USED(eth_dev);\n-\n-\tif (limit < OTX2_NIX_NUM_XSTATS_REG && xstats_names != NULL)\n-\t\treturn -ENOMEM;\n-\n-\tif (xstats_names) {\n-\t\tfor (i = 0; i < OTX2_NIX_NUM_TX_XSTATS; i++) {\n-\t\t\tsnprintf(xstats_names[count].name,\n-\t\t\t\t sizeof(xstats_names[count].name),\n-\t\t\t\t \"%s\", nix_tx_xstats[i].name);\n-\t\t\tcount++;\n-\t\t}\n-\n-\t\tfor (i = 0; i < OTX2_NIX_NUM_RX_XSTATS; i++) {\n-\t\t\tsnprintf(xstats_names[count].name,\n-\t\t\t\t sizeof(xstats_names[count].name),\n-\t\t\t\t \"%s\", nix_rx_xstats[i].name);\n-\t\t\tcount++;\n-\t\t}\n-\n-\t\tfor (i = 0; i < OTX2_NIX_NUM_QUEUE_XSTATS; i++) {\n-\t\t\tsnprintf(xstats_names[count].name,\n-\t\t\t\t sizeof(xstats_names[count].name),\n-\t\t\t\t \"%s\", nix_q_xstats[i].name);\n-\t\t\tcount++;\n-\t\t}\n-\t}\n-\n-\treturn OTX2_NIX_NUM_XSTATS_REG;\n-}\n-\n-int\n-otx2_nix_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,\n-\t\t\t\tconst uint64_t *ids,\n-\t\t\t\tstruct rte_eth_xstat_name *xstats_names,\n-\t\t\t\tunsigned int limit)\n-{\n-\tstruct rte_eth_xstat_name xstats_names_copy[OTX2_NIX_NUM_XSTATS_REG];\n-\tuint16_t i;\n-\n-\tif (limit < OTX2_NIX_NUM_XSTATS_REG && ids == NULL)\n-\t\treturn OTX2_NIX_NUM_XSTATS_REG;\n-\n-\tif (limit > OTX2_NIX_NUM_XSTATS_REG)\n-\t\treturn -EINVAL;\n-\n-\tif (xstats_names == NULL)\n-\t\treturn -ENOMEM;\n-\n-\totx2_nix_xstats_get_names(eth_dev, xstats_names_copy, limit);\n-\n-\tfor (i = 0; i < OTX2_NIX_NUM_XSTATS_REG; i++) {\n-\t\tif (ids[i] >= OTX2_NIX_NUM_XSTATS_REG) {\n-\t\t\totx2_err(\"Invalid id value\");\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tstrncpy(xstats_names[i].name, xstats_names_copy[ids[i]].name,\n-\t\t\tsizeof(xstats_names[i].name));\n-\t}\n-\n-\treturn limit;\n-}\n-\n-int\n-otx2_nix_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,\n-\t\t\t uint64_t *values, unsigned int n)\n-{\n-\tstruct rte_eth_xstat xstats[OTX2_NIX_NUM_XSTATS_REG];\n-\tuint16_t i;\n-\n-\tif (n < OTX2_NIX_NUM_XSTATS_REG && ids == NULL)\n-\t\treturn OTX2_NIX_NUM_XSTATS_REG;\n-\n-\tif (n > OTX2_NIX_NUM_XSTATS_REG)\n-\t\treturn -EINVAL;\n-\n-\tif (values == NULL)\n-\t\treturn -ENOMEM;\n-\n-\totx2_nix_xstats_get(eth_dev, xstats, n);\n-\n-\tfor (i = 0; i < OTX2_NIX_NUM_XSTATS_REG; i++) {\n-\t\tif (ids[i] >= OTX2_NIX_NUM_XSTATS_REG) {\n-\t\t\totx2_err(\"Invalid id value\");\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t\tvalues[i] = xstats[ids[i]].value;\n-\t}\n-\n-\treturn n;\n-}\n-\n-static int\n-nix_queue_stats_reset(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_aq_enq_rsp *rsp;\n-\tstruct nix_aq_enq_req *aq;\n-\tuint32_t i;\n-\tint rc;\n-\n-\tfor (i = 0; i < eth_dev->data->nb_rx_queues; i++) {\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\taq->qidx = i;\n-\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n-\t\taq->op = NIX_AQ_INSTOP_READ;\n-\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to read rq context\");\n-\t\t\treturn rc;\n-\t\t}\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\taq->qidx = i;\n-\t\taq->ctype = NIX_AQ_CTYPE_RQ;\n-\t\taq->op = NIX_AQ_INSTOP_WRITE;\n-\t\totx2_mbox_memcpy(&aq->rq, &rsp->rq, sizeof(rsp->rq));\n-\t\totx2_mbox_memset(&aq->rq_mask, 0, sizeof(aq->rq_mask));\n-\t\taq->rq.octs = 0;\n-\t\taq->rq.pkts = 0;\n-\t\taq->rq.drop_octs = 0;\n-\t\taq->rq.drop_pkts = 0;\n-\t\taq->rq.re_pkts = 0;\n-\n-\t\taq->rq_mask.octs = ~(aq->rq_mask.octs);\n-\t\taq->rq_mask.pkts = ~(aq->rq_mask.pkts);\n-\t\taq->rq_mask.drop_octs = ~(aq->rq_mask.drop_octs);\n-\t\taq->rq_mask.drop_pkts = ~(aq->rq_mask.drop_pkts);\n-\t\taq->rq_mask.re_pkts = ~(aq->rq_mask.re_pkts);\n-\t\trc = otx2_mbox_process(mbox);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to write rq context\");\n-\t\t\treturn rc;\n-\t\t}\n-\t}\n-\n-\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\taq->qidx = i;\n-\t\taq->ctype = NIX_AQ_CTYPE_SQ;\n-\t\taq->op = NIX_AQ_INSTOP_READ;\n-\t\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to read sq context\");\n-\t\t\treturn rc;\n-\t\t}\n-\t\taq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\t\taq->qidx = i;\n-\t\taq->ctype = NIX_AQ_CTYPE_SQ;\n-\t\taq->op = NIX_AQ_INSTOP_WRITE;\n-\t\totx2_mbox_memcpy(&aq->sq, &rsp->sq, sizeof(rsp->sq));\n-\t\totx2_mbox_memset(&aq->sq_mask, 0, sizeof(aq->sq_mask));\n-\t\taq->sq.octs = 0;\n-\t\taq->sq.pkts = 0;\n-\t\taq->sq.drop_octs = 0;\n-\t\taq->sq.drop_pkts = 0;\n-\n-\t\taq->sq_mask.octs = ~(aq->sq_mask.octs);\n-\t\taq->sq_mask.pkts = ~(aq->sq_mask.pkts);\n-\t\taq->sq_mask.drop_octs = ~(aq->sq_mask.drop_octs);\n-\t\taq->sq_mask.drop_pkts = ~(aq->sq_mask.drop_pkts);\n-\t\trc = otx2_mbox_process(mbox);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to write sq context\");\n-\t\t\treturn rc;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_xstats_reset(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tint ret;\n-\n-\tif (otx2_mbox_alloc_msg_nix_stats_rst(mbox) == NULL)\n-\t\treturn -ENOMEM;\n-\n-\tret = otx2_mbox_process(mbox);\n-\tif (ret != 0)\n-\t\treturn ret;\n-\n-\t/* Reset queue stats */\n-\treturn nix_queue_stats_reset(eth_dev);\n-}\ndiff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c\ndeleted file mode 100644\nindex 6aff1f9587..0000000000\n--- a/drivers/net/octeontx2/otx2_tm.c\n+++ /dev/null\n@@ -1,3317 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_malloc.h>\n-\n-#include \"otx2_ethdev.h\"\n-#include \"otx2_tm.h\"\n-\n-/* Use last LVL_CNT nodes as default nodes */\n-#define NIX_DEFAULT_NODE_ID_START (RTE_TM_NODE_ID_NULL - NIX_TXSCH_LVL_CNT)\n-\n-enum otx2_tm_node_level {\n-\tOTX2_TM_LVL_ROOT = 0,\n-\tOTX2_TM_LVL_SCH1,\n-\tOTX2_TM_LVL_SCH2,\n-\tOTX2_TM_LVL_SCH3,\n-\tOTX2_TM_LVL_SCH4,\n-\tOTX2_TM_LVL_QUEUE,\n-\tOTX2_TM_LVL_MAX,\n-};\n-\n-static inline\n-uint64_t shaper2regval(struct shaper_params *shaper)\n-{\n-\treturn (shaper->burst_exponent << 37) | (shaper->burst_mantissa << 29) |\n-\t\t(shaper->div_exp << 13) | (shaper->exponent << 9) |\n-\t\t(shaper->mantissa << 1);\n-}\n-\n-int\n-otx2_nix_get_link(struct otx2_eth_dev *dev)\n-{\n-\tint link = 13 /* SDP */;\n-\tuint16_t lmac_chan;\n-\tuint16_t map;\n-\n-\tlmac_chan = dev->tx_chan_base;\n-\n-\t/* CGX lmac link */\n-\tif (lmac_chan >= 0x800) {\n-\t\tmap = lmac_chan & 0x7FF;\n-\t\tlink = 4 * ((map >> 8) & 0xF) + ((map >> 4) & 0xF);\n-\t} else if (lmac_chan < 0x700) {\n-\t\t/* LBK channel */\n-\t\tlink = 12;\n-\t}\n-\n-\treturn link;\n-}\n-\n-static uint8_t\n-nix_get_relchan(struct otx2_eth_dev *dev)\n-{\n-\treturn dev->tx_chan_base & 0xff;\n-}\n-\n-static bool\n-nix_tm_have_tl1_access(struct otx2_eth_dev *dev)\n-{\n-\tbool is_lbk = otx2_dev_is_lbk(dev);\n-\treturn otx2_dev_is_pf(dev) && !otx2_dev_is_Ax(dev) && !is_lbk;\n-}\n-\n-static bool\n-nix_tm_is_leaf(struct otx2_eth_dev *dev, int lvl)\n-{\n-\tif (nix_tm_have_tl1_access(dev))\n-\t\treturn (lvl == OTX2_TM_LVL_QUEUE);\n-\n-\treturn (lvl == OTX2_TM_LVL_SCH4);\n-}\n-\n-static int\n-find_prio_anchor(struct otx2_eth_dev *dev, uint32_t node_id)\n-{\n-\tstruct otx2_nix_tm_node *child_node;\n-\n-\tTAILQ_FOREACH(child_node, &dev->node_list, node) {\n-\t\tif (!child_node->parent)\n-\t\t\tcontinue;\n-\t\tif (!(child_node->parent->id == node_id))\n-\t\t\tcontinue;\n-\t\tif (child_node->priority == child_node->parent->rr_prio)\n-\t\t\tcontinue;\n-\t\treturn child_node->hw_id - child_node->priority;\n-\t}\n-\treturn 0;\n-}\n-\n-\n-static struct otx2_nix_tm_shaper_profile *\n-nix_tm_shaper_profile_search(struct otx2_eth_dev *dev, uint32_t shaper_id)\n-{\n-\tstruct otx2_nix_tm_shaper_profile *tm_shaper_profile;\n-\n-\tTAILQ_FOREACH(tm_shaper_profile, &dev->shaper_profile_list, shaper) {\n-\t\tif (tm_shaper_profile->shaper_profile_id == shaper_id)\n-\t\t\treturn tm_shaper_profile;\n-\t}\n-\treturn NULL;\n-}\n-\n-static inline uint64_t\n-shaper_rate_to_nix(uint64_t value, uint64_t *exponent_p,\n-\t\t uint64_t *mantissa_p, uint64_t *div_exp_p)\n-{\n-\tuint64_t div_exp, exponent, mantissa;\n-\n-\t/* Boundary checks */\n-\tif (value < MIN_SHAPER_RATE ||\n-\t value > MAX_SHAPER_RATE)\n-\t\treturn 0;\n-\n-\tif (value <= SHAPER_RATE(0, 0, 0)) {\n-\t\t/* Calculate rate div_exp and mantissa using\n-\t\t * the following formula:\n-\t\t *\n-\t\t * value = (2E6 * (256 + mantissa)\n-\t\t * / ((1 << div_exp) * 256))\n-\t\t */\n-\t\tdiv_exp = 0;\n-\t\texponent = 0;\n-\t\tmantissa = MAX_RATE_MANTISSA;\n-\n-\t\twhile (value < (NIX_SHAPER_RATE_CONST / (1 << div_exp)))\n-\t\t\tdiv_exp += 1;\n-\n-\t\twhile (value <\n-\t\t ((NIX_SHAPER_RATE_CONST * (256 + mantissa)) /\n-\t\t\t((1 << div_exp) * 256)))\n-\t\t\tmantissa -= 1;\n-\t} else {\n-\t\t/* Calculate rate exponent and mantissa using\n-\t\t * the following formula:\n-\t\t *\n-\t\t * value = (2E6 * ((256 + mantissa) << exponent)) / 256\n-\t\t *\n-\t\t */\n-\t\tdiv_exp = 0;\n-\t\texponent = MAX_RATE_EXPONENT;\n-\t\tmantissa = MAX_RATE_MANTISSA;\n-\n-\t\twhile (value < (NIX_SHAPER_RATE_CONST * (1 << exponent)))\n-\t\t\texponent -= 1;\n-\n-\t\twhile (value < ((NIX_SHAPER_RATE_CONST *\n-\t\t\t\t((256 + mantissa) << exponent)) / 256))\n-\t\t\tmantissa -= 1;\n-\t}\n-\n-\tif (div_exp > MAX_RATE_DIV_EXP ||\n-\t exponent > MAX_RATE_EXPONENT || mantissa > MAX_RATE_MANTISSA)\n-\t\treturn 0;\n-\n-\tif (div_exp_p)\n-\t\t*div_exp_p = div_exp;\n-\tif (exponent_p)\n-\t\t*exponent_p = exponent;\n-\tif (mantissa_p)\n-\t\t*mantissa_p = mantissa;\n-\n-\t/* Calculate real rate value */\n-\treturn SHAPER_RATE(exponent, mantissa, div_exp);\n-}\n-\n-static inline uint64_t\n-shaper_burst_to_nix(uint64_t value, uint64_t *exponent_p,\n-\t\t uint64_t *mantissa_p)\n-{\n-\tuint64_t exponent, mantissa;\n-\n-\tif (value < MIN_SHAPER_BURST || value > MAX_SHAPER_BURST)\n-\t\treturn 0;\n-\n-\t/* Calculate burst exponent and mantissa using\n-\t * the following formula:\n-\t *\n-\t * value = (((256 + mantissa) << (exponent + 1)\n-\t / 256)\n-\t *\n-\t */\n-\texponent = MAX_BURST_EXPONENT;\n-\tmantissa = MAX_BURST_MANTISSA;\n-\n-\twhile (value < (1ull << (exponent + 1)))\n-\t\texponent -= 1;\n-\n-\twhile (value < ((256 + mantissa) << (exponent + 1)) / 256)\n-\t\tmantissa -= 1;\n-\n-\tif (exponent > MAX_BURST_EXPONENT || mantissa > MAX_BURST_MANTISSA)\n-\t\treturn 0;\n-\n-\tif (exponent_p)\n-\t\t*exponent_p = exponent;\n-\tif (mantissa_p)\n-\t\t*mantissa_p = mantissa;\n-\n-\treturn SHAPER_BURST(exponent, mantissa);\n-}\n-\n-static void\n-shaper_config_to_nix(struct otx2_nix_tm_shaper_profile *profile,\n-\t\t struct shaper_params *cir,\n-\t\t struct shaper_params *pir)\n-{\n-\tstruct rte_tm_shaper_params *param = &profile->params;\n-\n-\tif (!profile)\n-\t\treturn;\n-\n-\t/* Calculate CIR exponent and mantissa */\n-\tif (param->committed.rate)\n-\t\tcir->rate = shaper_rate_to_nix(param->committed.rate,\n-\t\t\t\t\t &cir->exponent,\n-\t\t\t\t\t &cir->mantissa,\n-\t\t\t\t\t &cir->div_exp);\n-\n-\t/* Calculate PIR exponent and mantissa */\n-\tif (param->peak.rate)\n-\t\tpir->rate = shaper_rate_to_nix(param->peak.rate,\n-\t\t\t\t\t &pir->exponent,\n-\t\t\t\t\t &pir->mantissa,\n-\t\t\t\t\t &pir->div_exp);\n-\n-\t/* Calculate CIR burst exponent and mantissa */\n-\tif (param->committed.size)\n-\t\tcir->burst = shaper_burst_to_nix(param->committed.size,\n-\t\t\t\t\t\t &cir->burst_exponent,\n-\t\t\t\t\t\t &cir->burst_mantissa);\n-\n-\t/* Calculate PIR burst exponent and mantissa */\n-\tif (param->peak.size)\n-\t\tpir->burst = shaper_burst_to_nix(param->peak.size,\n-\t\t\t\t\t\t &pir->burst_exponent,\n-\t\t\t\t\t\t &pir->burst_mantissa);\n-}\n-\n-static void\n-shaper_default_red_algo(struct otx2_eth_dev *dev,\n-\t\t\tstruct otx2_nix_tm_node *tm_node,\n-\t\t\tstruct otx2_nix_tm_shaper_profile *profile)\n-{\n-\tstruct shaper_params cir, pir;\n-\n-\t/* C0 doesn't support STALL when both PIR & CIR are enabled */\n-\tif (profile && otx2_dev_is_96xx_Cx(dev)) {\n-\t\tmemset(&cir, 0, sizeof(cir));\n-\t\tmemset(&pir, 0, sizeof(pir));\n-\t\tshaper_config_to_nix(profile, &cir, &pir);\n-\n-\t\tif (pir.rate && cir.rate) {\n-\t\t\ttm_node->red_algo = NIX_REDALG_DISCARD;\n-\t\t\ttm_node->flags |= NIX_TM_NODE_RED_DISCARD;\n-\t\t\treturn;\n-\t\t}\n-\t}\n-\n-\ttm_node->red_algo = NIX_REDALG_STD;\n-\ttm_node->flags &= ~NIX_TM_NODE_RED_DISCARD;\n-}\n-\n-static int\n-populate_tm_tl1_default(struct otx2_eth_dev *dev, uint32_t schq)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_txschq_config *req;\n-\n-\t/*\n-\t * Default config for TL1.\n-\t * For VF this is always ignored.\n-\t */\n-\n-\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\treq->lvl = NIX_TXSCH_LVL_TL1;\n-\n-\t/* Set DWRR quantum */\n-\treq->reg[0] = NIX_AF_TL1X_SCHEDULE(schq);\n-\treq->regval[0] = TXSCH_TL1_DFLT_RR_QTM;\n-\treq->num_regs++;\n-\n-\treq->reg[1] = NIX_AF_TL1X_TOPOLOGY(schq);\n-\treq->regval[1] = (TXSCH_TL1_DFLT_RR_PRIO << 1);\n-\treq->num_regs++;\n-\n-\treq->reg[2] = NIX_AF_TL1X_CIR(schq);\n-\treq->regval[2] = 0;\n-\treq->num_regs++;\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-static uint8_t\n-prepare_tm_sched_reg(struct otx2_eth_dev *dev,\n-\t\t struct otx2_nix_tm_node *tm_node,\n-\t\t volatile uint64_t *reg, volatile uint64_t *regval)\n-{\n-\tuint64_t strict_prio = tm_node->priority;\n-\tuint32_t hw_lvl = tm_node->hw_lvl;\n-\tuint32_t schq = tm_node->hw_id;\n-\tuint64_t rr_quantum;\n-\tuint8_t k = 0;\n-\n-\trr_quantum = NIX_TM_WEIGHT_TO_RR_QUANTUM(tm_node->weight);\n-\n-\t/* For children to root, strict prio is default if either\n-\t * device root is TL2 or TL1 Static Priority is disabled.\n-\t */\n-\tif (hw_lvl == NIX_TXSCH_LVL_TL2 &&\n-\t (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 ||\n-\t dev->tm_flags & NIX_TM_TL1_NO_SP))\n-\t\tstrict_prio = TXSCH_TL1_DFLT_RR_PRIO;\n-\n-\totx2_tm_dbg(\"Schedule config node %s(%u) lvl %u id %u, \"\n-\t\t \"prio 0x%\" PRIx64 \", rr_quantum 0x%\" PRIx64 \" (%p)\",\n-\t\t nix_hwlvl2str(tm_node->hw_lvl), schq, tm_node->lvl,\n-\t\t tm_node->id, strict_prio, rr_quantum, tm_node);\n-\n-\tswitch (hw_lvl) {\n-\tcase NIX_TXSCH_LVL_SMQ:\n-\t\treg[k] = NIX_AF_MDQX_SCHEDULE(schq);\n-\t\tregval[k] = (strict_prio << 24) | rr_quantum;\n-\t\tk++;\n-\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL4:\n-\t\treg[k] = NIX_AF_TL4X_SCHEDULE(schq);\n-\t\tregval[k] = (strict_prio << 24) | rr_quantum;\n-\t\tk++;\n-\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL3:\n-\t\treg[k] = NIX_AF_TL3X_SCHEDULE(schq);\n-\t\tregval[k] = (strict_prio << 24) | rr_quantum;\n-\t\tk++;\n-\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL2:\n-\t\treg[k] = NIX_AF_TL2X_SCHEDULE(schq);\n-\t\tregval[k] = (strict_prio << 24) | rr_quantum;\n-\t\tk++;\n-\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL1:\n-\t\treg[k] = NIX_AF_TL1X_SCHEDULE(schq);\n-\t\tregval[k] = rr_quantum;\n-\t\tk++;\n-\n-\t\tbreak;\n-\t}\n-\n-\treturn k;\n-}\n-\n-static uint8_t\n-prepare_tm_shaper_reg(struct otx2_nix_tm_node *tm_node,\n-\t\t struct otx2_nix_tm_shaper_profile *profile,\n-\t\t volatile uint64_t *reg, volatile uint64_t *regval)\n-{\n-\tstruct shaper_params cir, pir;\n-\tuint32_t schq = tm_node->hw_id;\n-\tuint64_t adjust = 0;\n-\tuint8_t k = 0;\n-\n-\tmemset(&cir, 0, sizeof(cir));\n-\tmemset(&pir, 0, sizeof(pir));\n-\tshaper_config_to_nix(profile, &cir, &pir);\n-\n-\t/* Packet length adjust */\n-\tif (tm_node->pkt_mode)\n-\t\tadjust = 1;\n-\telse if (profile)\n-\t\tadjust = profile->params.pkt_length_adjust & 0x1FF;\n-\n-\totx2_tm_dbg(\"Shaper config node %s(%u) lvl %u id %u, pir %\" PRIu64\n-\t\t \"(%\" PRIu64 \"B), cir %\" PRIu64 \"(%\" PRIu64 \"B)\"\n-\t\t \"adjust 0x%\" PRIx64 \"(pktmode %u) (%p)\",\n-\t\t nix_hwlvl2str(tm_node->hw_lvl), schq, tm_node->lvl,\n-\t\t tm_node->id, pir.rate, pir.burst, cir.rate, cir.burst,\n-\t\t adjust, tm_node->pkt_mode, tm_node);\n-\n-\tswitch (tm_node->hw_lvl) {\n-\tcase NIX_TXSCH_LVL_SMQ:\n-\t\t/* Configure PIR, CIR */\n-\t\treg[k] = NIX_AF_MDQX_PIR(schq);\n-\t\tregval[k] = (pir.rate && pir.burst) ?\n-\t\t\t\t(shaper2regval(&pir) | 1) : 0;\n-\t\tk++;\n-\n-\t\treg[k] = NIX_AF_MDQX_CIR(schq);\n-\t\tregval[k] = (cir.rate && cir.burst) ?\n-\t\t\t\t(shaper2regval(&cir) | 1) : 0;\n-\t\tk++;\n-\n-\t\t/* Configure RED ALG */\n-\t\treg[k] = NIX_AF_MDQX_SHAPE(schq);\n-\t\tregval[k] = (adjust |\n-\t\t\t (uint64_t)tm_node->red_algo << 9 |\n-\t\t\t (uint64_t)tm_node->pkt_mode << 24);\n-\t\tk++;\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL4:\n-\t\t/* Configure PIR, CIR */\n-\t\treg[k] = NIX_AF_TL4X_PIR(schq);\n-\t\tregval[k] = (pir.rate && pir.burst) ?\n-\t\t\t\t(shaper2regval(&pir) | 1) : 0;\n-\t\tk++;\n-\n-\t\treg[k] = NIX_AF_TL4X_CIR(schq);\n-\t\tregval[k] = (cir.rate && cir.burst) ?\n-\t\t\t\t(shaper2regval(&cir) | 1) : 0;\n-\t\tk++;\n-\n-\t\t/* Configure RED algo */\n-\t\treg[k] = NIX_AF_TL4X_SHAPE(schq);\n-\t\tregval[k] = (adjust |\n-\t\t\t (uint64_t)tm_node->red_algo << 9 |\n-\t\t\t (uint64_t)tm_node->pkt_mode << 24);\n-\t\tk++;\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL3:\n-\t\t/* Configure PIR, CIR */\n-\t\treg[k] = NIX_AF_TL3X_PIR(schq);\n-\t\tregval[k] = (pir.rate && pir.burst) ?\n-\t\t\t\t(shaper2regval(&pir) | 1) : 0;\n-\t\tk++;\n-\n-\t\treg[k] = NIX_AF_TL3X_CIR(schq);\n-\t\tregval[k] = (cir.rate && cir.burst) ?\n-\t\t\t\t(shaper2regval(&cir) | 1) : 0;\n-\t\tk++;\n-\n-\t\t/* Configure RED algo */\n-\t\treg[k] = NIX_AF_TL3X_SHAPE(schq);\n-\t\tregval[k] = (adjust |\n-\t\t\t (uint64_t)tm_node->red_algo << 9 |\n-\t\t\t (uint64_t)tm_node->pkt_mode << 24);\n-\t\tk++;\n-\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL2:\n-\t\t/* Configure PIR, CIR */\n-\t\treg[k] = NIX_AF_TL2X_PIR(schq);\n-\t\tregval[k] = (pir.rate && pir.burst) ?\n-\t\t\t\t(shaper2regval(&pir) | 1) : 0;\n-\t\tk++;\n-\n-\t\treg[k] = NIX_AF_TL2X_CIR(schq);\n-\t\tregval[k] = (cir.rate && cir.burst) ?\n-\t\t\t\t(shaper2regval(&cir) | 1) : 0;\n-\t\tk++;\n-\n-\t\t/* Configure RED algo */\n-\t\treg[k] = NIX_AF_TL2X_SHAPE(schq);\n-\t\tregval[k] = (adjust |\n-\t\t\t (uint64_t)tm_node->red_algo << 9 |\n-\t\t\t (uint64_t)tm_node->pkt_mode << 24);\n-\t\tk++;\n-\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL1:\n-\t\t/* Configure CIR */\n-\t\treg[k] = NIX_AF_TL1X_CIR(schq);\n-\t\tregval[k] = (cir.rate && cir.burst) ?\n-\t\t\t\t(shaper2regval(&cir) | 1) : 0;\n-\t\tk++;\n-\n-\t\t/* Configure length disable and adjust */\n-\t\treg[k] = NIX_AF_TL1X_SHAPE(schq);\n-\t\tregval[k] = (adjust |\n-\t\t\t (uint64_t)tm_node->pkt_mode << 24);\n-\t\tk++;\n-\t\tbreak;\n-\t}\n-\n-\treturn k;\n-}\n-\n-static uint8_t\n-prepare_tm_sw_xoff(struct otx2_nix_tm_node *tm_node, bool enable,\n-\t\t volatile uint64_t *reg, volatile uint64_t *regval)\n-{\n-\tuint32_t hw_lvl = tm_node->hw_lvl;\n-\tuint32_t schq = tm_node->hw_id;\n-\tuint8_t k = 0;\n-\n-\totx2_tm_dbg(\"sw xoff config node %s(%u) lvl %u id %u, enable %u (%p)\",\n-\t\t nix_hwlvl2str(hw_lvl), schq, tm_node->lvl,\n-\t\t tm_node->id, enable, tm_node);\n-\n-\tregval[k] = enable;\n-\n-\tswitch (hw_lvl) {\n-\tcase NIX_TXSCH_LVL_MDQ:\n-\t\treg[k] = NIX_AF_MDQX_SW_XOFF(schq);\n-\t\tk++;\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL4:\n-\t\treg[k] = NIX_AF_TL4X_SW_XOFF(schq);\n-\t\tk++;\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL3:\n-\t\treg[k] = NIX_AF_TL3X_SW_XOFF(schq);\n-\t\tk++;\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL2:\n-\t\treg[k] = NIX_AF_TL2X_SW_XOFF(schq);\n-\t\tk++;\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL1:\n-\t\treg[k] = NIX_AF_TL1X_SW_XOFF(schq);\n-\t\tk++;\n-\t\tbreak;\n-\tdefault:\n-\t\tbreak;\n-\t}\n-\n-\treturn k;\n-}\n-\n-static int\n-populate_tm_reg(struct otx2_eth_dev *dev,\n-\t\tstruct otx2_nix_tm_node *tm_node)\n-{\n-\tstruct otx2_nix_tm_shaper_profile *profile;\n-\tuint64_t regval_mask[MAX_REGS_PER_MBOX_MSG];\n-\tuint64_t regval[MAX_REGS_PER_MBOX_MSG];\n-\tuint64_t reg[MAX_REGS_PER_MBOX_MSG];\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tuint64_t parent = 0, child = 0;\n-\tuint32_t hw_lvl, rr_prio, schq;\n-\tstruct nix_txschq_config *req;\n-\tint rc = -EFAULT;\n-\tuint8_t k = 0;\n-\n-\tmemset(regval_mask, 0, sizeof(regval_mask));\n-\tprofile = nix_tm_shaper_profile_search(dev,\n-\t\t\t\t\ttm_node->params.shaper_profile_id);\n-\trr_prio = tm_node->rr_prio;\n-\thw_lvl = tm_node->hw_lvl;\n-\tschq = tm_node->hw_id;\n-\n-\t/* Root node will not have a parent node */\n-\tif (hw_lvl == dev->otx2_tm_root_lvl)\n-\t\tparent = tm_node->parent_hw_id;\n-\telse\n-\t\tparent = tm_node->parent->hw_id;\n-\n-\t/* Do we need this trigger to configure TL1 */\n-\tif (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 &&\n-\t hw_lvl == dev->otx2_tm_root_lvl) {\n-\t\trc = populate_tm_tl1_default(dev, parent);\n-\t\tif (rc)\n-\t\t\tgoto error;\n-\t}\n-\n-\tif (hw_lvl != NIX_TXSCH_LVL_SMQ)\n-\t\tchild = find_prio_anchor(dev, tm_node->id);\n-\n-\t/* Override default rr_prio when TL1\n-\t * Static Priority is disabled\n-\t */\n-\tif (hw_lvl == NIX_TXSCH_LVL_TL1 &&\n-\t dev->tm_flags & NIX_TM_TL1_NO_SP) {\n-\t\trr_prio = TXSCH_TL1_DFLT_RR_PRIO;\n-\t\tchild = 0;\n-\t}\n-\n-\totx2_tm_dbg(\"Topology config node %s(%u)->%s(%\"PRIu64\") lvl %u, id %u\"\n-\t\t \" prio_anchor %\"PRIu64\" rr_prio %u (%p)\",\n-\t\t nix_hwlvl2str(hw_lvl), schq, nix_hwlvl2str(hw_lvl + 1),\n-\t\t parent, tm_node->lvl, tm_node->id, child, rr_prio, tm_node);\n-\n-\t/* Prepare Topology and Link config */\n-\tswitch (hw_lvl) {\n-\tcase NIX_TXSCH_LVL_SMQ:\n-\n-\t\t/* Set xoff which will be cleared later and minimum length\n-\t\t * which will be used for zero padding if packet length is\n-\t\t * smaller\n-\t\t */\n-\t\treg[k] = NIX_AF_SMQX_CFG(schq);\n-\t\tregval[k] = BIT_ULL(50) | ((uint64_t)NIX_MAX_VTAG_INS << 36) |\n-\t\t\tNIX_MIN_HW_FRS;\n-\t\tregval_mask[k] = ~(BIT_ULL(50) | (0x7ULL << 36) | 0x7f);\n-\t\tk++;\n-\n-\t\t/* Parent and schedule conf */\n-\t\treg[k] = NIX_AF_MDQX_PARENT(schq);\n-\t\tregval[k] = parent << 16;\n-\t\tk++;\n-\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL4:\n-\t\t/* Parent and schedule conf */\n-\t\treg[k] = NIX_AF_TL4X_PARENT(schq);\n-\t\tregval[k] = parent << 16;\n-\t\tk++;\n-\n-\t\treg[k] = NIX_AF_TL4X_TOPOLOGY(schq);\n-\t\tregval[k] = (child << 32) | (rr_prio << 1);\n-\t\tk++;\n-\n-\t\t/* Configure TL4 to send to SDP channel instead of CGX/LBK */\n-\t\tif (otx2_dev_is_sdp(dev)) {\n-\t\t\treg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);\n-\t\t\tregval[k] = BIT_ULL(12);\n-\t\t\tk++;\n-\t\t}\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL3:\n-\t\t/* Parent and schedule conf */\n-\t\treg[k] = NIX_AF_TL3X_PARENT(schq);\n-\t\tregval[k] = parent << 16;\n-\t\tk++;\n-\n-\t\treg[k] = NIX_AF_TL3X_TOPOLOGY(schq);\n-\t\tregval[k] = (child << 32) | (rr_prio << 1);\n-\t\tk++;\n-\n-\t\t/* Link configuration */\n-\t\tif (!otx2_dev_is_sdp(dev) &&\n-\t\t dev->link_cfg_lvl == NIX_TXSCH_LVL_TL3) {\n-\t\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,\n-\t\t\t\t\t\totx2_nix_get_link(dev));\n-\t\t\tregval[k] = BIT_ULL(12) | nix_get_relchan(dev);\n-\t\t\tk++;\n-\t\t}\n-\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL2:\n-\t\t/* Parent and schedule conf */\n-\t\treg[k] = NIX_AF_TL2X_PARENT(schq);\n-\t\tregval[k] = parent << 16;\n-\t\tk++;\n-\n-\t\treg[k] = NIX_AF_TL2X_TOPOLOGY(schq);\n-\t\tregval[k] = (child << 32) | (rr_prio << 1);\n-\t\tk++;\n-\n-\t\t/* Link configuration */\n-\t\tif (!otx2_dev_is_sdp(dev) &&\n-\t\t dev->link_cfg_lvl == NIX_TXSCH_LVL_TL2) {\n-\t\t\treg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq,\n-\t\t\t\t\t\totx2_nix_get_link(dev));\n-\t\t\tregval[k] = BIT_ULL(12) | nix_get_relchan(dev);\n-\t\t\tk++;\n-\t\t}\n-\n-\t\tbreak;\n-\tcase NIX_TXSCH_LVL_TL1:\n-\t\treg[k] = NIX_AF_TL1X_TOPOLOGY(schq);\n-\t\tregval[k] = (child << 32) | (rr_prio << 1 /*RR_PRIO*/);\n-\t\tk++;\n-\n-\t\tbreak;\n-\t}\n-\n-\t/* Prepare schedule config */\n-\tk += prepare_tm_sched_reg(dev, tm_node, ®[k], ®val[k]);\n-\n-\t/* Prepare shaping config */\n-\tk += prepare_tm_shaper_reg(tm_node, profile, ®[k], ®val[k]);\n-\n-\tif (!k)\n-\t\treturn 0;\n-\n-\t/* Copy and send config mbox */\n-\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\treq->lvl = hw_lvl;\n-\treq->num_regs = k;\n-\n-\totx2_mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);\n-\totx2_mbox_memcpy(req->regval, regval, sizeof(uint64_t) * k);\n-\totx2_mbox_memcpy(req->regval_mask, regval_mask, sizeof(uint64_t) * k);\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\tgoto error;\n-\n-\treturn 0;\n-error:\n-\totx2_err(\"Txschq cfg request failed for node %p, rc=%d\", tm_node, rc);\n-\treturn rc;\n-}\n-\n-\n-static int\n-nix_tm_txsch_reg_config(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tuint32_t hw_lvl;\n-\tint rc = 0;\n-\n-\tfor (hw_lvl = 0; hw_lvl <= dev->otx2_tm_root_lvl; hw_lvl++) {\n-\t\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\t\tif (tm_node->hw_lvl == hw_lvl &&\n-\t\t\t tm_node->hw_lvl != NIX_TXSCH_LVL_CNT) {\n-\t\t\t\trc = populate_tm_reg(dev, tm_node);\n-\t\t\t\tif (rc)\n-\t\t\t\t\tgoto exit;\n-\t\t\t}\n-\t\t}\n-\t}\n-exit:\n-\treturn rc;\n-}\n-\n-static struct otx2_nix_tm_node *\n-nix_tm_node_search(struct otx2_eth_dev *dev,\n-\t\t uint32_t node_id, bool user)\n-{\n-\tstruct otx2_nix_tm_node *tm_node;\n-\n-\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (tm_node->id == node_id &&\n-\t\t (user == !!(tm_node->flags & NIX_TM_NODE_USER)))\n-\t\t\treturn tm_node;\n-\t}\n-\treturn NULL;\n-}\n-\n-static uint32_t\n-check_rr(struct otx2_eth_dev *dev, uint32_t priority, uint32_t parent_id)\n-{\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tuint32_t rr_num = 0;\n-\n-\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (!tm_node->parent)\n-\t\t\tcontinue;\n-\n-\t\tif (!(tm_node->parent->id == parent_id))\n-\t\t\tcontinue;\n-\n-\t\tif (tm_node->priority == priority)\n-\t\t\trr_num++;\n-\t}\n-\treturn rr_num;\n-}\n-\n-static int\n-nix_tm_update_parent_info(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_nix_tm_node *tm_node_child;\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tstruct otx2_nix_tm_node *parent;\n-\tuint32_t rr_num = 0;\n-\tuint32_t priority;\n-\n-\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (!tm_node->parent)\n-\t\t\tcontinue;\n-\t\t/* Count group of children of same priority i.e are RR */\n-\t\tparent = tm_node->parent;\n-\t\tpriority = tm_node->priority;\n-\t\trr_num = check_rr(dev, priority, parent->id);\n-\n-\t\t/* Assuming that multiple RR groups are\n-\t\t * not configured based on capability.\n-\t\t */\n-\t\tif (rr_num > 1) {\n-\t\t\tparent->rr_prio = priority;\n-\t\t\tparent->rr_num = rr_num;\n-\t\t}\n-\n-\t\t/* Find out static priority children that are not in RR */\n-\t\tTAILQ_FOREACH(tm_node_child, &dev->node_list, node) {\n-\t\t\tif (!tm_node_child->parent)\n-\t\t\t\tcontinue;\n-\t\t\tif (parent->id != tm_node_child->parent->id)\n-\t\t\t\tcontinue;\n-\t\t\tif (parent->max_prio == UINT32_MAX &&\n-\t\t\t tm_node_child->priority != parent->rr_prio)\n-\t\t\t\tparent->max_prio = 0;\n-\n-\t\t\tif (parent->max_prio < tm_node_child->priority &&\n-\t\t\t parent->rr_prio != tm_node_child->priority)\n-\t\t\t\tparent->max_prio = tm_node_child->priority;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id,\n-\t\t\tuint32_t parent_node_id, uint32_t priority,\n-\t\t\tuint32_t weight, uint16_t hw_lvl,\n-\t\t\tuint16_t lvl, bool user,\n-\t\t\tstruct rte_tm_node_params *params)\n-{\n-\tstruct otx2_nix_tm_shaper_profile *profile;\n-\tstruct otx2_nix_tm_node *tm_node, *parent_node;\n-\tuint32_t profile_id;\n-\n-\tprofile_id = params->shaper_profile_id;\n-\tprofile = nix_tm_shaper_profile_search(dev, profile_id);\n-\n-\tparent_node = nix_tm_node_search(dev, parent_node_id, user);\n-\n-\ttm_node = rte_zmalloc(\"otx2_nix_tm_node\",\n-\t\t\t sizeof(struct otx2_nix_tm_node), 0);\n-\tif (!tm_node)\n-\t\treturn -ENOMEM;\n-\n-\ttm_node->lvl = lvl;\n-\ttm_node->hw_lvl = hw_lvl;\n-\n-\t/* Maintain minimum weight */\n-\tif (!weight)\n-\t\tweight = 1;\n-\n-\ttm_node->id = node_id;\n-\ttm_node->priority = priority;\n-\ttm_node->weight = weight;\n-\ttm_node->rr_prio = 0xf;\n-\ttm_node->max_prio = UINT32_MAX;\n-\ttm_node->hw_id = UINT32_MAX;\n-\ttm_node->flags = 0;\n-\tif (user)\n-\t\ttm_node->flags = NIX_TM_NODE_USER;\n-\n-\t/* Packet mode */\n-\tif (!nix_tm_is_leaf(dev, lvl) &&\n-\t ((profile && profile->params.packet_mode) ||\n-\t (params->nonleaf.wfq_weight_mode &&\n-\t params->nonleaf.n_sp_priorities &&\n-\t !params->nonleaf.wfq_weight_mode[0])))\n-\t\ttm_node->pkt_mode = 1;\n-\n-\trte_memcpy(&tm_node->params, params, sizeof(struct rte_tm_node_params));\n-\n-\tif (profile)\n-\t\tprofile->reference_count++;\n-\n-\ttm_node->parent = parent_node;\n-\ttm_node->parent_hw_id = UINT32_MAX;\n-\tshaper_default_red_algo(dev, tm_node, profile);\n-\n-\tTAILQ_INSERT_TAIL(&dev->node_list, tm_node, node);\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_tm_clear_shaper_profiles(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_nix_tm_shaper_profile *shaper_profile;\n-\n-\twhile ((shaper_profile = TAILQ_FIRST(&dev->shaper_profile_list))) {\n-\t\tif (shaper_profile->reference_count)\n-\t\t\totx2_tm_dbg(\"Shaper profile %u has non zero references\",\n-\t\t\t\t shaper_profile->shaper_profile_id);\n-\t\tTAILQ_REMOVE(&dev->shaper_profile_list, shaper_profile, shaper);\n-\t\trte_free(shaper_profile);\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_clear_path_xoff(struct otx2_eth_dev *dev,\n-\t\t struct otx2_nix_tm_node *tm_node)\n-{\n-\tstruct nix_txschq_config *req;\n-\tstruct otx2_nix_tm_node *p;\n-\tint rc;\n-\n-\t/* Manipulating SW_XOFF not supported on Ax */\n-\tif (otx2_dev_is_Ax(dev))\n-\t\treturn 0;\n-\n-\t/* Enable nodes in path for flush to succeed */\n-\tif (!nix_tm_is_leaf(dev, tm_node->lvl))\n-\t\tp = tm_node;\n-\telse\n-\t\tp = tm_node->parent;\n-\twhile (p) {\n-\t\tif (!(p->flags & NIX_TM_NODE_ENABLED) &&\n-\t\t (p->flags & NIX_TM_NODE_HWRES)) {\n-\t\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);\n-\t\t\treq->lvl = p->hw_lvl;\n-\t\t\treq->num_regs = prepare_tm_sw_xoff(p, false, req->reg,\n-\t\t\t\t\t\t\t req->regval);\n-\t\t\trc = otx2_mbox_process(dev->mbox);\n-\t\t\tif (rc)\n-\t\t\t\treturn rc;\n-\n-\t\t\tp->flags |= NIX_TM_NODE_ENABLED;\n-\t\t}\n-\t\tp = p->parent;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_smq_xoff(struct otx2_eth_dev *dev,\n-\t struct otx2_nix_tm_node *tm_node,\n-\t bool enable)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_txschq_config *req;\n-\tuint16_t smq;\n-\tint rc;\n-\n-\tsmq = tm_node->hw_id;\n-\totx2_tm_dbg(\"Setting SMQ %u XOFF/FLUSH to %s\", smq,\n-\t\t enable ? \"enable\" : \"disable\");\n-\n-\trc = nix_clear_path_xoff(dev, tm_node);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\treq->lvl = NIX_TXSCH_LVL_SMQ;\n-\treq->num_regs = 1;\n-\n-\treq->reg[0] = NIX_AF_SMQX_CFG(smq);\n-\treq->regval[0] = enable ? (BIT_ULL(50) | BIT_ULL(49)) : 0;\n-\treq->regval_mask[0] = enable ?\n-\t\t\t\t~(BIT_ULL(50) | BIT_ULL(49)) : ~BIT_ULL(50);\n-\n-\treturn otx2_mbox_process(mbox);\n-}\n-\n-int\n-otx2_nix_sq_sqb_aura_fc(void *__txq, bool enable)\n-{\n-\tstruct otx2_eth_txq *txq = __txq;\n-\tstruct npa_aq_enq_req *req;\n-\tstruct npa_aq_enq_rsp *rsp;\n-\tstruct otx2_npa_lf *lf;\n-\tstruct otx2_mbox *mbox;\n-\tuint64_t aura_handle;\n-\tint rc;\n-\n-\totx2_tm_dbg(\"Setting SQ %u SQB aura FC to %s\", txq->sq,\n-\t\t enable ? \"enable\" : \"disable\");\n-\n-\tlf = otx2_npa_lf_obj_get();\n-\tif (!lf)\n-\t\treturn -EFAULT;\n-\tmbox = lf->mbox;\n-\t/* Set/clear sqb aura fc_ena */\n-\taura_handle = txq->sqb_pool->pool_id;\n-\treq = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\n-\treq->aura_id = npa_lf_aura_handle_to_aura(aura_handle);\n-\treq->ctype = NPA_AQ_CTYPE_AURA;\n-\treq->op = NPA_AQ_INSTOP_WRITE;\n-\t/* Below is not needed for aura writes but AF driver needs it */\n-\t/* AF will translate to associated poolctx */\n-\treq->aura.pool_addr = req->aura_id;\n-\n-\treq->aura.fc_ena = enable;\n-\treq->aura_mask.fc_ena = 1;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\t/* Read back npa aura ctx */\n-\treq = otx2_mbox_alloc_msg_npa_aq_enq(mbox);\n-\n-\treq->aura_id = npa_lf_aura_handle_to_aura(aura_handle);\n-\treq->ctype = NPA_AQ_CTYPE_AURA;\n-\treq->op = NPA_AQ_INSTOP_READ;\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\t/* Init when enabled as there might be no triggers */\n-\tif (enable)\n-\t\t*(volatile uint64_t *)txq->fc_mem = rsp->aura.count;\n-\telse\n-\t\t*(volatile uint64_t *)txq->fc_mem = txq->nb_sqb_bufs;\n-\t/* Sync write barrier */\n-\trte_wmb();\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_txq_flush_sq_spin(struct otx2_eth_txq *txq)\n-{\n-\tuint16_t sqb_cnt, head_off, tail_off;\n-\tstruct otx2_eth_dev *dev = txq->dev;\n-\tuint64_t wdata, val, prev;\n-\tuint16_t sq = txq->sq;\n-\tint64_t *regaddr;\n-\tuint64_t timeout;/* 10's of usec */\n-\n-\t/* Wait for enough time based on shaper min rate */\n-\ttimeout = (txq->qconf.nb_desc * NIX_MAX_HW_FRS * 8 * 1E5);\n-\ttimeout = timeout / dev->tm_rate_min;\n-\tif (!timeout)\n-\t\ttimeout = 10000;\n-\n-\twdata = ((uint64_t)sq << 32);\n-\tregaddr = (int64_t *)(dev->base + NIX_LF_SQ_OP_STATUS);\n-\tval = otx2_atomic64_add_nosync(wdata, regaddr);\n-\n-\t/* Spin multiple iterations as \"txq->fc_cache_pkts\" can still\n-\t * have space to send pkts even though fc_mem is disabled\n-\t */\n-\n-\twhile (true) {\n-\t\tprev = val;\n-\t\trte_delay_us(10);\n-\t\tval = otx2_atomic64_add_nosync(wdata, regaddr);\n-\t\t/* Continue on error */\n-\t\tif (val & BIT_ULL(63))\n-\t\t\tcontinue;\n-\n-\t\tif (prev != val)\n-\t\t\tcontinue;\n-\n-\t\tsqb_cnt = val & 0xFFFF;\n-\t\thead_off = (val >> 20) & 0x3F;\n-\t\ttail_off = (val >> 28) & 0x3F;\n-\n-\t\t/* SQ reached quiescent state */\n-\t\tif (sqb_cnt <= 1 && head_off == tail_off &&\n-\t\t (*txq->fc_mem == txq->nb_sqb_bufs)) {\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\t/* Timeout */\n-\t\tif (!timeout)\n-\t\t\tgoto exit;\n-\t\ttimeout--;\n-\t}\n-\n-\treturn 0;\n-exit:\n-\totx2_nix_tm_dump(dev);\n-\treturn -EFAULT;\n-}\n-\n-/* Flush and disable tx queue and its parent SMQ */\n-int otx2_nix_sq_flush_pre(void *_txq, bool dev_started)\n-{\n-\tstruct otx2_nix_tm_node *tm_node, *sibling;\n-\tstruct otx2_eth_txq *txq;\n-\tstruct otx2_eth_dev *dev;\n-\tuint16_t sq;\n-\tbool user;\n-\tint rc;\n-\n-\ttxq = _txq;\n-\tdev = txq->dev;\n-\tsq = txq->sq;\n-\n-\tuser = !!(dev->tm_flags & NIX_TM_COMMITTED);\n-\n-\t/* Find the node for this SQ */\n-\ttm_node = nix_tm_node_search(dev, sq, user);\n-\tif (!tm_node || !(tm_node->flags & NIX_TM_NODE_ENABLED)) {\n-\t\totx2_err(\"Invalid node/state for sq %u\", sq);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\t/* Enable CGX RXTX to drain pkts */\n-\tif (!dev_started) {\n-\t\t/* Though it enables both RX MCAM Entries and CGX Link\n-\t\t * we assume all the rx queues are stopped way back.\n-\t\t */\n-\t\totx2_mbox_alloc_msg_nix_lf_start_rx(dev->mbox);\n-\t\trc = otx2_mbox_process(dev->mbox);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"cgx start failed, rc=%d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t}\n-\n-\t/* Disable smq xoff for case it was enabled earlier */\n-\trc = nix_smq_xoff(dev, tm_node->parent, false);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to enable smq %u, rc=%d\",\n-\t\t\t tm_node->parent->hw_id, rc);\n-\t\treturn rc;\n-\t}\n-\n-\t/* As per HRM, to disable an SQ, all other SQ's\n-\t * that feed to same SMQ must be paused before SMQ flush.\n-\t */\n-\tTAILQ_FOREACH(sibling, &dev->node_list, node) {\n-\t\tif (sibling->parent != tm_node->parent)\n-\t\t\tcontinue;\n-\t\tif (!(sibling->flags & NIX_TM_NODE_ENABLED))\n-\t\t\tcontinue;\n-\n-\t\tsq = sibling->id;\n-\t\ttxq = dev->eth_dev->data->tx_queues[sq];\n-\t\tif (!txq)\n-\t\t\tcontinue;\n-\n-\t\trc = otx2_nix_sq_sqb_aura_fc(txq, false);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to disable sqb aura fc, rc=%d\", rc);\n-\t\t\tgoto cleanup;\n-\t\t}\n-\n-\t\t/* Wait for sq entries to be flushed */\n-\t\trc = nix_txq_flush_sq_spin(txq);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to drain sq %u, rc=%d\\n\", txq->sq, rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t}\n-\n-\ttm_node->flags &= ~NIX_TM_NODE_ENABLED;\n-\n-\t/* Disable and flush */\n-\trc = nix_smq_xoff(dev, tm_node->parent, true);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to disable smq %u, rc=%d\",\n-\t\t\t tm_node->parent->hw_id, rc);\n-\t\tgoto cleanup;\n-\t}\n-cleanup:\n-\t/* Restore cgx state */\n-\tif (!dev_started) {\n-\t\totx2_mbox_alloc_msg_nix_lf_stop_rx(dev->mbox);\n-\t\trc |= otx2_mbox_process(dev->mbox);\n-\t}\n-\n-\treturn rc;\n-}\n-\n-int otx2_nix_sq_flush_post(void *_txq)\n-{\n-\tstruct otx2_nix_tm_node *tm_node, *sibling;\n-\tstruct otx2_eth_txq *txq = _txq;\n-\tstruct otx2_eth_txq *s_txq;\n-\tstruct otx2_eth_dev *dev;\n-\tbool once = false;\n-\tuint16_t sq, s_sq;\n-\tbool user;\n-\tint rc;\n-\n-\tdev = txq->dev;\n-\tsq = txq->sq;\n-\tuser = !!(dev->tm_flags & NIX_TM_COMMITTED);\n-\n-\t/* Find the node for this SQ */\n-\ttm_node = nix_tm_node_search(dev, sq, user);\n-\tif (!tm_node) {\n-\t\totx2_err(\"Invalid node for sq %u\", sq);\n-\t\treturn -EFAULT;\n-\t}\n-\n-\t/* Enable all the siblings back */\n-\tTAILQ_FOREACH(sibling, &dev->node_list, node) {\n-\t\tif (sibling->parent != tm_node->parent)\n-\t\t\tcontinue;\n-\n-\t\tif (sibling->id == sq)\n-\t\t\tcontinue;\n-\n-\t\tif (!(sibling->flags & NIX_TM_NODE_ENABLED))\n-\t\t\tcontinue;\n-\n-\t\ts_sq = sibling->id;\n-\t\ts_txq = dev->eth_dev->data->tx_queues[s_sq];\n-\t\tif (!s_txq)\n-\t\t\tcontinue;\n-\n-\t\tif (!once) {\n-\t\t\t/* Enable back if any SQ is still present */\n-\t\t\trc = nix_smq_xoff(dev, tm_node->parent, false);\n-\t\t\tif (rc) {\n-\t\t\t\totx2_err(\"Failed to enable smq %u, rc=%d\",\n-\t\t\t\t\t tm_node->parent->hw_id, rc);\n-\t\t\t\treturn rc;\n-\t\t\t}\n-\t\t\tonce = true;\n-\t\t}\n-\n-\t\trc = otx2_nix_sq_sqb_aura_fc(s_txq, true);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to enable sqb aura fc, rc=%d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_sq_sched_data(struct otx2_eth_dev *dev,\n-\t\t struct otx2_nix_tm_node *tm_node,\n-\t\t bool rr_quantum_only)\n-{\n-\tstruct rte_eth_dev *eth_dev = dev->eth_dev;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tuint16_t sq = tm_node->id, smq;\n-\tstruct nix_aq_enq_req *req;\n-\tuint64_t rr_quantum;\n-\tint rc;\n-\n-\tsmq = tm_node->parent->hw_id;\n-\trr_quantum = NIX_TM_WEIGHT_TO_RR_QUANTUM(tm_node->weight);\n-\n-\tif (rr_quantum_only)\n-\t\totx2_tm_dbg(\"Update sq(%u) rr_quantum 0x%\"PRIx64, sq, rr_quantum);\n-\telse\n-\t\totx2_tm_dbg(\"Enabling sq(%u)->smq(%u), rr_quantum 0x%\"PRIx64,\n-\t\t\t sq, smq, rr_quantum);\n-\n-\tif (sq > eth_dev->data->nb_tx_queues)\n-\t\treturn -EFAULT;\n-\n-\treq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);\n-\treq->qidx = sq;\n-\treq->ctype = NIX_AQ_CTYPE_SQ;\n-\treq->op = NIX_AQ_INSTOP_WRITE;\n-\n-\t/* smq update only when needed */\n-\tif (!rr_quantum_only) {\n-\t\treq->sq.smq = smq;\n-\t\treq->sq_mask.smq = ~req->sq_mask.smq;\n-\t}\n-\treq->sq.smq_rr_quantum = rr_quantum;\n-\treq->sq_mask.smq_rr_quantum = ~req->sq_mask.smq_rr_quantum;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\totx2_err(\"Failed to set smq, rc=%d\", rc);\n-\treturn rc;\n-}\n-\n-int otx2_nix_sq_enable(void *_txq)\n-{\n-\tstruct otx2_eth_txq *txq = _txq;\n-\tint rc;\n-\n-\t/* Enable sqb_aura fc */\n-\trc = otx2_nix_sq_sqb_aura_fc(txq, true);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to enable sqb aura fc, rc=%d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_tm_free_resources(struct otx2_eth_dev *dev, uint32_t flags_mask,\n-\t\t uint32_t flags, bool hw_only)\n-{\n-\tstruct otx2_nix_tm_shaper_profile *profile;\n-\tstruct otx2_nix_tm_node *tm_node, *next_node;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_txsch_free_req *req;\n-\tuint32_t profile_id;\n-\tint rc = 0;\n-\n-\tnext_node = TAILQ_FIRST(&dev->node_list);\n-\twhile (next_node) {\n-\t\ttm_node = next_node;\n-\t\tnext_node = TAILQ_NEXT(tm_node, node);\n-\n-\t\t/* Check for only requested nodes */\n-\t\tif ((tm_node->flags & flags_mask) != flags)\n-\t\t\tcontinue;\n-\n-\t\tif (!nix_tm_is_leaf(dev, tm_node->lvl) &&\n-\t\t tm_node->hw_lvl != NIX_TXSCH_LVL_TL1 &&\n-\t\t tm_node->flags & NIX_TM_NODE_HWRES) {\n-\t\t\t/* Free specific HW resource */\n-\t\t\totx2_tm_dbg(\"Free hwres %s(%u) lvl %u id %u (%p)\",\n-\t\t\t\t nix_hwlvl2str(tm_node->hw_lvl),\n-\t\t\t\t tm_node->hw_id, tm_node->lvl,\n-\t\t\t\t tm_node->id, tm_node);\n-\n-\t\t\trc = nix_clear_path_xoff(dev, tm_node);\n-\t\t\tif (rc)\n-\t\t\t\treturn rc;\n-\n-\t\t\treq = otx2_mbox_alloc_msg_nix_txsch_free(mbox);\n-\t\t\treq->flags = 0;\n-\t\t\treq->schq_lvl = tm_node->hw_lvl;\n-\t\t\treq->schq = tm_node->hw_id;\n-\t\t\trc = otx2_mbox_process(mbox);\n-\t\t\tif (rc)\n-\t\t\t\treturn rc;\n-\t\t\ttm_node->flags &= ~NIX_TM_NODE_HWRES;\n-\t\t}\n-\n-\t\t/* Leave software elements if needed */\n-\t\tif (hw_only)\n-\t\t\tcontinue;\n-\n-\t\totx2_tm_dbg(\"Free node lvl %u id %u (%p)\",\n-\t\t\t tm_node->lvl, tm_node->id, tm_node);\n-\n-\t\tprofile_id = tm_node->params.shaper_profile_id;\n-\t\tprofile = nix_tm_shaper_profile_search(dev, profile_id);\n-\t\tif (profile)\n-\t\t\tprofile->reference_count--;\n-\n-\t\tTAILQ_REMOVE(&dev->node_list, tm_node, node);\n-\t\trte_free(tm_node);\n-\t}\n-\n-\tif (!flags_mask) {\n-\t\t/* Free all hw resources */\n-\t\treq = otx2_mbox_alloc_msg_nix_txsch_free(mbox);\n-\t\treq->flags = TXSCHQ_FREE_ALL;\n-\n-\t\treturn otx2_mbox_process(mbox);\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static uint8_t\n-nix_tm_copy_rsp_to_dev(struct otx2_eth_dev *dev,\n-\t\t struct nix_txsch_alloc_rsp *rsp)\n-{\n-\tuint16_t schq;\n-\tuint8_t lvl;\n-\n-\tfor (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {\n-\t\tfor (schq = 0; schq < MAX_TXSCHQ_PER_FUNC; schq++) {\n-\t\t\tdev->txschq_list[lvl][schq] = rsp->schq_list[lvl][schq];\n-\t\t\tdev->txschq_contig_list[lvl][schq] =\n-\t\t\t\trsp->schq_contig_list[lvl][schq];\n-\t\t}\n-\n-\t\tdev->txschq[lvl] = rsp->schq[lvl];\n-\t\tdev->txschq_contig[lvl] = rsp->schq_contig[lvl];\n-\t}\n-\treturn 0;\n-}\n-\n-static int\n-nix_tm_assign_id_to_node(struct otx2_eth_dev *dev,\n-\t\t\t struct otx2_nix_tm_node *child,\n-\t\t\t struct otx2_nix_tm_node *parent)\n-{\n-\tuint32_t hw_id, schq_con_index, prio_offset;\n-\tuint32_t l_id, schq_index;\n-\n-\totx2_tm_dbg(\"Assign hw id for child node %s lvl %u id %u (%p)\",\n-\t\t nix_hwlvl2str(child->hw_lvl), child->lvl, child->id, child);\n-\n-\tchild->flags |= NIX_TM_NODE_HWRES;\n-\n-\t/* Process root nodes */\n-\tif (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 &&\n-\t child->hw_lvl == dev->otx2_tm_root_lvl && !parent) {\n-\t\tint idx = 0;\n-\t\tuint32_t tschq_con_index;\n-\n-\t\tl_id = child->hw_lvl;\n-\t\ttschq_con_index = dev->txschq_contig_index[l_id];\n-\t\thw_id = dev->txschq_contig_list[l_id][tschq_con_index];\n-\t\tchild->hw_id = hw_id;\n-\t\tdev->txschq_contig_index[l_id]++;\n-\t\t/* Update TL1 hw_id for its parent for config purpose */\n-\t\tidx = dev->txschq_index[NIX_TXSCH_LVL_TL1]++;\n-\t\thw_id = dev->txschq_list[NIX_TXSCH_LVL_TL1][idx];\n-\t\tchild->parent_hw_id = hw_id;\n-\t\treturn 0;\n-\t}\n-\tif (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL1 &&\n-\t child->hw_lvl == dev->otx2_tm_root_lvl && !parent) {\n-\t\tuint32_t tschq_con_index;\n-\n-\t\tl_id = child->hw_lvl;\n-\t\ttschq_con_index = dev->txschq_index[l_id];\n-\t\thw_id = dev->txschq_list[l_id][tschq_con_index];\n-\t\tchild->hw_id = hw_id;\n-\t\tdev->txschq_index[l_id]++;\n-\t\treturn 0;\n-\t}\n-\n-\t/* Process children with parents */\n-\tl_id = child->hw_lvl;\n-\tschq_index = dev->txschq_index[l_id];\n-\tschq_con_index = dev->txschq_contig_index[l_id];\n-\n-\tif (child->priority == parent->rr_prio) {\n-\t\thw_id = dev->txschq_list[l_id][schq_index];\n-\t\tchild->hw_id = hw_id;\n-\t\tchild->parent_hw_id = parent->hw_id;\n-\t\tdev->txschq_index[l_id]++;\n-\t} else {\n-\t\tprio_offset = schq_con_index + child->priority;\n-\t\thw_id = dev->txschq_contig_list[l_id][prio_offset];\n-\t\tchild->hw_id = hw_id;\n-\t}\n-\treturn 0;\n-}\n-\n-static int\n-nix_tm_assign_hw_id(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_nix_tm_node *parent, *child;\n-\tuint32_t child_hw_lvl, con_index_inc, i;\n-\n-\tfor (i = NIX_TXSCH_LVL_TL1; i > 0; i--) {\n-\t\tTAILQ_FOREACH(parent, &dev->node_list, node) {\n-\t\t\tchild_hw_lvl = parent->hw_lvl - 1;\n-\t\t\tif (parent->hw_lvl != i)\n-\t\t\t\tcontinue;\n-\t\t\tTAILQ_FOREACH(child, &dev->node_list, node) {\n-\t\t\t\tif (!child->parent)\n-\t\t\t\t\tcontinue;\n-\t\t\t\tif (child->parent->id != parent->id)\n-\t\t\t\t\tcontinue;\n-\t\t\t\tnix_tm_assign_id_to_node(dev, child, parent);\n-\t\t\t}\n-\n-\t\t\tcon_index_inc = parent->max_prio + 1;\n-\t\t\tdev->txschq_contig_index[child_hw_lvl] += con_index_inc;\n-\n-\t\t\t/*\n-\t\t\t * Explicitly assign id to parent node if it\n-\t\t\t * doesn't have a parent\n-\t\t\t */\n-\t\t\tif (parent->hw_lvl == dev->otx2_tm_root_lvl)\n-\t\t\t\tnix_tm_assign_id_to_node(dev, parent, NULL);\n-\t\t}\n-\t}\n-\treturn 0;\n-}\n-\n-static uint8_t\n-nix_tm_count_req_schq(struct otx2_eth_dev *dev,\n-\t\t struct nix_txsch_alloc_req *req, uint8_t lvl)\n-{\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tuint8_t contig_count;\n-\n-\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (lvl == tm_node->hw_lvl) {\n-\t\t\treq->schq[lvl - 1] += tm_node->rr_num;\n-\t\t\tif (tm_node->max_prio != UINT32_MAX) {\n-\t\t\t\tcontig_count = tm_node->max_prio + 1;\n-\t\t\t\treq->schq_contig[lvl - 1] += contig_count;\n-\t\t\t}\n-\t\t}\n-\t\tif (lvl == dev->otx2_tm_root_lvl &&\n-\t\t dev->otx2_tm_root_lvl && lvl == NIX_TXSCH_LVL_TL2 &&\n-\t\t tm_node->hw_lvl == dev->otx2_tm_root_lvl) {\n-\t\t\treq->schq_contig[dev->otx2_tm_root_lvl]++;\n-\t\t}\n-\t}\n-\n-\treq->schq[NIX_TXSCH_LVL_TL1] = 1;\n-\treq->schq_contig[NIX_TXSCH_LVL_TL1] = 0;\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_tm_prepare_txschq_req(struct otx2_eth_dev *dev,\n-\t\t\t struct nix_txsch_alloc_req *req)\n-{\n-\tuint8_t i;\n-\n-\tfor (i = NIX_TXSCH_LVL_TL1; i > 0; i--)\n-\t\tnix_tm_count_req_schq(dev, req, i);\n-\n-\tfor (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {\n-\t\tdev->txschq_index[i] = 0;\n-\t\tdev->txschq_contig_index[i] = 0;\n-\t}\n-\treturn 0;\n-}\n-\n-static int\n-nix_tm_send_txsch_alloc_msg(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_txsch_alloc_req *req;\n-\tstruct nix_txsch_alloc_rsp *rsp;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_nix_txsch_alloc(mbox);\n-\n-\trc = nix_tm_prepare_txschq_req(dev, req);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tnix_tm_copy_rsp_to_dev(dev, rsp);\n-\tdev->link_cfg_lvl = rsp->link_cfg_lvl;\n-\n-\tnix_tm_assign_hw_id(dev);\n-\treturn 0;\n-}\n-\n-static int\n-nix_tm_alloc_resources(struct rte_eth_dev *eth_dev, bool xmit_enable)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tstruct otx2_eth_txq *txq;\n-\tuint16_t sq;\n-\tint rc;\n-\n-\tnix_tm_update_parent_info(dev);\n-\n-\trc = nix_tm_send_txsch_alloc_msg(dev);\n-\tif (rc) {\n-\t\totx2_err(\"TM failed to alloc tm resources=%d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\trc = nix_tm_txsch_reg_config(dev);\n-\tif (rc) {\n-\t\totx2_err(\"TM failed to configure sched registers=%d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\t/* Trigger MTU recalculate as SMQ needs MTU conf */\n-\tif (eth_dev->data->dev_started && eth_dev->data->nb_rx_queues) {\n-\t\trc = otx2_nix_recalc_mtu(eth_dev);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"TM MTU update failed, rc=%d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t}\n-\n-\t/* Mark all non-leaf's as enabled */\n-\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (!nix_tm_is_leaf(dev, tm_node->lvl))\n-\t\t\ttm_node->flags |= NIX_TM_NODE_ENABLED;\n-\t}\n-\n-\tif (!xmit_enable)\n-\t\treturn 0;\n-\n-\t/* Update SQ Sched Data while SQ is idle */\n-\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (!nix_tm_is_leaf(dev, tm_node->lvl))\n-\t\t\tcontinue;\n-\n-\t\trc = nix_sq_sched_data(dev, tm_node, false);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"SQ %u sched update failed, rc=%d\",\n-\t\t\t\t tm_node->id, rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t}\n-\n-\t/* Finally XON all SMQ's */\n-\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (tm_node->hw_lvl != NIX_TXSCH_LVL_SMQ)\n-\t\t\tcontinue;\n-\n-\t\trc = nix_smq_xoff(dev, tm_node, false);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to enable smq %u, rc=%d\",\n-\t\t\t\t tm_node->hw_id, rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t}\n-\n-\t/* Enable xmit as all the topology is ready */\n-\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (!nix_tm_is_leaf(dev, tm_node->lvl))\n-\t\t\tcontinue;\n-\n-\t\tsq = tm_node->id;\n-\t\ttxq = eth_dev->data->tx_queues[sq];\n-\n-\t\trc = otx2_nix_sq_enable(txq);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"TM sw xon failed on SQ %u, rc=%d\",\n-\t\t\t\t tm_node->id, rc);\n-\t\t\treturn rc;\n-\t\t}\n-\t\ttm_node->flags |= NIX_TM_NODE_ENABLED;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-send_tm_reqval(struct otx2_mbox *mbox,\n-\t struct nix_txschq_config *req,\n-\t struct rte_tm_error *error)\n-{\n-\tint rc;\n-\n-\tif (!req->num_regs ||\n-\t req->num_regs > MAX_REGS_PER_MBOX_MSG) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\terror->message = \"invalid config\";\n-\t\treturn -EIO;\n-\t}\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\terror->message = \"unexpected fatal error\";\n-\t}\n-\treturn rc;\n-}\n-\n-static uint16_t\n-nix_tm_lvl2nix(struct otx2_eth_dev *dev, uint32_t lvl)\n-{\n-\tif (nix_tm_have_tl1_access(dev)) {\n-\t\tswitch (lvl) {\n-\t\tcase OTX2_TM_LVL_ROOT:\n-\t\t\treturn NIX_TXSCH_LVL_TL1;\n-\t\tcase OTX2_TM_LVL_SCH1:\n-\t\t\treturn NIX_TXSCH_LVL_TL2;\n-\t\tcase OTX2_TM_LVL_SCH2:\n-\t\t\treturn NIX_TXSCH_LVL_TL3;\n-\t\tcase OTX2_TM_LVL_SCH3:\n-\t\t\treturn NIX_TXSCH_LVL_TL4;\n-\t\tcase OTX2_TM_LVL_SCH4:\n-\t\t\treturn NIX_TXSCH_LVL_SMQ;\n-\t\tdefault:\n-\t\t\treturn NIX_TXSCH_LVL_CNT;\n-\t\t}\n-\t} else {\n-\t\tswitch (lvl) {\n-\t\tcase OTX2_TM_LVL_ROOT:\n-\t\t\treturn NIX_TXSCH_LVL_TL2;\n-\t\tcase OTX2_TM_LVL_SCH1:\n-\t\t\treturn NIX_TXSCH_LVL_TL3;\n-\t\tcase OTX2_TM_LVL_SCH2:\n-\t\t\treturn NIX_TXSCH_LVL_TL4;\n-\t\tcase OTX2_TM_LVL_SCH3:\n-\t\t\treturn NIX_TXSCH_LVL_SMQ;\n-\t\tdefault:\n-\t\t\treturn NIX_TXSCH_LVL_CNT;\n-\t\t}\n-\t}\n-}\n-\n-static uint16_t\n-nix_max_prio(struct otx2_eth_dev *dev, uint16_t hw_lvl)\n-{\n-\tif (hw_lvl >= NIX_TXSCH_LVL_CNT)\n-\t\treturn 0;\n-\n-\t/* MDQ doesn't support SP */\n-\tif (hw_lvl == NIX_TXSCH_LVL_MDQ)\n-\t\treturn 0;\n-\n-\t/* PF's TL1 with VF's enabled doesn't support SP */\n-\tif (hw_lvl == NIX_TXSCH_LVL_TL1 &&\n-\t (dev->otx2_tm_root_lvl == NIX_TXSCH_LVL_TL2 ||\n-\t (dev->tm_flags & NIX_TM_TL1_NO_SP)))\n-\t\treturn 0;\n-\n-\treturn TXSCH_TLX_SP_PRIO_MAX - 1;\n-}\n-\n-\n-static int\n-validate_prio(struct otx2_eth_dev *dev, uint32_t lvl,\n-\t uint32_t parent_id, uint32_t priority,\n-\t struct rte_tm_error *error)\n-{\n-\tuint8_t priorities[TXSCH_TLX_SP_PRIO_MAX];\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tuint32_t rr_num = 0;\n-\tint i;\n-\n-\t/* Validate priority against max */\n-\tif (priority > nix_max_prio(dev, nix_tm_lvl2nix(dev, lvl - 1))) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_CAPABILITIES;\n-\t\terror->message = \"unsupported priority value\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (parent_id == RTE_TM_NODE_ID_NULL)\n-\t\treturn 0;\n-\n-\tmemset(priorities, 0, TXSCH_TLX_SP_PRIO_MAX);\n-\tpriorities[priority] = 1;\n-\n-\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (!tm_node->parent)\n-\t\t\tcontinue;\n-\n-\t\tif (!(tm_node->flags & NIX_TM_NODE_USER))\n-\t\t\tcontinue;\n-\n-\t\tif (tm_node->parent->id != parent_id)\n-\t\t\tcontinue;\n-\n-\t\tpriorities[tm_node->priority]++;\n-\t}\n-\n-\tfor (i = 0; i < TXSCH_TLX_SP_PRIO_MAX; i++)\n-\t\tif (priorities[i] > 1)\n-\t\t\trr_num++;\n-\n-\t/* At max, one rr groups per parent */\n-\tif (rr_num > 1) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_PRIORITY;\n-\t\terror->message = \"multiple DWRR node priority\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Check for previous priority to avoid holes in priorities */\n-\tif (priority && !priorities[priority - 1]) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_PRIORITY;\n-\t\terror->message = \"priority not in order\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-read_tm_reg(struct otx2_mbox *mbox, uint64_t reg,\n-\t uint64_t *regval, uint32_t hw_lvl)\n-{\n-\tvolatile struct nix_txschq_config *req;\n-\tstruct nix_txschq_config *rsp;\n-\tint rc;\n-\n-\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\treq->read = 1;\n-\treq->lvl = hw_lvl;\n-\treq->reg[0] = reg;\n-\treq->num_regs = 1;\n-\n-\trc = otx2_mbox_process_msg(mbox, (void **)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\t*regval = rsp->regval[0];\n-\treturn 0;\n-}\n-\n-/* Search for min rate in topology */\n-static void\n-nix_tm_shaper_profile_update_min(struct otx2_eth_dev *dev)\n-{\n-\tstruct otx2_nix_tm_shaper_profile *profile;\n-\tuint64_t rate_min = 1E9; /* 1 Gbps */\n-\n-\tTAILQ_FOREACH(profile, &dev->shaper_profile_list, shaper) {\n-\t\tif (profile->params.peak.rate &&\n-\t\t profile->params.peak.rate < rate_min)\n-\t\t\trate_min = profile->params.peak.rate;\n-\n-\t\tif (profile->params.committed.rate &&\n-\t\t profile->params.committed.rate < rate_min)\n-\t\t\trate_min = profile->params.committed.rate;\n-\t}\n-\n-\tdev->tm_rate_min = rate_min;\n-}\n-\n-static int\n-nix_xmit_disable(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint16_t sq_cnt = eth_dev->data->nb_tx_queues;\n-\tuint16_t sqb_cnt, head_off, tail_off;\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tstruct otx2_eth_txq *txq;\n-\tuint64_t wdata, val;\n-\tint i, rc;\n-\n-\totx2_tm_dbg(\"Disabling xmit on %s\", eth_dev->data->name);\n-\n-\t/* Enable CGX RXTX to drain pkts */\n-\tif (!eth_dev->data->dev_started) {\n-\t\totx2_mbox_alloc_msg_nix_lf_start_rx(dev->mbox);\n-\t\trc = otx2_mbox_process(dev->mbox);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\t}\n-\n-\t/* XON all SMQ's */\n-\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (tm_node->hw_lvl != NIX_TXSCH_LVL_SMQ)\n-\t\t\tcontinue;\n-\t\tif (!(tm_node->flags & NIX_TM_NODE_HWRES))\n-\t\t\tcontinue;\n-\n-\t\trc = nix_smq_xoff(dev, tm_node, false);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to enable smq %u, rc=%d\",\n-\t\t\t\t tm_node->hw_id, rc);\n-\t\t\tgoto cleanup;\n-\t\t}\n-\t}\n-\n-\t/* Flush all tx queues */\n-\tfor (i = 0; i < sq_cnt; i++) {\n-\t\ttxq = eth_dev->data->tx_queues[i];\n-\n-\t\trc = otx2_nix_sq_sqb_aura_fc(txq, false);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to disable sqb aura fc, rc=%d\", rc);\n-\t\t\tgoto cleanup;\n-\t\t}\n-\n-\t\t/* Wait for sq entries to be flushed */\n-\t\trc = nix_txq_flush_sq_spin(txq);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to drain sq, rc=%d\\n\", rc);\n-\t\t\tgoto cleanup;\n-\t\t}\n-\t}\n-\n-\t/* XOFF & Flush all SMQ's. HRM mandates\n-\t * all SQ's empty before SMQ flush is issued.\n-\t */\n-\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (tm_node->hw_lvl != NIX_TXSCH_LVL_SMQ)\n-\t\t\tcontinue;\n-\t\tif (!(tm_node->flags & NIX_TM_NODE_HWRES))\n-\t\t\tcontinue;\n-\n-\t\trc = nix_smq_xoff(dev, tm_node, true);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to enable smq %u, rc=%d\",\n-\t\t\t\t tm_node->hw_id, rc);\n-\t\t\tgoto cleanup;\n-\t\t}\n-\t}\n-\n-\t/* Verify sanity of all tx queues */\n-\tfor (i = 0; i < sq_cnt; i++) {\n-\t\ttxq = eth_dev->data->tx_queues[i];\n-\n-\t\twdata = ((uint64_t)txq->sq << 32);\n-\t\tval = otx2_atomic64_add_nosync(wdata,\n-\t\t\t (int64_t *)(dev->base + NIX_LF_SQ_OP_STATUS));\n-\n-\t\tsqb_cnt = val & 0xFFFF;\n-\t\thead_off = (val >> 20) & 0x3F;\n-\t\ttail_off = (val >> 28) & 0x3F;\n-\n-\t\tif (sqb_cnt > 1 || head_off != tail_off ||\n-\t\t (*txq->fc_mem != txq->nb_sqb_bufs))\n-\t\t\totx2_err(\"Failed to gracefully flush sq %u\", txq->sq);\n-\t}\n-\n-cleanup:\n-\t/* restore cgx state */\n-\tif (!eth_dev->data->dev_started) {\n-\t\totx2_mbox_alloc_msg_nix_lf_stop_rx(dev->mbox);\n-\t\trc |= otx2_mbox_process(dev->mbox);\n-\t}\n-\n-\treturn rc;\n-}\n-\n-static int\n-otx2_nix_tm_node_type_get(struct rte_eth_dev *eth_dev, uint32_t node_id,\n-\t\t\t int *is_leaf, struct rte_tm_error *error)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_nix_tm_node *tm_node;\n-\n-\tif (is_leaf == NULL) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\treturn -EINVAL;\n-\t}\n-\n-\ttm_node = nix_tm_node_search(dev, node_id, true);\n-\tif (node_id == RTE_TM_NODE_ID_NULL || !tm_node) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\treturn -EINVAL;\n-\t}\n-\tif (nix_tm_is_leaf(dev, tm_node->lvl))\n-\t\t*is_leaf = true;\n-\telse\n-\t\t*is_leaf = false;\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_tm_capa_get(struct rte_eth_dev *eth_dev,\n-\t\t struct rte_tm_capabilities *cap,\n-\t\t struct rte_tm_error *error)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tint rc, max_nr_nodes = 0, i;\n-\tstruct free_rsrcs_rsp *rsp;\n-\n-\tmemset(cap, 0, sizeof(*cap));\n-\n-\totx2_mbox_alloc_msg_free_rsrc_cnt(mbox);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\terror->message = \"unexpected fatal error\";\n-\t\treturn rc;\n-\t}\n-\n-\tfor (i = 0; i < NIX_TXSCH_LVL_TL1; i++)\n-\t\tmax_nr_nodes += rsp->schq[i];\n-\n-\tcap->n_nodes_max = max_nr_nodes + dev->tm_leaf_cnt;\n-\t/* TL1 level is reserved for PF */\n-\tcap->n_levels_max = nix_tm_have_tl1_access(dev) ?\n-\t\t\t\tOTX2_TM_LVL_MAX : OTX2_TM_LVL_MAX - 1;\n-\tcap->non_leaf_nodes_identical = 1;\n-\tcap->leaf_nodes_identical = 1;\n-\n-\t/* Shaper Capabilities */\n-\tcap->shaper_private_n_max = max_nr_nodes;\n-\tcap->shaper_n_max = max_nr_nodes;\n-\tcap->shaper_private_dual_rate_n_max = max_nr_nodes;\n-\tcap->shaper_private_rate_min = MIN_SHAPER_RATE / 8;\n-\tcap->shaper_private_rate_max = MAX_SHAPER_RATE / 8;\n-\tcap->shaper_private_packet_mode_supported = 1;\n-\tcap->shaper_private_byte_mode_supported = 1;\n-\tcap->shaper_pkt_length_adjust_min = NIX_LENGTH_ADJUST_MIN;\n-\tcap->shaper_pkt_length_adjust_max = NIX_LENGTH_ADJUST_MAX;\n-\n-\t/* Schedule Capabilities */\n-\tcap->sched_n_children_max = rsp->schq[NIX_TXSCH_LVL_MDQ];\n-\tcap->sched_sp_n_priorities_max = TXSCH_TLX_SP_PRIO_MAX;\n-\tcap->sched_wfq_n_children_per_group_max = cap->sched_n_children_max;\n-\tcap->sched_wfq_n_groups_max = 1;\n-\tcap->sched_wfq_weight_max = MAX_SCHED_WEIGHT;\n-\tcap->sched_wfq_packet_mode_supported = 1;\n-\tcap->sched_wfq_byte_mode_supported = 1;\n-\n-\tcap->dynamic_update_mask =\n-\t\tRTE_TM_UPDATE_NODE_PARENT_KEEP_LEVEL |\n-\t\tRTE_TM_UPDATE_NODE_SUSPEND_RESUME;\n-\tcap->stats_mask =\n-\t\tRTE_TM_STATS_N_PKTS |\n-\t\tRTE_TM_STATS_N_BYTES |\n-\t\tRTE_TM_STATS_N_PKTS_RED_DROPPED |\n-\t\tRTE_TM_STATS_N_BYTES_RED_DROPPED;\n-\n-\tfor (i = 0; i < RTE_COLORS; i++) {\n-\t\tcap->mark_vlan_dei_supported[i] = false;\n-\t\tcap->mark_ip_ecn_tcp_supported[i] = false;\n-\t\tcap->mark_ip_dscp_supported[i] = false;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_tm_level_capa_get(struct rte_eth_dev *eth_dev, uint32_t lvl,\n-\t\t\t\t struct rte_tm_level_capabilities *cap,\n-\t\t\t\t struct rte_tm_error *error)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct free_rsrcs_rsp *rsp;\n-\tuint16_t hw_lvl;\n-\tint rc;\n-\n-\tmemset(cap, 0, sizeof(*cap));\n-\n-\totx2_mbox_alloc_msg_free_rsrc_cnt(mbox);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\terror->message = \"unexpected fatal error\";\n-\t\treturn rc;\n-\t}\n-\n-\thw_lvl = nix_tm_lvl2nix(dev, lvl);\n-\n-\tif (nix_tm_is_leaf(dev, lvl)) {\n-\t\t/* Leaf */\n-\t\tcap->n_nodes_max = dev->tm_leaf_cnt;\n-\t\tcap->n_nodes_leaf_max = dev->tm_leaf_cnt;\n-\t\tcap->leaf_nodes_identical = 1;\n-\t\tcap->leaf.stats_mask =\n-\t\t\tRTE_TM_STATS_N_PKTS |\n-\t\t\tRTE_TM_STATS_N_BYTES;\n-\n-\t} else if (lvl == OTX2_TM_LVL_ROOT) {\n-\t\t/* Root node, aka TL2(vf)/TL1(pf) */\n-\t\tcap->n_nodes_max = 1;\n-\t\tcap->n_nodes_nonleaf_max = 1;\n-\t\tcap->non_leaf_nodes_identical = 1;\n-\n-\t\tcap->nonleaf.shaper_private_supported = true;\n-\t\tcap->nonleaf.shaper_private_dual_rate_supported =\n-\t\t\tnix_tm_have_tl1_access(dev) ? false : true;\n-\t\tcap->nonleaf.shaper_private_rate_min = MIN_SHAPER_RATE / 8;\n-\t\tcap->nonleaf.shaper_private_rate_max = MAX_SHAPER_RATE / 8;\n-\t\tcap->nonleaf.shaper_private_packet_mode_supported = 1;\n-\t\tcap->nonleaf.shaper_private_byte_mode_supported = 1;\n-\n-\t\tcap->nonleaf.sched_n_children_max = rsp->schq[hw_lvl - 1];\n-\t\tcap->nonleaf.sched_sp_n_priorities_max =\n-\t\t\t\t\tnix_max_prio(dev, hw_lvl) + 1;\n-\t\tcap->nonleaf.sched_wfq_n_groups_max = 1;\n-\t\tcap->nonleaf.sched_wfq_weight_max = MAX_SCHED_WEIGHT;\n-\t\tcap->nonleaf.sched_wfq_packet_mode_supported = 1;\n-\t\tcap->nonleaf.sched_wfq_byte_mode_supported = 1;\n-\n-\t\tif (nix_tm_have_tl1_access(dev))\n-\t\t\tcap->nonleaf.stats_mask =\n-\t\t\t\tRTE_TM_STATS_N_PKTS_RED_DROPPED |\n-\t\t\t\tRTE_TM_STATS_N_BYTES_RED_DROPPED;\n-\t} else if ((lvl < OTX2_TM_LVL_MAX) &&\n-\t\t (hw_lvl < NIX_TXSCH_LVL_CNT)) {\n-\t\t/* TL2, TL3, TL4, MDQ */\n-\t\tcap->n_nodes_max = rsp->schq[hw_lvl];\n-\t\tcap->n_nodes_nonleaf_max = cap->n_nodes_max;\n-\t\tcap->non_leaf_nodes_identical = 1;\n-\n-\t\tcap->nonleaf.shaper_private_supported = true;\n-\t\tcap->nonleaf.shaper_private_dual_rate_supported = true;\n-\t\tcap->nonleaf.shaper_private_rate_min = MIN_SHAPER_RATE / 8;\n-\t\tcap->nonleaf.shaper_private_rate_max = MAX_SHAPER_RATE / 8;\n-\t\tcap->nonleaf.shaper_private_packet_mode_supported = 1;\n-\t\tcap->nonleaf.shaper_private_byte_mode_supported = 1;\n-\n-\t\t/* MDQ doesn't support Strict Priority */\n-\t\tif (hw_lvl == NIX_TXSCH_LVL_MDQ)\n-\t\t\tcap->nonleaf.sched_n_children_max = dev->tm_leaf_cnt;\n-\t\telse\n-\t\t\tcap->nonleaf.sched_n_children_max =\n-\t\t\t\trsp->schq[hw_lvl - 1];\n-\t\tcap->nonleaf.sched_sp_n_priorities_max =\n-\t\t\tnix_max_prio(dev, hw_lvl) + 1;\n-\t\tcap->nonleaf.sched_wfq_n_groups_max = 1;\n-\t\tcap->nonleaf.sched_wfq_weight_max = MAX_SCHED_WEIGHT;\n-\t\tcap->nonleaf.sched_wfq_packet_mode_supported = 1;\n-\t\tcap->nonleaf.sched_wfq_byte_mode_supported = 1;\n-\t} else {\n-\t\t/* unsupported level */\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\treturn rc;\n-\t}\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_tm_node_capa_get(struct rte_eth_dev *eth_dev, uint32_t node_id,\n-\t\t\t struct rte_tm_node_capabilities *cap,\n-\t\t\t struct rte_tm_error *error)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tstruct free_rsrcs_rsp *rsp;\n-\tint rc, hw_lvl, lvl;\n-\n-\tmemset(cap, 0, sizeof(*cap));\n-\n-\ttm_node = nix_tm_node_search(dev, node_id, true);\n-\tif (!tm_node) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\terror->message = \"no such node\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\thw_lvl = tm_node->hw_lvl;\n-\tlvl = tm_node->lvl;\n-\n-\t/* Leaf node */\n-\tif (nix_tm_is_leaf(dev, lvl)) {\n-\t\tcap->stats_mask = RTE_TM_STATS_N_PKTS |\n-\t\t\t\t\tRTE_TM_STATS_N_BYTES;\n-\t\treturn 0;\n-\t}\n-\n-\totx2_mbox_alloc_msg_free_rsrc_cnt(mbox);\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\terror->message = \"unexpected fatal error\";\n-\t\treturn rc;\n-\t}\n-\n-\t/* Non Leaf Shaper */\n-\tcap->shaper_private_supported = true;\n-\tcap->shaper_private_dual_rate_supported =\n-\t\t(hw_lvl == NIX_TXSCH_LVL_TL1) ? false : true;\n-\tcap->shaper_private_rate_min = MIN_SHAPER_RATE / 8;\n-\tcap->shaper_private_rate_max = MAX_SHAPER_RATE / 8;\n-\tcap->shaper_private_packet_mode_supported = 1;\n-\tcap->shaper_private_byte_mode_supported = 1;\n-\n-\t/* Non Leaf Scheduler */\n-\tif (hw_lvl == NIX_TXSCH_LVL_MDQ)\n-\t\tcap->nonleaf.sched_n_children_max = dev->tm_leaf_cnt;\n-\telse\n-\t\tcap->nonleaf.sched_n_children_max = rsp->schq[hw_lvl - 1];\n-\n-\tcap->nonleaf.sched_sp_n_priorities_max = nix_max_prio(dev, hw_lvl) + 1;\n-\tcap->nonleaf.sched_wfq_n_children_per_group_max =\n-\t\tcap->nonleaf.sched_n_children_max;\n-\tcap->nonleaf.sched_wfq_n_groups_max = 1;\n-\tcap->nonleaf.sched_wfq_weight_max = MAX_SCHED_WEIGHT;\n-\tcap->nonleaf.sched_wfq_packet_mode_supported = 1;\n-\tcap->nonleaf.sched_wfq_byte_mode_supported = 1;\n-\n-\tif (hw_lvl == NIX_TXSCH_LVL_TL1)\n-\t\tcap->stats_mask = RTE_TM_STATS_N_PKTS_RED_DROPPED |\n-\t\t\tRTE_TM_STATS_N_BYTES_RED_DROPPED;\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_tm_shaper_profile_add(struct rte_eth_dev *eth_dev,\n-\t\t\t uint32_t profile_id,\n-\t\t\t struct rte_tm_shaper_params *params,\n-\t\t\t struct rte_tm_error *error)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_nix_tm_shaper_profile *profile;\n-\n-\tprofile = nix_tm_shaper_profile_search(dev, profile_id);\n-\tif (profile) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID;\n-\t\terror->message = \"shaper profile ID exist\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Committed rate and burst size can be enabled/disabled */\n-\tif (params->committed.size || params->committed.rate) {\n-\t\tif (params->committed.size < MIN_SHAPER_BURST ||\n-\t\t params->committed.size > MAX_SHAPER_BURST) {\n-\t\t\terror->type =\n-\t\t\t\tRTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_SIZE;\n-\t\t\treturn -EINVAL;\n-\t\t} else if (!shaper_rate_to_nix(params->committed.rate * 8,\n-\t\t\t\t\t NULL, NULL, NULL)) {\n-\t\t\terror->type =\n-\t\t\t\tRTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_RATE;\n-\t\t\terror->message = \"shaper committed rate invalid\";\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\t/* Peak rate and burst size can be enabled/disabled */\n-\tif (params->peak.size || params->peak.rate) {\n-\t\tif (params->peak.size < MIN_SHAPER_BURST ||\n-\t\t params->peak.size > MAX_SHAPER_BURST) {\n-\t\t\terror->type =\n-\t\t\t\tRTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_SIZE;\n-\t\t\treturn -EINVAL;\n-\t\t} else if (!shaper_rate_to_nix(params->peak.rate * 8,\n-\t\t\t\t\t NULL, NULL, NULL)) {\n-\t\t\terror->type =\n-\t\t\t\tRTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_RATE;\n-\t\t\terror->message = \"shaper peak rate invalid\";\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\tif (params->pkt_length_adjust < NIX_LENGTH_ADJUST_MIN ||\n-\t params->pkt_length_adjust > NIX_LENGTH_ADJUST_MAX) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PKT_ADJUST_LEN;\n-\t\terror->message = \"length adjust invalid\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tprofile = rte_zmalloc(\"otx2_nix_tm_shaper_profile\",\n-\t\t\t sizeof(struct otx2_nix_tm_shaper_profile), 0);\n-\tif (!profile)\n-\t\treturn -ENOMEM;\n-\n-\tprofile->shaper_profile_id = profile_id;\n-\trte_memcpy(&profile->params, params,\n-\t\t sizeof(struct rte_tm_shaper_params));\n-\tTAILQ_INSERT_TAIL(&dev->shaper_profile_list, profile, shaper);\n-\n-\totx2_tm_dbg(\"Added TM shaper profile %u, \"\n-\t\t \" pir %\" PRIu64 \" , pbs %\" PRIu64 \", cir %\" PRIu64\n-\t\t \", cbs %\" PRIu64 \" , adj %u, pkt mode %d\",\n-\t\t profile_id,\n-\t\t params->peak.rate * 8,\n-\t\t params->peak.size,\n-\t\t params->committed.rate * 8,\n-\t\t params->committed.size,\n-\t\t params->pkt_length_adjust,\n-\t\t params->packet_mode);\n-\n-\t/* Translate rate as bits per second */\n-\tprofile->params.peak.rate = profile->params.peak.rate * 8;\n-\tprofile->params.committed.rate = profile->params.committed.rate * 8;\n-\t/* Always use PIR for single rate shaping */\n-\tif (!params->peak.rate && params->committed.rate) {\n-\t\tprofile->params.peak = profile->params.committed;\n-\t\tmemset(&profile->params.committed, 0,\n-\t\t sizeof(profile->params.committed));\n-\t}\n-\n-\t/* update min rate */\n-\tnix_tm_shaper_profile_update_min(dev);\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_tm_shaper_profile_delete(struct rte_eth_dev *eth_dev,\n-\t\t\t\t uint32_t profile_id,\n-\t\t\t\t struct rte_tm_error *error)\n-{\n-\tstruct otx2_nix_tm_shaper_profile *profile;\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tprofile = nix_tm_shaper_profile_search(dev, profile_id);\n-\n-\tif (!profile) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID;\n-\t\terror->message = \"shaper profile ID not exist\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (profile->reference_count) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE;\n-\t\terror->message = \"shaper profile in use\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\totx2_tm_dbg(\"Removing TM shaper profile %u\", profile_id);\n-\tTAILQ_REMOVE(&dev->shaper_profile_list, profile, shaper);\n-\trte_free(profile);\n-\n-\t/* update min rate */\n-\tnix_tm_shaper_profile_update_min(dev);\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_tm_node_add(struct rte_eth_dev *eth_dev, uint32_t node_id,\n-\t\t uint32_t parent_node_id, uint32_t priority,\n-\t\t uint32_t weight, uint32_t lvl,\n-\t\t struct rte_tm_node_params *params,\n-\t\t struct rte_tm_error *error)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_nix_tm_shaper_profile *profile = NULL;\n-\tstruct otx2_nix_tm_node *parent_node;\n-\tint rc, pkt_mode, clear_on_fail = 0;\n-\tuint32_t exp_next_lvl, i;\n-\tuint32_t profile_id;\n-\tuint16_t hw_lvl;\n-\n-\t/* we don't support dynamic updates */\n-\tif (dev->tm_flags & NIX_TM_COMMITTED) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_CAPABILITIES;\n-\t\terror->message = \"dynamic update not supported\";\n-\t\treturn -EIO;\n-\t}\n-\n-\t/* Leaf nodes have to be same priority */\n-\tif (nix_tm_is_leaf(dev, lvl) && priority != 0) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_CAPABILITIES;\n-\t\terror->message = \"queue shapers must be priority 0\";\n-\t\treturn -EIO;\n-\t}\n-\n-\tparent_node = nix_tm_node_search(dev, parent_node_id, true);\n-\n-\t/* find the right level */\n-\tif (lvl == RTE_TM_NODE_LEVEL_ID_ANY) {\n-\t\tif (parent_node_id == RTE_TM_NODE_ID_NULL) {\n-\t\t\tlvl = OTX2_TM_LVL_ROOT;\n-\t\t} else if (parent_node) {\n-\t\t\tlvl = parent_node->lvl + 1;\n-\t\t} else {\n-\t\t\t/* Neigher proper parent nor proper level id given */\n-\t\t\terror->type = RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID;\n-\t\t\terror->message = \"invalid parent node id\";\n-\t\t\treturn -ERANGE;\n-\t\t}\n-\t}\n-\n-\t/* Translate rte_tm level id's to nix hw level id's */\n-\thw_lvl = nix_tm_lvl2nix(dev, lvl);\n-\tif (hw_lvl == NIX_TXSCH_LVL_CNT &&\n-\t !nix_tm_is_leaf(dev, lvl)) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_LEVEL_ID;\n-\t\terror->message = \"invalid level id\";\n-\t\treturn -ERANGE;\n-\t}\n-\n-\tif (node_id < dev->tm_leaf_cnt)\n-\t\texp_next_lvl = NIX_TXSCH_LVL_SMQ;\n-\telse\n-\t\texp_next_lvl = hw_lvl + 1;\n-\n-\t/* Check if there is no parent node yet */\n-\tif (hw_lvl != dev->otx2_tm_root_lvl &&\n-\t (!parent_node || parent_node->hw_lvl != exp_next_lvl)) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID;\n-\t\terror->message = \"invalid parent node id\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Check if a node already exists */\n-\tif (nix_tm_node_search(dev, node_id, true)) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\terror->message = \"node already exists\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (!nix_tm_is_leaf(dev, lvl)) {\n-\t\t/* Check if shaper profile exists for non leaf node */\n-\t\tprofile_id = params->shaper_profile_id;\n-\t\tprofile = nix_tm_shaper_profile_search(dev, profile_id);\n-\t\tif (profile_id != RTE_TM_SHAPER_PROFILE_ID_NONE && !profile) {\n-\t\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID;\n-\t\t\terror->message = \"invalid shaper profile\";\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\t/* Minimum static priority count is 1 */\n-\t\tif (!params->nonleaf.n_sp_priorities ||\n-\t\t params->nonleaf.n_sp_priorities > TXSCH_TLX_SP_PRIO_MAX) {\n-\t\t\terror->type =\n-\t\t\t\tRTE_TM_ERROR_TYPE_NODE_PARAMS_N_SP_PRIORITIES;\n-\t\t\terror->message = \"invalid sp priorities\";\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\tpkt_mode = 0;\n-\t\t/* Validate weight mode */\n-\t\tfor (i = 0; i < params->nonleaf.n_sp_priorities &&\n-\t\t params->nonleaf.wfq_weight_mode; i++) {\n-\t\t\tpkt_mode = !params->nonleaf.wfq_weight_mode[i];\n-\t\t\tif (pkt_mode == !params->nonleaf.wfq_weight_mode[0])\n-\t\t\t\tcontinue;\n-\n-\t\t\terror->type =\n-\t\t\t\tRTE_TM_ERROR_TYPE_NODE_PARAMS_WFQ_WEIGHT_MODE;\n-\t\t\terror->message = \"unsupported weight mode\";\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\tif (profile && params->nonleaf.n_sp_priorities &&\n-\t\t pkt_mode != profile->params.packet_mode) {\n-\t\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE;\n-\t\t\terror->message = \"shaper wfq packet mode mismatch\";\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\t/* Check if there is second DWRR already in siblings or holes in prio */\n-\tif (validate_prio(dev, lvl, parent_node_id, priority, error))\n-\t\treturn -EINVAL;\n-\n-\tif (weight > MAX_SCHED_WEIGHT) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_WEIGHT;\n-\t\terror->message = \"max weight exceeded\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\trc = nix_tm_node_add_to_list(dev, node_id, parent_node_id,\n-\t\t\t\t priority, weight, hw_lvl,\n-\t\t\t\t lvl, true, params);\n-\tif (rc) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\t/* cleanup user added nodes */\n-\t\tif (clear_on_fail)\n-\t\t\tnix_tm_free_resources(dev, NIX_TM_NODE_USER,\n-\t\t\t\t\t NIX_TM_NODE_USER, false);\n-\t\terror->message = \"failed to add node\";\n-\t\treturn rc;\n-\t}\n-\terror->type = RTE_TM_ERROR_TYPE_NONE;\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_tm_node_delete(struct rte_eth_dev *eth_dev, uint32_t node_id,\n-\t\t\tstruct rte_tm_error *error)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_nix_tm_node *tm_node, *child_node;\n-\tstruct otx2_nix_tm_shaper_profile *profile;\n-\tuint32_t profile_id;\n-\n-\t/* we don't support dynamic updates yet */\n-\tif (dev->tm_flags & NIX_TM_COMMITTED) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_CAPABILITIES;\n-\t\terror->message = \"hierarchy exists\";\n-\t\treturn -EIO;\n-\t}\n-\n-\tif (node_id == RTE_TM_NODE_ID_NULL) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\terror->message = \"invalid node id\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\ttm_node = nix_tm_node_search(dev, node_id, true);\n-\tif (!tm_node) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\terror->message = \"no such node\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Check for any existing children */\n-\tTAILQ_FOREACH(child_node, &dev->node_list, node) {\n-\t\tif (child_node->parent == tm_node) {\n-\t\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\t\terror->message = \"children exist\";\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\t/* Remove shaper profile reference */\n-\tprofile_id = tm_node->params.shaper_profile_id;\n-\tprofile = nix_tm_shaper_profile_search(dev, profile_id);\n-\tprofile->reference_count--;\n-\n-\tTAILQ_REMOVE(&dev->node_list, tm_node, node);\n-\trte_free(tm_node);\n-\treturn 0;\n-}\n-\n-static int\n-nix_tm_node_suspend_resume(struct rte_eth_dev *eth_dev, uint32_t node_id,\n-\t\t\t struct rte_tm_error *error, bool suspend)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tstruct nix_txschq_config *req;\n-\tuint16_t flags;\n-\tint rc;\n-\n-\ttm_node = nix_tm_node_search(dev, node_id, true);\n-\tif (!tm_node) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\terror->message = \"no such node\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (!(dev->tm_flags & NIX_TM_COMMITTED)) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\terror->message = \"hierarchy doesn't exist\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tflags = tm_node->flags;\n-\tflags = suspend ? (flags & ~NIX_TM_NODE_ENABLED) :\n-\t\t(flags | NIX_TM_NODE_ENABLED);\n-\n-\tif (tm_node->flags == flags)\n-\t\treturn 0;\n-\n-\t/* send mbox for state change */\n-\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\n-\treq->lvl = tm_node->hw_lvl;\n-\treq->num_regs =\tprepare_tm_sw_xoff(tm_node, suspend,\n-\t\t\t\t\t req->reg, req->regval);\n-\trc = send_tm_reqval(mbox, req, error);\n-\tif (!rc)\n-\t\ttm_node->flags = flags;\n-\treturn rc;\n-}\n-\n-static int\n-otx2_nix_tm_node_suspend(struct rte_eth_dev *eth_dev, uint32_t node_id,\n-\t\t\t struct rte_tm_error *error)\n-{\n-\treturn nix_tm_node_suspend_resume(eth_dev, node_id, error, true);\n-}\n-\n-static int\n-otx2_nix_tm_node_resume(struct rte_eth_dev *eth_dev, uint32_t node_id,\n-\t\t\tstruct rte_tm_error *error)\n-{\n-\treturn nix_tm_node_suspend_resume(eth_dev, node_id, error, false);\n-}\n-\n-static int\n-otx2_nix_tm_hierarchy_commit(struct rte_eth_dev *eth_dev,\n-\t\t\t int clear_on_fail,\n-\t\t\t struct rte_tm_error *error)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tuint32_t leaf_cnt = 0;\n-\tint rc;\n-\n-\tif (dev->tm_flags & NIX_TM_COMMITTED) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\terror->message = \"hierarchy exists\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Check if we have all the leaf nodes */\n-\tTAILQ_FOREACH(tm_node, &dev->node_list, node) {\n-\t\tif (tm_node->flags & NIX_TM_NODE_USER &&\n-\t\t tm_node->id < dev->tm_leaf_cnt)\n-\t\t\tleaf_cnt++;\n-\t}\n-\n-\tif (leaf_cnt != dev->tm_leaf_cnt) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\terror->message = \"incomplete hierarchy\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/*\n-\t * Disable xmit will be enabled when\n-\t * new topology is available.\n-\t */\n-\trc = nix_xmit_disable(eth_dev);\n-\tif (rc) {\n-\t\totx2_err(\"failed to disable TX, rc=%d\", rc);\n-\t\treturn -EIO;\n-\t}\n-\n-\t/* Delete default/ratelimit tree */\n-\tif (dev->tm_flags & (NIX_TM_DEFAULT_TREE | NIX_TM_RATE_LIMIT_TREE)) {\n-\t\trc = nix_tm_free_resources(dev, NIX_TM_NODE_USER, 0, false);\n-\t\tif (rc) {\n-\t\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\t\terror->message = \"failed to free default resources\";\n-\t\t\treturn rc;\n-\t\t}\n-\t\tdev->tm_flags &= ~(NIX_TM_DEFAULT_TREE |\n-\t\t\t\t NIX_TM_RATE_LIMIT_TREE);\n-\t}\n-\n-\t/* Free up user alloc'ed resources */\n-\trc = nix_tm_free_resources(dev, NIX_TM_NODE_USER,\n-\t\t\t\t NIX_TM_NODE_USER, true);\n-\tif (rc) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\terror->message = \"failed to free user resources\";\n-\t\treturn rc;\n-\t}\n-\n-\trc = nix_tm_alloc_resources(eth_dev, true);\n-\tif (rc) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\terror->message = \"alloc resources failed\";\n-\t\t/* TODO should we restore default config ? */\n-\t\tif (clear_on_fail)\n-\t\t\tnix_tm_free_resources(dev, 0, 0, false);\n-\t\treturn rc;\n-\t}\n-\n-\terror->type = RTE_TM_ERROR_TYPE_NONE;\n-\tdev->tm_flags |= NIX_TM_COMMITTED;\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_tm_node_shaper_update(struct rte_eth_dev *eth_dev,\n-\t\t\t uint32_t node_id,\n-\t\t\t uint32_t profile_id,\n-\t\t\t struct rte_tm_error *error)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_nix_tm_shaper_profile *profile = NULL;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tstruct nix_txschq_config *req;\n-\tuint8_t k;\n-\tint rc;\n-\n-\ttm_node = nix_tm_node_search(dev, node_id, true);\n-\tif (!tm_node || nix_tm_is_leaf(dev, tm_node->lvl)) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\terror->message = \"invalid node\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (profile_id == tm_node->params.shaper_profile_id)\n-\t\treturn 0;\n-\n-\tif (profile_id != RTE_TM_SHAPER_PROFILE_ID_NONE) {\n-\t\tprofile = nix_tm_shaper_profile_search(dev, profile_id);\n-\t\tif (!profile) {\n-\t\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID;\n-\t\t\terror->message = \"shaper profile ID not exist\";\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\tif (profile && profile->params.packet_mode != tm_node->pkt_mode) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID;\n-\t\terror->message = \"shaper profile pkt mode mismatch\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\ttm_node->params.shaper_profile_id = profile_id;\n-\n-\t/* Nothing to do if not yet committed */\n-\tif (!(dev->tm_flags & NIX_TM_COMMITTED))\n-\t\treturn 0;\n-\n-\ttm_node->flags &= ~NIX_TM_NODE_ENABLED;\n-\n-\t/* Flush the specific node with SW_XOFF */\n-\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\treq->lvl = tm_node->hw_lvl;\n-\tk = prepare_tm_sw_xoff(tm_node, true, req->reg, req->regval);\n-\treq->num_regs = k;\n-\n-\trc = send_tm_reqval(mbox, req, error);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tshaper_default_red_algo(dev, tm_node, profile);\n-\n-\t/* Update the PIR/CIR and clear SW XOFF */\n-\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\treq->lvl = tm_node->hw_lvl;\n-\n-\tk = prepare_tm_shaper_reg(tm_node, profile, req->reg, req->regval);\n-\n-\tk += prepare_tm_sw_xoff(tm_node, false, &req->reg[k], &req->regval[k]);\n-\n-\treq->num_regs = k;\n-\trc = send_tm_reqval(mbox, req, error);\n-\tif (!rc)\n-\t\ttm_node->flags |= NIX_TM_NODE_ENABLED;\n-\treturn rc;\n-}\n-\n-static int\n-otx2_nix_tm_node_parent_update(struct rte_eth_dev *eth_dev,\n-\t\t\t uint32_t node_id, uint32_t new_parent_id,\n-\t\t\t uint32_t priority, uint32_t weight,\n-\t\t\t struct rte_tm_error *error)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_nix_tm_node *tm_node, *sibling;\n-\tstruct otx2_nix_tm_node *new_parent;\n-\tstruct nix_txschq_config *req;\n-\tuint8_t k;\n-\tint rc;\n-\n-\tif (!(dev->tm_flags & NIX_TM_COMMITTED)) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\terror->message = \"hierarchy doesn't exist\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\ttm_node = nix_tm_node_search(dev, node_id, true);\n-\tif (!tm_node) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\terror->message = \"no such node\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Parent id valid only for non root nodes */\n-\tif (tm_node->hw_lvl != dev->otx2_tm_root_lvl) {\n-\t\tnew_parent = nix_tm_node_search(dev, new_parent_id, true);\n-\t\tif (!new_parent) {\n-\t\t\terror->type = RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID;\n-\t\t\terror->message = \"no such parent node\";\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\n-\t\t/* Current support is only for dynamic weight update */\n-\t\tif (tm_node->parent != new_parent ||\n-\t\t tm_node->priority != priority) {\n-\t\t\terror->type = RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID;\n-\t\t\terror->message = \"only weight update supported\";\n-\t\t\treturn -EINVAL;\n-\t\t}\n-\t}\n-\n-\t/* Skip if no change */\n-\tif (tm_node->weight == weight)\n-\t\treturn 0;\n-\n-\ttm_node->weight = weight;\n-\n-\t/* For leaf nodes, SQ CTX needs update */\n-\tif (nix_tm_is_leaf(dev, tm_node->lvl)) {\n-\t\t/* Update SQ quantum data on the fly */\n-\t\trc = nix_sq_sched_data(dev, tm_node, true);\n-\t\tif (rc) {\n-\t\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\t\terror->message = \"sq sched data update failed\";\n-\t\t\treturn rc;\n-\t\t}\n-\t} else {\n-\t\t/* XOFF Parent node */\n-\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);\n-\t\treq->lvl = tm_node->parent->hw_lvl;\n-\t\treq->num_regs = prepare_tm_sw_xoff(tm_node->parent, true,\n-\t\t\t\t\t\t req->reg, req->regval);\n-\t\trc = send_tm_reqval(dev->mbox, req, error);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\n-\t\t/* XOFF this node and all other siblings */\n-\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);\n-\t\treq->lvl = tm_node->hw_lvl;\n-\n-\t\tk = 0;\n-\t\tTAILQ_FOREACH(sibling, &dev->node_list, node) {\n-\t\t\tif (sibling->parent != tm_node->parent)\n-\t\t\t\tcontinue;\n-\t\t\tk += prepare_tm_sw_xoff(sibling, true, &req->reg[k],\n-\t\t\t\t\t\t&req->regval[k]);\n-\t\t}\n-\t\treq->num_regs = k;\n-\t\trc = send_tm_reqval(dev->mbox, req, error);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\n-\t\t/* Update new weight for current node */\n-\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);\n-\t\treq->lvl = tm_node->hw_lvl;\n-\t\treq->num_regs = prepare_tm_sched_reg(dev, tm_node,\n-\t\t\t\t\t\t req->reg, req->regval);\n-\t\trc = send_tm_reqval(dev->mbox, req, error);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\n-\t\t/* XON this node and all other siblings */\n-\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);\n-\t\treq->lvl = tm_node->hw_lvl;\n-\n-\t\tk = 0;\n-\t\tTAILQ_FOREACH(sibling, &dev->node_list, node) {\n-\t\t\tif (sibling->parent != tm_node->parent)\n-\t\t\t\tcontinue;\n-\t\t\tk += prepare_tm_sw_xoff(sibling, false, &req->reg[k],\n-\t\t\t\t\t\t&req->regval[k]);\n-\t\t}\n-\t\treq->num_regs = k;\n-\t\trc = send_tm_reqval(dev->mbox, req, error);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\n-\t\t/* XON Parent node */\n-\t\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(dev->mbox);\n-\t\treq->lvl = tm_node->parent->hw_lvl;\n-\t\treq->num_regs = prepare_tm_sw_xoff(tm_node->parent, false,\n-\t\t\t\t\t\t req->reg, req->regval);\n-\t\trc = send_tm_reqval(dev->mbox, req, error);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\t}\n-\treturn 0;\n-}\n-\n-static int\n-otx2_nix_tm_node_stats_read(struct rte_eth_dev *eth_dev, uint32_t node_id,\n-\t\t\t struct rte_tm_node_stats *stats,\n-\t\t\t uint64_t *stats_mask, int clear,\n-\t\t\t struct rte_tm_error *error)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tuint64_t reg, val;\n-\tint64_t *addr;\n-\tint rc = 0;\n-\n-\ttm_node = nix_tm_node_search(dev, node_id, true);\n-\tif (!tm_node) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\terror->message = \"no such node\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (!(tm_node->flags & NIX_TM_NODE_HWRES)) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\terror->message = \"HW resources not allocated\";\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Stats support only for leaf node or TL1 root */\n-\tif (nix_tm_is_leaf(dev, tm_node->lvl)) {\n-\t\treg = (((uint64_t)tm_node->id) << 32);\n-\n-\t\t/* Packets */\n-\t\taddr = (int64_t *)(dev->base + NIX_LF_SQ_OP_PKTS);\n-\t\tval = otx2_atomic64_add_nosync(reg, addr);\n-\t\tif (val & OP_ERR)\n-\t\t\tval = 0;\n-\t\tstats->n_pkts = val - tm_node->last_pkts;\n-\n-\t\t/* Bytes */\n-\t\taddr = (int64_t *)(dev->base + NIX_LF_SQ_OP_OCTS);\n-\t\tval = otx2_atomic64_add_nosync(reg, addr);\n-\t\tif (val & OP_ERR)\n-\t\t\tval = 0;\n-\t\tstats->n_bytes = val - tm_node->last_bytes;\n-\n-\t\tif (clear) {\n-\t\t\ttm_node->last_pkts = stats->n_pkts;\n-\t\t\ttm_node->last_bytes = stats->n_bytes;\n-\t\t}\n-\n-\t\t*stats_mask = RTE_TM_STATS_N_PKTS | RTE_TM_STATS_N_BYTES;\n-\n-\t} else if (tm_node->hw_lvl == NIX_TXSCH_LVL_TL1) {\n-\t\terror->type = RTE_TM_ERROR_TYPE_UNSPECIFIED;\n-\t\terror->message = \"stats read error\";\n-\n-\t\t/* RED Drop packets */\n-\t\treg = NIX_AF_TL1X_DROPPED_PACKETS(tm_node->hw_id);\n-\t\trc = read_tm_reg(dev->mbox, reg, &val, NIX_TXSCH_LVL_TL1);\n-\t\tif (rc)\n-\t\t\tgoto exit;\n-\t\tstats->leaf.n_pkts_dropped[RTE_COLOR_RED] =\n-\t\t\t\t\t\tval - tm_node->last_pkts;\n-\n-\t\t/* RED Drop bytes */\n-\t\treg = NIX_AF_TL1X_DROPPED_BYTES(tm_node->hw_id);\n-\t\trc = read_tm_reg(dev->mbox, reg, &val, NIX_TXSCH_LVL_TL1);\n-\t\tif (rc)\n-\t\t\tgoto exit;\n-\t\tstats->leaf.n_bytes_dropped[RTE_COLOR_RED] =\n-\t\t\t\t\t\tval - tm_node->last_bytes;\n-\n-\t\t/* Clear stats */\n-\t\tif (clear) {\n-\t\t\ttm_node->last_pkts =\n-\t\t\t\tstats->leaf.n_pkts_dropped[RTE_COLOR_RED];\n-\t\t\ttm_node->last_bytes =\n-\t\t\t\tstats->leaf.n_bytes_dropped[RTE_COLOR_RED];\n-\t\t}\n-\n-\t\t*stats_mask = RTE_TM_STATS_N_PKTS_RED_DROPPED |\n-\t\t\tRTE_TM_STATS_N_BYTES_RED_DROPPED;\n-\n-\t} else {\n-\t\terror->type = RTE_TM_ERROR_TYPE_NODE_ID;\n-\t\terror->message = \"unsupported node\";\n-\t\trc = -EINVAL;\n-\t}\n-\n-exit:\n-\treturn rc;\n-}\n-\n-const struct rte_tm_ops otx2_tm_ops = {\n-\t.node_type_get = otx2_nix_tm_node_type_get,\n-\n-\t.capabilities_get = otx2_nix_tm_capa_get,\n-\t.level_capabilities_get = otx2_nix_tm_level_capa_get,\n-\t.node_capabilities_get = otx2_nix_tm_node_capa_get,\n-\n-\t.shaper_profile_add = otx2_nix_tm_shaper_profile_add,\n-\t.shaper_profile_delete = otx2_nix_tm_shaper_profile_delete,\n-\n-\t.node_add = otx2_nix_tm_node_add,\n-\t.node_delete = otx2_nix_tm_node_delete,\n-\t.node_suspend = otx2_nix_tm_node_suspend,\n-\t.node_resume = otx2_nix_tm_node_resume,\n-\t.hierarchy_commit = otx2_nix_tm_hierarchy_commit,\n-\n-\t.node_shaper_update = otx2_nix_tm_node_shaper_update,\n-\t.node_parent_update = otx2_nix_tm_node_parent_update,\n-\t.node_stats_read = otx2_nix_tm_node_stats_read,\n-};\n-\n-static int\n-nix_tm_prepare_default_tree(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint32_t def = eth_dev->data->nb_tx_queues;\n-\tstruct rte_tm_node_params params;\n-\tuint32_t leaf_parent, i;\n-\tint rc = 0, leaf_level;\n-\n-\t/* Default params */\n-\tmemset(¶ms, 0, sizeof(params));\n-\tparams.shaper_profile_id = RTE_TM_SHAPER_PROFILE_ID_NONE;\n-\n-\tif (nix_tm_have_tl1_access(dev)) {\n-\t\tdev->otx2_tm_root_lvl = NIX_TXSCH_LVL_TL1;\n-\t\trc = nix_tm_node_add_to_list(dev, def, RTE_TM_NODE_ID_NULL, 0,\n-\t\t\t\t\t DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t NIX_TXSCH_LVL_TL1,\n-\t\t\t\t\t OTX2_TM_LVL_ROOT, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto exit;\n-\t\trc = nix_tm_node_add_to_list(dev, def + 1, def, 0,\n-\t\t\t\t\t DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t NIX_TXSCH_LVL_TL2,\n-\t\t\t\t\t OTX2_TM_LVL_SCH1, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto exit;\n-\n-\t\trc = nix_tm_node_add_to_list(dev, def + 2, def + 1, 0,\n-\t\t\t\t\t DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t NIX_TXSCH_LVL_TL3,\n-\t\t\t\t\t OTX2_TM_LVL_SCH2, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto exit;\n-\n-\t\trc = nix_tm_node_add_to_list(dev, def + 3, def + 2, 0,\n-\t\t\t\t\t DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t NIX_TXSCH_LVL_TL4,\n-\t\t\t\t\t OTX2_TM_LVL_SCH3, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto exit;\n-\n-\t\trc = nix_tm_node_add_to_list(dev, def + 4, def + 3, 0,\n-\t\t\t\t\t DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t NIX_TXSCH_LVL_SMQ,\n-\t\t\t\t\t OTX2_TM_LVL_SCH4, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto exit;\n-\n-\t\tleaf_parent = def + 4;\n-\t\tleaf_level = OTX2_TM_LVL_QUEUE;\n-\t} else {\n-\t\tdev->otx2_tm_root_lvl = NIX_TXSCH_LVL_TL2;\n-\t\trc = nix_tm_node_add_to_list(dev, def, RTE_TM_NODE_ID_NULL, 0,\n-\t\t\t\t\t DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t NIX_TXSCH_LVL_TL2,\n-\t\t\t\t\t OTX2_TM_LVL_ROOT, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto exit;\n-\n-\t\trc = nix_tm_node_add_to_list(dev, def + 1, def, 0,\n-\t\t\t\t\t DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t NIX_TXSCH_LVL_TL3,\n-\t\t\t\t\t OTX2_TM_LVL_SCH1, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto exit;\n-\n-\t\trc = nix_tm_node_add_to_list(dev, def + 2, def + 1, 0,\n-\t\t\t\t\t DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t NIX_TXSCH_LVL_TL4,\n-\t\t\t\t\t OTX2_TM_LVL_SCH2, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto exit;\n-\n-\t\trc = nix_tm_node_add_to_list(dev, def + 3, def + 2, 0,\n-\t\t\t\t\t DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t NIX_TXSCH_LVL_SMQ,\n-\t\t\t\t\t OTX2_TM_LVL_SCH3, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto exit;\n-\n-\t\tleaf_parent = def + 3;\n-\t\tleaf_level = OTX2_TM_LVL_SCH4;\n-\t}\n-\n-\t/* Add leaf nodes */\n-\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n-\t\trc = nix_tm_node_add_to_list(dev, i, leaf_parent, 0,\n-\t\t\t\t\t DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t NIX_TXSCH_LVL_CNT,\n-\t\t\t\t\t leaf_level, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tbreak;\n-\t}\n-\n-exit:\n-\treturn rc;\n-}\n-\n-void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tTAILQ_INIT(&dev->node_list);\n-\tTAILQ_INIT(&dev->shaper_profile_list);\n-\tdev->tm_rate_min = 1E9; /* 1Gbps */\n-}\n-\n-int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint16_t sq_cnt = eth_dev->data->nb_tx_queues;\n-\tint rc;\n-\n-\t/* Free up all resources already held */\n-\trc = nix_tm_free_resources(dev, 0, 0, false);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to freeup existing resources,rc=%d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\t/* Clear shaper profiles */\n-\tnix_tm_clear_shaper_profiles(dev);\n-\tdev->tm_flags = NIX_TM_DEFAULT_TREE;\n-\n-\t/* Disable TL1 Static Priority when VF's are enabled\n-\t * as otherwise VF's TL2 reallocation will be needed\n-\t * runtime to support a specific topology of PF.\n-\t */\n-\tif (pci_dev->max_vfs)\n-\t\tdev->tm_flags |= NIX_TM_TL1_NO_SP;\n-\n-\trc = nix_tm_prepare_default_tree(eth_dev);\n-\tif (rc != 0)\n-\t\treturn rc;\n-\n-\trc = nix_tm_alloc_resources(eth_dev, false);\n-\tif (rc != 0)\n-\t\treturn rc;\n-\tdev->tm_leaf_cnt = sq_cnt;\n-\n-\treturn 0;\n-}\n-\n-static int\n-nix_tm_prepare_rate_limited_tree(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint32_t def = eth_dev->data->nb_tx_queues;\n-\tstruct rte_tm_node_params params;\n-\tuint32_t leaf_parent, i, rc = 0;\n-\n-\tmemset(¶ms, 0, sizeof(params));\n-\n-\tif (nix_tm_have_tl1_access(dev)) {\n-\t\tdev->otx2_tm_root_lvl = NIX_TXSCH_LVL_TL1;\n-\t\trc = nix_tm_node_add_to_list(dev, def, RTE_TM_NODE_ID_NULL, 0,\n-\t\t\t\t\tDEFAULT_RR_WEIGHT,\n-\t\t\t\t\tNIX_TXSCH_LVL_TL1,\n-\t\t\t\t\tOTX2_TM_LVL_ROOT, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto error;\n-\t\trc = nix_tm_node_add_to_list(dev, def + 1, def, 0,\n-\t\t\t\t\tDEFAULT_RR_WEIGHT,\n-\t\t\t\t\tNIX_TXSCH_LVL_TL2,\n-\t\t\t\t\tOTX2_TM_LVL_SCH1, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto error;\n-\t\trc = nix_tm_node_add_to_list(dev, def + 2, def + 1, 0,\n-\t\t\t\t\tDEFAULT_RR_WEIGHT,\n-\t\t\t\t\tNIX_TXSCH_LVL_TL3,\n-\t\t\t\t\tOTX2_TM_LVL_SCH2, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto error;\n-\t\trc = nix_tm_node_add_to_list(dev, def + 3, def + 2, 0,\n-\t\t\t\t\tDEFAULT_RR_WEIGHT,\n-\t\t\t\t\tNIX_TXSCH_LVL_TL4,\n-\t\t\t\t\tOTX2_TM_LVL_SCH3, false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto error;\n-\t\tleaf_parent = def + 3;\n-\n-\t\t/* Add per queue SMQ nodes */\n-\t\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n-\t\t\trc = nix_tm_node_add_to_list(dev, leaf_parent + 1 + i,\n-\t\t\t\t\t\tleaf_parent,\n-\t\t\t\t\t\t0, DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t\tNIX_TXSCH_LVL_SMQ,\n-\t\t\t\t\t\tOTX2_TM_LVL_SCH4,\n-\t\t\t\t\t\tfalse, ¶ms);\n-\t\t\tif (rc)\n-\t\t\t\tgoto error;\n-\t\t}\n-\n-\t\t/* Add leaf nodes */\n-\t\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n-\t\t\trc = nix_tm_node_add_to_list(dev, i,\n-\t\t\t\t\t\t leaf_parent + 1 + i, 0,\n-\t\t\t\t\t\t DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t\t NIX_TXSCH_LVL_CNT,\n-\t\t\t\t\t\t OTX2_TM_LVL_QUEUE,\n-\t\t\t\t\t\t false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto error;\n-\t\t}\n-\n-\t\treturn 0;\n-\t}\n-\n-\tdev->otx2_tm_root_lvl = NIX_TXSCH_LVL_TL2;\n-\trc = nix_tm_node_add_to_list(dev, def, RTE_TM_NODE_ID_NULL, 0,\n-\t\t\t\tDEFAULT_RR_WEIGHT, NIX_TXSCH_LVL_TL2,\n-\t\t\t\tOTX2_TM_LVL_ROOT, false, ¶ms);\n-\tif (rc)\n-\t\tgoto error;\n-\trc = nix_tm_node_add_to_list(dev, def + 1, def, 0,\n-\t\t\t\tDEFAULT_RR_WEIGHT, NIX_TXSCH_LVL_TL3,\n-\t\t\t\tOTX2_TM_LVL_SCH1, false, ¶ms);\n-\tif (rc)\n-\t\tgoto error;\n-\trc = nix_tm_node_add_to_list(dev, def + 2, def + 1, 0,\n-\t\t\t\t DEFAULT_RR_WEIGHT, NIX_TXSCH_LVL_TL4,\n-\t\t\t\t OTX2_TM_LVL_SCH2, false, ¶ms);\n-\tif (rc)\n-\t\tgoto error;\n-\tleaf_parent = def + 2;\n-\n-\t/* Add per queue SMQ nodes */\n-\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n-\t\trc = nix_tm_node_add_to_list(dev, leaf_parent + 1 + i,\n-\t\t\t\t\t leaf_parent,\n-\t\t\t\t\t 0, DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t NIX_TXSCH_LVL_SMQ,\n-\t\t\t\t\t OTX2_TM_LVL_SCH3,\n-\t\t\t\t\t false, ¶ms);\n-\t\tif (rc)\n-\t\t\tgoto error;\n-\t}\n-\n-\t/* Add leaf nodes */\n-\tfor (i = 0; i < eth_dev->data->nb_tx_queues; i++) {\n-\t\trc = nix_tm_node_add_to_list(dev, i, leaf_parent + 1 + i, 0,\n-\t\t\t\t\t DEFAULT_RR_WEIGHT,\n-\t\t\t\t\t NIX_TXSCH_LVL_CNT,\n-\t\t\t\t\t OTX2_TM_LVL_SCH4,\n-\t\t\t\t\t false, ¶ms);\n-\t\tif (rc)\n-\t\t\tbreak;\n-\t}\n-error:\n-\treturn rc;\n-}\n-\n-static int\n-otx2_nix_tm_rate_limit_mdq(struct rte_eth_dev *eth_dev,\n-\t\t\t struct otx2_nix_tm_node *tm_node,\n-\t\t\t uint64_t tx_rate)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_nix_tm_shaper_profile profile;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tvolatile uint64_t *reg, *regval;\n-\tstruct nix_txschq_config *req;\n-\tuint16_t flags;\n-\tuint8_t k = 0;\n-\tint rc;\n-\n-\tflags = tm_node->flags;\n-\n-\treq = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox);\n-\treq->lvl = NIX_TXSCH_LVL_MDQ;\n-\treg = req->reg;\n-\tregval = req->regval;\n-\n-\tif (tx_rate == 0) {\n-\t\tk += prepare_tm_sw_xoff(tm_node, true, ®[k], ®val[k]);\n-\t\tflags &= ~NIX_TM_NODE_ENABLED;\n-\t\tgoto exit;\n-\t}\n-\n-\tif (!(flags & NIX_TM_NODE_ENABLED)) {\n-\t\tk += prepare_tm_sw_xoff(tm_node, false, ®[k], ®val[k]);\n-\t\tflags |= NIX_TM_NODE_ENABLED;\n-\t}\n-\n-\t/* Use only PIR for rate limit */\n-\tmemset(&profile, 0, sizeof(profile));\n-\tprofile.params.peak.rate = tx_rate;\n-\t/* Minimum burst of ~4us Bytes of Tx */\n-\tprofile.params.peak.size = RTE_MAX(NIX_MAX_HW_FRS,\n-\t\t\t\t\t (4ull * tx_rate) / (1E6 * 8));\n-\tif (!dev->tm_rate_min || dev->tm_rate_min > tx_rate)\n-\t\tdev->tm_rate_min = tx_rate;\n-\n-\tk += prepare_tm_shaper_reg(tm_node, &profile, ®[k], ®val[k]);\n-exit:\n-\treq->num_regs = k;\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\ttm_node->flags = flags;\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,\n-\t\t\t\tuint16_t queue_idx, uint16_t tx_rate_mbps)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint64_t tx_rate = tx_rate_mbps * (uint64_t)1E6;\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tint rc;\n-\n-\t/* Check for supported revisions */\n-\tif (otx2_dev_is_95xx_Ax(dev) ||\n-\t otx2_dev_is_96xx_Ax(dev))\n-\t\treturn -EINVAL;\n-\n-\tif (queue_idx >= eth_dev->data->nb_tx_queues)\n-\t\treturn -EINVAL;\n-\n-\tif (!(dev->tm_flags & NIX_TM_DEFAULT_TREE) &&\n-\t !(dev->tm_flags & NIX_TM_RATE_LIMIT_TREE))\n-\t\tgoto error;\n-\n-\tif ((dev->tm_flags & NIX_TM_DEFAULT_TREE) &&\n-\t eth_dev->data->nb_tx_queues > 1) {\n-\t\t/* For TM topology change ethdev needs to be stopped */\n-\t\tif (eth_dev->data->dev_started)\n-\t\t\treturn -EBUSY;\n-\n-\t\t/*\n-\t\t * Disable xmit will be enabled when\n-\t\t * new topology is available.\n-\t\t */\n-\t\trc = nix_xmit_disable(eth_dev);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"failed to disable TX, rc=%d\", rc);\n-\t\t\treturn -EIO;\n-\t\t}\n-\n-\t\trc = nix_tm_free_resources(dev, 0, 0, false);\n-\t\tif (rc < 0) {\n-\t\t\totx2_tm_dbg(\"failed to free default resources, rc %d\",\n-\t\t\t\t rc);\n-\t\t\treturn -EIO;\n-\t\t}\n-\n-\t\trc = nix_tm_prepare_rate_limited_tree(eth_dev);\n-\t\tif (rc < 0) {\n-\t\t\totx2_tm_dbg(\"failed to prepare tm tree, rc=%d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\n-\t\trc = nix_tm_alloc_resources(eth_dev, true);\n-\t\tif (rc != 0) {\n-\t\t\totx2_tm_dbg(\"failed to allocate tm tree, rc=%d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\n-\t\tdev->tm_flags &= ~NIX_TM_DEFAULT_TREE;\n-\t\tdev->tm_flags |= NIX_TM_RATE_LIMIT_TREE;\n-\t}\n-\n-\ttm_node = nix_tm_node_search(dev, queue_idx, false);\n-\n-\t/* check if we found a valid leaf node */\n-\tif (!tm_node ||\n-\t !nix_tm_is_leaf(dev, tm_node->lvl) ||\n-\t !tm_node->parent ||\n-\t tm_node->parent->hw_id == UINT32_MAX)\n-\t\treturn -EIO;\n-\n-\treturn otx2_nix_tm_rate_limit_mdq(eth_dev, tm_node->parent, tx_rate);\n-error:\n-\totx2_tm_dbg(\"Unsupported TM tree 0x%0x\", dev->tm_flags);\n-\treturn -EINVAL;\n-}\n-\n-int\n-otx2_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *arg)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tif (!arg)\n-\t\treturn -EINVAL;\n-\n-\t/* Check for supported revisions */\n-\tif (otx2_dev_is_95xx_Ax(dev) ||\n-\t otx2_dev_is_96xx_Ax(dev))\n-\t\treturn -EINVAL;\n-\n-\t*(const void **)arg = &otx2_tm_ops;\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_tm_fini(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint rc;\n-\n-\t/* Xmit is assumed to be disabled */\n-\t/* Free up resources already held */\n-\trc = nix_tm_free_resources(dev, 0, 0, false);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to freeup existing resources,rc=%d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\t/* Clear shaper profiles */\n-\tnix_tm_clear_shaper_profiles(dev);\n-\n-\tdev->tm_flags = 0;\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,\n-\t\t\t uint32_t *rr_quantum, uint16_t *smq)\n-{\n-\tstruct otx2_nix_tm_node *tm_node;\n-\tint rc;\n-\n-\t/* 0..sq_cnt-1 are leaf nodes */\n-\tif (sq >= dev->tm_leaf_cnt)\n-\t\treturn -EINVAL;\n-\n-\t/* Search for internal node first */\n-\ttm_node = nix_tm_node_search(dev, sq, false);\n-\tif (!tm_node)\n-\t\ttm_node = nix_tm_node_search(dev, sq, true);\n-\n-\t/* Check if we found a valid leaf node */\n-\tif (!tm_node || !nix_tm_is_leaf(dev, tm_node->lvl) ||\n-\t !tm_node->parent || tm_node->parent->hw_id == UINT32_MAX) {\n-\t\treturn -EIO;\n-\t}\n-\n-\t/* Get SMQ Id of leaf node's parent */\n-\t*smq = tm_node->parent->hw_id;\n-\t*rr_quantum = NIX_TM_WEIGHT_TO_RR_QUANTUM(tm_node->weight);\n-\n-\trc = nix_smq_xoff(dev, tm_node->parent, false);\n-\tif (rc)\n-\t\treturn rc;\n-\ttm_node->flags |= NIX_TM_NODE_ENABLED;\n-\n-\treturn 0;\n-}\ndiff --git a/drivers/net/octeontx2/otx2_tm.h b/drivers/net/octeontx2/otx2_tm.h\ndeleted file mode 100644\nindex db44d4891f..0000000000\n--- a/drivers/net/octeontx2/otx2_tm.h\n+++ /dev/null\n@@ -1,176 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_TM_H__\n-#define __OTX2_TM_H__\n-\n-#include <stdbool.h>\n-\n-#include <rte_tm_driver.h>\n-\n-#define NIX_TM_DEFAULT_TREE\tBIT_ULL(0)\n-#define NIX_TM_COMMITTED\tBIT_ULL(1)\n-#define NIX_TM_RATE_LIMIT_TREE\tBIT_ULL(2)\n-#define NIX_TM_TL1_NO_SP\tBIT_ULL(3)\n-\n-struct otx2_eth_dev;\n-\n-void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev);\n-int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev);\n-int otx2_nix_tm_fini(struct rte_eth_dev *eth_dev);\n-int otx2_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);\n-int otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,\n-\t\t\t uint32_t *rr_quantum, uint16_t *smq);\n-int otx2_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,\n-\t\t\t\t uint16_t queue_idx, uint16_t tx_rate);\n-int otx2_nix_sq_flush_pre(void *_txq, bool dev_started);\n-int otx2_nix_sq_flush_post(void *_txq);\n-int otx2_nix_sq_enable(void *_txq);\n-int otx2_nix_get_link(struct otx2_eth_dev *dev);\n-int otx2_nix_sq_sqb_aura_fc(void *_txq, bool enable);\n-\n-struct otx2_nix_tm_node {\n-\tTAILQ_ENTRY(otx2_nix_tm_node) node;\n-\tuint32_t id;\n-\tuint32_t hw_id;\n-\tuint32_t priority;\n-\tuint32_t weight;\n-\tuint16_t lvl;\n-\tuint16_t hw_lvl;\n-\tuint32_t rr_prio;\n-\tuint32_t rr_num;\n-\tuint32_t max_prio;\n-\tuint32_t parent_hw_id;\n-\tuint32_t flags:16;\n-#define NIX_TM_NODE_HWRES\tBIT_ULL(0)\n-#define NIX_TM_NODE_ENABLED\tBIT_ULL(1)\n-#define NIX_TM_NODE_USER\tBIT_ULL(2)\n-#define NIX_TM_NODE_RED_DISCARD BIT_ULL(3)\n-\t/* Shaper algorithm for RED state @NIX_REDALG_E */\n-\tuint32_t red_algo:2;\n-\tuint32_t pkt_mode:1;\n-\n-\tstruct otx2_nix_tm_node *parent;\n-\tstruct rte_tm_node_params params;\n-\n-\t/* Last stats */\n-\tuint64_t last_pkts;\n-\tuint64_t last_bytes;\n-};\n-\n-struct otx2_nix_tm_shaper_profile {\n-\tTAILQ_ENTRY(otx2_nix_tm_shaper_profile) shaper;\n-\tuint32_t shaper_profile_id;\n-\tuint32_t reference_count;\n-\tstruct rte_tm_shaper_params params; /* Rate in bits/sec */\n-};\n-\n-struct shaper_params {\n-\tuint64_t burst_exponent;\n-\tuint64_t burst_mantissa;\n-\tuint64_t div_exp;\n-\tuint64_t exponent;\n-\tuint64_t mantissa;\n-\tuint64_t burst;\n-\tuint64_t rate;\n-};\n-\n-TAILQ_HEAD(otx2_nix_tm_node_list, otx2_nix_tm_node);\n-TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);\n-\n-#define MAX_SCHED_WEIGHT ((uint8_t)~0)\n-#define NIX_TM_RR_QUANTUM_MAX (BIT_ULL(24) - 1)\n-#define NIX_TM_WEIGHT_TO_RR_QUANTUM(__weight)\t\t\t\\\n-\t\t((((__weight) & MAX_SCHED_WEIGHT) * \\\n-\t\t NIX_TM_RR_QUANTUM_MAX) / MAX_SCHED_WEIGHT)\n-\n-/* DEFAULT_RR_WEIGHT * NIX_TM_RR_QUANTUM_MAX / MAX_SCHED_WEIGHT */\n-/* = NIX_MAX_HW_MTU */\n-#define DEFAULT_RR_WEIGHT 71\n-\n-/** NIX rate limits */\n-#define MAX_RATE_DIV_EXP 12\n-#define MAX_RATE_EXPONENT 0xf\n-#define MAX_RATE_MANTISSA 0xff\n-\n-#define NIX_SHAPER_RATE_CONST ((uint64_t)2E6)\n-\n-/* NIX rate calculation in Bits/Sec\n- *\tPIR_ADD = ((256 + NIX_*_PIR[RATE_MANTISSA])\n- *\t\t<< NIX_*_PIR[RATE_EXPONENT]) / 256\n- *\tPIR = (2E6 * PIR_ADD / (1 << NIX_*_PIR[RATE_DIVIDER_EXPONENT]))\n- *\n- *\tCIR_ADD = ((256 + NIX_*_CIR[RATE_MANTISSA])\n- *\t\t<< NIX_*_CIR[RATE_EXPONENT]) / 256\n- *\tCIR = (2E6 * CIR_ADD / (CCLK_TICKS << NIX_*_CIR[RATE_DIVIDER_EXPONENT]))\n- */\n-#define SHAPER_RATE(exponent, mantissa, div_exp) \\\n-\t((NIX_SHAPER_RATE_CONST * ((256 + (mantissa)) << (exponent)))\\\n-\t\t/ (((1ull << (div_exp)) * 256)))\n-\n-/* 96xx rate limits in Bits/Sec */\n-#define MIN_SHAPER_RATE \\\n-\tSHAPER_RATE(0, 0, MAX_RATE_DIV_EXP)\n-\n-#define MAX_SHAPER_RATE \\\n-\tSHAPER_RATE(MAX_RATE_EXPONENT, MAX_RATE_MANTISSA, 0)\n-\n-/* Min is limited so that NIX_AF_SMQX_CFG[MINLEN]+ADJUST is not -ve */\n-#define NIX_LENGTH_ADJUST_MIN ((int)-NIX_MIN_HW_FRS + 1)\n-#define NIX_LENGTH_ADJUST_MAX 255\n-\n-/** TM Shaper - low level operations */\n-\n-/** NIX burst limits */\n-#define MAX_BURST_EXPONENT 0xf\n-#define MAX_BURST_MANTISSA 0xff\n-\n-/* NIX burst calculation\n- *\tPIR_BURST = ((256 + NIX_*_PIR[BURST_MANTISSA])\n- *\t\t<< (NIX_*_PIR[BURST_EXPONENT] + 1))\n- *\t\t\t/ 256\n- *\n- *\tCIR_BURST = ((256 + NIX_*_CIR[BURST_MANTISSA])\n- *\t\t<< (NIX_*_CIR[BURST_EXPONENT] + 1))\n- *\t\t\t/ 256\n- */\n-#define SHAPER_BURST(exponent, mantissa) \\\n-\t(((256 + (mantissa)) << ((exponent) + 1)) / 256)\n-\n-/** Shaper burst limits */\n-#define MIN_SHAPER_BURST \\\n-\tSHAPER_BURST(0, 0)\n-\n-#define MAX_SHAPER_BURST \\\n-\tSHAPER_BURST(MAX_BURST_EXPONENT,\\\n-\t\tMAX_BURST_MANTISSA)\n-\n-/* Default TL1 priority and Quantum from AF */\n-#define TXSCH_TL1_DFLT_RR_QTM ((1 << 24) - 1)\n-#define TXSCH_TL1_DFLT_RR_PRIO 1\n-\n-#define TXSCH_TLX_SP_PRIO_MAX 10\n-\n-static inline const char *\n-nix_hwlvl2str(uint32_t hw_lvl)\n-{\n-\tswitch (hw_lvl) {\n-\tcase NIX_TXSCH_LVL_MDQ:\n-\t\treturn \"SMQ/MDQ\";\n-\tcase NIX_TXSCH_LVL_TL4:\n-\t\treturn \"TL4\";\n-\tcase NIX_TXSCH_LVL_TL3:\n-\t\treturn \"TL3\";\n-\tcase NIX_TXSCH_LVL_TL2:\n-\t\treturn \"TL2\";\n-\tcase NIX_TXSCH_LVL_TL1:\n-\t\treturn \"TL1\";\n-\tdefault:\n-\t\tbreak;\n-\t}\n-\n-\treturn \"???\";\n-}\n-\n-#endif /* __OTX2_TM_H__ */\ndiff --git a/drivers/net/octeontx2/otx2_tx.c b/drivers/net/octeontx2/otx2_tx.c\ndeleted file mode 100644\nindex e95184632f..0000000000\n--- a/drivers/net/octeontx2/otx2_tx.c\n+++ /dev/null\n@@ -1,1077 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_vect.h>\n-\n-#include \"otx2_ethdev.h\"\n-\n-#define NIX_XMIT_FC_OR_RETURN(txq, pkts) do {\t\t\t\t\\\n-\t/* Cached value is low, Update the fc_cache_pkts */\t\t\\\n-\tif (unlikely((txq)->fc_cache_pkts < (pkts))) {\t\t\t\\\n-\t\t/* Multiply with sqe_per_sqb to express in pkts */\t\\\n-\t\t(txq)->fc_cache_pkts =\t\t\t\t\t\\\n-\t\t\t((txq)->nb_sqb_bufs_adj - *(txq)->fc_mem) << \\\n-\t\t\t\t(txq)->sqes_per_sqb_log2;\t\t\\\n-\t\t/* Check it again for the room */\t\t\t\\\n-\t\tif (unlikely((txq)->fc_cache_pkts < (pkts)))\t\t\\\n-\t\t\treturn 0;\t\t\t\t\t\\\n-\t}\t\t\t\t\t\t\t\t\\\n-} while (0)\n-\n-\n-static __rte_always_inline uint16_t\n-nix_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t uint16_t pkts, uint64_t *cmd, const uint16_t flags)\n-{\n-\tstruct otx2_eth_txq *txq = tx_queue; uint16_t i;\n-\tconst rte_iova_t io_addr = txq->io_addr;\n-\tvoid *lmt_addr = txq->lmt_addr;\n-\tuint64_t lso_tun_fmt;\n-\n-\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n-\n-\totx2_lmt_mov(cmd, &txq->cmd[0], otx2_nix_tx_ext_subs(flags));\n-\n-\t/* Perform header writes before barrier for TSO */\n-\tif (flags & NIX_TX_OFFLOAD_TSO_F) {\n-\t\tlso_tun_fmt = txq->lso_tun_fmt;\n-\t\tfor (i = 0; i < pkts; i++)\n-\t\t\totx2_nix_xmit_prepare_tso(tx_pkts[i], flags);\n-\t}\n-\n-\t/* Lets commit any changes in the packet here as no further changes\n-\t * to the packet will be done unless no fast free is enabled.\n-\t */\n-\tif (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))\n-\t\trte_io_wmb();\n-\n-\tfor (i = 0; i < pkts; i++) {\n-\t\totx2_nix_xmit_prepare(tx_pkts[i], cmd, flags, lso_tun_fmt);\n-\t\t/* Passing no of segdw as 4: HDR + EXT + SG + SMEM */\n-\t\totx2_nix_xmit_prepare_tstamp(cmd, &txq->cmd[0],\n-\t\t\t\t\t tx_pkts[i]->ol_flags, 4, flags);\n-\t\totx2_nix_xmit_one(cmd, lmt_addr, io_addr, flags);\n-\t}\n-\n-\t/* Reduce the cached count */\n-\ttxq->fc_cache_pkts -= pkts;\n-\n-\treturn pkts;\n-}\n-\n-static __rte_always_inline uint16_t\n-nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t uint16_t pkts, uint64_t *cmd, const uint16_t flags)\n-{\n-\tstruct otx2_eth_txq *txq = tx_queue; uint64_t i;\n-\tconst rte_iova_t io_addr = txq->io_addr;\n-\tvoid *lmt_addr = txq->lmt_addr;\n-\tuint64_t lso_tun_fmt;\n-\tuint16_t segdw;\n-\n-\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n-\n-\totx2_lmt_mov(cmd, &txq->cmd[0], otx2_nix_tx_ext_subs(flags));\n-\n-\t/* Perform header writes before barrier for TSO */\n-\tif (flags & NIX_TX_OFFLOAD_TSO_F) {\n-\t\tlso_tun_fmt = txq->lso_tun_fmt;\n-\t\tfor (i = 0; i < pkts; i++)\n-\t\t\totx2_nix_xmit_prepare_tso(tx_pkts[i], flags);\n-\t}\n-\n-\t/* Lets commit any changes in the packet here as no further changes\n-\t * to the packet will be done unless no fast free is enabled.\n-\t */\n-\tif (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))\n-\t\trte_io_wmb();\n-\n-\tfor (i = 0; i < pkts; i++) {\n-\t\totx2_nix_xmit_prepare(tx_pkts[i], cmd, flags, lso_tun_fmt);\n-\t\tsegdw = otx2_nix_prepare_mseg(tx_pkts[i], cmd, flags);\n-\t\totx2_nix_xmit_prepare_tstamp(cmd, &txq->cmd[0],\n-\t\t\t\t\t tx_pkts[i]->ol_flags, segdw,\n-\t\t\t\t\t flags);\n-\t\totx2_nix_xmit_mseg_one(cmd, lmt_addr, io_addr, segdw);\n-\t}\n-\n-\t/* Reduce the cached count */\n-\ttxq->fc_cache_pkts -= pkts;\n-\n-\treturn pkts;\n-}\n-\n-#if defined(RTE_ARCH_ARM64)\n-\n-#define NIX_DESCS_PER_LOOP\t4\n-static __rte_always_inline uint16_t\n-nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t uint16_t pkts, uint64_t *cmd, const uint16_t flags)\n-{\n-\tuint64x2_t dataoff_iova0, dataoff_iova1, dataoff_iova2, dataoff_iova3;\n-\tuint64x2_t len_olflags0, len_olflags1, len_olflags2, len_olflags3;\n-\tuint64_t *mbuf0, *mbuf1, *mbuf2, *mbuf3;\n-\tuint64x2_t senddesc01_w0, senddesc23_w0;\n-\tuint64x2_t senddesc01_w1, senddesc23_w1;\n-\tuint64x2_t sgdesc01_w0, sgdesc23_w0;\n-\tuint64x2_t sgdesc01_w1, sgdesc23_w1;\n-\tstruct otx2_eth_txq *txq = tx_queue;\n-\tuint64_t *lmt_addr = txq->lmt_addr;\n-\trte_iova_t io_addr = txq->io_addr;\n-\tuint64x2_t ltypes01, ltypes23;\n-\tuint64x2_t xtmp128, ytmp128;\n-\tuint64x2_t xmask01, xmask23;\n-\tuint64x2_t cmd00, cmd01;\n-\tuint64x2_t cmd10, cmd11;\n-\tuint64x2_t cmd20, cmd21;\n-\tuint64x2_t cmd30, cmd31;\n-\tuint64_t lmt_status, i;\n-\tuint16_t pkts_left;\n-\n-\tNIX_XMIT_FC_OR_RETURN(txq, pkts);\n-\n-\tpkts_left = pkts & (NIX_DESCS_PER_LOOP - 1);\n-\tpkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);\n-\n-\t/* Reduce the cached count */\n-\ttxq->fc_cache_pkts -= pkts;\n-\n-\t/* Lets commit any changes in the packet here as no further changes\n-\t * to the packet will be done unless no fast free is enabled.\n-\t */\n-\tif (!(flags & NIX_TX_OFFLOAD_MBUF_NOFF_F))\n-\t\trte_io_wmb();\n-\n-\tsenddesc01_w0 = vld1q_dup_u64(&txq->cmd[0]);\n-\tsenddesc23_w0 = senddesc01_w0;\n-\tsenddesc01_w1 = vdupq_n_u64(0);\n-\tsenddesc23_w1 = senddesc01_w1;\n-\tsgdesc01_w0 = vld1q_dup_u64(&txq->cmd[2]);\n-\tsgdesc23_w0 = sgdesc01_w0;\n-\n-\tfor (i = 0; i < pkts; i += NIX_DESCS_PER_LOOP) {\n-\t\t/* Clear lower 32bit of SEND_HDR_W0 and SEND_SG_W0 */\n-\t\tsenddesc01_w0 = vbicq_u64(senddesc01_w0,\n-\t\t\t\t\t vdupq_n_u64(0xFFFFFFFF));\n-\t\tsgdesc01_w0 = vbicq_u64(sgdesc01_w0,\n-\t\t\t\t\tvdupq_n_u64(0xFFFFFFFF));\n-\n-\t\tsenddesc23_w0 = senddesc01_w0;\n-\t\tsgdesc23_w0 = sgdesc01_w0;\n-\n-\t\t/* Move mbufs to iova */\n-\t\tmbuf0 = (uint64_t *)tx_pkts[0];\n-\t\tmbuf1 = (uint64_t *)tx_pkts[1];\n-\t\tmbuf2 = (uint64_t *)tx_pkts[2];\n-\t\tmbuf3 = (uint64_t *)tx_pkts[3];\n-\n-\t\tmbuf0 = (uint64_t *)((uintptr_t)mbuf0 +\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf1 = (uint64_t *)((uintptr_t)mbuf1 +\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf2 = (uint64_t *)((uintptr_t)mbuf2 +\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf3 = (uint64_t *)((uintptr_t)mbuf3 +\n-\t\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\t/*\n-\t\t * Get mbuf's, olflags, iova, pktlen, dataoff\n-\t\t * dataoff_iovaX.D[0] = iova,\n-\t\t * dataoff_iovaX.D[1](15:0) = mbuf->dataoff\n-\t\t * len_olflagsX.D[0] = ol_flags,\n-\t\t * len_olflagsX.D[1](63:32) = mbuf->pkt_len\n-\t\t */\n-\t\tdataoff_iova0 = vld1q_u64(mbuf0);\n-\t\tlen_olflags0 = vld1q_u64(mbuf0 + 2);\n-\t\tdataoff_iova1 = vld1q_u64(mbuf1);\n-\t\tlen_olflags1 = vld1q_u64(mbuf1 + 2);\n-\t\tdataoff_iova2 = vld1q_u64(mbuf2);\n-\t\tlen_olflags2 = vld1q_u64(mbuf2 + 2);\n-\t\tdataoff_iova3 = vld1q_u64(mbuf3);\n-\t\tlen_olflags3 = vld1q_u64(mbuf3 + 2);\n-\n-\t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n-\t\t\tstruct rte_mbuf *mbuf;\n-\t\t\t/* Set don't free bit if reference count > 1 */\n-\t\t\txmask01 = vdupq_n_u64(0);\n-\t\t\txmask23 = xmask01;\n-\n-\t\t\tmbuf = (struct rte_mbuf *)((uintptr_t)mbuf0 -\n-\t\t\t\toffsetof(struct rte_mbuf, buf_iova));\n-\n-\t\t\tif (otx2_nix_prefree_seg(mbuf))\n-\t\t\t\tvsetq_lane_u64(0x80000, xmask01, 0);\n-\t\t\telse\n-\t\t\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool,\n-\t\t\t\t\t\t\t(void **)&mbuf,\n-\t\t\t\t\t\t\t1, 0);\n-\n-\t\t\tmbuf = (struct rte_mbuf *)((uintptr_t)mbuf1 -\n-\t\t\t\toffsetof(struct rte_mbuf, buf_iova));\n-\t\t\tif (otx2_nix_prefree_seg(mbuf))\n-\t\t\t\tvsetq_lane_u64(0x80000, xmask01, 1);\n-\t\t\telse\n-\t\t\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool,\n-\t\t\t\t\t\t\t(void **)&mbuf,\n-\t\t\t\t\t\t\t1, 0);\n-\n-\t\t\tmbuf = (struct rte_mbuf *)((uintptr_t)mbuf2 -\n-\t\t\t\toffsetof(struct rte_mbuf, buf_iova));\n-\t\t\tif (otx2_nix_prefree_seg(mbuf))\n-\t\t\t\tvsetq_lane_u64(0x80000, xmask23, 0);\n-\t\t\telse\n-\t\t\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool,\n-\t\t\t\t\t\t\t(void **)&mbuf,\n-\t\t\t\t\t\t\t1, 0);\n-\n-\t\t\tmbuf = (struct rte_mbuf *)((uintptr_t)mbuf3 -\n-\t\t\t\toffsetof(struct rte_mbuf, buf_iova));\n-\t\t\tif (otx2_nix_prefree_seg(mbuf))\n-\t\t\t\tvsetq_lane_u64(0x80000, xmask23, 1);\n-\t\t\telse\n-\t\t\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool,\n-\t\t\t\t\t\t\t(void **)&mbuf,\n-\t\t\t\t\t\t\t1, 0);\n-\t\t\tsenddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);\n-\t\t\tsenddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);\n-\t\t\t/* Ensuring mbuf fields which got updated in\n-\t\t\t * otx2_nix_prefree_seg are written before LMTST.\n-\t\t\t */\n-\t\t\trte_io_wmb();\n-\t\t} else {\n-\t\t\tstruct rte_mbuf *mbuf;\n-\t\t\t/* Mark mempool object as \"put\" since\n-\t\t\t * it is freed by NIX\n-\t\t\t */\n-\t\t\tmbuf = (struct rte_mbuf *)((uintptr_t)mbuf0 -\n-\t\t\t\toffsetof(struct rte_mbuf, buf_iova));\n-\t\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf,\n-\t\t\t\t\t\t1, 0);\n-\n-\t\t\tmbuf = (struct rte_mbuf *)((uintptr_t)mbuf1 -\n-\t\t\t\toffsetof(struct rte_mbuf, buf_iova));\n-\t\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf,\n-\t\t\t\t\t\t1, 0);\n-\n-\t\t\tmbuf = (struct rte_mbuf *)((uintptr_t)mbuf2 -\n-\t\t\t\toffsetof(struct rte_mbuf, buf_iova));\n-\t\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf,\n-\t\t\t\t\t\t1, 0);\n-\n-\t\t\tmbuf = (struct rte_mbuf *)((uintptr_t)mbuf3 -\n-\t\t\t\toffsetof(struct rte_mbuf, buf_iova));\n-\t\t\tRTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf,\n-\t\t\t\t\t\t1, 0);\n-\t\t\tRTE_SET_USED(mbuf);\n-\t\t}\n-\n-\t\t/* Move mbufs to point pool */\n-\t\tmbuf0 = (uint64_t *)((uintptr_t)mbuf0 +\n-\t\t\t offsetof(struct rte_mbuf, pool) -\n-\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf1 = (uint64_t *)((uintptr_t)mbuf1 +\n-\t\t\t offsetof(struct rte_mbuf, pool) -\n-\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf2 = (uint64_t *)((uintptr_t)mbuf2 +\n-\t\t\t offsetof(struct rte_mbuf, pool) -\n-\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\t\tmbuf3 = (uint64_t *)((uintptr_t)mbuf3 +\n-\t\t\t offsetof(struct rte_mbuf, pool) -\n-\t\t\t offsetof(struct rte_mbuf, buf_iova));\n-\n-\t\tif (flags &\n-\t\t (NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |\n-\t\t NIX_TX_OFFLOAD_L3_L4_CSUM_F)) {\n-\t\t\t/* Get tx_offload for ol2, ol3, l2, l3 lengths */\n-\t\t\t/*\n-\t\t\t * E(8):OL2_LEN(7):OL3_LEN(9):E(24):L3_LEN(9):L2_LEN(7)\n-\t\t\t * E(8):OL2_LEN(7):OL3_LEN(9):E(24):L3_LEN(9):L2_LEN(7)\n-\t\t\t */\n-\n-\t\t\tasm volatile (\"LD1 {%[a].D}[0],[%[in]]\\n\\t\" :\n-\t\t\t\t [a]\"+w\"(senddesc01_w1) :\n-\t\t\t\t [in]\"r\"(mbuf0 + 2) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[a].D}[1],[%[in]]\\n\\t\" :\n-\t\t\t\t [a]\"+w\"(senddesc01_w1) :\n-\t\t\t\t [in]\"r\"(mbuf1 + 2) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[b].D}[0],[%[in]]\\n\\t\" :\n-\t\t\t\t [b]\"+w\"(senddesc23_w1) :\n-\t\t\t\t [in]\"r\"(mbuf2 + 2) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[b].D}[1],[%[in]]\\n\\t\" :\n-\t\t\t\t [b]\"+w\"(senddesc23_w1) :\n-\t\t\t\t [in]\"r\"(mbuf3 + 2) : \"memory\");\n-\n-\t\t\t/* Get pool pointer alone */\n-\t\t\tmbuf0 = (uint64_t *)*mbuf0;\n-\t\t\tmbuf1 = (uint64_t *)*mbuf1;\n-\t\t\tmbuf2 = (uint64_t *)*mbuf2;\n-\t\t\tmbuf3 = (uint64_t *)*mbuf3;\n-\t\t} else {\n-\t\t\t/* Get pool pointer alone */\n-\t\t\tmbuf0 = (uint64_t *)*mbuf0;\n-\t\t\tmbuf1 = (uint64_t *)*mbuf1;\n-\t\t\tmbuf2 = (uint64_t *)*mbuf2;\n-\t\t\tmbuf3 = (uint64_t *)*mbuf3;\n-\t\t}\n-\n-\t\tconst uint8x16_t shuf_mask2 = {\n-\t\t\t0x4, 0x5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n-\t\t\t0xc, 0xd, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n-\t\t};\n-\t\txtmp128 = vzip2q_u64(len_olflags0, len_olflags1);\n-\t\tytmp128 = vzip2q_u64(len_olflags2, len_olflags3);\n-\n-\t\t/* Clear dataoff_iovaX.D[1] bits other than dataoff(15:0) */\n-\t\tconst uint64x2_t and_mask0 = {\n-\t\t\t0xFFFFFFFFFFFFFFFF,\n-\t\t\t0x000000000000FFFF,\n-\t\t};\n-\n-\t\tdataoff_iova0 = vandq_u64(dataoff_iova0, and_mask0);\n-\t\tdataoff_iova1 = vandq_u64(dataoff_iova1, and_mask0);\n-\t\tdataoff_iova2 = vandq_u64(dataoff_iova2, and_mask0);\n-\t\tdataoff_iova3 = vandq_u64(dataoff_iova3, and_mask0);\n-\n-\t\t/*\n-\t\t * Pick only 16 bits of pktlen preset at bits 63:32\n-\t\t * and place them at bits 15:0.\n-\t\t */\n-\t\txtmp128 = vqtbl1q_u8(xtmp128, shuf_mask2);\n-\t\tytmp128 = vqtbl1q_u8(ytmp128, shuf_mask2);\n-\n-\t\t/* Add pairwise to get dataoff + iova in sgdesc_w1 */\n-\t\tsgdesc01_w1 = vpaddq_u64(dataoff_iova0, dataoff_iova1);\n-\t\tsgdesc23_w1 = vpaddq_u64(dataoff_iova2, dataoff_iova3);\n-\n-\t\t/* Orr both sgdesc_w0 and senddesc_w0 with 16 bits of\n-\t\t * pktlen at 15:0 position.\n-\t\t */\n-\t\tsgdesc01_w0 = vorrq_u64(sgdesc01_w0, xtmp128);\n-\t\tsgdesc23_w0 = vorrq_u64(sgdesc23_w0, ytmp128);\n-\t\tsenddesc01_w0 = vorrq_u64(senddesc01_w0, xtmp128);\n-\t\tsenddesc23_w0 = vorrq_u64(senddesc23_w0, ytmp128);\n-\n-\t\tif ((flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F) &&\n-\t\t !(flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)) {\n-\t\t\t/*\n-\t\t\t * Lookup table to translate ol_flags to\n-\t\t\t * il3/il4 types. But we still use ol3/ol4 types in\n-\t\t\t * senddesc_w1 as only one header processing is enabled.\n-\t\t\t */\n-\t\t\tconst uint8x16_t tbl = {\n-\t\t\t\t/* [0-15] = il4type:il3type */\n-\t\t\t\t0x04, /* none (IPv6 assumed) */\n-\t\t\t\t0x14, /* RTE_MBUF_F_TX_TCP_CKSUM (IPv6 assumed) */\n-\t\t\t\t0x24, /* RTE_MBUF_F_TX_SCTP_CKSUM (IPv6 assumed) */\n-\t\t\t\t0x34, /* RTE_MBUF_F_TX_UDP_CKSUM (IPv6 assumed) */\n-\t\t\t\t0x03, /* RTE_MBUF_F_TX_IP_CKSUM */\n-\t\t\t\t0x13, /* RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_TCP_CKSUM */\n-\t\t\t\t0x23, /* RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_SCTP_CKSUM */\n-\t\t\t\t0x33, /* RTE_MBUF_F_TX_IP_CKSUM | RTE_MBUF_F_TX_UDP_CKSUM */\n-\t\t\t\t0x02, /* RTE_MBUF_F_TX_IPV4 */\n-\t\t\t\t0x12, /* RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_TCP_CKSUM */\n-\t\t\t\t0x22, /* RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_SCTP_CKSUM */\n-\t\t\t\t0x32, /* RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_UDP_CKSUM */\n-\t\t\t\t0x03, /* RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IP_CKSUM */\n-\t\t\t\t0x13, /* RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IP_CKSUM |\n-\t\t\t\t * RTE_MBUF_F_TX_TCP_CKSUM\n-\t\t\t\t */\n-\t\t\t\t0x23, /* RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IP_CKSUM |\n-\t\t\t\t * RTE_MBUF_F_TX_SCTP_CKSUM\n-\t\t\t\t */\n-\t\t\t\t0x33, /* RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IP_CKSUM |\n-\t\t\t\t * RTE_MBUF_F_TX_UDP_CKSUM\n-\t\t\t\t */\n-\t\t\t};\n-\n-\t\t\t/* Extract olflags to translate to iltypes */\n-\t\t\txtmp128 = vzip1q_u64(len_olflags0, len_olflags1);\n-\t\t\tytmp128 = vzip1q_u64(len_olflags2, len_olflags3);\n-\n-\t\t\t/*\n-\t\t\t * E(47):L3_LEN(9):L2_LEN(7+z)\n-\t\t\t * E(47):L3_LEN(9):L2_LEN(7+z)\n-\t\t\t */\n-\t\t\tsenddesc01_w1 = vshlq_n_u64(senddesc01_w1, 1);\n-\t\t\tsenddesc23_w1 = vshlq_n_u64(senddesc23_w1, 1);\n-\n-\t\t\t/* Move OLFLAGS bits 55:52 to 51:48\n-\t\t\t * with zeros preprended on the byte and rest\n-\t\t\t * don't care\n-\t\t\t */\n-\t\t\txtmp128 = vshrq_n_u8(xtmp128, 4);\n-\t\t\tytmp128 = vshrq_n_u8(ytmp128, 4);\n-\t\t\t/*\n-\t\t\t * E(48):L3_LEN(8):L2_LEN(z+7)\n-\t\t\t * E(48):L3_LEN(8):L2_LEN(z+7)\n-\t\t\t */\n-\t\t\tconst int8x16_t tshft3 = {\n-\t\t\t\t-1, 0, 8, 8, 8,\t8, 8, 8,\n-\t\t\t\t-1, 0, 8, 8, 8,\t8, 8, 8,\n-\t\t\t};\n-\n-\t\t\tsenddesc01_w1 = vshlq_u8(senddesc01_w1, tshft3);\n-\t\t\tsenddesc23_w1 = vshlq_u8(senddesc23_w1, tshft3);\n-\n-\t\t\t/* Do the lookup */\n-\t\t\tltypes01 = vqtbl1q_u8(tbl, xtmp128);\n-\t\t\tltypes23 = vqtbl1q_u8(tbl, ytmp128);\n-\n-\t\t\t/* Just use ld1q to retrieve aura\n-\t\t\t * when we don't need tx_offload\n-\t\t\t */\n-\t\t\tmbuf0 = (uint64_t *)((uintptr_t)mbuf0 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\tmbuf1 = (uint64_t *)((uintptr_t)mbuf1 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\tmbuf2 = (uint64_t *)((uintptr_t)mbuf2 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\tmbuf3 = (uint64_t *)((uintptr_t)mbuf3 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\n-\t\t\t/* Pick only relevant fields i.e Bit 48:55 of iltype\n-\t\t\t * and place it in ol3/ol4type of senddesc_w1\n-\t\t\t */\n-\t\t\tconst uint8x16_t shuf_mask0 = {\n-\t\t\t\t0xFF, 0xFF, 0xFF, 0xFF,\t0x6, 0xFF, 0xFF, 0xFF,\n-\t\t\t\t0xFF, 0xFF, 0xFF, 0xFF, 0xE, 0xFF, 0xFF, 0xFF,\n-\t\t\t};\n-\n-\t\t\tltypes01 = vqtbl1q_u8(ltypes01, shuf_mask0);\n-\t\t\tltypes23 = vqtbl1q_u8(ltypes23, shuf_mask0);\n-\n-\t\t\t/* Prepare ol4ptr, ol3ptr from ol3len, ol2len.\n-\t\t\t * a [E(32):E(16):OL3(8):OL2(8)]\n-\t\t\t * a = a + (a << 8)\n-\t\t\t * a [E(32):E(16):(OL3+OL2):OL2]\n-\t\t\t * => E(32):E(16)::OL4PTR(8):OL3PTR(8)\n-\t\t\t */\n-\t\t\tsenddesc01_w1 = vaddq_u8(senddesc01_w1,\n-\t\t\t\t\t\t vshlq_n_u16(senddesc01_w1, 8));\n-\t\t\tsenddesc23_w1 = vaddq_u8(senddesc23_w1,\n-\t\t\t\t\t\t vshlq_n_u16(senddesc23_w1, 8));\n-\n-\t\t\t/* Create first half of 4W cmd for 4 mbufs (sgdesc) */\n-\t\t\tcmd01 = vzip1q_u64(sgdesc01_w0, sgdesc01_w1);\n-\t\t\tcmd11 = vzip2q_u64(sgdesc01_w0, sgdesc01_w1);\n-\t\t\tcmd21 = vzip1q_u64(sgdesc23_w0, sgdesc23_w1);\n-\t\t\tcmd31 = vzip2q_u64(sgdesc23_w0, sgdesc23_w1);\n-\n-\t\t\txmask01 = vdupq_n_u64(0);\n-\t\t\txmask23 = xmask01;\n-\t\t\tasm volatile (\"LD1 {%[a].H}[0],[%[in]]\\n\\t\" :\n-\t\t\t\t[a]\"+w\"(xmask01) : [in]\"r\"(mbuf0) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[a].H}[4],[%[in]]\\n\\t\" :\n-\t\t\t\t [a]\"+w\"(xmask01) : [in]\"r\"(mbuf1) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[b].H}[0],[%[in]]\\n\\t\" :\n-\t\t\t\t [b]\"+w\"(xmask23) : [in]\"r\"(mbuf2) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[b].H}[4],[%[in]]\\n\\t\" :\n-\t\t\t\t [b]\"+w\"(xmask23) : [in]\"r\"(mbuf3) : \"memory\");\n-\t\t\txmask01 = vshlq_n_u64(xmask01, 20);\n-\t\t\txmask23 = vshlq_n_u64(xmask23, 20);\n-\n-\t\t\tsenddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);\n-\t\t\tsenddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);\n-\t\t\t/* Move ltypes to senddesc*_w1 */\n-\t\t\tsenddesc01_w1 = vorrq_u64(senddesc01_w1, ltypes01);\n-\t\t\tsenddesc23_w1 = vorrq_u64(senddesc23_w1, ltypes23);\n-\n-\t\t\t/* Create first half of 4W cmd for 4 mbufs (sendhdr) */\n-\t\t\tcmd00 = vzip1q_u64(senddesc01_w0, senddesc01_w1);\n-\t\t\tcmd10 = vzip2q_u64(senddesc01_w0, senddesc01_w1);\n-\t\t\tcmd20 = vzip1q_u64(senddesc23_w0, senddesc23_w1);\n-\t\t\tcmd30 = vzip2q_u64(senddesc23_w0, senddesc23_w1);\n-\n-\t\t} else if (!(flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F) &&\n-\t\t\t (flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)) {\n-\t\t\t/*\n-\t\t\t * Lookup table to translate ol_flags to\n-\t\t\t * ol3/ol4 types.\n-\t\t\t */\n-\n-\t\t\tconst uint8x16_t tbl = {\n-\t\t\t\t/* [0-15] = ol4type:ol3type */\n-\t\t\t\t0x00, /* none */\n-\t\t\t\t0x03, /* OUTER_IP_CKSUM */\n-\t\t\t\t0x02, /* OUTER_IPV4 */\n-\t\t\t\t0x03, /* OUTER_IPV4 | OUTER_IP_CKSUM */\n-\t\t\t\t0x04, /* OUTER_IPV6 */\n-\t\t\t\t0x00, /* OUTER_IPV6 | OUTER_IP_CKSUM */\n-\t\t\t\t0x00, /* OUTER_IPV6 | OUTER_IPV4 */\n-\t\t\t\t0x00, /* OUTER_IPV6 | OUTER_IPV4 |\n-\t\t\t\t * OUTER_IP_CKSUM\n-\t\t\t\t */\n-\t\t\t\t0x00, /* OUTER_UDP_CKSUM */\n-\t\t\t\t0x33, /* OUTER_UDP_CKSUM | OUTER_IP_CKSUM */\n-\t\t\t\t0x32, /* OUTER_UDP_CKSUM | OUTER_IPV4 */\n-\t\t\t\t0x33, /* OUTER_UDP_CKSUM | OUTER_IPV4 |\n-\t\t\t\t * OUTER_IP_CKSUM\n-\t\t\t\t */\n-\t\t\t\t0x34, /* OUTER_UDP_CKSUM | OUTER_IPV6 */\n-\t\t\t\t0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |\n-\t\t\t\t * OUTER_IP_CKSUM\n-\t\t\t\t */\n-\t\t\t\t0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |\n-\t\t\t\t * OUTER_IPV4\n-\t\t\t\t */\n-\t\t\t\t0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |\n-\t\t\t\t * OUTER_IPV4 | OUTER_IP_CKSUM\n-\t\t\t\t */\n-\t\t\t};\n-\n-\t\t\t/* Extract olflags to translate to iltypes */\n-\t\t\txtmp128 = vzip1q_u64(len_olflags0, len_olflags1);\n-\t\t\tytmp128 = vzip1q_u64(len_olflags2, len_olflags3);\n-\n-\t\t\t/*\n-\t\t\t * E(47):OL3_LEN(9):OL2_LEN(7+z)\n-\t\t\t * E(47):OL3_LEN(9):OL2_LEN(7+z)\n-\t\t\t */\n-\t\t\tconst uint8x16_t shuf_mask5 = {\n-\t\t\t\t0x6, 0x5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n-\t\t\t\t0xE, 0xD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,\n-\t\t\t};\n-\t\t\tsenddesc01_w1 = vqtbl1q_u8(senddesc01_w1, shuf_mask5);\n-\t\t\tsenddesc23_w1 = vqtbl1q_u8(senddesc23_w1, shuf_mask5);\n-\n-\t\t\t/* Extract outer ol flags only */\n-\t\t\tconst uint64x2_t o_cksum_mask = {\n-\t\t\t\t0x1C00020000000000,\n-\t\t\t\t0x1C00020000000000,\n-\t\t\t};\n-\n-\t\t\txtmp128 = vandq_u64(xtmp128, o_cksum_mask);\n-\t\t\tytmp128 = vandq_u64(ytmp128, o_cksum_mask);\n-\n-\t\t\t/* Extract OUTER_UDP_CKSUM bit 41 and\n-\t\t\t * move it to bit 61\n-\t\t\t */\n-\n-\t\t\txtmp128 = xtmp128 | vshlq_n_u64(xtmp128, 20);\n-\t\t\tytmp128 = ytmp128 | vshlq_n_u64(ytmp128, 20);\n-\n-\t\t\t/* Shift oltype by 2 to start nibble from BIT(56)\n-\t\t\t * instead of BIT(58)\n-\t\t\t */\n-\t\t\txtmp128 = vshrq_n_u8(xtmp128, 2);\n-\t\t\tytmp128 = vshrq_n_u8(ytmp128, 2);\n-\t\t\t/*\n-\t\t\t * E(48):L3_LEN(8):L2_LEN(z+7)\n-\t\t\t * E(48):L3_LEN(8):L2_LEN(z+7)\n-\t\t\t */\n-\t\t\tconst int8x16_t tshft3 = {\n-\t\t\t\t-1, 0, 8, 8, 8, 8, 8, 8,\n-\t\t\t\t-1, 0, 8, 8, 8, 8, 8, 8,\n-\t\t\t};\n-\n-\t\t\tsenddesc01_w1 = vshlq_u8(senddesc01_w1, tshft3);\n-\t\t\tsenddesc23_w1 = vshlq_u8(senddesc23_w1, tshft3);\n-\n-\t\t\t/* Do the lookup */\n-\t\t\tltypes01 = vqtbl1q_u8(tbl, xtmp128);\n-\t\t\tltypes23 = vqtbl1q_u8(tbl, ytmp128);\n-\n-\t\t\t/* Just use ld1q to retrieve aura\n-\t\t\t * when we don't need tx_offload\n-\t\t\t */\n-\t\t\tmbuf0 = (uint64_t *)((uintptr_t)mbuf0 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\tmbuf1 = (uint64_t *)((uintptr_t)mbuf1 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\tmbuf2 = (uint64_t *)((uintptr_t)mbuf2 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\tmbuf3 = (uint64_t *)((uintptr_t)mbuf3 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\n-\t\t\t/* Pick only relevant fields i.e Bit 56:63 of oltype\n-\t\t\t * and place it in ol3/ol4type of senddesc_w1\n-\t\t\t */\n-\t\t\tconst uint8x16_t shuf_mask0 = {\n-\t\t\t\t0xFF, 0xFF, 0xFF, 0xFF,\t0x7, 0xFF, 0xFF, 0xFF,\n-\t\t\t\t0xFF, 0xFF, 0xFF, 0xFF, 0xF, 0xFF, 0xFF, 0xFF,\n-\t\t\t};\n-\n-\t\t\tltypes01 = vqtbl1q_u8(ltypes01, shuf_mask0);\n-\t\t\tltypes23 = vqtbl1q_u8(ltypes23, shuf_mask0);\n-\n-\t\t\t/* Prepare ol4ptr, ol3ptr from ol3len, ol2len.\n-\t\t\t * a [E(32):E(16):OL3(8):OL2(8)]\n-\t\t\t * a = a + (a << 8)\n-\t\t\t * a [E(32):E(16):(OL3+OL2):OL2]\n-\t\t\t * => E(32):E(16)::OL4PTR(8):OL3PTR(8)\n-\t\t\t */\n-\t\t\tsenddesc01_w1 = vaddq_u8(senddesc01_w1,\n-\t\t\t\t\t\t vshlq_n_u16(senddesc01_w1, 8));\n-\t\t\tsenddesc23_w1 = vaddq_u8(senddesc23_w1,\n-\t\t\t\t\t\t vshlq_n_u16(senddesc23_w1, 8));\n-\n-\t\t\t/* Create second half of 4W cmd for 4 mbufs (sgdesc) */\n-\t\t\tcmd01 = vzip1q_u64(sgdesc01_w0, sgdesc01_w1);\n-\t\t\tcmd11 = vzip2q_u64(sgdesc01_w0, sgdesc01_w1);\n-\t\t\tcmd21 = vzip1q_u64(sgdesc23_w0, sgdesc23_w1);\n-\t\t\tcmd31 = vzip2q_u64(sgdesc23_w0, sgdesc23_w1);\n-\n-\t\t\txmask01 = vdupq_n_u64(0);\n-\t\t\txmask23 = xmask01;\n-\t\t\tasm volatile (\"LD1 {%[a].H}[0],[%[in]]\\n\\t\" :\n-\t\t\t\t [a]\"+w\"(xmask01) : [in]\"r\"(mbuf0) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[a].H}[4],[%[in]]\\n\\t\" :\n-\t\t\t\t [a]\"+w\"(xmask01) : [in]\"r\"(mbuf1) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[b].H}[0],[%[in]]\\n\\t\" :\n-\t\t\t\t [b]\"+w\"(xmask23) : [in]\"r\"(mbuf2) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[b].H}[4],[%[in]]\\n\\t\" :\n-\t\t\t\t [b]\"+w\"(xmask23) : [in]\"r\"(mbuf3) : \"memory\");\n-\t\t\txmask01 = vshlq_n_u64(xmask01, 20);\n-\t\t\txmask23 = vshlq_n_u64(xmask23, 20);\n-\n-\t\t\tsenddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);\n-\t\t\tsenddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);\n-\t\t\t/* Move ltypes to senddesc*_w1 */\n-\t\t\tsenddesc01_w1 = vorrq_u64(senddesc01_w1, ltypes01);\n-\t\t\tsenddesc23_w1 = vorrq_u64(senddesc23_w1, ltypes23);\n-\n-\t\t\t/* Create first half of 4W cmd for 4 mbufs (sendhdr) */\n-\t\t\tcmd00 = vzip1q_u64(senddesc01_w0, senddesc01_w1);\n-\t\t\tcmd10 = vzip2q_u64(senddesc01_w0, senddesc01_w1);\n-\t\t\tcmd20 = vzip1q_u64(senddesc23_w0, senddesc23_w1);\n-\t\t\tcmd30 = vzip2q_u64(senddesc23_w0, senddesc23_w1);\n-\n-\t\t} else if ((flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F) &&\n-\t\t\t (flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)) {\n-\t\t\t/* Lookup table to translate ol_flags to\n-\t\t\t * ol4type, ol3type, il4type, il3type of senddesc_w1\n-\t\t\t */\n-\t\t\tconst uint8x16x2_t tbl = {\n-\t\t\t{\n-\t\t\t\t{\n-\t\t\t\t\t/* [0-15] = il4type:il3type */\n-\t\t\t\t\t0x04, /* none (IPv6) */\n-\t\t\t\t\t0x14, /* RTE_MBUF_F_TX_TCP_CKSUM (IPv6) */\n-\t\t\t\t\t0x24, /* RTE_MBUF_F_TX_SCTP_CKSUM (IPv6) */\n-\t\t\t\t\t0x34, /* RTE_MBUF_F_TX_UDP_CKSUM (IPv6) */\n-\t\t\t\t\t0x03, /* RTE_MBUF_F_TX_IP_CKSUM */\n-\t\t\t\t\t0x13, /* RTE_MBUF_F_TX_IP_CKSUM |\n-\t\t\t\t\t * RTE_MBUF_F_TX_TCP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x23, /* RTE_MBUF_F_TX_IP_CKSUM |\n-\t\t\t\t\t * RTE_MBUF_F_TX_SCTP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x33, /* RTE_MBUF_F_TX_IP_CKSUM |\n-\t\t\t\t\t * RTE_MBUF_F_TX_UDP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x02, /* RTE_MBUF_F_TX_IPV4 */\n-\t\t\t\t\t0x12, /* RTE_MBUF_F_TX_IPV4 |\n-\t\t\t\t\t * RTE_MBUF_F_TX_TCP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x22, /* RTE_MBUF_F_TX_IPV4 |\n-\t\t\t\t\t * RTE_MBUF_F_TX_SCTP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x32, /* RTE_MBUF_F_TX_IPV4 |\n-\t\t\t\t\t * RTE_MBUF_F_TX_UDP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x03, /* RTE_MBUF_F_TX_IPV4 |\n-\t\t\t\t\t * RTE_MBUF_F_TX_IP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x13, /* RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IP_CKSUM |\n-\t\t\t\t\t * RTE_MBUF_F_TX_TCP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x23, /* RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IP_CKSUM |\n-\t\t\t\t\t * RTE_MBUF_F_TX_SCTP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x33, /* RTE_MBUF_F_TX_IPV4 | RTE_MBUF_F_TX_IP_CKSUM |\n-\t\t\t\t\t * RTE_MBUF_F_TX_UDP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t},\n-\n-\t\t\t\t{\n-\t\t\t\t\t/* [16-31] = ol4type:ol3type */\n-\t\t\t\t\t0x00, /* none */\n-\t\t\t\t\t0x03, /* OUTER_IP_CKSUM */\n-\t\t\t\t\t0x02, /* OUTER_IPV4 */\n-\t\t\t\t\t0x03, /* OUTER_IPV4 | OUTER_IP_CKSUM */\n-\t\t\t\t\t0x04, /* OUTER_IPV6 */\n-\t\t\t\t\t0x00, /* OUTER_IPV6 | OUTER_IP_CKSUM */\n-\t\t\t\t\t0x00, /* OUTER_IPV6 | OUTER_IPV4 */\n-\t\t\t\t\t0x00, /* OUTER_IPV6 | OUTER_IPV4 |\n-\t\t\t\t\t * OUTER_IP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x00, /* OUTER_UDP_CKSUM */\n-\t\t\t\t\t0x33, /* OUTER_UDP_CKSUM |\n-\t\t\t\t\t * OUTER_IP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x32, /* OUTER_UDP_CKSUM |\n-\t\t\t\t\t * OUTER_IPV4\n-\t\t\t\t\t */\n-\t\t\t\t\t0x33, /* OUTER_UDP_CKSUM |\n-\t\t\t\t\t * OUTER_IPV4 | OUTER_IP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x34, /* OUTER_UDP_CKSUM |\n-\t\t\t\t\t * OUTER_IPV6\n-\t\t\t\t\t */\n-\t\t\t\t\t0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |\n-\t\t\t\t\t * OUTER_IP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t\t0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |\n-\t\t\t\t\t * OUTER_IPV4\n-\t\t\t\t\t */\n-\t\t\t\t\t0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |\n-\t\t\t\t\t * OUTER_IPV4 | OUTER_IP_CKSUM\n-\t\t\t\t\t */\n-\t\t\t\t},\n-\t\t\t}\n-\t\t\t};\n-\n-\t\t\t/* Extract olflags to translate to oltype & iltype */\n-\t\t\txtmp128 = vzip1q_u64(len_olflags0, len_olflags1);\n-\t\t\tytmp128 = vzip1q_u64(len_olflags2, len_olflags3);\n-\n-\t\t\t/*\n-\t\t\t * E(8):OL2_LN(7):OL3_LN(9):E(23):L3_LN(9):L2_LN(7+z)\n-\t\t\t * E(8):OL2_LN(7):OL3_LN(9):E(23):L3_LN(9):L2_LN(7+z)\n-\t\t\t */\n-\t\t\tconst uint32x4_t tshft_4 = {\n-\t\t\t\t1, 0,\n-\t\t\t\t1, 0,\n-\t\t\t};\n-\t\t\tsenddesc01_w1 = vshlq_u32(senddesc01_w1, tshft_4);\n-\t\t\tsenddesc23_w1 = vshlq_u32(senddesc23_w1, tshft_4);\n-\n-\t\t\t/*\n-\t\t\t * E(32):L3_LEN(8):L2_LEN(7+Z):OL3_LEN(8):OL2_LEN(7+Z)\n-\t\t\t * E(32):L3_LEN(8):L2_LEN(7+Z):OL3_LEN(8):OL2_LEN(7+Z)\n-\t\t\t */\n-\t\t\tconst uint8x16_t shuf_mask5 = {\n-\t\t\t\t0x6, 0x5, 0x0, 0x1, 0xFF, 0xFF, 0xFF, 0xFF,\n-\t\t\t\t0xE, 0xD, 0x8, 0x9, 0xFF, 0xFF,\t0xFF, 0xFF,\n-\t\t\t};\n-\t\t\tsenddesc01_w1 = vqtbl1q_u8(senddesc01_w1, shuf_mask5);\n-\t\t\tsenddesc23_w1 = vqtbl1q_u8(senddesc23_w1, shuf_mask5);\n-\n-\t\t\t/* Extract outer and inner header ol_flags */\n-\t\t\tconst uint64x2_t oi_cksum_mask = {\n-\t\t\t\t0x1CF0020000000000,\n-\t\t\t\t0x1CF0020000000000,\n-\t\t\t};\n-\n-\t\t\txtmp128 = vandq_u64(xtmp128, oi_cksum_mask);\n-\t\t\tytmp128 = vandq_u64(ytmp128, oi_cksum_mask);\n-\n-\t\t\t/* Extract OUTER_UDP_CKSUM bit 41 and\n-\t\t\t * move it to bit 61\n-\t\t\t */\n-\n-\t\t\txtmp128 = xtmp128 | vshlq_n_u64(xtmp128, 20);\n-\t\t\tytmp128 = ytmp128 | vshlq_n_u64(ytmp128, 20);\n-\n-\t\t\t/* Shift right oltype by 2 and iltype by 4\n-\t\t\t * to start oltype nibble from BIT(58)\n-\t\t\t * instead of BIT(56) and iltype nibble from BIT(48)\n-\t\t\t * instead of BIT(52).\n-\t\t\t */\n-\t\t\tconst int8x16_t tshft5 = {\n-\t\t\t\t8, 8, 8, 8, 8, 8, -4, -2,\n-\t\t\t\t8, 8, 8, 8, 8, 8, -4, -2,\n-\t\t\t};\n-\n-\t\t\txtmp128 = vshlq_u8(xtmp128, tshft5);\n-\t\t\tytmp128 = vshlq_u8(ytmp128, tshft5);\n-\t\t\t/*\n-\t\t\t * E(32):L3_LEN(8):L2_LEN(8):OL3_LEN(8):OL2_LEN(8)\n-\t\t\t * E(32):L3_LEN(8):L2_LEN(8):OL3_LEN(8):OL2_LEN(8)\n-\t\t\t */\n-\t\t\tconst int8x16_t tshft3 = {\n-\t\t\t\t-1, 0, -1, 0, 0, 0, 0, 0,\n-\t\t\t\t-1, 0, -1, 0, 0, 0, 0, 0,\n-\t\t\t};\n-\n-\t\t\tsenddesc01_w1 = vshlq_u8(senddesc01_w1, tshft3);\n-\t\t\tsenddesc23_w1 = vshlq_u8(senddesc23_w1, tshft3);\n-\n-\t\t\t/* Mark Bit(4) of oltype */\n-\t\t\tconst uint64x2_t oi_cksum_mask2 = {\n-\t\t\t\t0x1000000000000000,\n-\t\t\t\t0x1000000000000000,\n-\t\t\t};\n-\n-\t\t\txtmp128 = vorrq_u64(xtmp128, oi_cksum_mask2);\n-\t\t\tytmp128 = vorrq_u64(ytmp128, oi_cksum_mask2);\n-\n-\t\t\t/* Do the lookup */\n-\t\t\tltypes01 = vqtbl2q_u8(tbl, xtmp128);\n-\t\t\tltypes23 = vqtbl2q_u8(tbl, ytmp128);\n-\n-\t\t\t/* Just use ld1q to retrieve aura\n-\t\t\t * when we don't need tx_offload\n-\t\t\t */\n-\t\t\tmbuf0 = (uint64_t *)((uintptr_t)mbuf0 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\tmbuf1 = (uint64_t *)((uintptr_t)mbuf1 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\tmbuf2 = (uint64_t *)((uintptr_t)mbuf2 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\tmbuf3 = (uint64_t *)((uintptr_t)mbuf3 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\n-\t\t\t/* Pick only relevant fields i.e Bit 48:55 of iltype and\n-\t\t\t * Bit 56:63 of oltype and place it in corresponding\n-\t\t\t * place in senddesc_w1.\n-\t\t\t */\n-\t\t\tconst uint8x16_t shuf_mask0 = {\n-\t\t\t\t0xFF, 0xFF, 0xFF, 0xFF, 0x7, 0x6, 0xFF, 0xFF,\n-\t\t\t\t0xFF, 0xFF, 0xFF, 0xFF,\t0xF, 0xE, 0xFF, 0xFF,\n-\t\t\t};\n-\n-\t\t\tltypes01 = vqtbl1q_u8(ltypes01, shuf_mask0);\n-\t\t\tltypes23 = vqtbl1q_u8(ltypes23, shuf_mask0);\n-\n-\t\t\t/* Prepare l4ptr, l3ptr, ol4ptr, ol3ptr from\n-\t\t\t * l3len, l2len, ol3len, ol2len.\n-\t\t\t * a [E(32):L3(8):L2(8):OL3(8):OL2(8)]\n-\t\t\t * a = a + (a << 8)\n-\t\t\t * a [E:(L3+L2):(L2+OL3):(OL3+OL2):OL2]\n-\t\t\t * a = a + (a << 16)\n-\t\t\t * a [E:(L3+L2+OL3+OL2):(L2+OL3+OL2):(OL3+OL2):OL2]\n-\t\t\t * => E(32):IL4PTR(8):IL3PTR(8):OL4PTR(8):OL3PTR(8)\n-\t\t\t */\n-\t\t\tsenddesc01_w1 = vaddq_u8(senddesc01_w1,\n-\t\t\t\t\t\t vshlq_n_u32(senddesc01_w1, 8));\n-\t\t\tsenddesc23_w1 = vaddq_u8(senddesc23_w1,\n-\t\t\t\t\t\t vshlq_n_u32(senddesc23_w1, 8));\n-\n-\t\t\t/* Create second half of 4W cmd for 4 mbufs (sgdesc) */\n-\t\t\tcmd01 = vzip1q_u64(sgdesc01_w0, sgdesc01_w1);\n-\t\t\tcmd11 = vzip2q_u64(sgdesc01_w0, sgdesc01_w1);\n-\t\t\tcmd21 = vzip1q_u64(sgdesc23_w0, sgdesc23_w1);\n-\t\t\tcmd31 = vzip2q_u64(sgdesc23_w0, sgdesc23_w1);\n-\n-\t\t\t/* Continue preparing l4ptr, l3ptr, ol4ptr, ol3ptr */\n-\t\t\tsenddesc01_w1 = vaddq_u8(senddesc01_w1,\n-\t\t\t\t\t\tvshlq_n_u32(senddesc01_w1, 16));\n-\t\t\tsenddesc23_w1 = vaddq_u8(senddesc23_w1,\n-\t\t\t\t\t\tvshlq_n_u32(senddesc23_w1, 16));\n-\n-\t\t\txmask01 = vdupq_n_u64(0);\n-\t\t\txmask23 = xmask01;\n-\t\t\tasm volatile (\"LD1 {%[a].H}[0],[%[in]]\\n\\t\" :\n-\t\t\t\t [a]\"+w\"(xmask01) : [in]\"r\"(mbuf0) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[a].H}[4],[%[in]]\\n\\t\" :\n-\t\t\t\t [a]\"+w\"(xmask01) : [in]\"r\"(mbuf1) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[b].H}[0],[%[in]]\\n\\t\" :\n-\t\t\t\t [b]\"+w\"(xmask23) : [in]\"r\"(mbuf2) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[b].H}[4],[%[in]]\\n\\t\" :\n-\t\t\t\t [b]\"+w\"(xmask23) : [in]\"r\"(mbuf3) : \"memory\");\n-\t\t\txmask01 = vshlq_n_u64(xmask01, 20);\n-\t\t\txmask23 = vshlq_n_u64(xmask23, 20);\n-\n-\t\t\tsenddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);\n-\t\t\tsenddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);\n-\t\t\t/* Move ltypes to senddesc*_w1 */\n-\t\t\tsenddesc01_w1 = vorrq_u64(senddesc01_w1, ltypes01);\n-\t\t\tsenddesc23_w1 = vorrq_u64(senddesc23_w1, ltypes23);\n-\n-\t\t\t/* Create first half of 4W cmd for 4 mbufs (sendhdr) */\n-\t\t\tcmd00 = vzip1q_u64(senddesc01_w0, senddesc01_w1);\n-\t\t\tcmd10 = vzip2q_u64(senddesc01_w0, senddesc01_w1);\n-\t\t\tcmd20 = vzip1q_u64(senddesc23_w0, senddesc23_w1);\n-\t\t\tcmd30 = vzip2q_u64(senddesc23_w0, senddesc23_w1);\n-\t\t} else {\n-\t\t\t/* Just use ld1q to retrieve aura\n-\t\t\t * when we don't need tx_offload\n-\t\t\t */\n-\t\t\tmbuf0 = (uint64_t *)((uintptr_t)mbuf0 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\tmbuf1 = (uint64_t *)((uintptr_t)mbuf1 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\tmbuf2 = (uint64_t *)((uintptr_t)mbuf2 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\tmbuf3 = (uint64_t *)((uintptr_t)mbuf3 +\n-\t\t\t\t\toffsetof(struct rte_mempool, pool_id));\n-\t\t\txmask01 = vdupq_n_u64(0);\n-\t\t\txmask23 = xmask01;\n-\t\t\tasm volatile (\"LD1 {%[a].H}[0],[%[in]]\\n\\t\" :\n-\t\t\t\t [a]\"+w\"(xmask01) : [in]\"r\"(mbuf0) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[a].H}[4],[%[in]]\\n\\t\" :\n-\t\t\t\t [a]\"+w\"(xmask01) : [in]\"r\"(mbuf1) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[b].H}[0],[%[in]]\\n\\t\" :\n-\t\t\t\t [b]\"+w\"(xmask23) : [in]\"r\"(mbuf2) : \"memory\");\n-\n-\t\t\tasm volatile (\"LD1 {%[b].H}[4],[%[in]]\\n\\t\" :\n-\t\t\t\t [b]\"+w\"(xmask23) : [in]\"r\"(mbuf3) : \"memory\");\n-\t\t\txmask01 = vshlq_n_u64(xmask01, 20);\n-\t\t\txmask23 = vshlq_n_u64(xmask23, 20);\n-\n-\t\t\tsenddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);\n-\t\t\tsenddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);\n-\n-\t\t\t/* Create 4W cmd for 4 mbufs (sendhdr, sgdesc) */\n-\t\t\tcmd00 = vzip1q_u64(senddesc01_w0, senddesc01_w1);\n-\t\t\tcmd01 = vzip1q_u64(sgdesc01_w0, sgdesc01_w1);\n-\t\t\tcmd10 = vzip2q_u64(senddesc01_w0, senddesc01_w1);\n-\t\t\tcmd11 = vzip2q_u64(sgdesc01_w0, sgdesc01_w1);\n-\t\t\tcmd20 = vzip1q_u64(senddesc23_w0, senddesc23_w1);\n-\t\t\tcmd21 = vzip1q_u64(sgdesc23_w0, sgdesc23_w1);\n-\t\t\tcmd30 = vzip2q_u64(senddesc23_w0, senddesc23_w1);\n-\t\t\tcmd31 = vzip2q_u64(sgdesc23_w0, sgdesc23_w1);\n-\t\t}\n-\n-\t\tdo {\n-\t\t\tvst1q_u64(lmt_addr, cmd00);\n-\t\t\tvst1q_u64(lmt_addr + 2, cmd01);\n-\t\t\tvst1q_u64(lmt_addr + 4, cmd10);\n-\t\t\tvst1q_u64(lmt_addr + 6, cmd11);\n-\t\t\tvst1q_u64(lmt_addr + 8, cmd20);\n-\t\t\tvst1q_u64(lmt_addr + 10, cmd21);\n-\t\t\tvst1q_u64(lmt_addr + 12, cmd30);\n-\t\t\tvst1q_u64(lmt_addr + 14, cmd31);\n-\t\t\tlmt_status = otx2_lmt_submit(io_addr);\n-\n-\t\t} while (lmt_status == 0);\n-\t\ttx_pkts = tx_pkts + NIX_DESCS_PER_LOOP;\n-\t}\n-\n-\tif (unlikely(pkts_left))\n-\t\tpkts += nix_xmit_pkts(tx_queue, tx_pkts, pkts_left, cmd, flags);\n-\n-\treturn pkts;\n-}\n-\n-#else\n-static __rte_always_inline uint16_t\n-nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,\n-\t\t uint16_t pkts, uint64_t *cmd, const uint16_t flags)\n-{\n-\tRTE_SET_USED(tx_queue);\n-\tRTE_SET_USED(tx_pkts);\n-\tRTE_SET_USED(pkts);\n-\tRTE_SET_USED(cmd);\n-\tRTE_SET_USED(flags);\n-\treturn 0;\n-}\n-#endif\n-\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-static uint16_t __rte_noinline\t__rte_hot\t\t\t\t\t\\\n-otx2_nix_xmit_pkts_ ## name(void *tx_queue,\t\t\t\t\\\n-\t\t\tstruct rte_mbuf **tx_pkts, uint16_t pkts)\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tuint64_t cmd[sz];\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\t/* For TSO inner checksum is a must */\t\t\t\t\\\n-\tif (((flags) & NIX_TX_OFFLOAD_TSO_F) &&\t\t\t\t\\\n-\t !((flags) & NIX_TX_OFFLOAD_L3_L4_CSUM_F))\t\t\t\\\n-\t\treturn 0;\t\t\t\t\t\t\\\n-\treturn nix_xmit_pkts(tx_queue, tx_pkts, pkts, cmd, flags);\t\\\n-}\n-\n-NIX_TX_FASTPATH_MODES\n-#undef T\n-\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-static uint16_t __rte_noinline\t__rte_hot\t\t\t\t\t\\\n-otx2_nix_xmit_pkts_mseg_ ## name(void *tx_queue,\t\t\t\\\n-\t\t\tstruct rte_mbuf **tx_pkts, uint16_t pkts)\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tuint64_t cmd[(sz) + NIX_TX_MSEG_SG_DWORDS - 2];\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\t/* For TSO inner checksum is a must */\t\t\t\t\\\n-\tif (((flags) & NIX_TX_OFFLOAD_TSO_F) &&\t\t\t\t\\\n-\t !((flags) & NIX_TX_OFFLOAD_L3_L4_CSUM_F))\t\t\t\\\n-\t\treturn 0;\t\t\t\t\t\t\\\n-\treturn nix_xmit_pkts_mseg(tx_queue, tx_pkts, pkts, cmd,\t\t\\\n-\t\t\t\t (flags) | NIX_TX_MULTI_SEG_F);\t\\\n-}\n-\n-NIX_TX_FASTPATH_MODES\n-#undef T\n-\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-static uint16_t __rte_noinline\t__rte_hot\t\t\t\t\t\\\n-otx2_nix_xmit_pkts_vec_ ## name(void *tx_queue,\t\t\t\t\\\n-\t\t\tstruct rte_mbuf **tx_pkts, uint16_t pkts)\t\\\n-{\t\t\t\t\t\t\t\t\t\\\n-\tuint64_t cmd[sz];\t\t\t\t\t\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-\t/* VLAN, TSTMP, TSO is not supported by vec */\t\t\t\\\n-\tif ((flags) & NIX_TX_OFFLOAD_VLAN_QINQ_F ||\t\t\t\\\n-\t (flags) & NIX_TX_OFFLOAD_TSTAMP_F ||\t\t\t\\\n-\t (flags) & NIX_TX_OFFLOAD_TSO_F)\t\t\t\t\\\n-\t\treturn 0;\t\t\t\t\t\t\\\n-\treturn nix_xmit_pkts_vector(tx_queue, tx_pkts, pkts, cmd, (flags)); \\\n-}\n-\n-NIX_TX_FASTPATH_MODES\n-#undef T\n-\n-static inline void\n-pick_tx_func(struct rte_eth_dev *eth_dev,\n-\t const eth_tx_burst_t tx_burst[2][2][2][2][2][2][2])\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\t/* [SEC] [TSTMP] [NOFF] [VLAN] [OL3_OL4_CSUM] [IL3_IL4_CSUM] */\n-\teth_dev->tx_pkt_burst = tx_burst\n-\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_SECURITY_F)]\n-\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F)]\n-\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F)]\n-\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)]\n-\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_VLAN_QINQ_F)]\n-\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)]\n-\t\t[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F)];\n-}\n-\n-void\n-otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\n-\tconst eth_tx_burst_t nix_eth_tx_burst[2][2][2][2][2][2][2] = {\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-\t[f6][f5][f4][f3][f2][f1][f0] = otx2_nix_xmit_pkts_ ## name,\n-\n-NIX_TX_FASTPATH_MODES\n-#undef T\n-\t};\n-\n-\tconst eth_tx_burst_t nix_eth_tx_burst_mseg[2][2][2][2][2][2][2] = {\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-\t[f6][f5][f4][f3][f2][f1][f0] = otx2_nix_xmit_pkts_mseg_ ## name,\n-\n-NIX_TX_FASTPATH_MODES\n-#undef T\n-\t};\n-\n-\tconst eth_tx_burst_t nix_eth_tx_vec_burst[2][2][2][2][2][2][2] = {\n-#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags)\t\t\t\\\n-\t[f6][f5][f4][f3][f2][f1][f0] = otx2_nix_xmit_pkts_vec_ ## name,\n-\n-NIX_TX_FASTPATH_MODES\n-#undef T\n-\t};\n-\n-\tif (dev->scalar_ena ||\n-\t (dev->tx_offload_flags &\n-\t (NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSTAMP_F |\n-\t NIX_TX_OFFLOAD_TSO_F)))\n-\t\tpick_tx_func(eth_dev, nix_eth_tx_burst);\n-\telse\n-\t\tpick_tx_func(eth_dev, nix_eth_tx_vec_burst);\n-\n-\tif (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_MULTI_SEGS)\n-\t\tpick_tx_func(eth_dev, nix_eth_tx_burst_mseg);\n-\n-\trte_mb();\n-}\ndiff --git a/drivers/net/octeontx2/otx2_tx.h b/drivers/net/octeontx2/otx2_tx.h\ndeleted file mode 100644\nindex 4bbd5a390f..0000000000\n--- a/drivers/net/octeontx2/otx2_tx.h\n+++ /dev/null\n@@ -1,791 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#ifndef __OTX2_TX_H__\n-#define __OTX2_TX_H__\n-\n-#define NIX_TX_OFFLOAD_NONE\t\t(0)\n-#define NIX_TX_OFFLOAD_L3_L4_CSUM_F\tBIT(0)\n-#define NIX_TX_OFFLOAD_OL3_OL4_CSUM_F\tBIT(1)\n-#define NIX_TX_OFFLOAD_VLAN_QINQ_F\tBIT(2)\n-#define NIX_TX_OFFLOAD_MBUF_NOFF_F\tBIT(3)\n-#define NIX_TX_OFFLOAD_TSTAMP_F\t\tBIT(4)\n-#define NIX_TX_OFFLOAD_TSO_F\t\tBIT(5)\n-#define NIX_TX_OFFLOAD_SECURITY_F\tBIT(6)\n-\n-/* Flags to control xmit_prepare function.\n- * Defining it from backwards to denote its been\n- * not used as offload flags to pick function\n- */\n-#define NIX_TX_MULTI_SEG_F\t\tBIT(15)\n-\n-#define NIX_TX_NEED_SEND_HDR_W1\t\\\n-\t(NIX_TX_OFFLOAD_L3_L4_CSUM_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |\t\\\n-\t NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSO_F)\n-\n-#define NIX_TX_NEED_EXT_HDR \\\n-\t(NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSTAMP_F | \\\n-\t NIX_TX_OFFLOAD_TSO_F)\n-\n-#define NIX_UDP_TUN_BITMASK \\\n-\t((1ull << (RTE_MBUF_F_TX_TUNNEL_VXLAN >> 45)) | \\\n-\t (1ull << (RTE_MBUF_F_TX_TUNNEL_GENEVE >> 45)))\n-\n-#define NIX_LSO_FORMAT_IDX_TSOV4\t(0)\n-#define NIX_LSO_FORMAT_IDX_TSOV6\t(1)\n-\n-/* Function to determine no of tx subdesc required in case ext\n- * sub desc is enabled.\n- */\n-static __rte_always_inline int\n-otx2_nix_tx_ext_subs(const uint16_t flags)\n-{\n-\treturn (flags & NIX_TX_OFFLOAD_TSTAMP_F) ? 2 :\n-\t\t((flags & (NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSO_F)) ?\n-\t\t 1 : 0);\n-}\n-\n-static __rte_always_inline void\n-otx2_nix_xmit_prepare_tstamp(uint64_t *cmd, const uint64_t *send_mem_desc,\n-\t\t\t const uint64_t ol_flags, const uint16_t no_segdw,\n-\t\t\t const uint16_t flags)\n-{\n-\tif (flags & NIX_TX_OFFLOAD_TSTAMP_F) {\n-\t\tstruct nix_send_mem_s *send_mem;\n-\t\tuint16_t off = (no_segdw - 1) << 1;\n-\t\tconst uint8_t is_ol_tstamp = !(ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST);\n-\n-\t\tsend_mem = (struct nix_send_mem_s *)(cmd + off);\n-\t\tif (flags & NIX_TX_MULTI_SEG_F) {\n-\t\t\t/* Retrieving the default desc values */\n-\t\t\tcmd[off] = send_mem_desc[6];\n-\n-\t\t\t/* Using compiler barier to avoid voilation of C\n-\t\t\t * aliasing rules.\n-\t\t\t */\n-\t\t\trte_compiler_barrier();\n-\t\t}\n-\n-\t\t/* Packets for which RTE_MBUF_F_TX_IEEE1588_TMST is not set, tx tstamp\n-\t\t * should not be recorded, hence changing the alg type to\n-\t\t * NIX_SENDMEMALG_SET and also changing send mem addr field to\n-\t\t * next 8 bytes as it corrpt the actual tx tstamp registered\n-\t\t * address.\n-\t\t */\n-\t\tsend_mem->alg = NIX_SENDMEMALG_SETTSTMP - (is_ol_tstamp);\n-\n-\t\tsend_mem->addr = (rte_iova_t)((uint64_t *)send_mem_desc[7] +\n-\t\t\t\t\t (is_ol_tstamp));\n-\t}\n-}\n-\n-static __rte_always_inline uint64_t\n-otx2_pktmbuf_detach(struct rte_mbuf *m)\n-{\n-\tstruct rte_mempool *mp = m->pool;\n-\tuint32_t mbuf_size, buf_len;\n-\tstruct rte_mbuf *md;\n-\tuint16_t priv_size;\n-\tuint16_t refcount;\n-\n-\t/* Update refcount of direct mbuf */\n-\tmd = rte_mbuf_from_indirect(m);\n-\trefcount = rte_mbuf_refcnt_update(md, -1);\n-\n-\tpriv_size = rte_pktmbuf_priv_size(mp);\n-\tmbuf_size = (uint32_t)(sizeof(struct rte_mbuf) + priv_size);\n-\tbuf_len = rte_pktmbuf_data_room_size(mp);\n-\n-\tm->priv_size = priv_size;\n-\tm->buf_addr = (char *)m + mbuf_size;\n-\tm->buf_iova = rte_mempool_virt2iova(m) + mbuf_size;\n-\tm->buf_len = (uint16_t)buf_len;\n-\trte_pktmbuf_reset_headroom(m);\n-\tm->data_len = 0;\n-\tm->ol_flags = 0;\n-\tm->next = NULL;\n-\tm->nb_segs = 1;\n-\n-\t/* Now indirect mbuf is safe to free */\n-\trte_pktmbuf_free(m);\n-\n-\tif (refcount == 0) {\n-\t\trte_mbuf_refcnt_set(md, 1);\n-\t\tmd->data_len = 0;\n-\t\tmd->ol_flags = 0;\n-\t\tmd->next = NULL;\n-\t\tmd->nb_segs = 1;\n-\t\treturn 0;\n-\t} else {\n-\t\treturn 1;\n-\t}\n-}\n-\n-static __rte_always_inline uint64_t\n-otx2_nix_prefree_seg(struct rte_mbuf *m)\n-{\n-\tif (likely(rte_mbuf_refcnt_read(m) == 1)) {\n-\t\tif (!RTE_MBUF_DIRECT(m))\n-\t\t\treturn otx2_pktmbuf_detach(m);\n-\n-\t\tm->next = NULL;\n-\t\tm->nb_segs = 1;\n-\t\treturn 0;\n-\t} else if (rte_mbuf_refcnt_update(m, -1) == 0) {\n-\t\tif (!RTE_MBUF_DIRECT(m))\n-\t\t\treturn otx2_pktmbuf_detach(m);\n-\n-\t\trte_mbuf_refcnt_set(m, 1);\n-\t\tm->next = NULL;\n-\t\tm->nb_segs = 1;\n-\t\treturn 0;\n-\t}\n-\n-\t/* Mbuf is having refcount more than 1 so need not to be freed */\n-\treturn 1;\n-}\n-\n-static __rte_always_inline void\n-otx2_nix_xmit_prepare_tso(struct rte_mbuf *m, const uint64_t flags)\n-{\n-\tuint64_t mask, ol_flags = m->ol_flags;\n-\n-\tif (flags & NIX_TX_OFFLOAD_TSO_F &&\n-\t (ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {\n-\t\tuintptr_t mdata = rte_pktmbuf_mtod(m, uintptr_t);\n-\t\tuint16_t *iplen, *oiplen, *oudplen;\n-\t\tuint16_t lso_sb, paylen;\n-\n-\t\tmask = -!!(ol_flags & (RTE_MBUF_F_TX_OUTER_IPV4 | RTE_MBUF_F_TX_OUTER_IPV6));\n-\t\tlso_sb = (mask & (m->outer_l2_len + m->outer_l3_len)) +\n-\t\t\tm->l2_len + m->l3_len + m->l4_len;\n-\n-\t\t/* Reduce payload len from base headers */\n-\t\tpaylen = m->pkt_len - lso_sb;\n-\n-\t\t/* Get iplen position assuming no tunnel hdr */\n-\t\tiplen = (uint16_t *)(mdata + m->l2_len +\n-\t\t\t\t (2 << !!(ol_flags & RTE_MBUF_F_TX_IPV6)));\n-\t\t/* Handle tunnel tso */\n-\t\tif ((flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) &&\n-\t\t (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)) {\n-\t\t\tconst uint8_t is_udp_tun = (NIX_UDP_TUN_BITMASK >>\n-\t\t\t\t((ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) >> 45)) & 0x1;\n-\n-\t\t\toiplen = (uint16_t *)(mdata + m->outer_l2_len +\n-\t\t\t\t(2 << !!(ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)));\n-\t\t\t*oiplen = rte_cpu_to_be_16(rte_be_to_cpu_16(*oiplen) -\n-\t\t\t\t\t\t paylen);\n-\n-\t\t\t/* Update format for UDP tunneled packet */\n-\t\t\tif (is_udp_tun) {\n-\t\t\t\toudplen = (uint16_t *)(mdata + m->outer_l2_len +\n-\t\t\t\t\t\t m->outer_l3_len + 4);\n-\t\t\t\t*oudplen =\n-\t\t\t\trte_cpu_to_be_16(rte_be_to_cpu_16(*oudplen) -\n-\t\t\t\t\t\t paylen);\n-\t\t\t}\n-\n-\t\t\t/* Update iplen position to inner ip hdr */\n-\t\t\tiplen = (uint16_t *)(mdata + lso_sb - m->l3_len -\n-\t\t\t\tm->l4_len + (2 << !!(ol_flags & RTE_MBUF_F_TX_IPV6)));\n-\t\t}\n-\n-\t\t*iplen = rte_cpu_to_be_16(rte_be_to_cpu_16(*iplen) - paylen);\n-\t}\n-}\n-\n-static __rte_always_inline void\n-otx2_nix_xmit_prepare(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags,\n-\t\t const uint64_t lso_tun_fmt)\n-{\n-\tstruct nix_send_ext_s *send_hdr_ext;\n-\tstruct nix_send_hdr_s *send_hdr;\n-\tuint64_t ol_flags = 0, mask;\n-\tunion nix_send_hdr_w1_u w1;\n-\tunion nix_send_sg_s *sg;\n-\n-\tsend_hdr = (struct nix_send_hdr_s *)cmd;\n-\tif (flags & NIX_TX_NEED_EXT_HDR) {\n-\t\tsend_hdr_ext = (struct nix_send_ext_s *)(cmd + 2);\n-\t\tsg = (union nix_send_sg_s *)(cmd + 4);\n-\t\t/* Clear previous markings */\n-\t\tsend_hdr_ext->w0.lso = 0;\n-\t\tsend_hdr_ext->w1.u = 0;\n-\t} else {\n-\t\tsg = (union nix_send_sg_s *)(cmd + 2);\n-\t}\n-\n-\tif (flags & NIX_TX_NEED_SEND_HDR_W1) {\n-\t\tol_flags = m->ol_flags;\n-\t\tw1.u = 0;\n-\t}\n-\n-\tif (!(flags & NIX_TX_MULTI_SEG_F)) {\n-\t\tsend_hdr->w0.total = m->data_len;\n-\t\tsend_hdr->w0.aura =\n-\t\t\tnpa_lf_aura_handle_to_aura(m->pool->pool_id);\n-\t}\n-\n-\t/*\n-\t * L3type: 2 => IPV4\n-\t * 3 => IPV4 with csum\n-\t * 4 => IPV6\n-\t * L3type and L3ptr needs to be set for either\n-\t * L3 csum or L4 csum or LSO\n-\t *\n-\t */\n-\n-\tif ((flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) &&\n-\t (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F)) {\n-\t\tconst uint8_t csum = !!(ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM);\n-\t\tconst uint8_t ol3type =\n-\t\t\t((!!(ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)) << 1) +\n-\t\t\t((!!(ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)) << 2) +\n-\t\t\t!!(ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM);\n-\n-\t\t/* Outer L3 */\n-\t\tw1.ol3type = ol3type;\n-\t\tmask = 0xffffull << ((!!ol3type) << 4);\n-\t\tw1.ol3ptr = ~mask & m->outer_l2_len;\n-\t\tw1.ol4ptr = ~mask & (w1.ol3ptr + m->outer_l3_len);\n-\n-\t\t/* Outer L4 */\n-\t\tw1.ol4type = csum + (csum << 1);\n-\n-\t\t/* Inner L3 */\n-\t\tw1.il3type = ((!!(ol_flags & RTE_MBUF_F_TX_IPV4)) << 1) +\n-\t\t\t((!!(ol_flags & RTE_MBUF_F_TX_IPV6)) << 2);\n-\t\tw1.il3ptr = w1.ol4ptr + m->l2_len;\n-\t\tw1.il4ptr = w1.il3ptr + m->l3_len;\n-\t\t/* Increment it by 1 if it is IPV4 as 3 is with csum */\n-\t\tw1.il3type = w1.il3type + !!(ol_flags & RTE_MBUF_F_TX_IP_CKSUM);\n-\n-\t\t/* Inner L4 */\n-\t\tw1.il4type = (ol_flags & RTE_MBUF_F_TX_L4_MASK) >> 52;\n-\n-\t\t/* In case of no tunnel header use only\n-\t\t * shift IL3/IL4 fields a bit to use\n-\t\t * OL3/OL4 for header checksum\n-\t\t */\n-\t\tmask = !ol3type;\n-\t\tw1.u = ((w1.u & 0xFFFFFFFF00000000) >> (mask << 3)) |\n-\t\t\t((w1.u & 0X00000000FFFFFFFF) >> (mask << 4));\n-\n-\t} else if (flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) {\n-\t\tconst uint8_t csum = !!(ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM);\n-\t\tconst uint8_t outer_l2_len = m->outer_l2_len;\n-\n-\t\t/* Outer L3 */\n-\t\tw1.ol3ptr = outer_l2_len;\n-\t\tw1.ol4ptr = outer_l2_len + m->outer_l3_len;\n-\t\t/* Increment it by 1 if it is IPV4 as 3 is with csum */\n-\t\tw1.ol3type = ((!!(ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)) << 1) +\n-\t\t\t((!!(ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)) << 2) +\n-\t\t\t!!(ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM);\n-\n-\t\t/* Outer L4 */\n-\t\tw1.ol4type = csum + (csum << 1);\n-\n-\t} else if (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F) {\n-\t\tconst uint8_t l2_len = m->l2_len;\n-\n-\t\t/* Always use OLXPTR and OLXTYPE when only\n-\t\t * when one header is present\n-\t\t */\n-\n-\t\t/* Inner L3 */\n-\t\tw1.ol3ptr = l2_len;\n-\t\tw1.ol4ptr = l2_len + m->l3_len;\n-\t\t/* Increment it by 1 if it is IPV4 as 3 is with csum */\n-\t\tw1.ol3type = ((!!(ol_flags & RTE_MBUF_F_TX_IPV4)) << 1) +\n-\t\t\t((!!(ol_flags & RTE_MBUF_F_TX_IPV6)) << 2) +\n-\t\t\t!!(ol_flags & RTE_MBUF_F_TX_IP_CKSUM);\n-\n-\t\t/* Inner L4 */\n-\t\tw1.ol4type = (ol_flags & RTE_MBUF_F_TX_L4_MASK) >> 52;\n-\t}\n-\n-\tif (flags & NIX_TX_NEED_EXT_HDR &&\n-\t flags & NIX_TX_OFFLOAD_VLAN_QINQ_F) {\n-\t\tsend_hdr_ext->w1.vlan1_ins_ena = !!(ol_flags & RTE_MBUF_F_TX_VLAN);\n-\t\t/* HW will update ptr after vlan0 update */\n-\t\tsend_hdr_ext->w1.vlan1_ins_ptr = 12;\n-\t\tsend_hdr_ext->w1.vlan1_ins_tci = m->vlan_tci;\n-\n-\t\tsend_hdr_ext->w1.vlan0_ins_ena = !!(ol_flags & RTE_MBUF_F_TX_QINQ);\n-\t\t/* 2B before end of l2 header */\n-\t\tsend_hdr_ext->w1.vlan0_ins_ptr = 12;\n-\t\tsend_hdr_ext->w1.vlan0_ins_tci = m->vlan_tci_outer;\n-\t}\n-\n-\tif (flags & NIX_TX_OFFLOAD_TSO_F &&\n-\t (ol_flags & RTE_MBUF_F_TX_TCP_SEG)) {\n-\t\tuint16_t lso_sb;\n-\t\tuint64_t mask;\n-\n-\t\tmask = -(!w1.il3type);\n-\t\tlso_sb = (mask & w1.ol4ptr) + (~mask & w1.il4ptr) + m->l4_len;\n-\n-\t\tsend_hdr_ext->w0.lso_sb = lso_sb;\n-\t\tsend_hdr_ext->w0.lso = 1;\n-\t\tsend_hdr_ext->w0.lso_mps = m->tso_segsz;\n-\t\tsend_hdr_ext->w0.lso_format =\n-\t\t\tNIX_LSO_FORMAT_IDX_TSOV4 + !!(ol_flags & RTE_MBUF_F_TX_IPV6);\n-\t\tw1.ol4type = NIX_SENDL4TYPE_TCP_CKSUM;\n-\n-\t\t/* Handle tunnel tso */\n-\t\tif ((flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) &&\n-\t\t (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)) {\n-\t\t\tconst uint8_t is_udp_tun = (NIX_UDP_TUN_BITMASK >>\n-\t\t\t\t((ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) >> 45)) & 0x1;\n-\t\t\tuint8_t shift = is_udp_tun ? 32 : 0;\n-\n-\t\t\tshift += (!!(ol_flags & RTE_MBUF_F_TX_OUTER_IPV6) << 4);\n-\t\t\tshift += (!!(ol_flags & RTE_MBUF_F_TX_IPV6) << 3);\n-\n-\t\t\tw1.il4type = NIX_SENDL4TYPE_TCP_CKSUM;\n-\t\t\tw1.ol4type = is_udp_tun ? NIX_SENDL4TYPE_UDP_CKSUM : 0;\n-\t\t\t/* Update format for UDP tunneled packet */\n-\t\t\tsend_hdr_ext->w0.lso_format = (lso_tun_fmt >> shift);\n-\t\t}\n-\t}\n-\n-\tif (flags & NIX_TX_NEED_SEND_HDR_W1)\n-\t\tsend_hdr->w1.u = w1.u;\n-\n-\tif (!(flags & NIX_TX_MULTI_SEG_F)) {\n-\t\tsg->seg1_size = m->data_len;\n-\t\t*(rte_iova_t *)(++sg) = rte_mbuf_data_iova(m);\n-\n-\t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n-\t\t\t/* DF bit = 1 if refcount of current mbuf or parent mbuf\n-\t\t\t *\t\tis greater than 1\n-\t\t\t * DF bit = 0 otherwise\n-\t\t\t */\n-\t\t\tsend_hdr->w0.df = otx2_nix_prefree_seg(m);\n-\t\t\t/* Ensuring mbuf fields which got updated in\n-\t\t\t * otx2_nix_prefree_seg are written before LMTST.\n-\t\t\t */\n-\t\t\trte_io_wmb();\n-\t\t}\n-\t\t/* Mark mempool object as \"put\" since it is freed by NIX */\n-\t\tif (!send_hdr->w0.df)\n-\t\t\tRTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);\n-\t}\n-}\n-\n-\n-static __rte_always_inline void\n-otx2_nix_xmit_one(uint64_t *cmd, void *lmt_addr,\n-\t\t const rte_iova_t io_addr, const uint32_t flags)\n-{\n-\tuint64_t lmt_status;\n-\n-\tdo {\n-\t\totx2_lmt_mov(lmt_addr, cmd, otx2_nix_tx_ext_subs(flags));\n-\t\tlmt_status = otx2_lmt_submit(io_addr);\n-\t} while (lmt_status == 0);\n-}\n-\n-static __rte_always_inline void\n-otx2_nix_xmit_prep_lmt(uint64_t *cmd, void *lmt_addr, const uint32_t flags)\n-{\n-\totx2_lmt_mov(lmt_addr, cmd, otx2_nix_tx_ext_subs(flags));\n-}\n-\n-static __rte_always_inline uint64_t\n-otx2_nix_xmit_submit_lmt(const rte_iova_t io_addr)\n-{\n-\treturn otx2_lmt_submit(io_addr);\n-}\n-\n-static __rte_always_inline uint64_t\n-otx2_nix_xmit_submit_lmt_release(const rte_iova_t io_addr)\n-{\n-\treturn otx2_lmt_submit_release(io_addr);\n-}\n-\n-static __rte_always_inline uint16_t\n-otx2_nix_prepare_mseg(struct rte_mbuf *m, uint64_t *cmd, const uint16_t flags)\n-{\n-\tstruct nix_send_hdr_s *send_hdr;\n-\tunion nix_send_sg_s *sg;\n-\tstruct rte_mbuf *m_next;\n-\tuint64_t *slist, sg_u;\n-\tuint64_t nb_segs;\n-\tuint64_t segdw;\n-\tuint8_t off, i;\n-\n-\tsend_hdr = (struct nix_send_hdr_s *)cmd;\n-\tsend_hdr->w0.total = m->pkt_len;\n-\tsend_hdr->w0.aura = npa_lf_aura_handle_to_aura(m->pool->pool_id);\n-\n-\tif (flags & NIX_TX_NEED_EXT_HDR)\n-\t\toff = 2;\n-\telse\n-\t\toff = 0;\n-\n-\tsg = (union nix_send_sg_s *)&cmd[2 + off];\n-\t/* Clear sg->u header before use */\n-\tsg->u &= 0xFC00000000000000;\n-\tsg_u = sg->u;\n-\tslist = &cmd[3 + off];\n-\n-\ti = 0;\n-\tnb_segs = m->nb_segs;\n-\n-\t/* Fill mbuf segments */\n-\tdo {\n-\t\tm_next = m->next;\n-\t\tsg_u = sg_u | ((uint64_t)m->data_len << (i << 4));\n-\t\t*slist = rte_mbuf_data_iova(m);\n-\t\t/* Set invert df if buffer is not to be freed by H/W */\n-\t\tif (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {\n-\t\t\tsg_u |=\t(otx2_nix_prefree_seg(m) << (i + 55));\n-\t\t\t/* Commit changes to mbuf */\n-\t\t\trte_io_wmb();\n-\t\t}\n-\t\t/* Mark mempool object as \"put\" since it is freed by NIX */\n-#ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n-\t\tif (!(sg_u & (1ULL << (i + 55))))\n-\t\t\tRTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0);\n-\t\trte_io_wmb();\n-#endif\n-\t\tslist++;\n-\t\ti++;\n-\t\tnb_segs--;\n-\t\tif (i > 2 && nb_segs) {\n-\t\t\ti = 0;\n-\t\t\t/* Next SG subdesc */\n-\t\t\t*(uint64_t *)slist = sg_u & 0xFC00000000000000;\n-\t\t\tsg->u = sg_u;\n-\t\t\tsg->segs = 3;\n-\t\t\tsg = (union nix_send_sg_s *)slist;\n-\t\t\tsg_u = sg->u;\n-\t\t\tslist++;\n-\t\t}\n-\t\tm = m_next;\n-\t} while (nb_segs);\n-\n-\tsg->u = sg_u;\n-\tsg->segs = i;\n-\tsegdw = (uint64_t *)slist - (uint64_t *)&cmd[2 + off];\n-\t/* Roundup extra dwords to multiple of 2 */\n-\tsegdw = (segdw >> 1) + (segdw & 0x1);\n-\t/* Default dwords */\n-\tsegdw += (off >> 1) + 1 + !!(flags & NIX_TX_OFFLOAD_TSTAMP_F);\n-\tsend_hdr->w0.sizem1 = segdw - 1;\n-\n-\treturn segdw;\n-}\n-\n-static __rte_always_inline void\n-otx2_nix_xmit_mseg_prep_lmt(uint64_t *cmd, void *lmt_addr, uint16_t segdw)\n-{\n-\totx2_lmt_mov_seg(lmt_addr, (const void *)cmd, segdw);\n-}\n-\n-static __rte_always_inline void\n-otx2_nix_xmit_mseg_one(uint64_t *cmd, void *lmt_addr,\n-\t\t rte_iova_t io_addr, uint16_t segdw)\n-{\n-\tuint64_t lmt_status;\n-\n-\tdo {\n-\t\totx2_lmt_mov_seg(lmt_addr, (const void *)cmd, segdw);\n-\t\tlmt_status = otx2_lmt_submit(io_addr);\n-\t} while (lmt_status == 0);\n-}\n-\n-static __rte_always_inline void\n-otx2_nix_xmit_mseg_one_release(uint64_t *cmd, void *lmt_addr,\n-\t\t rte_iova_t io_addr, uint16_t segdw)\n-{\n-\tuint64_t lmt_status;\n-\n-\trte_io_wmb();\n-\tdo {\n-\t\totx2_lmt_mov_seg(lmt_addr, (const void *)cmd, segdw);\n-\t\tlmt_status = otx2_lmt_submit(io_addr);\n-\t} while (lmt_status == 0);\n-}\n-\n-#define L3L4CSUM_F NIX_TX_OFFLOAD_L3_L4_CSUM_F\n-#define OL3OL4CSUM_F NIX_TX_OFFLOAD_OL3_OL4_CSUM_F\n-#define VLAN_F NIX_TX_OFFLOAD_VLAN_QINQ_F\n-#define NOFF_F NIX_TX_OFFLOAD_MBUF_NOFF_F\n-#define TSP_F NIX_TX_OFFLOAD_TSTAMP_F\n-#define TSO_F NIX_TX_OFFLOAD_TSO_F\n-#define TX_SEC_F NIX_TX_OFFLOAD_SECURITY_F\n-\n-/* [SEC] [TSO] [TSTMP] [NOFF] [VLAN] [OL3OL4CSUM] [L3L4CSUM] */\n-#define NIX_TX_FASTPATH_MODES\t\t\t\t\t\t\\\n-T(no_offload,\t\t\t\t0, 0, 0, 0, 0, 0, 0,\t4,\t\\\n-\t\tNIX_TX_OFFLOAD_NONE)\t\t\t\t\t\\\n-T(l3l4csum,\t\t\t\t0, 0, 0, 0, 0, 0, 1,\t4,\t\\\n-\t\tL3L4CSUM_F)\t\t\t\t\t\t\\\n-T(ol3ol4csum,\t\t\t\t0, 0, 0, 0, 0, 1, 0,\t4,\t\\\n-\t\tOL3OL4CSUM_F)\t\t\t\t\t\t\\\n-T(ol3ol4csum_l3l4csum,\t\t\t0, 0, 0, 0, 0, 1, 1,\t4,\t\\\n-\t\tOL3OL4CSUM_F | L3L4CSUM_F)\t\t\t\t\\\n-T(vlan,\t\t\t\t\t0, 0, 0, 0, 1, 0, 0,\t6,\t\\\n-\t\tVLAN_F)\t\t\t\t\t\t\t\\\n-T(vlan_l3l4csum,\t\t\t0, 0, 0, 0, 1, 0, 1,\t6,\t\\\n-\t\tVLAN_F | L3L4CSUM_F)\t\t\t\t\t\\\n-T(vlan_ol3ol4csum,\t\t\t0, 0, 0, 0, 1, 1, 0,\t6,\t\\\n-\t\tVLAN_F | OL3OL4CSUM_F)\t\t\t\t\t\\\n-T(vlan_ol3ol4csum_l3l4csum,\t\t0, 0, 0, 0, 1, 1, 1,\t6,\t\\\n-\t\tVLAN_F | OL3OL4CSUM_F |\tL3L4CSUM_F)\t\t\t\\\n-T(noff,\t\t\t\t\t0, 0, 0, 1, 0, 0, 0,\t4,\t\\\n-\t\tNOFF_F)\t\t\t\t\t\t\t\\\n-T(noff_l3l4csum,\t\t\t0, 0, 0, 1, 0, 0, 1,\t4,\t\\\n-\t\tNOFF_F | L3L4CSUM_F)\t\t\t\t\t\\\n-T(noff_ol3ol4csum,\t\t\t0, 0, 0, 1, 0, 1, 0,\t4,\t\\\n-\t\tNOFF_F | OL3OL4CSUM_F)\t\t\t\t\t\\\n-T(noff_ol3ol4csum_l3l4csum,\t\t0, 0, 0, 1, 0, 1, 1,\t4,\t\\\n-\t\tNOFF_F | OL3OL4CSUM_F |\tL3L4CSUM_F)\t\t\t\\\n-T(noff_vlan,\t\t\t\t0, 0, 0, 1, 1, 0, 0,\t6,\t\\\n-\t\tNOFF_F | VLAN_F)\t\t\t\t\t\\\n-T(noff_vlan_l3l4csum,\t\t\t0, 0, 0, 1, 1, 0, 1,\t6,\t\\\n-\t\tNOFF_F | VLAN_F | L3L4CSUM_F)\t\t\t\t\\\n-T(noff_vlan_ol3ol4csum,\t\t\t0, 0, 0, 1, 1, 1, 0,\t6,\t\\\n-\t\tNOFF_F | VLAN_F | OL3OL4CSUM_F)\t\t\t\t\\\n-T(noff_vlan_ol3ol4csum_l3l4csum,\t0, 0, 0, 1, 1, 1, 1,\t6,\t\\\n-\t\tNOFF_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\\\n-T(ts,\t\t\t\t\t0, 0, 1, 0, 0, 0, 0,\t8,\t\\\n-\t\tTSP_F)\t\t\t\t\t\t\t\\\n-T(ts_l3l4csum,\t\t\t\t0, 0, 1, 0, 0, 0, 1,\t8,\t\\\n-\t\tTSP_F | L3L4CSUM_F)\t\t\t\t\t\\\n-T(ts_ol3ol4csum,\t\t\t0, 0, 1, 0, 0, 1, 0,\t8,\t\\\n-\t\tTSP_F | OL3OL4CSUM_F)\t\t\t\t\t\\\n-T(ts_ol3ol4csum_l3l4csum,\t\t0, 0, 1, 0, 0, 1, 1,\t8,\t\\\n-\t\tTSP_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\t\\\n-T(ts_vlan,\t\t\t\t0, 0, 1, 0, 1, 0, 0,\t8,\t\\\n-\t\tTSP_F | VLAN_F)\t\t\t\t\t\t\\\n-T(ts_vlan_l3l4csum,\t\t\t0, 0, 1, 0, 1, 0, 1,\t8,\t\\\n-\t\tTSP_F | VLAN_F | L3L4CSUM_F)\t\t\t\t\\\n-T(ts_vlan_ol3ol4csum,\t\t\t0, 0, 1, 0, 1, 1, 0,\t8,\t\\\n-\t\tTSP_F | VLAN_F | OL3OL4CSUM_F)\t\t\t\t\\\n-T(ts_vlan_ol3ol4csum_l3l4csum,\t\t0, 0, 1, 0, 1, 1, 1,\t8,\t\\\n-\t\tTSP_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\\\n-T(ts_noff,\t\t\t\t0, 0, 1, 1, 0, 0, 0,\t8,\t\\\n-\t\tTSP_F | NOFF_F)\t\t\t\t\t\t\\\n-T(ts_noff_l3l4csum,\t\t\t0, 0, 1, 1, 0, 0, 1,\t8,\t\\\n-\t\tTSP_F | NOFF_F | L3L4CSUM_F)\t\t\t\t\\\n-T(ts_noff_ol3ol4csum,\t\t\t0, 0, 1, 1, 0, 1, 0,\t8,\t\\\n-\t\tTSP_F | NOFF_F | OL3OL4CSUM_F)\t\t\t\t\\\n-T(ts_noff_ol3ol4csum_l3l4csum,\t\t0, 0, 1, 1, 0, 1, 1,\t8,\t\\\n-\t\tTSP_F | NOFF_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\\\n-T(ts_noff_vlan,\t\t\t\t0, 0, 1, 1, 1, 0, 0,\t8,\t\\\n-\t\tTSP_F | NOFF_F | VLAN_F)\t\t\t\t\\\n-T(ts_noff_vlan_l3l4csum,\t\t0, 0, 1, 1, 1, 0, 1,\t8,\t\\\n-\t\tTSP_F | NOFF_F | VLAN_F | L3L4CSUM_F)\t\t\t\\\n-T(ts_noff_vlan_ol3ol4csum,\t\t0, 0, 1, 1, 1, 1, 0,\t8,\t\\\n-\t\tTSP_F | NOFF_F | VLAN_F | OL3OL4CSUM_F)\t\t\t\\\n-T(ts_noff_vlan_ol3ol4csum_l3l4csum,\t0, 0, 1, 1, 1, 1, 1,\t8,\t\\\n-\t\tTSP_F | NOFF_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n-\t\t\t\t\t\t\t\t\t\\\n-T(tso,\t\t\t\t\t0, 1, 0, 0, 0, 0, 0,\t6,\t\\\n-\t\tTSO_F)\t\t\t\t\t\t\t\\\n-T(tso_l3l4csum,\t\t\t\t0, 1, 0, 0, 0, 0, 1,\t6,\t\\\n-\t\tTSO_F | L3L4CSUM_F)\t\t\t\t\t\\\n-T(tso_ol3ol4csum,\t\t\t0, 1, 0, 0, 0, 1, 0,\t6,\t\\\n-\t\tTSO_F | OL3OL4CSUM_F)\t\t\t\t\t\\\n-T(tso_ol3ol4csum_l3l4csum,\t\t0, 1, 0, 0, 0, 1, 1,\t6,\t\\\n-\t\tTSO_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\t\\\n-T(tso_vlan,\t\t\t\t0, 1, 0, 0, 1, 0, 0,\t6,\t\\\n-\t\tTSO_F | VLAN_F)\t\t\t\t\t\t\\\n-T(tso_vlan_l3l4csum,\t\t\t0, 1, 0, 0, 1, 0, 1,\t6,\t\\\n-\t\tTSO_F | VLAN_F | L3L4CSUM_F)\t\t\t\t\\\n-T(tso_vlan_ol3ol4csum,\t\t\t0, 1, 0, 0, 1, 1, 0,\t6,\t\\\n-\t\tTSO_F | VLAN_F | OL3OL4CSUM_F)\t\t\t\t\\\n-T(tso_vlan_ol3ol4csum_l3l4csum,\t\t0, 1, 0, 0, 1, 1, 1,\t6,\t\\\n-\t\tTSO_F | VLAN_F | OL3OL4CSUM_F |\tL3L4CSUM_F)\t\t\\\n-T(tso_noff,\t\t\t\t0, 1, 0, 1, 0, 0, 0,\t6,\t\\\n-\t\tTSO_F | NOFF_F)\t\t\t\t\t\t\\\n-T(tso_noff_l3l4csum,\t\t\t0, 1, 0, 1, 0, 0, 1,\t6,\t\\\n-\t\tTSO_F | NOFF_F | L3L4CSUM_F)\t\t\t\t\\\n-T(tso_noff_ol3ol4csum,\t\t\t0, 1, 0, 1, 0, 1, 0,\t6,\t\\\n-\t\tTSO_F | NOFF_F | OL3OL4CSUM_F)\t\t\t\t\\\n-T(tso_noff_ol3ol4csum_l3l4csum,\t\t0, 1, 0, 1, 0, 1, 1,\t6,\t\\\n-\t\tTSO_F | NOFF_F | OL3OL4CSUM_F |\tL3L4CSUM_F)\t\t\\\n-T(tso_noff_vlan,\t\t\t0, 1, 0, 1, 1, 0, 0,\t6,\t\\\n-\t\tTSO_F | NOFF_F | VLAN_F)\t\t\t\t\\\n-T(tso_noff_vlan_l3l4csum,\t\t0, 1, 0, 1, 1, 0, 1,\t6,\t\\\n-\t\tTSO_F | NOFF_F | VLAN_F | L3L4CSUM_F)\t\t\t\\\n-T(tso_noff_vlan_ol3ol4csum,\t\t0, 1, 0, 1, 1, 1, 0,\t6,\t\\\n-\t\tTSO_F | NOFF_F | VLAN_F | OL3OL4CSUM_F)\t\t\t\\\n-T(tso_noff_vlan_ol3ol4csum_l3l4csum,\t0, 1, 0, 1, 1, 1, 1,\t6,\t\\\n-\t\tTSO_F | NOFF_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n-T(tso_ts,\t\t\t\t0, 1, 1, 0, 0, 0, 0,\t8,\t\\\n-\t\tTSO_F | TSP_F)\t\t\t\t\t\t\\\n-T(tso_ts_l3l4csum,\t\t\t0, 1, 1, 0, 0, 0, 1,\t8,\t\\\n-\t\tTSO_F | TSP_F | L3L4CSUM_F)\t\t\t\t\\\n-T(tso_ts_ol3ol4csum,\t\t\t0, 1, 1, 0, 0, 1, 0,\t8,\t\\\n-\t\tTSO_F | TSP_F | OL3OL4CSUM_F)\t\t\t\t\\\n-T(tso_ts_ol3ol4csum_l3l4csum,\t\t0, 1, 1, 0, 0, 1, 1,\t8,\t\\\n-\t\tTSO_F | TSP_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\\\n-T(tso_ts_vlan,\t\t\t\t0, 1, 1, 0, 1, 0, 0,\t8,\t\\\n-\t\tTSO_F | TSP_F | VLAN_F)\t\t\t\t\t\\\n-T(tso_ts_vlan_l3l4csum,\t\t\t0, 1, 1, 0, 1, 0, 1,\t8,\t\\\n-\t\tTSO_F | TSP_F | VLAN_F | L3L4CSUM_F)\t\t\t\\\n-T(tso_ts_vlan_ol3ol4csum,\t\t0, 1, 1, 0, 1, 1, 0,\t8,\t\\\n-\t\tTSO_F | TSP_F | VLAN_F | OL3OL4CSUM_F)\t\t\t\\\n-T(tso_ts_vlan_ol3ol4csum_l3l4csum,\t0, 1, 1, 0, 1, 1, 1,\t8,\t\\\n-\t\tTSO_F | TSP_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n-T(tso_ts_noff,\t\t\t\t0, 1, 1, 1, 0, 0, 0,\t8,\t\\\n-\t\tTSO_F | TSP_F | NOFF_F)\t\t\t\t\t\\\n-T(tso_ts_noff_l3l4csum,\t\t\t0, 1, 1, 1, 0, 0, 1,\t8,\t\\\n-\t\tTSO_F | TSP_F | NOFF_F | L3L4CSUM_F)\t\t\t\\\n-T(tso_ts_noff_ol3ol4csum,\t\t0, 1, 1, 1, 0, 1, 0,\t8,\t\\\n-\t\tTSO_F | TSP_F | NOFF_F | OL3OL4CSUM_F)\t\t\t\\\n-T(tso_ts_noff_ol3ol4csum_l3l4csum,\t0, 1, 1, 1, 0, 1, 1,\t8,\t\\\n-\t\tTSO_F | TSP_F | NOFF_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n-T(tso_ts_noff_vlan,\t\t\t0, 1, 1, 1, 1, 0, 0,\t8,\t\\\n-\t\tTSO_F | TSP_F | NOFF_F | VLAN_F)\t\t\t\\\n-T(tso_ts_noff_vlan_l3l4csum,\t\t0, 1, 1, 1, 1, 0, 1,\t8,\t\\\n-\t\tTSO_F | TSP_F | NOFF_F | VLAN_F | L3L4CSUM_F)\t\t\\\n-T(tso_ts_noff_vlan_ol3ol4csum,\t\t0, 1, 1, 1, 1, 1, 0,\t8,\t\\\n-\t\tTSO_F | TSP_F | NOFF_F | VLAN_F | OL3OL4CSUM_F)\t\t\\\n-T(tso_ts_noff_vlan_ol3ol4csum_l3l4csum,\t0, 1, 1, 1, 1, 1, 1,\t8,\t\\\n-\t\tTSO_F | TSP_F | NOFF_F | VLAN_F | OL3OL4CSUM_F |\t\\\n-\t\tL3L4CSUM_F)\t\t\t\t\t\t\\\n-T(sec,\t\t\t\t\t1, 0, 0, 0, 0, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F)\t\t\t\t\t\t\\\n-T(sec_l3l4csum,\t\t\t\t1, 0, 0, 0, 0, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | L3L4CSUM_F)\t\t\t\t\t\\\n-T(sec_ol3ol4csum,\t\t\t1, 0, 0, 0, 0, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | OL3OL4CSUM_F)\t\t\t\t\\\n-T(sec_ol3ol4csum_l3l4csum,\t\t1, 0, 0, 0, 0, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\t\\\n-T(sec_vlan,\t\t\t\t1, 0, 0, 0, 1, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | VLAN_F)\t\t\t\t\t\\\n-T(sec_vlan_l3l4csum,\t\t\t1, 0, 0, 0, 1, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | VLAN_F | L3L4CSUM_F)\t\t\t\t\\\n-T(sec_vlan_ol3ol4csum,\t\t\t1, 0, 0, 0, 1, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | VLAN_F | OL3OL4CSUM_F)\t\t\t\\\n-T(sec_vlan_ol3ol4csum_l3l4csum,\t\t1, 0, 0, 0, 1, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\\\n-T(sec_noff,\t\t\t\t1, 0, 0, 1, 0, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | NOFF_F)\t\t\t\t\t\\\n-T(sec_noff_l3l4csum,\t\t\t1, 0, 0, 1, 0, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | NOFF_F | L3L4CSUM_F)\t\t\t\t\\\n-T(sec_noff_ol3ol4csum,\t\t\t1, 0, 0, 1, 0, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | NOFF_F | OL3OL4CSUM_F)\t\t\t\\\n-T(sec_noff_ol3ol4csum_l3l4csum,\t\t1, 0, 0, 1, 0, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | NOFF_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\\\n-T(sec_noff_vlan,\t\t\t1, 0, 0, 1, 1, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | NOFF_F | VLAN_F)\t\t\t\t\\\n-T(sec_noff_vlan_l3l4csum,\t\t1, 0, 0, 1, 1, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | NOFF_F | VLAN_F | L3L4CSUM_F)\t\t\\\n-T(sec_noff_vlan_ol3ol4csum,\t\t1, 0, 0, 1, 1, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | NOFF_F | VLAN_F | OL3OL4CSUM_F)\t\t\\\n-T(sec_noff_vlan_ol3ol4csum_l3l4csum,\t1, 0, 0, 1, 1, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | NOFF_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n-T(sec_ts,\t\t\t\t1, 0, 1, 0, 0, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F)\t\t\t\t\t\\\n-T(sec_ts_l3l4csum,\t\t\t1, 0, 1, 0, 0, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | L3L4CSUM_F)\t\t\t\t\\\n-T(sec_ts_ol3ol4csum,\t\t\t1, 0, 1, 0, 0, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | OL3OL4CSUM_F)\t\t\t\\\n-T(sec_ts_ol3ol4csum_l3l4csum,\t\t1, 0, 1, 0, 0, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\\\n-T(sec_ts_vlan,\t\t\t\t1, 0, 1, 0, 1, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | VLAN_F)\t\t\t\t\\\n-T(sec_ts_vlan_l3l4csum,\t\t\t1, 0, 1, 0, 1, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | VLAN_F | L3L4CSUM_F)\t\t\t\\\n-T(sec_ts_vlan_ol3ol4csum,\t\t1, 0, 1, 0, 1, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | VLAN_F | OL3OL4CSUM_F)\t\t\\\n-T(sec_ts_vlan_ol3ol4csum_l3l4csum,\t1, 0, 1, 0, 1, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n-T(sec_ts_noff,\t\t\t\t1, 0, 1, 1, 0, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | NOFF_F)\t\t\t\t\\\n-T(sec_ts_noff_l3l4csum,\t\t\t1, 0, 1, 1, 0, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | NOFF_F | L3L4CSUM_F)\t\t\t\\\n-T(sec_ts_noff_ol3ol4csum,\t\t1, 0, 1, 1, 0, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | NOFF_F | OL3OL4CSUM_F)\t\t\\\n-T(sec_ts_noff_ol3ol4csum_l3l4csum,\t1, 0, 1, 1, 0, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | NOFF_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n-T(sec_ts_noff_vlan,\t\t\t1, 0, 1, 1, 1, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | NOFF_F | VLAN_F)\t\t\t\\\n-T(sec_ts_noff_vlan_l3l4csum,\t\t1, 0, 1, 1, 1, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | NOFF_F | VLAN_F | L3L4CSUM_F)\t\\\n-T(sec_ts_noff_vlan_ol3ol4csum,\t\t1, 0, 1, 1, 1, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | NOFF_F | VLAN_F | OL3OL4CSUM_F)\t\\\n-T(sec_ts_noff_vlan_ol3ol4csum_l3l4csum,\t1, 0, 1, 1, 1, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSP_F | NOFF_F | VLAN_F | OL3OL4CSUM_F |\t\\\n-\t\tL3L4CSUM_F)\t\t\t\t\t\t\\\n-T(sec_tso,\t\t\t\t1, 1, 0, 0, 0, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F)\t\t\t\t\t\\\n-T(sec_tso_l3l4csum,\t\t\t1, 1, 0, 0, 0, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | L3L4CSUM_F)\t\t\t\t\\\n-T(sec_tso_ol3ol4csum,\t\t\t1, 1, 0, 0, 0, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | OL3OL4CSUM_F)\t\t\t\\\n-T(sec_tso_ol3ol4csum_l3l4csum,\t\t1, 1, 0, 0, 0, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\t\\\n-T(sec_tso_vlan,\t\t\t\t1, 1, 0, 0, 1, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | VLAN_F)\t\t\t\t\\\n-T(sec_tso_vlan_l3l4csum,\t\t1, 1, 0, 0, 1, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | VLAN_F | L3L4CSUM_F)\t\t\t\\\n-T(sec_tso_vlan_ol3ol4csum,\t\t1, 1, 0, 0, 1, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | VLAN_F | OL3OL4CSUM_F)\t\t\\\n-T(sec_tso_vlan_ol3ol4csum_l3l4csum,\t1, 1, 0, 0, 1, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | VLAN_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n-T(sec_tso_noff,\t\t\t\t1, 1, 0, 1, 0, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | NOFF_F)\t\t\t\t\\\n-T(sec_tso_noff_l3l4csum,\t\t1, 1, 0, 1, 0, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | NOFF_F | L3L4CSUM_F)\t\t\t\\\n-T(sec_tso_noff_ol3ol4csum,\t\t1, 1, 0, 1, 0, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | NOFF_F | OL3OL4CSUM_F)\t\t\\\n-T(sec_tso_noff_ol3ol4csum_l3l4csum,\t1, 1, 0, 1, 0, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | NOFF_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n-T(sec_tso_noff_vlan,\t\t\t1, 1, 0, 1, 1, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | NOFF_F | VLAN_F)\t\t\t\\\n-T(sec_tso_noff_vlan_l3l4csum,\t\t1, 1, 0, 1, 1, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | NOFF_F | VLAN_F | L3L4CSUM_F)\t\\\n-T(sec_tso_noff_vlan_ol3ol4csum,\t\t1, 1, 0, 1, 1, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | NOFF_F | VLAN_F | OL3OL4CSUM_F)\t\\\n-T(sec_tso_noff_vlan_ol3ol4csum_l3l4csum,\t\t\t\t\\\n-\t\t\t\t\t1, 1, 0, 1, 1, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | NOFF_F | VLAN_F | OL3OL4CSUM_F |\t\\\n-\t\tL3L4CSUM_F)\t\t\t\t\t\t\\\n-T(sec_tso_ts,\t\t\t\t1, 1, 1, 0, 0, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F)\t\t\t\t\\\n-T(sec_tso_ts_l3l4csum,\t\t\t1, 1, 1, 0, 0, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | L3L4CSUM_F)\t\t\t\\\n-T(sec_tso_ts_ol3ol4csum,\t\t1, 1, 1, 0, 0, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | OL3OL4CSUM_F)\t\t\\\n-T(sec_tso_ts_ol3ol4csum_l3l4csum,\t1, 1, 1, 0, 0, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | OL3OL4CSUM_F | L3L4CSUM_F)\t\\\n-T(sec_tso_ts_vlan,\t\t\t1, 1, 1, 0, 1, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | VLAN_F)\t\t\t\\\n-T(sec_tso_ts_vlan_l3l4csum,\t\t1, 1, 1, 0, 1, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | VLAN_F | L3L4CSUM_F)\t\t\\\n-T(sec_tso_ts_vlan_ol3ol4csum,\t\t1, 1, 1, 0, 1, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | VLAN_F | OL3OL4CSUM_F)\t\\\n-T(sec_tso_ts_vlan_ol3ol4csum_l3l4csum,\t1, 1, 1, 0, 1, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | VLAN_F | OL3OL4CSUM_F |\t\\\n-\t\tL3L4CSUM_F)\t\t\t\t\t\t\\\n-T(sec_tso_ts_noff,\t\t\t1, 1, 1, 1, 0, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | NOFF_F)\t\t\t\\\n-T(sec_tso_ts_noff_l3l4csum,\t\t1, 1, 1, 1, 0, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | NOFF_F | L3L4CSUM_F)\t\t\\\n-T(sec_tso_ts_noff_ol3ol4csum,\t\t1, 1, 1, 1, 0, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | NOFF_F | OL3OL4CSUM_F)\t\\\n-T(sec_tso_ts_noff_ol3ol4csum_l3l4csum,\t1, 1, 1, 1, 0, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | NOFF_F | OL3OL4CSUM_F |\t\\\n-\t\tL3L4CSUM_F)\t\t\t\t\t\t\\\n-T(sec_tso_ts_noff_vlan,\t\t\t1, 1, 1, 1, 1, 0, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | NOFF_F | VLAN_F)\t\t\\\n-T(sec_tso_ts_noff_vlan_l3l4csum,\t1, 1, 1, 1, 1, 0, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | NOFF_F | VLAN_F | L3L4CSUM_F)\\\n-T(sec_tso_ts_noff_vlan_ol3ol4csum,\t1, 1, 1, 1, 1, 1, 0,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | NOFF_F | VLAN_F |\t\t\\\n-\t\tOL3OL4CSUM_F)\t\t\t\t\t\t\\\n-T(sec_tso_ts_noff_vlan_ol3ol4csum_l3l4csum,\t\t\t\t\\\n-\t\t\t\t\t1, 1, 1, 1, 1, 1, 1,\t8,\t\\\n-\t\tTX_SEC_F | TSO_F | TSP_F | NOFF_F | VLAN_F |\t\t\\\n-\t\tOL3OL4CSUM_F | L3L4CSUM_F)\n-#endif /* __OTX2_TX_H__ */\ndiff --git a/drivers/net/octeontx2/otx2_vlan.c b/drivers/net/octeontx2/otx2_vlan.c\ndeleted file mode 100644\nindex cce643b7b5..0000000000\n--- a/drivers/net/octeontx2/otx2_vlan.c\n+++ /dev/null\n@@ -1,1035 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(C) 2019 Marvell International Ltd.\n- */\n-\n-#include <rte_malloc.h>\n-#include <rte_tailq.h>\n-\n-#include \"otx2_ethdev.h\"\n-#include \"otx2_flow.h\"\n-\n-\n-#define VLAN_ID_MATCH\t0x1\n-#define VTAG_F_MATCH\t0x2\n-#define MAC_ADDR_MATCH\t0x4\n-#define QINQ_F_MATCH\t0x8\n-#define VLAN_DROP\t0x10\n-#define DEF_F_ENTRY\t0x20\n-\n-enum vtag_cfg_dir {\n-\tVTAG_TX,\n-\tVTAG_RX\n-};\n-\n-static int\n-nix_vlan_mcam_enb_dis(struct otx2_eth_dev *dev,\n-\t\t uint32_t entry, const int enable)\n-{\n-\tstruct npc_mcam_ena_dis_entry_req *req;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tint rc = -EINVAL;\n-\n-\tif (enable)\n-\t\treq = otx2_mbox_alloc_msg_npc_mcam_ena_entry(mbox);\n-\telse\n-\t\treq = otx2_mbox_alloc_msg_npc_mcam_dis_entry(mbox);\n-\n-\treq->entry = entry;\n-\n-\trc = otx2_mbox_process_msg(mbox, NULL);\n-\treturn rc;\n-}\n-\n-static void\n-nix_set_rx_vlan_action(struct rte_eth_dev *eth_dev,\n-\t\t struct mcam_entry *entry, bool qinq, bool drop)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint pcifunc = otx2_pfvf_func(dev->pf, dev->vf);\n-\tuint64_t action = 0, vtag_action = 0;\n-\n-\taction = NIX_RX_ACTIONOP_UCAST;\n-\n-\tif (eth_dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {\n-\t\taction = NIX_RX_ACTIONOP_RSS;\n-\t\taction |= (uint64_t)(dev->rss_info.alg_idx) << 56;\n-\t}\n-\n-\taction |= (uint64_t)pcifunc << 4;\n-\tentry->action = action;\n-\n-\tif (drop) {\n-\t\tentry->action &= ~((uint64_t)0xF);\n-\t\tentry->action |= NIX_RX_ACTIONOP_DROP;\n-\t\treturn;\n-\t}\n-\n-\tif (!qinq) {\n-\t\t/* VTAG0 fields denote CTAG in single vlan case */\n-\t\tvtag_action |= (NIX_RX_VTAGACTION_VTAG_VALID << 15);\n-\t\tvtag_action |= (NPC_LID_LB << 8);\n-\t\tvtag_action |= NIX_RX_VTAGACTION_VTAG0_RELPTR;\n-\t} else {\n-\t\t/* VTAG0 & VTAG1 fields denote CTAG & STAG respectively */\n-\t\tvtag_action |= (NIX_RX_VTAGACTION_VTAG_VALID << 15);\n-\t\tvtag_action |= (NPC_LID_LB << 8);\n-\t\tvtag_action |= NIX_RX_VTAGACTION_VTAG1_RELPTR;\n-\t\tvtag_action |= (NIX_RX_VTAGACTION_VTAG_VALID << 47);\n-\t\tvtag_action |= ((uint64_t)(NPC_LID_LB) << 40);\n-\t\tvtag_action |= (NIX_RX_VTAGACTION_VTAG0_RELPTR << 32);\n-\t}\n-\n-\tentry->vtag_action = vtag_action;\n-}\n-\n-static void\n-nix_set_tx_vlan_action(struct mcam_entry *entry, enum rte_vlan_type type,\n-\t\t int vtag_index)\n-{\n-\tunion {\n-\t\tuint64_t reg;\n-\t\tstruct nix_tx_vtag_action_s act;\n-\t} vtag_action;\n-\n-\tuint64_t action;\n-\n-\taction = NIX_TX_ACTIONOP_UCAST_DEFAULT;\n-\n-\t/*\n-\t * Take offset from LA since in case of untagged packet,\n-\t * lbptr is zero.\n-\t */\n-\tif (type == RTE_ETH_VLAN_TYPE_OUTER) {\n-\t\tvtag_action.act.vtag0_def = vtag_index;\n-\t\tvtag_action.act.vtag0_lid = NPC_LID_LA;\n-\t\tvtag_action.act.vtag0_op = NIX_TX_VTAGOP_INSERT;\n-\t\tvtag_action.act.vtag0_relptr = NIX_TX_VTAGACTION_VTAG0_RELPTR;\n-\t} else {\n-\t\tvtag_action.act.vtag1_def = vtag_index;\n-\t\tvtag_action.act.vtag1_lid = NPC_LID_LA;\n-\t\tvtag_action.act.vtag1_op = NIX_TX_VTAGOP_INSERT;\n-\t\tvtag_action.act.vtag1_relptr = NIX_TX_VTAGACTION_VTAG1_RELPTR;\n-\t}\n-\n-\tentry->action = action;\n-\tentry->vtag_action = vtag_action.reg;\n-}\n-\n-static int\n-nix_vlan_mcam_free(struct otx2_eth_dev *dev, uint32_t entry)\n-{\n-\tstruct npc_mcam_free_entry_req *req;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tint rc = -EINVAL;\n-\n-\treq = otx2_mbox_alloc_msg_npc_mcam_free_entry(mbox);\n-\treq->entry = entry;\n-\n-\trc = otx2_mbox_process_msg(mbox, NULL);\n-\treturn rc;\n-}\n-\n-static int\n-nix_vlan_mcam_write(struct rte_eth_dev *eth_dev, uint16_t ent_idx,\n-\t\t struct mcam_entry *entry, uint8_t intf, uint8_t ena)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct npc_mcam_write_entry_req *req;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct msghdr *rsp;\n-\tint rc = -EINVAL;\n-\n-\treq = otx2_mbox_alloc_msg_npc_mcam_write_entry(mbox);\n-\n-\treq->entry = ent_idx;\n-\treq->intf = intf;\n-\treq->enable_entry = ena;\n-\tmemcpy(&req->entry_data, entry, sizeof(struct mcam_entry));\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\treturn rc;\n-}\n-\n-static int\n-nix_vlan_mcam_alloc_and_write(struct rte_eth_dev *eth_dev,\n-\t\t\t struct mcam_entry *entry,\n-\t\t\t uint8_t intf, bool drop)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct npc_mcam_alloc_and_write_entry_req *req;\n-\tstruct npc_mcam_alloc_and_write_entry_rsp *rsp;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tint rc = -EINVAL;\n-\n-\treq = otx2_mbox_alloc_msg_npc_mcam_alloc_and_write_entry(mbox);\n-\n-\tif (intf == NPC_MCAM_RX) {\n-\t\tif (!drop && dev->vlan_info.def_rx_mcam_idx) {\n-\t\t\treq->priority = NPC_MCAM_HIGHER_PRIO;\n-\t\t\treq->ref_entry = dev->vlan_info.def_rx_mcam_idx;\n-\t\t} else if (drop && dev->vlan_info.qinq_mcam_idx) {\n-\t\t\treq->priority = NPC_MCAM_LOWER_PRIO;\n-\t\t\treq->ref_entry = dev->vlan_info.qinq_mcam_idx;\n-\t\t} else {\n-\t\t\treq->priority = NPC_MCAM_ANY_PRIO;\n-\t\t\treq->ref_entry = 0;\n-\t\t}\n-\t} else {\n-\t\treq->priority = NPC_MCAM_ANY_PRIO;\n-\t\treq->ref_entry = 0;\n-\t}\n-\n-\treq->intf = intf;\n-\treq->enable_entry = 1;\n-\tmemcpy(&req->entry_data, entry, sizeof(struct mcam_entry));\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\treturn rsp->entry;\n-}\n-\n-static void\n-nix_vlan_update_mac(struct rte_eth_dev *eth_dev, int mcam_index,\n-\t\t\t int enable)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct vlan_mkex_info *mkex = &dev->vlan_info.mkex;\n-\tvolatile uint8_t *key_data, *key_mask;\n-\tstruct npc_mcam_read_entry_req *req;\n-\tstruct npc_mcam_read_entry_rsp *rsp;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tuint64_t mcam_data, mcam_mask;\n-\tstruct mcam_entry entry;\n-\tuint8_t intf, mcam_ena;\n-\tint idx, rc = -EINVAL;\n-\tuint8_t *mac_addr;\n-\n-\tmemset(&entry, 0, sizeof(struct mcam_entry));\n-\n-\t/* Read entry first */\n-\treq = otx2_mbox_alloc_msg_npc_mcam_read_entry(mbox);\n-\n-\treq->entry = mcam_index;\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to read entry %d\", mcam_index);\n-\t\treturn;\n-\t}\n-\n-\tentry = rsp->entry_data;\n-\tintf = rsp->intf;\n-\tmcam_ena = rsp->enable;\n-\n-\t/* Update mcam address */\n-\tkey_data = (volatile uint8_t *)entry.kw;\n-\tkey_mask = (volatile uint8_t *)entry.kw_mask;\n-\n-\tif (enable) {\n-\t\tmcam_mask = 0;\n-\t\totx2_mbox_memcpy(key_mask + mkex->la_xtract.key_off,\n-\t\t\t\t &mcam_mask, mkex->la_xtract.len + 1);\n-\n-\t} else {\n-\t\tmcam_data = 0ULL;\n-\t\tmac_addr = dev->mac_addr;\n-\t\tfor (idx = RTE_ETHER_ADDR_LEN - 1; idx >= 0; idx--)\n-\t\t\tmcam_data |= ((uint64_t)*mac_addr++) << (8 * idx);\n-\n-\t\tmcam_mask = BIT_ULL(48) - 1;\n-\n-\t\totx2_mbox_memcpy(key_data + mkex->la_xtract.key_off,\n-\t\t\t\t &mcam_data, mkex->la_xtract.len + 1);\n-\t\totx2_mbox_memcpy(key_mask + mkex->la_xtract.key_off,\n-\t\t\t\t &mcam_mask, mkex->la_xtract.len + 1);\n-\t}\n-\n-\t/* Write back the mcam entry */\n-\trc = nix_vlan_mcam_write(eth_dev, mcam_index,\n-\t\t\t\t &entry, intf, mcam_ena);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to write entry %d\", mcam_index);\n-\t\treturn;\n-\t}\n-}\n-\n-void\n-otx2_nix_vlan_update_promisc(struct rte_eth_dev *eth_dev, int enable)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_vlan_info *vlan = &dev->vlan_info;\n-\tstruct vlan_entry *entry;\n-\n-\t/* Already in required mode */\n-\tif (enable == vlan->promisc_on)\n-\t\treturn;\n-\n-\t/* Update default rx entry */\n-\tif (vlan->def_rx_mcam_idx)\n-\t\tnix_vlan_update_mac(eth_dev, vlan->def_rx_mcam_idx, enable);\n-\n-\t/* Update all other rx filter entries */\n-\tTAILQ_FOREACH(entry, &vlan->fltr_tbl, next)\n-\t\tnix_vlan_update_mac(eth_dev, entry->mcam_idx, enable);\n-\n-\tvlan->promisc_on = enable;\n-}\n-\n-/* Configure mcam entry with required MCAM search rules */\n-static int\n-nix_vlan_mcam_config(struct rte_eth_dev *eth_dev,\n-\t\t uint16_t vlan_id, uint16_t flags)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct vlan_mkex_info *mkex = &dev->vlan_info.mkex;\n-\tvolatile uint8_t *key_data, *key_mask;\n-\tuint64_t mcam_data, mcam_mask;\n-\tstruct mcam_entry entry;\n-\tuint8_t *mac_addr;\n-\tint idx, kwi = 0;\n-\n-\tmemset(&entry, 0, sizeof(struct mcam_entry));\n-\tkey_data = (volatile uint8_t *)entry.kw;\n-\tkey_mask = (volatile uint8_t *)entry.kw_mask;\n-\n-\t/* Channel base extracted to KW0[11:0] */\n-\tentry.kw[kwi] = dev->rx_chan_base;\n-\tentry.kw_mask[kwi] = BIT_ULL(12) - 1;\n-\n-\t/* Adds vlan_id & LB CTAG flag to MCAM KW */\n-\tif (flags & VLAN_ID_MATCH) {\n-\t\tentry.kw[kwi] |= (NPC_LT_LB_CTAG | NPC_LT_LB_STAG_QINQ)\n-\t\t\t\t\t\t\t<< mkex->lb_lt_offset;\n-\t\tentry.kw_mask[kwi] |=\n-\t\t\t(0xF & ~(NPC_LT_LB_CTAG ^ NPC_LT_LB_STAG_QINQ))\n-\t\t\t\t\t\t\t<< mkex->lb_lt_offset;\n-\n-\t\tmcam_data = (uint16_t)vlan_id;\n-\t\tmcam_mask = (BIT_ULL(16) - 1);\n-\t\totx2_mbox_memcpy(key_data + mkex->lb_xtract.key_off,\n-\t\t\t\t &mcam_data, mkex->lb_xtract.len);\n-\t\totx2_mbox_memcpy(key_mask + mkex->lb_xtract.key_off,\n-\t\t\t\t &mcam_mask, mkex->lb_xtract.len);\n-\t}\n-\n-\t/* Adds LB STAG flag to MCAM KW */\n-\tif (flags & QINQ_F_MATCH) {\n-\t\tentry.kw[kwi] |= NPC_LT_LB_STAG_QINQ << mkex->lb_lt_offset;\n-\t\tentry.kw_mask[kwi] |= 0xFULL << mkex->lb_lt_offset;\n-\t}\n-\n-\t/* Adds LB CTAG & LB STAG flags to MCAM KW */\n-\tif (flags & VTAG_F_MATCH) {\n-\t\tentry.kw[kwi] |= (NPC_LT_LB_CTAG | NPC_LT_LB_STAG_QINQ)\n-\t\t\t\t\t\t\t<< mkex->lb_lt_offset;\n-\t\tentry.kw_mask[kwi] |=\n-\t\t\t(0xF & ~(NPC_LT_LB_CTAG ^ NPC_LT_LB_STAG_QINQ))\n-\t\t\t\t\t\t\t<< mkex->lb_lt_offset;\n-\t}\n-\n-\t/* Adds port MAC address to MCAM KW */\n-\tif (flags & MAC_ADDR_MATCH) {\n-\t\tmcam_data = 0ULL;\n-\t\tmac_addr = dev->mac_addr;\n-\t\tfor (idx = RTE_ETHER_ADDR_LEN - 1; idx >= 0; idx--)\n-\t\t\tmcam_data |= ((uint64_t)*mac_addr++) << (8 * idx);\n-\n-\t\tmcam_mask = BIT_ULL(48) - 1;\n-\t\totx2_mbox_memcpy(key_data + mkex->la_xtract.key_off,\n-\t\t\t\t &mcam_data, mkex->la_xtract.len + 1);\n-\t\totx2_mbox_memcpy(key_mask + mkex->la_xtract.key_off,\n-\t\t\t\t &mcam_mask, mkex->la_xtract.len + 1);\n-\t}\n-\n-\t/* VLAN_DROP: for drop action for all vlan packets when filter is on.\n-\t * For QinQ, enable vtag action for both outer & inner tags\n-\t */\n-\tif (flags & VLAN_DROP)\n-\t\tnix_set_rx_vlan_action(eth_dev, &entry, false, true);\n-\telse if (flags & QINQ_F_MATCH)\n-\t\tnix_set_rx_vlan_action(eth_dev, &entry, true, false);\n-\telse\n-\t\tnix_set_rx_vlan_action(eth_dev, &entry, false, false);\n-\n-\tif (flags & DEF_F_ENTRY)\n-\t\tdev->vlan_info.def_rx_mcam_ent = entry;\n-\n-\treturn nix_vlan_mcam_alloc_and_write(eth_dev, &entry, NIX_INTF_RX,\n-\t\t\t\t\t flags & VLAN_DROP);\n-}\n-\n-/* Installs/Removes/Modifies default rx entry */\n-static int\n-nix_vlan_handle_default_rx_entry(struct rte_eth_dev *eth_dev, bool strip,\n-\t\t\t\t bool filter, bool enable)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_vlan_info *vlan = &dev->vlan_info;\n-\tuint16_t flags = 0;\n-\tint mcam_idx, rc;\n-\n-\t/* Use default mcam entry to either drop vlan traffic when\n-\t * vlan filter is on or strip vtag when strip is enabled.\n-\t * Allocate default entry which matches port mac address\n-\t * and vtag(ctag/stag) flags with drop action.\n-\t */\n-\tif (!vlan->def_rx_mcam_idx) {\n-\t\tif (!eth_dev->data->promiscuous)\n-\t\t\tflags = MAC_ADDR_MATCH;\n-\n-\t\tif (filter && enable)\n-\t\t\tflags |= VTAG_F_MATCH | VLAN_DROP;\n-\t\telse if (strip && enable)\n-\t\t\tflags |= VTAG_F_MATCH;\n-\t\telse\n-\t\t\treturn 0;\n-\n-\t\tflags |= DEF_F_ENTRY;\n-\n-\t\tmcam_idx = nix_vlan_mcam_config(eth_dev, 0, flags);\n-\t\tif (mcam_idx < 0) {\n-\t\t\totx2_err(\"Failed to config vlan mcam\");\n-\t\t\treturn -mcam_idx;\n-\t\t}\n-\n-\t\tvlan->def_rx_mcam_idx = mcam_idx;\n-\t\treturn 0;\n-\t}\n-\n-\t/* Filter is already enabled, so packets would be dropped anyways. No\n-\t * processing needed for enabling strip wrt mcam entry.\n-\t */\n-\n-\t/* Filter disable request */\n-\tif (vlan->filter_on && filter && !enable) {\n-\t\tvlan->def_rx_mcam_ent.action &= ~((uint64_t)0xF);\n-\n-\t\t/* Free default rx entry only when\n-\t\t * 1. strip is not on and\n-\t\t * 2. qinq entry is allocated before default entry.\n-\t\t */\n-\t\tif (vlan->strip_on ||\n-\t\t (vlan->qinq_on && !vlan->qinq_before_def)) {\n-\t\t\tif (eth_dev->data->dev_conf.rxmode.mq_mode ==\n-\t\t\t\t\t\t\t\tRTE_ETH_MQ_RX_RSS)\n-\t\t\t\tvlan->def_rx_mcam_ent.action |=\n-\t\t\t\t\t\t\tNIX_RX_ACTIONOP_RSS;\n-\t\t\telse\n-\t\t\t\tvlan->def_rx_mcam_ent.action |=\n-\t\t\t\t\t\t\tNIX_RX_ACTIONOP_UCAST;\n-\t\t\treturn nix_vlan_mcam_write(eth_dev,\n-\t\t\t\t\t\t vlan->def_rx_mcam_idx,\n-\t\t\t\t\t\t &vlan->def_rx_mcam_ent,\n-\t\t\t\t\t\t NIX_INTF_RX, 1);\n-\t\t} else {\n-\t\t\trc = nix_vlan_mcam_free(dev, vlan->def_rx_mcam_idx);\n-\t\t\tif (rc)\n-\t\t\t\treturn rc;\n-\t\t\tvlan->def_rx_mcam_idx = 0;\n-\t\t}\n-\t}\n-\n-\t/* Filter enable request */\n-\tif (!vlan->filter_on && filter && enable) {\n-\t\tvlan->def_rx_mcam_ent.action &= ~((uint64_t)0xF);\n-\t\tvlan->def_rx_mcam_ent.action |= NIX_RX_ACTIONOP_DROP;\n-\t\treturn nix_vlan_mcam_write(eth_dev, vlan->def_rx_mcam_idx,\n-\t\t\t\t &vlan->def_rx_mcam_ent, NIX_INTF_RX, 1);\n-\t}\n-\n-\t/* Strip disable request */\n-\tif (vlan->strip_on && strip && !enable) {\n-\t\tif (!vlan->filter_on &&\n-\t\t !(vlan->qinq_on && !vlan->qinq_before_def)) {\n-\t\t\trc = nix_vlan_mcam_free(dev, vlan->def_rx_mcam_idx);\n-\t\t\tif (rc)\n-\t\t\t\treturn rc;\n-\t\t\tvlan->def_rx_mcam_idx = 0;\n-\t\t}\n-\t}\n-\n-\treturn 0;\n-}\n-\n-/* Installs/Removes default tx entry */\n-static int\n-nix_vlan_handle_default_tx_entry(struct rte_eth_dev *eth_dev,\n-\t\t\t\t enum rte_vlan_type type, int vtag_index,\n-\t\t\t\t int enable)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_vlan_info *vlan = &dev->vlan_info;\n-\tstruct mcam_entry entry;\n-\tuint16_t pf_func;\n-\tint rc;\n-\n-\tif (!vlan->def_tx_mcam_idx && enable) {\n-\t\tmemset(&entry, 0, sizeof(struct mcam_entry));\n-\n-\t\t/* Only pf_func is matched, swap it's bytes */\n-\t\tpf_func = (dev->pf_func & 0xff) << 8;\n-\t\tpf_func |= (dev->pf_func >> 8) & 0xff;\n-\n-\t\t/* PF Func extracted to KW1[47:32] */\n-\t\tentry.kw[0] = (uint64_t)pf_func << 32;\n-\t\tentry.kw_mask[0] = (BIT_ULL(16) - 1) << 32;\n-\n-\t\tnix_set_tx_vlan_action(&entry, type, vtag_index);\n-\t\tvlan->def_tx_mcam_ent = entry;\n-\n-\t\treturn nix_vlan_mcam_alloc_and_write(eth_dev, &entry,\n-\t\t\t\t\t\t NIX_INTF_TX, 0);\n-\t}\n-\n-\tif (vlan->def_tx_mcam_idx && !enable) {\n-\t\trc = nix_vlan_mcam_free(dev, vlan->def_tx_mcam_idx);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\t\tvlan->def_rx_mcam_idx = 0;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-/* Configure vlan stripping on or off */\n-static int\n-nix_vlan_hw_strip(struct rte_eth_dev *eth_dev, const uint8_t enable)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tstruct nix_vtag_config *vtag_cfg;\n-\tint rc = -EINVAL;\n-\n-\trc = nix_vlan_handle_default_rx_entry(eth_dev, true, false, enable);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to config default rx entry\");\n-\t\treturn rc;\n-\t}\n-\n-\tvtag_cfg = otx2_mbox_alloc_msg_nix_vtag_cfg(mbox);\n-\t/* cfg_type = 1 for rx vlan cfg */\n-\tvtag_cfg->cfg_type = VTAG_RX;\n-\n-\tif (enable)\n-\t\tvtag_cfg->rx.strip_vtag = 1;\n-\telse\n-\t\tvtag_cfg->rx.strip_vtag = 0;\n-\n-\t/* Always capture */\n-\tvtag_cfg->rx.capture_vtag = 1;\n-\tvtag_cfg->vtag_size = NIX_VTAGSIZE_T4;\n-\t/* Use rx vtag type index[0] for now */\n-\tvtag_cfg->rx.vtag_type = 0;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tdev->vlan_info.strip_on = enable;\n-\treturn rc;\n-}\n-\n-/* Configure vlan filtering on or off for all vlans if vlan_id == 0 */\n-static int\n-nix_vlan_hw_filter(struct rte_eth_dev *eth_dev, const uint8_t enable,\n-\t\t uint16_t vlan_id)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_vlan_info *vlan = &dev->vlan_info;\n-\tstruct vlan_entry *entry;\n-\tint rc = -EINVAL;\n-\n-\tif (!vlan_id && enable) {\n-\t\trc = nix_vlan_handle_default_rx_entry(eth_dev, false, true,\n-\t\t\t\t\t\t enable);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to config vlan mcam\");\n-\t\t\treturn rc;\n-\t\t}\n-\t\tdev->vlan_info.filter_on = enable;\n-\t\treturn 0;\n-\t}\n-\n-\t/* Enable/disable existing vlan filter entries */\n-\tTAILQ_FOREACH(entry, &vlan->fltr_tbl, next) {\n-\t\tif (vlan_id) {\n-\t\t\tif (entry->vlan_id == vlan_id) {\n-\t\t\t\trc = nix_vlan_mcam_enb_dis(dev,\n-\t\t\t\t\t\t\t entry->mcam_idx,\n-\t\t\t\t\t\t\t enable);\n-\t\t\t\tif (rc)\n-\t\t\t\t\treturn rc;\n-\t\t\t}\n-\t\t} else {\n-\t\t\trc = nix_vlan_mcam_enb_dis(dev, entry->mcam_idx,\n-\t\t\t\t\t\t enable);\n-\t\t\tif (rc)\n-\t\t\t\treturn rc;\n-\t\t}\n-\t}\n-\n-\tif (!vlan_id && !enable) {\n-\t\trc = nix_vlan_handle_default_rx_entry(eth_dev, false, true,\n-\t\t\t\t\t\t enable);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to config vlan mcam\");\n-\t\t\treturn rc;\n-\t\t}\n-\t\tdev->vlan_info.filter_on = enable;\n-\t\treturn 0;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-/* Enable/disable vlan filtering for the given vlan_id */\n-int\n-otx2_nix_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id,\n-\t\t\t int on)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_vlan_info *vlan = &dev->vlan_info;\n-\tstruct vlan_entry *entry;\n-\tint entry_exists = 0;\n-\tint rc = -EINVAL;\n-\tint mcam_idx;\n-\n-\tif (!vlan_id) {\n-\t\totx2_err(\"Vlan Id can't be zero\");\n-\t\treturn rc;\n-\t}\n-\n-\tif (!vlan->def_rx_mcam_idx) {\n-\t\totx2_err(\"Vlan Filtering is disabled, enable it first\");\n-\t\treturn rc;\n-\t}\n-\n-\tif (on) {\n-\t\tTAILQ_FOREACH(entry, &vlan->fltr_tbl, next) {\n-\t\t\tif (entry->vlan_id == vlan_id) {\n-\t\t\t\t/* Vlan entry already exists */\n-\t\t\t\tentry_exists = 1;\n-\t\t\t\t/* Mcam entry already allocated */\n-\t\t\t\tif (entry->mcam_idx) {\n-\t\t\t\t\trc = nix_vlan_hw_filter(eth_dev, on,\n-\t\t\t\t\t\t\t\tvlan_id);\n-\t\t\t\t\treturn rc;\n-\t\t\t\t}\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\n-\t\tif (!entry_exists) {\n-\t\t\tentry = rte_zmalloc(\"otx2_nix_vlan_entry\",\n-\t\t\t\t\t sizeof(struct vlan_entry), 0);\n-\t\t\tif (!entry) {\n-\t\t\t\totx2_err(\"Failed to allocate memory\");\n-\t\t\t\treturn -ENOMEM;\n-\t\t\t}\n-\t\t}\n-\n-\t\t/* Enables vlan_id & mac address based filtering */\n-\t\tif (eth_dev->data->promiscuous)\n-\t\t\tmcam_idx = nix_vlan_mcam_config(eth_dev, vlan_id,\n-\t\t\t\t\t\t\tVLAN_ID_MATCH);\n-\t\telse\n-\t\t\tmcam_idx = nix_vlan_mcam_config(eth_dev, vlan_id,\n-\t\t\t\t\t\t\tVLAN_ID_MATCH |\n-\t\t\t\t\t\t\tMAC_ADDR_MATCH);\n-\t\tif (mcam_idx < 0) {\n-\t\t\totx2_err(\"Failed to config vlan mcam\");\n-\t\t\tTAILQ_REMOVE(&vlan->fltr_tbl, entry, next);\n-\t\t\trte_free(entry);\n-\t\t\treturn mcam_idx;\n-\t\t}\n-\n-\t\tentry->mcam_idx = mcam_idx;\n-\t\tif (!entry_exists) {\n-\t\t\tentry->vlan_id = vlan_id;\n-\t\t\tTAILQ_INSERT_HEAD(&vlan->fltr_tbl, entry, next);\n-\t\t}\n-\t} else {\n-\t\tTAILQ_FOREACH(entry, &vlan->fltr_tbl, next) {\n-\t\t\tif (entry->vlan_id == vlan_id) {\n-\t\t\t\trc = nix_vlan_mcam_free(dev, entry->mcam_idx);\n-\t\t\t\tif (rc)\n-\t\t\t\t\treturn rc;\n-\t\t\t\tTAILQ_REMOVE(&vlan->fltr_tbl, entry, next);\n-\t\t\t\trte_free(entry);\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t}\n-\t}\n-\treturn 0;\n-}\n-\n-/* Configure double vlan(qinq) on or off */\n-static int\n-otx2_nix_config_double_vlan(struct rte_eth_dev *eth_dev,\n-\t\t\t const uint8_t enable)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_vlan_info *vlan_info;\n-\tint mcam_idx;\n-\tint rc;\n-\n-\tvlan_info = &dev->vlan_info;\n-\n-\tif (!enable) {\n-\t\tif (!vlan_info->qinq_mcam_idx)\n-\t\t\treturn 0;\n-\n-\t\trc = nix_vlan_mcam_free(dev, vlan_info->qinq_mcam_idx);\n-\t\tif (rc)\n-\t\t\treturn rc;\n-\n-\t\tvlan_info->qinq_mcam_idx = 0;\n-\t\tdev->vlan_info.qinq_on = 0;\n-\t\tvlan_info->qinq_before_def = 0;\n-\t\treturn 0;\n-\t}\n-\n-\tif (eth_dev->data->promiscuous)\n-\t\tmcam_idx = nix_vlan_mcam_config(eth_dev, 0, QINQ_F_MATCH);\n-\telse\n-\t\tmcam_idx = nix_vlan_mcam_config(eth_dev, 0,\n-\t\t\t\t\t\tQINQ_F_MATCH | MAC_ADDR_MATCH);\n-\tif (mcam_idx < 0)\n-\t\treturn mcam_idx;\n-\n-\tif (!vlan_info->def_rx_mcam_idx)\n-\t\tvlan_info->qinq_before_def = 1;\n-\n-\tvlan_info->qinq_mcam_idx = mcam_idx;\n-\tdev->vlan_info.qinq_on = 1;\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tuint64_t offloads = dev->rx_offloads;\n-\tstruct rte_eth_rxmode *rxmode;\n-\tint rc = 0;\n-\n-\trxmode = ð_dev->data->dev_conf.rxmode;\n-\n-\tif (mask & RTE_ETH_VLAN_STRIP_MASK) {\n-\t\tif (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) {\n-\t\t\toffloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;\n-\t\t\trc = nix_vlan_hw_strip(eth_dev, true);\n-\t\t} else {\n-\t\t\toffloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP;\n-\t\t\trc = nix_vlan_hw_strip(eth_dev, false);\n-\t\t}\n-\t\tif (rc)\n-\t\t\tgoto done;\n-\t}\n-\n-\tif (mask & RTE_ETH_VLAN_FILTER_MASK) {\n-\t\tif (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) {\n-\t\t\toffloads |= RTE_ETH_RX_OFFLOAD_VLAN_FILTER;\n-\t\t\trc = nix_vlan_hw_filter(eth_dev, true, 0);\n-\t\t} else {\n-\t\t\toffloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_FILTER;\n-\t\t\trc = nix_vlan_hw_filter(eth_dev, false, 0);\n-\t\t}\n-\t\tif (rc)\n-\t\t\tgoto done;\n-\t}\n-\n-\tif (rxmode->offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP) {\n-\t\tif (!dev->vlan_info.qinq_on) {\n-\t\t\toffloads |= RTE_ETH_RX_OFFLOAD_QINQ_STRIP;\n-\t\t\trc = otx2_nix_config_double_vlan(eth_dev, true);\n-\t\t\tif (rc)\n-\t\t\t\tgoto done;\n-\t\t}\n-\t} else {\n-\t\tif (dev->vlan_info.qinq_on) {\n-\t\t\toffloads &= ~RTE_ETH_RX_OFFLOAD_QINQ_STRIP;\n-\t\t\trc = otx2_nix_config_double_vlan(eth_dev, false);\n-\t\t\tif (rc)\n-\t\t\t\tgoto done;\n-\t\t}\n-\t}\n-\n-\tif (offloads & (RTE_ETH_RX_OFFLOAD_VLAN_STRIP |\n-\t\t\tRTE_ETH_RX_OFFLOAD_QINQ_STRIP)) {\n-\t\tdev->rx_offloads |= offloads;\n-\t\tdev->rx_offload_flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;\n-\t\totx2_eth_set_rx_function(eth_dev);\n-\t}\n-\n-done:\n-\treturn rc;\n-}\n-\n-int\n-otx2_nix_vlan_tpid_set(struct rte_eth_dev *eth_dev,\n-\t\t enum rte_vlan_type type, uint16_t tpid)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct nix_set_vlan_tpid *tpid_cfg;\n-\tstruct otx2_mbox *mbox = dev->mbox;\n-\tint rc;\n-\n-\ttpid_cfg = otx2_mbox_alloc_msg_nix_set_vlan_tpid(mbox);\n-\n-\ttpid_cfg->tpid = tpid;\n-\tif (type == RTE_ETH_VLAN_TYPE_OUTER)\n-\t\ttpid_cfg->vlan_type = NIX_VLAN_TYPE_OUTER;\n-\telse\n-\t\ttpid_cfg->vlan_type = NIX_VLAN_TYPE_INNER;\n-\n-\trc = otx2_mbox_process(mbox);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tif (type == RTE_ETH_VLAN_TYPE_OUTER)\n-\t\tdev->vlan_info.outer_vlan_tpid = tpid;\n-\telse\n-\t\tdev->vlan_info.inner_vlan_tpid = tpid;\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)\n-{\n-\tstruct otx2_eth_dev *otx2_dev = otx2_eth_pmd_priv(dev);\n-\tstruct otx2_mbox *mbox = otx2_dev->mbox;\n-\tstruct nix_vtag_config *vtag_cfg;\n-\tstruct nix_vtag_config_rsp *rsp;\n-\tstruct otx2_vlan_info *vlan;\n-\tint rc, rc1, vtag_index = 0;\n-\n-\tif (vlan_id == 0) {\n-\t\totx2_err(\"vlan id can't be zero\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tvlan = &otx2_dev->vlan_info;\n-\n-\tif (on && vlan->pvid_insert_on && vlan->pvid == vlan_id) {\n-\t\totx2_err(\"pvid %d is already enabled\", vlan_id);\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tif (on && vlan->pvid_insert_on && vlan->pvid != vlan_id) {\n-\t\totx2_err(\"another pvid is enabled, disable that first\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* No pvid active */\n-\tif (!on && !vlan->pvid_insert_on)\n-\t\treturn 0;\n-\n-\t/* Given pvid already disabled */\n-\tif (!on && vlan->pvid != vlan_id)\n-\t\treturn 0;\n-\n-\tvtag_cfg = otx2_mbox_alloc_msg_nix_vtag_cfg(mbox);\n-\n-\tif (on) {\n-\t\tvtag_cfg->cfg_type = VTAG_TX;\n-\t\tvtag_cfg->vtag_size = NIX_VTAGSIZE_T4;\n-\n-\t\tif (vlan->outer_vlan_tpid)\n-\t\t\tvtag_cfg->tx.vtag0 = ((uint32_t)vlan->outer_vlan_tpid\n-\t\t\t\t\t << 16) | vlan_id;\n-\t\telse\n-\t\t\tvtag_cfg->tx.vtag0 =\n-\t\t\t\t((RTE_ETHER_TYPE_VLAN << 16) | vlan_id);\n-\t\tvtag_cfg->tx.cfg_vtag0 = 1;\n-\t} else {\n-\t\tvtag_cfg->cfg_type = VTAG_TX;\n-\t\tvtag_cfg->vtag_size = NIX_VTAGSIZE_T4;\n-\n-\t\tvtag_cfg->tx.vtag0_idx = vlan->outer_vlan_idx;\n-\t\tvtag_cfg->tx.free_vtag0 = 1;\n-\t}\n-\n-\trc = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tif (on) {\n-\t\tvtag_index = rsp->vtag0_idx;\n-\t} else {\n-\t\tvlan->pvid = 0;\n-\t\tvlan->pvid_insert_on = 0;\n-\t\tvlan->outer_vlan_idx = 0;\n-\t}\n-\n-\trc = nix_vlan_handle_default_tx_entry(dev, RTE_ETH_VLAN_TYPE_OUTER,\n-\t\t\t\t\t vtag_index, on);\n-\tif (rc < 0) {\n-\t\tprintf(\"Default tx entry failed with rc %d\\n\", rc);\n-\t\tvtag_cfg->tx.vtag0_idx = vtag_index;\n-\t\tvtag_cfg->tx.free_vtag0 = 1;\n-\t\tvtag_cfg->tx.cfg_vtag0 = 0;\n-\n-\t\trc1 = otx2_mbox_process_msg(mbox, (void *)&rsp);\n-\t\tif (rc1)\n-\t\t\totx2_err(\"Vtag free failed\");\n-\n-\t\treturn rc;\n-\t}\n-\n-\tif (on) {\n-\t\tvlan->pvid = vlan_id;\n-\t\tvlan->pvid_insert_on = 1;\n-\t\tvlan->outer_vlan_idx = vtag_index;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-void otx2_nix_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,\n-\t\t\t\t __rte_unused uint16_t queue,\n-\t\t\t\t __rte_unused int on)\n-{\n-\totx2_err(\"Not Supported\");\n-}\n-\n-static int\n-nix_vlan_rx_mkex_offset(uint64_t mask)\n-{\n-\tint nib_count = 0;\n-\n-\twhile (mask) {\n-\t\tnib_count += mask & 1;\n-\t\tmask >>= 1;\n-\t}\n-\n-\treturn nib_count * 4;\n-}\n-\n-static int\n-nix_vlan_get_mkex_info(struct otx2_eth_dev *dev)\n-{\n-\tstruct vlan_mkex_info *mkex = &dev->vlan_info.mkex;\n-\tstruct otx2_npc_flow_info *npc = &dev->npc_flow;\n-\tstruct npc_xtract_info *x_info = NULL;\n-\tuint64_t rx_keyx;\n-\totx2_dxcfg_t *p;\n-\tint rc = -EINVAL;\n-\n-\tif (npc == NULL) {\n-\t\totx2_err(\"Missing npc mkex configuration\");\n-\t\treturn rc;\n-\t}\n-\n-#define NPC_KEX_CHAN_NIBBLE_ENA\t\t\t0x7ULL\n-#define NPC_KEX_LB_LTYPE_NIBBLE_ENA\t\t0x1000ULL\n-#define NPC_KEX_LB_LTYPE_NIBBLE_MASK\t\t0xFFFULL\n-\n-\trx_keyx = npc->keyx_supp_nmask[NPC_MCAM_RX];\n-\tif ((rx_keyx & NPC_KEX_CHAN_NIBBLE_ENA) != NPC_KEX_CHAN_NIBBLE_ENA)\n-\t\treturn rc;\n-\n-\tif ((rx_keyx & NPC_KEX_LB_LTYPE_NIBBLE_ENA) !=\n-\t NPC_KEX_LB_LTYPE_NIBBLE_ENA)\n-\t\treturn rc;\n-\n-\tmkex->lb_lt_offset =\n-\t nix_vlan_rx_mkex_offset(rx_keyx & NPC_KEX_LB_LTYPE_NIBBLE_MASK);\n-\n-\tp = &npc->prx_dxcfg;\n-\tx_info = &(*p)[NPC_MCAM_RX][NPC_LID_LA][NPC_LT_LA_ETHER].xtract[0];\n-\tmemcpy(&mkex->la_xtract, x_info, sizeof(struct npc_xtract_info));\n-\tx_info = &(*p)[NPC_MCAM_RX][NPC_LID_LB][NPC_LT_LB_CTAG].xtract[0];\n-\tmemcpy(&mkex->lb_xtract, x_info, sizeof(struct npc_xtract_info));\n-\n-\treturn 0;\n-}\n-\n-static void nix_vlan_reinstall_vlan_filters(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct vlan_entry *entry;\n-\tint rc;\n-\n-\t/* VLAN filters can't be set without setting filtern on */\n-\trc = nix_vlan_handle_default_rx_entry(eth_dev, false, true, true);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to reinstall vlan filters\");\n-\t\treturn;\n-\t}\n-\n-\tTAILQ_FOREACH(entry, &dev->vlan_info.fltr_tbl, next) {\n-\t\trc = otx2_nix_vlan_filter_set(eth_dev, entry->vlan_id, true);\n-\t\tif (rc)\n-\t\t\totx2_err(\"Failed to reinstall filter for vlan:%d\",\n-\t\t\t\t entry->vlan_id);\n-\t}\n-}\n-\n-int\n-otx2_nix_vlan_offload_init(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tint rc, mask;\n-\n-\t/* Port initialized for first time or restarted */\n-\tif (!dev->configured) {\n-\t\trc = nix_vlan_get_mkex_info(dev);\n-\t\tif (rc) {\n-\t\t\totx2_err(\"Failed to get vlan mkex info rc=%d\", rc);\n-\t\t\treturn rc;\n-\t\t}\n-\n-\t\tTAILQ_INIT(&dev->vlan_info.fltr_tbl);\n-\t} else {\n-\t\t/* Reinstall all mcam entries now if filter offload is set */\n-\t\tif (eth_dev->data->dev_conf.rxmode.offloads &\n-\t\t RTE_ETH_RX_OFFLOAD_VLAN_FILTER)\n-\t\t\tnix_vlan_reinstall_vlan_filters(eth_dev);\n-\t}\n-\n-\tmask =\n-\t RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK;\n-\trc = otx2_nix_vlan_offload_set(eth_dev, mask);\n-\tif (rc) {\n-\t\totx2_err(\"Failed to set vlan offload rc=%d\", rc);\n-\t\treturn rc;\n-\t}\n-\n-\treturn 0;\n-}\n-\n-int\n-otx2_nix_vlan_fini(struct rte_eth_dev *eth_dev)\n-{\n-\tstruct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);\n-\tstruct otx2_vlan_info *vlan = &dev->vlan_info;\n-\tstruct vlan_entry *entry;\n-\tint rc;\n-\n-\tTAILQ_FOREACH(entry, &vlan->fltr_tbl, next) {\n-\t\tif (!dev->configured) {\n-\t\t\tTAILQ_REMOVE(&vlan->fltr_tbl, entry, next);\n-\t\t\trte_free(entry);\n-\t\t} else {\n-\t\t\t/* MCAM entries freed by flow_fini & lf_free on\n-\t\t\t * port stop.\n-\t\t\t */\n-\t\t\tentry->mcam_idx = 0;\n-\t\t}\n-\t}\n-\n-\tif (!dev->configured) {\n-\t\tif (vlan->def_rx_mcam_idx) {\n-\t\t\trc = nix_vlan_mcam_free(dev, vlan->def_rx_mcam_idx);\n-\t\t\tif (rc)\n-\t\t\t\treturn rc;\n-\t\t}\n-\t}\n-\n-\totx2_nix_config_double_vlan(eth_dev, false);\n-\tvlan->def_rx_mcam_idx = 0;\n-\treturn 0;\n-}\ndiff --git a/drivers/net/octeontx2/version.map b/drivers/net/octeontx2/version.map\ndeleted file mode 100644\nindex c2e0723b4c..0000000000\n--- a/drivers/net/octeontx2/version.map\n+++ /dev/null\n@@ -1,3 +0,0 @@\n-DPDK_22 {\n-\tlocal: *;\n-};\ndiff --git a/drivers/net/octeontx_ep/otx2_ep_vf.h b/drivers/net/octeontx_ep/otx2_ep_vf.h\nindex 9326925025..dc720368ab 100644\n--- a/drivers/net/octeontx_ep/otx2_ep_vf.h\n+++ b/drivers/net/octeontx_ep/otx2_ep_vf.h\n@@ -113,7 +113,7 @@\n #define otx2_read64(addr) rte_read64_relaxed((void *)(addr))\n #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))\n \n-#define PCI_DEVID_OCTEONTX2_EP_NET_VF\t\t0xB203 /* OCTEON TX2 EP mode */\n+#define PCI_DEVID_CN9K_EP_NET_VF\t\t0xB203 /* OCTEON 9 EP mode */\n #define PCI_DEVID_CN98XX_EP_NET_VF\t\t0xB103\n \n int\ndiff --git a/drivers/net/octeontx_ep/otx_ep_common.h b/drivers/net/octeontx_ep/otx_ep_common.h\nindex fd5e8ed263..8a59a1a194 100644\n--- a/drivers/net/octeontx_ep/otx_ep_common.h\n+++ b/drivers/net/octeontx_ep/otx_ep_common.h\n@@ -150,7 +150,7 @@ struct otx_ep_iq_config {\n \n /** The instruction (input) queue.\n * The input queue is used to post raw (instruction) mode data or packet data\n- * to OCTEON TX2 device from the host. Each IQ of a OTX_EP EP VF device has one\n+ * to OCTEON 9 device from the host. Each IQ of a OTX_EP EP VF device has one\n * such structure to represent it.\n */\n struct otx_ep_instr_queue {\n@@ -170,12 +170,12 @@ struct otx_ep_instr_queue {\n \t/* Input ring index, where the driver should write the next packet */\n \tuint32_t host_write_index;\n \n-\t/* Input ring index, where the OCTEON TX2 should read the next packet */\n+\t/* Input ring index, where the OCTEON 9 should read the next packet */\n \tuint32_t otx_read_index;\n \n \tuint32_t reset_instr_cnt;\n \n-\t/** This index aids in finding the window in the queue where OCTEON TX2\n+\t/** This index aids in finding the window in the queue where OCTEON 9\n \t * has read the commands.\n \t */\n \tuint32_t flush_index;\n@@ -195,7 +195,7 @@ struct otx_ep_instr_queue {\n \t/* OTX_EP instruction count register for this ring. */\n \tvoid *inst_cnt_reg;\n \n-\t/* Number of instructions pending to be posted to OCTEON TX2. */\n+\t/* Number of instructions pending to be posted to OCTEON 9. */\n \tuint32_t fill_cnt;\n \n \t/* Statistics for this input queue. */\n@@ -230,8 +230,8 @@ union otx_ep_rh {\n };\n #define OTX_EP_RH_SIZE (sizeof(union otx_ep_rh))\n \n-/** Information about packet DMA'ed by OCTEON TX2.\n- * The format of the information available at Info Pointer after OCTEON TX2\n+/** Information about packet DMA'ed by OCTEON 9.\n+ * The format of the information available at Info Pointer after OCTEON 9\n * has posted a packet. Not all descriptors have valid information. Only\n * the Info field of the first descriptor for a packet has information\n * about the packet.\n@@ -295,7 +295,7 @@ struct otx_ep_droq {\n \t/* Driver should read the next packet at this index */\n \tuint32_t read_idx;\n \n-\t/* OCTEON TX2 will write the next packet at this index */\n+\t/* OCTEON 9 will write the next packet at this index */\n \tuint32_t write_idx;\n \n \t/* At this index, the driver will refill the descriptor's buffer */\n@@ -326,7 +326,7 @@ struct otx_ep_droq {\n \t */\n \tvoid *pkts_credit_reg;\n \n-\t/** Pointer to the mapped packet sent register. OCTEON TX2 writes the\n+\t/** Pointer to the mapped packet sent register. OCTEON 9 writes the\n \t * number of packets DMA'ed to host memory in this register.\n \t */\n \tvoid *pkts_sent_reg;\ndiff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c\nindex c3cec6d833..806add246b 100644\n--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c\n+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c\n@@ -102,7 +102,7 @@ otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)\n \t\tret = otx_ep_vf_setup_device(otx_epvf);\n \t\totx_epvf->fn_list.disable_io_queues(otx_epvf);\n \t\tbreak;\n-\tcase PCI_DEVID_OCTEONTX2_EP_NET_VF:\n+\tcase PCI_DEVID_CN9K_EP_NET_VF:\n \tcase PCI_DEVID_CN98XX_EP_NET_VF:\n \t\totx_epvf->chip_id = dev_id;\n \t\tret = otx2_ep_vf_setup_device(otx_epvf);\n@@ -137,7 +137,7 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)\n \totx_epvf->eth_dev->rx_pkt_burst = &otx_ep_recv_pkts;\n \tif (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF)\n \t\totx_epvf->eth_dev->tx_pkt_burst = &otx_ep_xmit_pkts;\n-\telse if (otx_epvf->chip_id == PCI_DEVID_OCTEONTX2_EP_NET_VF ||\n+\telse if (otx_epvf->chip_id == PCI_DEVID_CN9K_EP_NET_VF ||\n \t\t otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF)\n \t\totx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;\n \tethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);\n@@ -422,7 +422,7 @@ otx_ep_eth_dev_init(struct rte_eth_dev *eth_dev)\n \totx_epvf->pdev = pdev;\n \n \totx_epdev_init(otx_epvf);\n-\tif (pdev->id.device_id == PCI_DEVID_OCTEONTX2_EP_NET_VF)\n+\tif (pdev->id.device_id == PCI_DEVID_CN9K_EP_NET_VF)\n \t\totx_epvf->pkind = SDP_OTX2_PKIND;\n \telse\n \t\totx_epvf->pkind = SDP_PKIND;\n@@ -450,7 +450,7 @@ otx_ep_eth_dev_pci_remove(struct rte_pci_device *pci_dev)\n /* Set of PCI devices this driver supports */\n static const struct rte_pci_id pci_id_otx_ep_map[] = {\n \t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX_EP_VF) },\n-\t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_EP_NET_VF) },\n+\t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_EP_NET_VF) },\n \t{ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN98XX_EP_NET_VF) },\n \t{ .vendor_id = 0, /* sentinel */ }\n };\ndiff --git a/drivers/net/octeontx_ep/otx_ep_rxtx.c b/drivers/net/octeontx_ep/otx_ep_rxtx.c\nindex 9338b30672..59df6ad857 100644\n--- a/drivers/net/octeontx_ep/otx_ep_rxtx.c\n+++ b/drivers/net/octeontx_ep/otx_ep_rxtx.c\n@@ -85,7 +85,7 @@ otx_ep_init_instr_queue(struct otx_ep_device *otx_ep, int iq_no, int num_descs,\n \tiq = otx_ep->instr_queue[iq_no];\n \tq_size = conf->iq.instr_type * num_descs;\n \n-\t/* IQ memory creation for Instruction submission to OCTEON TX2 */\n+\t/* IQ memory creation for Instruction submission to OCTEON 9 */\n \tiq->iq_mz = rte_eth_dma_zone_reserve(otx_ep->eth_dev,\n \t\t\t\t\t \"instr_queue\", iq_no, q_size,\n \t\t\t\t\t OTX_EP_PCI_RING_ALIGN,\n@@ -106,8 +106,8 @@ otx_ep_init_instr_queue(struct otx_ep_device *otx_ep, int iq_no, int num_descs,\n \tiq->nb_desc = num_descs;\n \n \t/* Create a IQ request list to hold requests that have been\n-\t * posted to OCTEON TX2. This list will be used for freeing the IQ\n-\t * data buffer(s) later once the OCTEON TX2 fetched the requests.\n+\t * posted to OCTEON 9. This list will be used for freeing the IQ\n+\t * data buffer(s) later once the OCTEON 9 fetched the requests.\n \t */\n \tiq->req_list = rte_zmalloc_socket(\"request_list\",\n \t\t\t(iq->nb_desc * OTX_EP_IQREQ_LIST_SIZE),\n@@ -450,7 +450,7 @@ post_iqcmd(struct otx_ep_instr_queue *iq, uint8_t *iqcmd)\n \tuint8_t *iqptr, cmdsize;\n \n \t/* This ensures that the read index does not wrap around to\n-\t * the same position if queue gets full before OCTEON TX2 could\n+\t * the same position if queue gets full before OCTEON 9 could\n \t * fetch any instr.\n \t */\n \tif (iq->instr_pending > (iq->nb_desc - 1))\n@@ -979,7 +979,7 @@ otx_ep_check_droq_pkts(struct otx_ep_droq *droq)\n \treturn new_pkts;\n }\n \n-/* Check for response arrival from OCTEON TX2\n+/* Check for response arrival from OCTEON 9\n * returns number of requests completed\n */\n uint16_t\ndiff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py\nindex 6cea732228..ace4627218 100755\n--- a/usertools/dpdk-devbind.py\n+++ b/usertools/dpdk-devbind.py\n@@ -65,11 +65,11 @@\n intel_ntb_icx = {'Class': '06', 'Vendor': '8086', 'Device': '347e',\n 'SVendor': None, 'SDevice': None}\n \n-octeontx2_sso = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f9,a0fa',\n+cnxk_sso = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f9,a0fa',\n 'SVendor': None, 'SDevice': None}\n-octeontx2_npa = {'Class': '08', 'Vendor': '177d', 'Device': 'a0fb,a0fc',\n+cnxk_npa = {'Class': '08', 'Vendor': '177d', 'Device': 'a0fb,a0fc',\n 'SVendor': None, 'SDevice': None}\n-octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',\n+cn9k_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',\n 'SVendor': None, 'SDevice': None}\n \n network_devices = [network_class, cavium_pkx, avp_vnic, ifpga_class]\n@@ -77,10 +77,10 @@\n crypto_devices = [encryption_class, intel_processor_class]\n dma_devices = [cnxk_dma, hisilicon_dma,\n intel_idxd_spr, intel_ioat_bdw, intel_ioat_icx, intel_ioat_skx]\n-eventdev_devices = [cavium_sso, cavium_tim, intel_dlb, octeontx2_sso]\n-mempool_devices = [cavium_fpa, octeontx2_npa]\n+eventdev_devices = [cavium_sso, cavium_tim, intel_dlb, cnxk_sso]\n+mempool_devices = [cavium_fpa, cnxk_npa]\n compress_devices = [cavium_zip]\n-regex_devices = [octeontx2_ree]\n+regex_devices = [cn9k_ree]\n misc_devices = [cnxk_bphy, cnxk_bphy_cgx, cnxk_inl_dev,\n intel_ntb_skx, intel_ntb_icx]\n \n", "prefixes": [ "v1" ] }