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GET /api/patches/104966/?format=api
{ "id": 104966, "url": "http://patchwork.dpdk.org/api/patches/104966/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1638859858-734-13-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1638859858-734-13-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1638859858-734-13-git-send-email-anoobj@marvell.com", "date": "2021-12-07T06:50:45", "name": "[12/25] crypto/cnxk: account for CPT CTX updates and flush delays", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9fdcf5dc5978639593464c5675abeb132550b1d5", "submitter": { "id": 1205, "url": "http://patchwork.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1638859858-734-13-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 20882, "url": "http://patchwork.dpdk.org/api/series/20882/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20882", "date": "2021-12-07T06:50:34", "name": "New features and improvements in cnxk crypto PMD", "version": 1, "mbox": "http://patchwork.dpdk.org/series/20882/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/104966/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/104966/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 32776A034F;\n\tTue, 7 Dec 2021 07:52:06 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2172342712;\n\tTue, 7 Dec 2021 07:51:53 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 56115411CB\n for <dev@dpdk.org>; Tue, 7 Dec 2021 07:51:51 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1B75a0oN014933\n for <dev@dpdk.org>; Mon, 6 Dec 2021 22:51:50 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ct1hyg7eb-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 06 Dec 2021 22:51:50 -0800", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 6 Dec 2021 22:51:48 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 6 Dec 2021 22:51:48 -0800", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id 7C52F3F7071;\n Mon, 6 Dec 2021 22:51:46 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=lUupCfPhoh7ZLpolk4eOqSXxgsd7E/63pLqp6YctdJc=;\n b=Z/zoCbu1EAeH+SsJIvDLL+TaFsxZl2yxgBj/Ez4Ys92h4xVzvT8cFI1PtsD9JAo4DrAj\n 2CffUBZ5gi7tT755KVLCS2Yy0PF55HW5KnibvnAQ0EwtqJh9723a67E0jik0IqNe9O6V\n Q0CW4BzuibsvJImb06KAUDUJWxq1f8paq2Sqgx7GkVjJKxxwP2ol6UkZvpz7MSB+RpwI\n 09zgAPbmx9HewiLLMn0ECMp48YYS/PLzvosHnem5yADfJKqQ5KwqQQmtdtIgUyYmw0+p\n TtdNYrvf+Y83rLP7ug0Lc1OHdRSqkJef9AH1zMTLRJbWt+wwJRgJ1UXpzQK4DHnAGwGa KQ==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Jerin Jacob <jerinj@marvell.com>", "CC": "Anoob Joseph <anoobj@marvell.com>, Archana Muniganti\n <marchana@marvell.com>,\n Tejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 12/25] crypto/cnxk: account for CPT CTX updates and flush\n delays", "Date": "Tue, 7 Dec 2021 12:20:45 +0530", "Message-ID": "<1638859858-734-13-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1638859858-734-1-git-send-email-anoobj@marvell.com>", "References": "<1638859858-734-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "LXxq_SU2-zd8uMtCwcf-DEfJvnuA1Uvn", "X-Proofpoint-GUID": "LXxq_SU2-zd8uMtCwcf-DEfJvnuA1Uvn", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-07_02,2021-12-06_02,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "CPT CTX write with microcode would require CPT flush to complete to have\nDRAM updated with the SA. Since datapath requires SA direction field,\nintroduce a new flag for the same.\n\nSession destroy path is also updated to clear sa.valid bit using CTX\nreload operation.\n\nSession is updated with marker to differentiate s/w immutable and s/w\nmutable portions.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\n---\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 4 +--\n drivers/crypto/cnxk/cn10k_ipsec.c | 60 ++++++++++++++++++++++++-------\n drivers/crypto/cnxk/cn10k_ipsec.h | 25 ++++++++-----\n drivers/crypto/cnxk/cn10k_ipsec_la_ops.h | 18 +++++-----\n 4 files changed, 76 insertions(+), 31 deletions(-)", "diff": "diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex d25a17c..7617bdc 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -53,7 +53,6 @@ cpt_sec_inst_fill(struct rte_crypto_op *op, struct cn10k_sec_session *sess,\n \t\t struct cpt_inflight_req *infl_req, struct cpt_inst_s *inst)\n {\n \tstruct rte_crypto_sym_op *sym_op = op->sym;\n-\tunion roc_ot_ipsec_sa_word2 *w2;\n \tstruct cn10k_ipsec_sa *sa;\n \tint ret;\n \n@@ -68,9 +67,8 @@ cpt_sec_inst_fill(struct rte_crypto_op *op, struct cn10k_sec_session *sess,\n \t}\n \n \tsa = &sess->sa;\n-\tw2 = (union roc_ot_ipsec_sa_word2 *)&sa->in_sa.w2;\n \n-\tif (w2->s.dir == ROC_IE_SA_DIR_OUTBOUND)\n+\tif (sa->is_outbound)\n \t\tret = process_outb_sa(op, sa, inst);\n \telse {\n \t\tinfl_req->op_flags |= CPT_OP_FLAGS_IPSEC_DIR_INBOUND;\ndiff --git a/drivers/crypto/cnxk/cn10k_ipsec.c b/drivers/crypto/cnxk/cn10k_ipsec.c\nindex a11a6b7..b4acbac 100644\n--- a/drivers/crypto/cnxk/cn10k_ipsec.c\n+++ b/drivers/crypto/cnxk/cn10k_ipsec.c\n@@ -67,7 +67,7 @@ cn10k_ipsec_outb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,\n \t\tgoto sa_dptr_free;\n \t}\n \n-\tsa->inst.w7 = ipsec_cpt_inst_w7_get(roc_cpt, sa);\n+\tsa->inst.w7 = ipsec_cpt_inst_w7_get(roc_cpt, out_sa);\n \n #ifdef LA_IPSEC_DEBUG\n \t/* Use IV from application in debug mode */\n@@ -89,6 +89,8 @@ cn10k_ipsec_outb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,\n \t}\n #endif\n \n+\tsa->is_outbound = true;\n+\n \t/* Get Rlen calculation data */\n \tret = cnxk_ipsec_outb_rlens_get(&rlens, ipsec_xfrm, crypto_xfrm);\n \tif (ret)\n@@ -127,6 +129,8 @@ cn10k_ipsec_outb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,\n \t/* Copy word0 from sa_dptr to populate ctx_push_sz ctx_size fields */\n \tmemcpy(out_sa, sa_dptr, 8);\n \n+\tplt_atomic_thread_fence(__ATOMIC_SEQ_CST);\n+\n \t/* Write session using microcode opcode */\n \tret = roc_cpt_ctx_write(lf, sa_dptr, out_sa,\n \t\t\t\tROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ);\n@@ -135,9 +139,11 @@ cn10k_ipsec_outb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,\n \t\tgoto sa_dptr_free;\n \t}\n \n-\t/* Trigger CTX flush to write dirty data back to DRAM */\n+\t/* Trigger CTX flush so that data is written back to DRAM */\n \troc_cpt_lf_ctx_flush(lf, out_sa, false);\n \n+\tplt_atomic_thread_fence(__ATOMIC_SEQ_CST);\n+\n sa_dptr_free:\n \tplt_free(sa_dptr);\n \n@@ -178,7 +184,8 @@ cn10k_ipsec_inb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,\n \t\tgoto sa_dptr_free;\n \t}\n \n-\tsa->inst.w7 = ipsec_cpt_inst_w7_get(roc_cpt, sa);\n+\tsa->is_outbound = false;\n+\tsa->inst.w7 = ipsec_cpt_inst_w7_get(roc_cpt, in_sa);\n \n \t/* pre-populate CPT INST word 4 */\n \tinst_w4.u64 = 0;\n@@ -214,6 +221,8 @@ cn10k_ipsec_inb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,\n \t/* Copy word0 from sa_dptr to populate ctx_push_sz ctx_size fields */\n \tmemcpy(in_sa, sa_dptr, 8);\n \n+\tplt_atomic_thread_fence(__ATOMIC_SEQ_CST);\n+\n \t/* Write session using microcode opcode */\n \tret = roc_cpt_ctx_write(lf, sa_dptr, in_sa,\n \t\t\t\tROC_NIX_INL_OT_IPSEC_INB_HW_SZ);\n@@ -222,9 +231,11 @@ cn10k_ipsec_inb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,\n \t\tgoto sa_dptr_free;\n \t}\n \n-\t/* Trigger CTX flush to write dirty data back to DRAM */\n+\t/* Trigger CTX flush so that data is written back to DRAM */\n \troc_cpt_lf_ctx_flush(lf, in_sa, false);\n \n+\tplt_atomic_thread_fence(__ATOMIC_SEQ_CST);\n+\n sa_dptr_free:\n \tplt_free(sa_dptr);\n \n@@ -300,21 +311,46 @@ cn10k_sec_session_create(void *device, struct rte_security_session_conf *conf,\n }\n \n static int\n-cn10k_sec_session_destroy(void *device __rte_unused,\n-\t\t\t struct rte_security_session *sess)\n+cn10k_sec_session_destroy(void *dev, struct rte_security_session *sec_sess)\n {\n-\tstruct cn10k_sec_session *priv;\n+\tstruct rte_cryptodev *crypto_dev = dev;\n+\tunion roc_ot_ipsec_sa_word2 *w2;\n+\tstruct cn10k_sec_session *sess;\n \tstruct rte_mempool *sess_mp;\n+\tstruct cn10k_ipsec_sa *sa;\n+\tstruct cnxk_cpt_qp *qp;\n+\tstruct roc_cpt_lf *lf;\n \n-\tpriv = get_sec_session_private_data(sess);\n+\tsess = get_sec_session_private_data(sec_sess);\n+\tif (sess == NULL)\n+\t\treturn 0;\n \n-\tif (priv == NULL)\n+\tqp = crypto_dev->data->queue_pairs[0];\n+\tif (qp == NULL)\n \t\treturn 0;\n \n-\tsess_mp = rte_mempool_from_obj(priv);\n+\tlf = &qp->lf;\n \n-\tset_sec_session_private_data(sess, NULL);\n-\trte_mempool_put(sess_mp, priv);\n+\tsa = &sess->sa;\n+\n+\t/* Trigger CTX flush to write dirty data back to DRAM */\n+\troc_cpt_lf_ctx_flush(lf, &sa->in_sa, false);\n+\n+\t/* Wait for 1 ms so that flush is complete */\n+\trte_delay_ms(1);\n+\n+\tw2 = (union roc_ot_ipsec_sa_word2 *)&sa->in_sa.w2;\n+\tw2->s.valid = 0;\n+\n+\tplt_atomic_thread_fence(__ATOMIC_SEQ_CST);\n+\n+\t/* Trigger CTX reload to fetch new data from DRAM */\n+\troc_cpt_lf_ctx_reload(lf, &sa->in_sa);\n+\n+\tsess_mp = rte_mempool_from_obj(sess);\n+\n+\tset_sec_session_private_data(sec_sess, NULL);\n+\trte_mempool_put(sess_mp, sess);\n \n \treturn 0;\n }\ndiff --git a/drivers/crypto/cnxk/cn10k_ipsec.h b/drivers/crypto/cnxk/cn10k_ipsec.h\nindex 86cd248..8be1fee 100644\n--- a/drivers/crypto/cnxk/cn10k_ipsec.h\n+++ b/drivers/crypto/cnxk/cn10k_ipsec.h\n@@ -7,24 +7,33 @@\n \n #include <rte_security.h>\n \n+#include \"roc_api.h\"\n+\n #include \"cnxk_ipsec.h\"\n \n-#define CN10K_IPSEC_SA_CTX_HDR_SIZE 1\n+typedef void *CN10K_SA_CONTEXT_MARKER[0];\n \n struct cn10k_ipsec_sa {\n-\tunion {\n-\t\t/** Inbound SA */\n-\t\tstruct roc_ot_ipsec_inb_sa in_sa;\n-\t\t/** Outbound SA */\n-\t\tstruct roc_ot_ipsec_outb_sa out_sa;\n-\t};\n \t/** Pre-populated CPT inst words */\n \tstruct cnxk_cpt_inst_tmpl inst;\n \tuint16_t max_extended_len;\n \tuint16_t iv_offset;\n \tuint8_t iv_length;\n \tbool ip_csum_enable;\n-};\n+\tbool is_outbound;\n+\n+\t/**\n+\t * End of SW mutable area\n+\t */\n+\tCN10K_SA_CONTEXT_MARKER sw_area_end __rte_aligned(ROC_ALIGN);\n+\n+\tunion {\n+\t\t/** Inbound SA */\n+\t\tstruct roc_ot_ipsec_inb_sa in_sa;\n+\t\t/** Outbound SA */\n+\t\tstruct roc_ot_ipsec_outb_sa out_sa;\n+\t};\n+} __rte_aligned(ROC_ALIGN);\n \n struct cn10k_sec_session {\n \tstruct cn10k_ipsec_sa sa;\ndiff --git a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h\nindex 881fbd1..cab6a50 100644\n--- a/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h\n+++ b/drivers/crypto/cnxk/cn10k_ipsec_la_ops.h\n@@ -54,6 +54,7 @@ process_outb_sa(struct rte_crypto_op *cop, struct cn10k_ipsec_sa *sess,\n \tstruct rte_crypto_sym_op *sym_op = cop->sym;\n \tstruct rte_mbuf *m_src = sym_op->m_src;\n \tuint64_t inst_w4_u64 = sess->inst.w4;\n+\tuint64_t dptr;\n \n \tif (unlikely(rte_pktmbuf_tailroom(m_src) < sess->max_extended_len)) {\n \t\tplt_dp_err(\"Not enough tail room\");\n@@ -76,10 +77,10 @@ process_outb_sa(struct rte_crypto_op *cop, struct cn10k_ipsec_sa *sess,\n \t\tinst_w4_u64 &= ~BIT_ULL(32);\n \n \t/* Prepare CPT instruction */\n-\tinst->w4.u64 = inst_w4_u64;\n-\tinst->w4.s.dlen = rte_pktmbuf_pkt_len(m_src);\n-\tinst->dptr = rte_pktmbuf_iova(m_src);\n-\tinst->rptr = inst->dptr;\n+\tinst->w4.u64 = inst_w4_u64 | rte_pktmbuf_pkt_len(m_src);\n+\tdptr = rte_pktmbuf_iova(m_src);\n+\tinst->dptr = dptr;\n+\tinst->rptr = dptr;\n \n \treturn 0;\n }\n@@ -90,12 +91,13 @@ process_inb_sa(struct rte_crypto_op *cop, struct cn10k_ipsec_sa *sa,\n {\n \tstruct rte_crypto_sym_op *sym_op = cop->sym;\n \tstruct rte_mbuf *m_src = sym_op->m_src;\n+\tuint64_t dptr;\n \n \t/* Prepare CPT instruction */\n-\tinst->w4.u64 = sa->inst.w4;\n-\tinst->w4.s.dlen = rte_pktmbuf_pkt_len(m_src);\n-\tinst->dptr = rte_pktmbuf_iova(m_src);\n-\tinst->rptr = inst->dptr;\n+\tinst->w4.u64 = sa->inst.w4 | rte_pktmbuf_pkt_len(m_src);\n+\tdptr = rte_pktmbuf_iova(m_src);\n+\tinst->dptr = dptr;\n+\tinst->rptr = dptr;\n \n \treturn 0;\n }\n", "prefixes": [ "12/25" ] }