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GET /api/patches/104985/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 104985,
    "url": "http://patchwork.dpdk.org/api/patches/104985/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211207085946.121032-1-dapengx.yu@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20211207085946.121032-1-dapengx.yu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20211207085946.121032-1-dapengx.yu@intel.com",
    "date": "2021-12-07T08:59:46",
    "name": "net/i40e: enable max frame size at port level",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "011e7cc4edbe54b05689ba1a3f6e815f1511baa0",
    "submitter": {
        "id": 2042,
        "url": "http://patchwork.dpdk.org/api/people/2042/?format=api",
        "name": "Yu, DapengX",
        "email": "dapengx.yu@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patchwork.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211207085946.121032-1-dapengx.yu@intel.com/mbox/",
    "series": [
        {
            "id": 20883,
            "url": "http://patchwork.dpdk.org/api/series/20883/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20883",
            "date": "2021-12-07T08:59:46",
            "name": "net/i40e: enable max frame size at port level",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/20883/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/104985/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/104985/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CD3C4A034F;\n\tTue,  7 Dec 2021 10:02:19 +0100 (CET)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5A29A41152;\n\tTue,  7 Dec 2021 10:02:19 +0100 (CET)",
            "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 7701C4114F;\n Tue,  7 Dec 2021 10:02:17 +0100 (CET)",
            "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 07 Dec 2021 01:00:35 -0800",
            "from unknown (HELO localhost.localdomain) ([10.240.183.93])\n by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 07 Dec 2021 01:00:33 -0800"
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6200,9189,10190\"; a=\"300915694\"",
            "E=Sophos;i=\"5.87,293,1631602800\"; d=\"scan'208\";a=\"300915694\"",
            "E=Sophos;i=\"5.87,293,1631602800\"; d=\"scan'208\";a=\"515195383\""
        ],
        "From": "dapengx.yu@intel.com",
        "To": "Beilei Xing <beilei.xing@intel.com>",
        "Cc": "dev@dpdk.org,\n\tDapeng Yu <dapengx.yu@intel.com>,\n\tstable@dpdk.org",
        "Subject": "[PATCH] net/i40e: enable max frame size at port level",
        "Date": "Tue,  7 Dec 2021 16:59:46 +0800",
        "Message-Id": "<20211207085946.121032-1-dapengx.yu@intel.com>",
        "X-Mailer": "git-send-email 2.27.0",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "From: Dapeng Yu <dapengx.yu@intel.com>\n\nCurrently max frame size is set at queue level, which makes the values\nof the following counters wrong when a jumbo frame is received.\n\nThe expected value:\nrx_good_bytes: 0\nrx_errors: 1\nrx_oversize_errors: 1\n\nThe actual value:\nrx_good_bytes: 1626\nrx_errors: 0\nrx_oversize_errors: 0\n\nThis patch enables setting max frame size at port level, and makes the\nvalues above right.\n\nCc: stable@dpdk.org\n\nSigned-off-by: Dapeng Yu <dapengx.yu@intel.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 41 ++++++++++++++++++++++++++++------\n 1 file changed, 34 insertions(+), 7 deletions(-)",
    "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex c0bfff43ee..ef9b2b2414 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -386,6 +386,7 @@ static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,\n \t\t\t\t      struct rte_ether_addr *mac_addr);\n \n static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);\n+static void i40e_set_mac_max_frame(struct rte_eth_dev *dev, uint16_t size);\n \n static int i40e_ethertype_filter_convert(\n \tconst struct rte_eth_ethertype_filter *input,\n@@ -1709,11 +1710,6 @@ eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)\n \t */\n \ti40e_add_tx_flow_control_drop_filter(pf);\n \n-\t/* Set the max frame size to 0x2600 by default,\n-\t * in case other drivers changed the default value.\n-\t */\n-\ti40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);\n-\n \t/* initialize RSS rule list */\n \tTAILQ_INIT(&pf->rss_config_list);\n \n@@ -2364,6 +2360,7 @@ i40e_dev_start(struct rte_eth_dev *dev)\n \tuint32_t intr_vector = 0;\n \tstruct i40e_vsi *vsi;\n \tuint16_t nb_rxq, nb_txq;\n+\tuint16_t max_frame_size;\n \n \thw->adapter_stopped = 0;\n \n@@ -2502,6 +2499,9 @@ i40e_dev_start(struct rte_eth_dev *dev)\n \t\t\t    \"please call hierarchy_commit() \"\n \t\t\t    \"before starting the port\");\n \n+\tmax_frame_size = dev->data->mtu + I40E_ETH_OVERHEAD;\n+\ti40e_set_mac_max_frame(dev, max_frame_size);\n+\n \treturn I40E_SUCCESS;\n \n tx_err:\n@@ -2848,6 +2848,9 @@ i40e_dev_set_link_down(struct rte_eth_dev *dev)\n \treturn i40e_phy_conf_link(hw, abilities, speed, false);\n }\n \n+#define CHECK_INTERVAL             100  /* 100ms */\n+#define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */\n+\n static __rte_always_inline void\n update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)\n {\n@@ -2914,8 +2917,6 @@ static __rte_always_inline void\n update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,\n \tbool enable_lse, int wait_to_complete)\n {\n-#define CHECK_INTERVAL             100  /* 100ms */\n-#define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */\n \tuint32_t rep_cnt = MAX_REPEAT_TIME;\n \tstruct i40e_link_status link_status;\n \tint status;\n@@ -6719,6 +6720,7 @@ i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)\n \t\t\tif (!ret)\n \t\t\t\trte_eth_dev_callback_process(dev,\n \t\t\t\t\tRTE_ETH_EVENT_INTR_LSC, NULL);\n+\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tPMD_DRV_LOG(DEBUG, \"Request %u is not supported yet\",\n@@ -12103,6 +12105,31 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf)\n \treturn ret;\n }\n \n+static void\n+i40e_set_mac_max_frame(struct rte_eth_dev *dev, uint16_t size)\n+{\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint32_t rep_cnt = MAX_REPEAT_TIME;\n+\tstruct rte_eth_link link;\n+\tenum i40e_status_code status;\n+\n+\tdo {\n+\t\tupdate_link_reg(hw, &link);\n+\t\tif (link.link_status)\n+\t\t\tbreak;\n+\n+\t\trte_delay_ms(CHECK_INTERVAL);\n+\t} while (--rep_cnt);\n+\n+\tif (link.link_status) {\n+\t\tstatus = i40e_aq_set_mac_config(hw, size, TRUE, 0, false, NULL);\n+\t\tif (status != I40E_SUCCESS)\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to set max frame size at port level\");\n+\t} else {\n+\t\tPMD_DRV_LOG(ERR, \"Set max frame size at port level not applicable on link down\");\n+\t}\n+}\n+\n RTE_LOG_REGISTER_SUFFIX(i40e_logtype_init, init, NOTICE);\n RTE_LOG_REGISTER_SUFFIX(i40e_logtype_driver, driver, NOTICE);\n #ifdef RTE_ETHDEV_DEBUG_RX\n",
    "prefixes": []
}