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GET /api/patches/105043/?format=api
{ "id": 105043, "url": "http://patchwork.dpdk.org/api/patches/105043/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211209091342.27017-4-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211209091342.27017-4-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211209091342.27017-4-ndabilpuram@marvell.com", "date": "2021-12-09T09:13:38", "name": "[4/8] common/cnxk: reset stale values on error debug registers", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "286df98bcb84b899f4ff7d7e7e93eba9532ee263", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211209091342.27017-4-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 20897, "url": "http://patchwork.dpdk.org/api/series/20897/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20897", "date": "2021-12-09T09:13:35", "name": "[1/8] common/cnxk: fix shift offset for tl3 length disable", "version": 1, "mbox": "http://patchwork.dpdk.org/series/20897/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/105043/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/105043/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 40EB3A00C2;\n\tThu, 9 Dec 2021 10:14:15 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DC6A441160;\n\tThu, 9 Dec 2021 10:14:01 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 443C5426F0\n for <dev@dpdk.org>; Thu, 9 Dec 2021 10:14:00 +0100 (CET)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1B97c3Lx010140\n for <dev@dpdk.org>; Thu, 9 Dec 2021 01:13:59 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3cudjt0apc-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 09 Dec 2021 01:13:59 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 9 Dec 2021 01:13:57 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 9 Dec 2021 01:13:57 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 6BFDF3F7054;\n Thu, 9 Dec 2021 01:13:55 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=OqXZiqNfIGOLO/nuqLOeSLvlIiH/ZCXc1zFWTjSEvGQ=;\n b=GMCXPs/UUHUuzLqI0tYBCZDqKNfFZ/nWjA04tZ77Jq8CTiag0o56svyF4gCpY1L4m4Wu\n Km4xn7v+Ma0JRPGXyJepbSB6wcPgW2oAlSqatP4+fxagZEIKEDSchHmzjEe+0Wq92Obp\n Ur+2pIz+BFqC1x9XOWaO9zjCiWLdAM3hCEmtDDa9YpgS39nhf0UaUQ1H+gtwWvbtRtZ/\n C3d4GOWnkKdaB7HzNtM50kwRumHqKYWLMN+111P5UlnN240vRe9uqKutaOj6cckRdW+O\n E1Avj/ouVI/Y/uSSL9v1xvLX1uOM6xTU69ndnbwRcmSruyDHzvFu52mHaInM5uo6pGR3 Eg==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Harman Kalra <hkalra@marvell.com>", "Subject": "[PATCH 4/8] common/cnxk: reset stale values on error debug registers", "Date": "Thu, 9 Dec 2021 14:43:38 +0530", "Message-ID": "<20211209091342.27017-4-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20211209091342.27017-1-ndabilpuram@marvell.com>", "References": "<20211209091342.27017-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "aIz6q_bZ-jOAw6OLRMY9MFQ5Ydpey3hQ", "X-Proofpoint-GUID": "aIz6q_bZ-jOAw6OLRMY9MFQ5Ydpey3hQ", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-09_04,2021-12-08_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Harman Kalra <hkalra@marvell.com>\n\nLF's error debug registers like NIX_LF_SQ_OP_ERR_DBG,\nNIX_LF_MNQ_ERR_DBG, NIX_LF_SEND_ERR_DBG captures debug\ninfo for an error detected during LMT operation or meta\nenqueue or after meta enqueue granted respectively. HW\nsets a valid bit when info is captured and SW is expected\nto clear this valid bit by writing 1, else these registers\nwill show stale values of first interrupt when occurred and\nwill never update with subsequent interrupts.\n\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/common/cnxk/roc_nix_irq.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c\nindex a5cd9d4..7dcd533 100644\n--- a/drivers/common/cnxk/roc_nix_irq.c\n+++ b/drivers/common/cnxk/roc_nix_irq.c\n@@ -202,9 +202,12 @@ nix_lf_sq_debug_reg(struct nix *nix, uint32_t off)\n \tuint64_t reg;\n \n \treg = plt_read64(nix->base + off);\n-\tif (reg & BIT_ULL(44))\n+\tif (reg & BIT_ULL(44)) {\n \t\tplt_err(\"SQ=%d err_code=0x%x\", (int)((reg >> 8) & 0xfffff),\n \t\t\t(uint8_t)(reg & 0xff));\n+\t\t/* Clear valid bit */\n+\t\tplt_write64(BIT_ULL(44), nix->base + off);\n+\t}\n }\n \n static void\n", "prefixes": [ "4/8" ] }