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GET /api/patches/105045/?format=api
{ "id": 105045, "url": "http://patchwork.dpdk.org/api/patches/105045/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211209091342.27017-6-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211209091342.27017-6-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211209091342.27017-6-ndabilpuram@marvell.com", "date": "2021-12-09T09:13:40", "name": "[6/8] common/cnxk: handle issues from static analysis", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "b9af3a3c2e134bfeb409030e15adb618bb221846", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211209091342.27017-6-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 20897, "url": "http://patchwork.dpdk.org/api/series/20897/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=20897", "date": "2021-12-09T09:13:35", "name": "[1/8] common/cnxk: fix shift offset for tl3 length disable", "version": 1, "mbox": "http://patchwork.dpdk.org/series/20897/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/105045/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/105045/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 36E7EA00C2;\n\tThu, 9 Dec 2021 10:14:27 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1B8DA426FB;\n\tThu, 9 Dec 2021 10:14:08 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id A455E426FB\n for <dev@dpdk.org>; Thu, 9 Dec 2021 10:14:06 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 1B98xk3t005051\n for <dev@dpdk.org>; Thu, 9 Dec 2021 01:14:05 -0800", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cues701xq-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 09 Dec 2021 01:14:05 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 9 Dec 2021 01:14:03 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 9 Dec 2021 01:14:04 -0800", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 081C13F7054;\n Thu, 9 Dec 2021 01:14:01 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=z+orUC4J9IWl1TCdxUv2oTFBDzfS3tsiqI0T6lDiJXM=;\n b=AYY7j3Q9EVeVb5Zw+UrUc6umyOiafnjglUUxD4jJZThmhw2ruWJRfOVT2ZOaYI+ltMHc\n MaUQU8q8kIxSDC5rlxGx3waDTH+cBDLqTDko7Lw9fjdYo8KiUGtVs/nD7hSUVM3ASJA+\n tIXjfe4BkuNJ9Gz6a/uqSuFyC0N2c11ZTmbjzCOdTbjb6Z33vYlmh9syxNzCmcKHuonz\n xt1Lhurnyx9LN042ANwXKoL2+TF/4F7iHwvp66K/2pQopYzA3rhWVX23sbZ4TmBlARXa\n m1m6BbWOf4zYKAG8yRhoesLgWciVBTWDpYLhhkswLPJI/NhCEj9pb48c+iIx5nbCDVwo oQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>", "Subject": "[PATCH 6/8] common/cnxk: handle issues from static analysis", "Date": "Thu, 9 Dec 2021 14:43:40 +0530", "Message-ID": "<20211209091342.27017-6-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20211209091342.27017-1-ndabilpuram@marvell.com>", "References": "<20211209091342.27017-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "5P_lSfU0BartY3FKFePI7vC8KQdqHZUt", "X-Proofpoint-ORIG-GUID": "5P_lSfU0BartY3FKFePI7vC8KQdqHZUt", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513\n definitions=2021-12-09_04,2021-12-08_01,2021-12-02_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\n\nHandle issues reported by static analysis tool such as\nnull pointer dereferences, variable initialization, etc.\n\nSigned-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_cpt.c | 7 +++--\n drivers/common/cnxk/roc_dev.c | 21 ++++++++++++-\n drivers/common/cnxk/roc_nix_debug.c | 6 ++++\n drivers/common/cnxk/roc_nix_fc.c | 12 ++++++++\n drivers/common/cnxk/roc_nix_queue.c | 61 ++++++++++++++++++++++++++++++++++---\n drivers/common/cnxk/roc_nix_stats.c | 18 +++++++++++\n drivers/common/cnxk/roc_nix_tm.c | 8 ++++-\n 7 files changed, 125 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c\nindex 8f8e6d3..0e2dc45 100644\n--- a/drivers/common/cnxk/roc_cpt.c\n+++ b/drivers/common/cnxk/roc_cpt.c\n@@ -385,6 +385,9 @@ cpt_lfs_alloc(struct dev *dev, uint8_t eng_grpmsk, uint8_t blkaddr,\n \t\treturn -EINVAL;\n \n \treq = mbox_alloc_msg_cpt_lf_alloc(mbox);\n+\tif (!req)\n+\t\treturn -ENOSPC;\n+\n \treq->nix_pf_func = 0;\n \tif (inl_dev_sso && nix_inl_dev_pffunc_get())\n \t\treq->sso_pf_func = nix_inl_dev_pffunc_get();\n@@ -812,9 +815,9 @@ roc_cpt_eng_grp_add(struct roc_cpt *roc_cpt, enum cpt_eng_type eng_type)\n void\n roc_cpt_iq_disable(struct roc_cpt_lf *lf)\n {\n+\tvolatile union cpt_lf_q_grp_ptr grp_ptr = {.u = 0x0};\n+\tvolatile union cpt_lf_inprog lf_inprog = {.u = 0x0};\n \tunion cpt_lf_ctl lf_ctl = {.u = 0x0};\n-\tunion cpt_lf_q_grp_ptr grp_ptr;\n-\tunion cpt_lf_inprog lf_inprog;\n \tint timeout = 20;\n \tint cnt;\n \ndiff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c\nindex 926a916..9a86969 100644\n--- a/drivers/common/cnxk/roc_dev.c\n+++ b/drivers/common/cnxk/roc_dev.c\n@@ -57,7 +57,7 @@ pf_af_sync_msg(struct dev *dev, struct mbox_msghdr **rsp)\n \tstruct mbox *mbox = dev->mbox;\n \tstruct mbox_dev *mdev = &mbox->dev[0];\n \n-\tvolatile uint64_t int_status;\n+\tvolatile uint64_t int_status = 0;\n \tstruct mbox_msghdr *msghdr;\n \tuint64_t off;\n \tint rc = 0;\n@@ -152,6 +152,11 @@ af_pf_wait_msg(struct dev *dev, uint16_t vf, int num_msg)\n \t\t/* Reserve PF/VF mbox message */\n \t\tsize = PLT_ALIGN(size, MBOX_MSG_ALIGN);\n \t\trsp = mbox_alloc_msg(&dev->mbox_vfpf, vf, size);\n+\t\tif (!rsp) {\n+\t\t\tplt_err(\"Failed to reserve VF%d message\", vf);\n+\t\t\tcontinue;\n+\t\t}\n+\n \t\tmbox_rsp_init(msg->id, rsp);\n \n \t\t/* Copy message from AF<->PF mbox to PF<->VF mbox */\n@@ -236,6 +241,12 @@ vf_pf_process_msgs(struct dev *dev, uint16_t vf)\n \t\t\t\tBIT_ULL(vf % max_bits);\n \t\t\trsp = (struct ready_msg_rsp *)mbox_alloc_msg(\n \t\t\t\tmbox, vf, sizeof(*rsp));\n+\t\t\tif (!rsp) {\n+\t\t\t\tplt_err(\"Failed to alloc VF%d READY message\",\n+\t\t\t\t\tvf);\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n \t\t\tmbox_rsp_init(msg->id, rsp);\n \n \t\t\t/* PF/VF function ID */\n@@ -988,6 +999,9 @@ dev_setup_shared_lmt_region(struct mbox *mbox, bool valid_iova, uint64_t iova)\n \tstruct lmtst_tbl_setup_req *req;\n \n \treq = mbox_alloc_msg_lmtst_tbl_setup(mbox);\n+\tif (!req)\n+\t\treturn -ENOSPC;\n+\n \t/* This pcifunc is defined with primary pcifunc whose LMT address\n \t * will be shared. If call contains valid IOVA, following pcifunc\n \t * field is of no use.\n@@ -1061,6 +1075,11 @@ dev_lmt_setup(struct dev *dev)\n \t */\n \tif (!dev->disable_shared_lmt) {\n \t\tidev = idev_get_cfg();\n+\t\tif (!idev) {\n+\t\t\terrno = EFAULT;\n+\t\t\tgoto free;\n+\t\t}\n+\n \t\tif (!__atomic_load_n(&idev->lmt_pf_func, __ATOMIC_ACQUIRE)) {\n \t\t\tidev->lmt_base_addr = dev->lmt_base;\n \t\t\tidev->lmt_pf_func = dev->pf_func;\ndiff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c\nindex 266935a..7dc54f3 100644\n--- a/drivers/common/cnxk/roc_nix_debug.c\n+++ b/drivers/common/cnxk/roc_nix_debug.c\n@@ -323,6 +323,9 @@ nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid, __io void **ctx_p)\n \t\tint rc;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = qid;\n \t\taq->ctype = ctype;\n \t\taq->op = NIX_AQ_INSTOP_READ;\n@@ -341,6 +344,9 @@ nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid, __io void **ctx_p)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = qid;\n \t\taq->ctype = ctype;\n \t\taq->op = NIX_AQ_INSTOP_READ;\ndiff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c\nindex ca29cd2..d311371 100644\n--- a/drivers/common/cnxk/roc_nix_fc.c\n+++ b/drivers/common/cnxk/roc_nix_fc.c\n@@ -113,6 +113,9 @@ nix_fc_cq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = fc_cfg->cq_cfg.rq;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n \t\taq->op = NIX_AQ_INSTOP_READ;\n@@ -120,6 +123,9 @@ nix_fc_cq_config_get(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = fc_cfg->cq_cfg.rq;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n \t\taq->op = NIX_AQ_INSTOP_READ;\n@@ -147,6 +153,9 @@ nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = fc_cfg->cq_cfg.rq;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -164,6 +173,9 @@ nix_fc_cq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = fc_cfg->cq_cfg.rq;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 4455fc1..f99cdd0 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -38,6 +38,9 @@ nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable)\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = rq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -48,6 +51,9 @@ nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = rq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -80,6 +86,9 @@ nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,\n \tstruct nix_aq_enq_req *aq;\n \n \taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\tif (!aq)\n+\t\treturn -ENOSPC;\n+\n \taq->qidx = rq->qid;\n \taq->ctype = NIX_AQ_CTYPE_RQ;\n \taq->op = cfg ? NIX_AQ_INSTOP_WRITE : NIX_AQ_INSTOP_INIT;\n@@ -195,6 +204,9 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,\n \tstruct mbox *mbox = dev->mbox;\n \n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\tif (!aq)\n+\t\treturn -ENOSPC;\n+\n \taq->qidx = rq->qid;\n \taq->ctype = NIX_AQ_CTYPE_RQ;\n \taq->op = cfg ? NIX_AQ_INSTOP_WRITE : NIX_AQ_INSTOP_INIT;\n@@ -463,6 +475,9 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = cq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n \t\taq->op = NIX_AQ_INSTOP_INIT;\n@@ -471,6 +486,9 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = cq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n \t\taq->op = NIX_AQ_INSTOP_INIT;\n@@ -547,6 +565,9 @@ roc_nix_cq_fini(struct roc_nix_cq *cq)\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = cq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -558,6 +579,9 @@ roc_nix_cq_fini(struct roc_nix_cq *cq)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = cq->qid;\n \t\taq->ctype = NIX_AQ_CTYPE_CQ;\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -649,7 +673,7 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)\n \treturn rc;\n }\n \n-static void\n+static int\n sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,\n \t uint16_t smq)\n {\n@@ -657,6 +681,9 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,\n \tstruct nix_aq_enq_req *aq;\n \n \taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\tif (!aq)\n+\t\treturn -ENOSPC;\n+\n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n \taq->op = NIX_AQ_INSTOP_INIT;\n@@ -685,6 +712,7 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,\n \t * might result in software missing the interrupt.\n \t */\n \taq->sq.qint_idx = 0;\n+\treturn 0;\n }\n \n static int\n@@ -698,6 +726,9 @@ sq_cn9k_fini(struct nix *nix, struct roc_nix_sq *sq)\n \tint rc, count;\n \n \taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\tif (!aq)\n+\t\treturn -ENOSPC;\n+\n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n \taq->op = NIX_AQ_INSTOP_READ;\n@@ -711,6 +742,9 @@ sq_cn9k_fini(struct nix *nix, struct roc_nix_sq *sq)\n \n \t/* Disable sq */\n \taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\tif (!aq)\n+\t\treturn -ENOSPC;\n+\n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n \taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -722,6 +756,9 @@ sq_cn9k_fini(struct nix *nix, struct roc_nix_sq *sq)\n \n \t/* Read SQ and free sqb's */\n \taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\tif (!aq)\n+\t\treturn -ENOSPC;\n+\n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n \taq->op = NIX_AQ_INSTOP_READ;\n@@ -753,7 +790,7 @@ sq_cn9k_fini(struct nix *nix, struct roc_nix_sq *sq)\n \treturn 0;\n }\n \n-static void\n+static int\n sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,\n \tuint16_t smq)\n {\n@@ -761,6 +798,9 @@ sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,\n \tstruct nix_cn10k_aq_enq_req *aq;\n \n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\tif (!aq)\n+\t\treturn -ENOSPC;\n+\n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n \taq->op = NIX_AQ_INSTOP_INIT;\n@@ -788,6 +828,7 @@ sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,\n \t * might result in software missing the interrupt.\n \t */\n \taq->sq.qint_idx = 0;\n+\treturn 0;\n }\n \n static int\n@@ -801,6 +842,9 @@ sq_fini(struct nix *nix, struct roc_nix_sq *sq)\n \tint rc, count;\n \n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\tif (!aq)\n+\t\treturn -ENOSPC;\n+\n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n \taq->op = NIX_AQ_INSTOP_READ;\n@@ -814,6 +858,9 @@ sq_fini(struct nix *nix, struct roc_nix_sq *sq)\n \n \t/* Disable sq */\n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\tif (!aq)\n+\t\treturn -ENOSPC;\n+\n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n \taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -825,6 +872,9 @@ sq_fini(struct nix *nix, struct roc_nix_sq *sq)\n \n \t/* Read SQ and free sqb's */\n \taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\tif (!aq)\n+\t\treturn -ENOSPC;\n+\n \taq->qidx = sq->qid;\n \taq->ctype = NIX_AQ_CTYPE_SQ;\n \taq->op = NIX_AQ_INSTOP_READ;\n@@ -895,9 +945,12 @@ roc_nix_sq_init(struct roc_nix *roc_nix, struct roc_nix_sq *sq)\n \n \t/* Init SQ context */\n \tif (roc_model_is_cn9k())\n-\t\tsq_cn9k_init(nix, sq, rr_quantum, smq);\n+\t\trc = sq_cn9k_init(nix, sq, rr_quantum, smq);\n \telse\n-\t\tsq_init(nix, sq, rr_quantum, smq);\n+\t\trc = sq_init(nix, sq, rr_quantum, smq);\n+\n+\tif (rc)\n+\t\tgoto nomem;\n \n \trc = mbox_process(mbox);\n \tif (rc)\ndiff --git a/drivers/common/cnxk/roc_nix_stats.c b/drivers/common/cnxk/roc_nix_stats.c\nindex c50c8fa..756111f 100644\n--- a/drivers/common/cnxk/roc_nix_stats.c\n+++ b/drivers/common/cnxk/roc_nix_stats.c\n@@ -124,6 +124,9 @@ nix_stat_rx_queue_reset(struct nix *nix, uint16_t qid)\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -143,6 +146,9 @@ nix_stat_rx_queue_reset(struct nix *nix, uint16_t qid)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_RQ;\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -174,6 +180,9 @@ nix_stat_tx_queue_reset(struct nix *nix, uint16_t qid)\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_SQ;\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -190,6 +199,9 @@ nix_stat_tx_queue_reset(struct nix *nix, uint16_t qid)\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_SQ;\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -295,6 +307,9 @@ roc_nix_xstats_get(struct roc_nix *roc_nix, struct roc_nix_xstat *xstats,\n \n \tif (roc_model_is_cn9k()) {\n \t\treq = mbox_alloc_msg_cgx_stats(mbox);\n+\t\tif (!req)\n+\t\t\treturn -ENOSPC;\n+\n \t\treq->hdr.pcifunc = roc_nix_get_pf_func(roc_nix);\n \n \t\trc = mbox_process_msg(mbox, (void *)&cgx_resp);\n@@ -316,6 +331,9 @@ roc_nix_xstats_get(struct roc_nix *roc_nix, struct roc_nix_xstat *xstats,\n \t\t}\n \t} else {\n \t\treq = mbox_alloc_msg_rpm_stats(mbox);\n+\t\tif (!req)\n+\t\t\treturn -ENOSPC;\n+\n \t\treq->hdr.pcifunc = roc_nix_get_pf_func(roc_nix);\n \n \t\trc = mbox_process_msg(mbox, (void *)&rpm_resp);\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex fe9e83f..a0448be 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -424,7 +424,7 @@ nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled)\n \n \tif (req) {\n \t\treq->num_regs = k;\n-\t\trc = mbox_process(mbox);\n+\t\trc = mbox_process_msg(mbox, (void **)&rsp);\n \t\tif (rc)\n \t\t\tgoto err;\n \t\t/* Report it as enabled only if enabled or all */\n@@ -766,6 +766,9 @@ nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,\n \t\tstruct nix_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_SQ;\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n@@ -781,6 +784,9 @@ nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,\n \t\tstruct nix_cn10k_aq_enq_req *aq;\n \n \t\taq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);\n+\t\tif (!aq)\n+\t\t\treturn -ENOSPC;\n+\n \t\taq->qidx = qid;\n \t\taq->ctype = NIX_AQ_CTYPE_SQ;\n \t\taq->op = NIX_AQ_INSTOP_WRITE;\n", "prefixes": [ "6/8" ] }