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GET /api/patches/105462/?format=api
{ "id": 105462, "url": "http://patchwork.dpdk.org/api/patches/105462/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20211228092043.3360072-1-dkozlyuk@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20211228092043.3360072-1-dkozlyuk@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20211228092043.3360072-1-dkozlyuk@nvidia.com", "date": "2021-12-28T09:20:43", "name": "net/mlx5: relax headroom assertion", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c6110d01db76f62682a8f0f011dc46d2668f4fe2", "submitter": { "id": 2248, "url": "http://patchwork.dpdk.org/api/people/2248/?format=api", "name": "Dmitry Kozlyuk", "email": "dkozlyuk@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20211228092043.3360072-1-dkozlyuk@nvidia.com/mbox/", "series": [ { "id": 21033, "url": "http://patchwork.dpdk.org/api/series/21033/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=21033", "date": "2021-12-28T09:20:43", "name": "net/mlx5: relax headroom assertion", "version": 1, "mbox": "http://patchwork.dpdk.org/series/21033/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/105462/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/105462/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 902E2A034F;\n\tTue, 28 Dec 2021 10:21:03 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3433140040;\n\tTue, 28 Dec 2021 10:21:03 +0100 (CET)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2089.outbound.protection.outlook.com [40.107.237.89])\n by mails.dpdk.org (Postfix) with ESMTP id E4CB44003C;\n Tue, 28 Dec 2021 10:21:01 +0100 (CET)", "from MW4PR03CA0312.namprd03.prod.outlook.com (2603:10b6:303:dd::17)\n by BL0PR12MB2452.namprd12.prod.outlook.com (2603:10b6:207:3f::32)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4823.19; 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helo=mail.nvidia.com;", "From": "Dmitry Kozlyuk <dkozlyuk@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<viacheslavo@nvidia.com>, <stable@dpdk.org>,\n Matan Azrad <matan@nvidia.com>", "Subject": "[PATCH] net/mlx5: relax headroom assertion", "Date": "Tue, 28 Dec 2021 11:20:43 +0200", "Message-ID": "<20211228092043.3360072-1-dkozlyuk@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "fc18fa80-14ac-4cd1-6d85-08d9c9e35c96", "X-MS-TrafficTypeDiagnostic": "BL0PR12MB2452:EE_", "X-Microsoft-Antispam-PRVS": "\n <BL0PR12MB24520D0AA74F69AB326F48ECB9439@BL0PR12MB2452.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:669;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n H1bEQKgMtR1ZsYCx58NQA63yIUETpYaYbxrhP/e3jWdpjmnHcA367ed+19zhe0xCgdrMlEhiwBA+jOy9YOeV2t7GyGwsKzZSRpLOgj/xGElvjfnj5/JPAvNi2jqT/XqCy6nA9faCQ+jpLyW35WHnKquv/SbOPCrxCYWbPcQc3xics59QiuAUCroXdEtvUWDIXTaxTaHcN5JR7wxD0mkjz9j0toHNL+hhbWaoJnWVs0+1aft8aW03JHsX50aOCalNB/oNh8BxTigzWd84mW40TGR3g28AtYBLNL1jv9Uppq+rGnxguHvVpCxr6kBJVp6mmxJGedSbJnhZFTGD5mo2L4gkDyx4mtkKDHGRQEOB6L+htRtO53lPTX5v82cjmhzgdfLuAZGCnKZ4zh9SpWQnakiDKdA8cKEbO3Wcbj4dm+Hf2xKD/JQ5MzKDthrGSVN+L9ZsyIdlERDKVygjUL2THT80QVoLjweAgl4kokGlYiyY1+zhkQi3uosr719CIpk2TD+4dIyZiBmgI1CCPlkA4tW4ycgIZ9BKKYq9jYEJ06IMRf5Vv58OOUgaevXtTHGteA8IpTOccad4fMBk4cnwb2g8ywZvIYE4lAOGJqvYlMrSokyEEjH1Uw4ShDSuPr8n/CB16q1lY9ktcqxtYbqT8xGiua2ONDMXVzQzOwOJhm5fzrzGd05vNG6BmfDzRLaXDosMIqIxnF4KardQyj4BT97exr1lu+JXWHvp6v/TOBxJSoIZVKaOl8JhTVeq2/L/n05xoev1GgUTBL4mrbGIlbrS+zlzUs33jxZ+5ZoA1LY=", "X-Forefront-Antispam-Report": "CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(40470700002)(5660300002)(6666004)(8936002)(82310400004)(47076005)(86362001)(26005)(2906002)(16526019)(55016003)(450100002)(70206006)(40460700001)(186003)(70586007)(81166007)(4326008)(508600001)(356005)(316002)(36756003)(6286002)(6916009)(2616005)(83380400001)(1076003)(7696005)(36860700001)(336012)(426003)(107886003)(54906003)(8676002)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Dec 2021 09:20:59.6507 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n fc18fa80-14ac-4cd1-6d85-08d9c9e35c96", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT034.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL0PR12MB2452", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "A debug assertion in Single-Packet Receive Queue (SPRQ) mode\nrequired all Rx mbufs to have a 128 byte headroom,\nbased on the assumption that rte_pktmbuf_init() sets it.\nHowever, rte_pktmbuf_init() may set a smaller headroom\nif the dataroom is insufficient, e.g. this is a natural case\nfor split buffer segments. The headroom can also be larger.\nOnly check the headroom size when vectored Rx routines\nare used because they rely on it. Relax the assertion\nto require sufficient headroom size, not an exact one.\n\nFixes: a0a45e8af723 (\"net/mlx5: configure Rx queue for buffer split\")\nCc: viacheslavo@nvidia.com\nCc: stable@dpdk.org\n\nSigned-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rxq.c | 8 +++++---\n 1 file changed, 5 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex f77d42dedf..baf676d3b4 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -139,6 +139,7 @@ rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)\n \tunsigned int elts_n = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?\n \t\t(1 << rxq_ctrl->rxq.elts_n) * (1 << rxq_ctrl->rxq.strd_num_n) :\n \t\t(1 << rxq_ctrl->rxq.elts_n);\n+\tbool has_vec_support = mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0;\n \tunsigned int i;\n \tint err;\n \n@@ -160,8 +161,9 @@ rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)\n \t\t\trte_errno = ENOMEM;\n \t\t\tgoto error;\n \t\t}\n-\t\t/* Headroom is reserved by rte_pktmbuf_alloc(). */\n-\t\tMLX5_ASSERT(DATA_OFF(buf) == RTE_PKTMBUF_HEADROOM);\n+\t\t/* Only vectored Rx routines rely on headroom size. */\n+\t\tMLX5_ASSERT(!has_vec_support ||\n+\t\t\t DATA_OFF(buf) >= RTE_PKTMBUF_HEADROOM);\n \t\t/* Buffer is supposed to be empty. */\n \t\tMLX5_ASSERT(rte_pktmbuf_data_len(buf) == 0);\n \t\tMLX5_ASSERT(rte_pktmbuf_pkt_len(buf) == 0);\n@@ -174,7 +176,7 @@ rxq_alloc_elts_sprq(struct mlx5_rxq_ctrl *rxq_ctrl)\n \t\t(*rxq_ctrl->rxq.elts)[i] = buf;\n \t}\n \t/* If Rx vector is activated. */\n-\tif (mlx5_rxq_check_vec_support(&rxq_ctrl->rxq) > 0) {\n+\tif (has_vec_support) {\n \t\tstruct mlx5_rxq_data *rxq = &rxq_ctrl->rxq;\n \t\tstruct rte_mbuf *mbuf_init = &rxq->fake_mbuf;\n \t\tstruct rte_pktmbuf_pool_private *priv =\n", "prefixes": [] }