Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/105597/?format=api
{ "id": 105597, "url": "http://patchwork.dpdk.org/api/patches/105597/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220104024100.14318-1-eagostini@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220104024100.14318-1-eagostini@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220104024100.14318-1-eagostini@nvidia.com", "date": "2022-01-04T02:41:00", "name": "[v2] gpudev: pin GPU memory", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4e3b7728c69436f9f36d5eee91996bb6770e69d5", "submitter": { "id": 1571, "url": "http://patchwork.dpdk.org/api/people/1571/?format=api", "name": "Elena Agostini", "email": "eagostini@nvidia.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220104024100.14318-1-eagostini@nvidia.com/mbox/", "series": [ { "id": 21058, "url": "http://patchwork.dpdk.org/api/series/21058/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=21058", "date": "2022-01-04T02:41:00", "name": "[v2] gpudev: pin GPU memory", "version": 2, "mbox": "http://patchwork.dpdk.org/series/21058/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/105597/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/105597/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3A7DAA034D;\n\tMon, 3 Jan 2022 19:31:14 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2877F40042;\n\tMon, 3 Jan 2022 19:31:14 +0100 (CET)", "from NAM02-SN1-obe.outbound.protection.outlook.com\n (mail-sn1anam02on2089.outbound.protection.outlook.com [40.107.96.89])\n by mails.dpdk.org (Postfix) with ESMTP id 25C954003C\n for <dev@dpdk.org>; Mon, 3 Jan 2022 19:31:13 +0100 (CET)", "from DM6PR01CA0029.prod.exchangelabs.com (2603:10b6:5:296::34) by\n PH0PR12MB5499.namprd12.prod.outlook.com (2603:10b6:510:d5::23) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.4844.15; Mon, 3 Jan 2022 18:31:10 +0000", "from DM6NAM11FT023.eop-nam11.prod.protection.outlook.com\n (2603:10b6:5:296:cafe::30) by DM6PR01CA0029.outlook.office365.com\n (2603:10b6:5:296::34) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4844.13 via Frontend\n Transport; Mon, 3 Jan 2022 18:31:10 +0000", "from mail.nvidia.com (12.22.5.234) by\n DM6NAM11FT023.mail.protection.outlook.com (10.13.173.96) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4844.14 via Frontend Transport; Mon, 3 Jan 2022 18:31:10 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com\n (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 3 Jan 2022 18:31:09 +0000", "from nvidia.com (172.20.187.5) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.986.9; Mon, 3 Jan 2022\n 10:31:08 -0800" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=iK6muUTL5X5UgPJdYWiRArqwOgCcapdY7f7DJoO/XhEB3CNQ+LCrLdvmg2TCSE6BGXYKFaxBASn1YPh+g2nZDyRV7fNkp+HJ8w7ooPn9gzz2OVsUY3h4I0bqGxwKulKh4ElTZNVvS5krqx4HV005qtoqIY/f0I/4xdDhmOkZQ5FEj+OC2KXPDs0xxQL1VQ7U2XNQU6w/J1nOnrmpZWG9sv9HG+4T5s2d72/1CssErO7pQ+K4ybozUStB3Ri2pLL43nG+vEuBS3JrBAO45bsHCP+2DGYlA50lQDS/lrFsF+QtamNZYHVRngHaARjjyCI1Z29hYY2KsNY0GBcIAzx8LA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=1I7bbJBUHfbkz49nDILaI2CWQz6uYo+22tb4B43xjlk=;\n b=mYupah+zqWR1hrCcAfBL6IBFvF2NPM7ocQ+UxPjMy+x6tTAIamqUzSiEW04Va4cISMstPmPFeFOULiZvTuEUeqChKDkY5WVwUcpaRwFpLnA5VllKbnJ0KWFuXN5HuobtE+MYP4SvZ03t59wGSI+4RQrVepD4KyEC4uqWiOZBZ6hsdpTOYj9aUYrQRF7vz0ucPUFCxuUJ7nsxhzKiB2HWmkAReeWBMXA1rXP+Tcih2i9ESzrTNX7Ev2f4P7MwVECCE0DGONwOwpZDI9GHPp1m4hn5Q911Fa1/MK85Of1A/dRrKv4GWjoL/h3Za56dbFpGIKFrPVGOonXncW2ubacLKQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 12.22.5.234) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass\n (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none\n (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=1I7bbJBUHfbkz49nDILaI2CWQz6uYo+22tb4B43xjlk=;\n b=FY+gK7qEN2zedwbpkSRS3yKZBY/F/anIFM3rEaVtqak/w3whhXmsg4Jn/7gBuwYjLK547y0dzUiaiWWWNxGCKTprjhW2grU1Vq9B6p+qIprECQHqR/7gM05schGyyC8UMuD7EgPu9wne0A3zBqUjyQoJ4pCvXm5/+00tCZB+8t6Ampcv/nbMh1Mh25deMsy+0Vf8MQA/oQc8k6Kuuq46mTI5UdclZq9mj+5JQRDPvN/WEaIUxfISK3tJPEWxg9Hd3An4tjesT2sL9gBo/GDBefXo3DtTiGhEoRG9GMu+hofih22o/l3aXJaS57nwJmMlbJYmw5KJ966PGkH2+tFpfw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 12.22.5.234)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 12.22.5.234 as permitted sender) receiver=protection.outlook.com;\n client-ip=12.22.5.234; helo=mail.nvidia.com;", "From": "<eagostini@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Elena Agostini <eagostini@nvidia.com>", "Subject": "[PATCH v2] gpudev: pin GPU memory", "Date": "Tue, 4 Jan 2022 02:41:00 +0000", "Message-ID": "<20220104024100.14318-1-eagostini@nvidia.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20220104023408.13379-1-eagostini@nvidia.com>", "References": "<20220104023408.13379-1-eagostini@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL111.nvidia.com (172.20.187.18) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "0c92fd30-9485-44d7-2967-08d9cee73710", "X-MS-TrafficTypeDiagnostic": "PH0PR12MB5499:EE_", "X-Microsoft-Antispam-PRVS": "\n <PH0PR12MB5499CBB26D153C8D97D2C6C1CD499@PH0PR12MB5499.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:267;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n n4EAY8jS0O29QZPLrm720XecihM6L+QyRlxLjpGve9dLBWQR3sU/Pf+e4VaNY6NtgkmyCC0xT5Eki/kSCxfD1Xi1tEhd1vf6G1r2KrceYq7sIgWxlEUxfxRqQiHZZqbIwrBXlUteRj9nve2UKXe+MCLFJNvxKR/xjsiuHPOOt+8Wqq9dFgd2BfAnZvzWFnb0nHj5i5aXs+C9EkOO7Dm2AExClUUNJV/NIvoH3DW9pFos16mc5Q0cuYbWOu8FvCwxWM2tuxxcuAmVkAK2lSMkttkdG8oDUk2j6hv/cMWdX6i3Lz9ZIzav1y3CHfouyFq+dJ7H2EJb/BaPI+/0QWMBks5+GhabTYHDoGhpudcrXcIEsoh/t1cqkkSQf2ugeXrqIgQFL/zFtvHD5scPAuh3bb3xcP7zE9Y0CGebjkXkN3QMeUpf7gaOSiCg0uR2NJgnUt6UzvXmr4QvE5DuJDyrVBWw0/IgQFDp8kTPnQvnTwlWty99z9VjeXgIEN+4LzI2XC7iAZ+N3Bwvb8slqVZIrI39YkNW+GPXozRgBFNq+DLmWQVOqA2lAJNgcV2RCYhdCuDz2IO03nXcd7UqcraVLGi33DRg1A8ka9WA2OSnCFuSQTU/cHQToZVYjcXTOhdpC+l2pTQhj27x8ns+b6xfGrFrvPW3P+Rb2onMmV8YOdcpmlhxKwZOvel6cFm5dGdErXgkhLpBD2sgcGw7O5fTFr8ZwLTeKEKbSCK8Wa01k700IDms3Z8AsknbAu/eJpXI1PxDH5tpSIjS7PE6VeOMt0onxwlPhiinjv/s9hMv4aI=", "X-Forefront-Antispam-Report": "CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(4636009)(46966006)(40470700002)(36840700001)(508600001)(81166007)(356005)(16526019)(186003)(6666004)(36860700001)(4326008)(83380400001)(6286002)(2876002)(1076003)(336012)(8676002)(2616005)(70586007)(2906002)(70206006)(6916009)(7696005)(86362001)(36756003)(107886003)(40460700001)(55016003)(26005)(82310400004)(8936002)(47076005)(426003)(316002)(5660300002)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "03 Jan 2022 18:31:10.4959 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0c92fd30-9485-44d7-2967-08d9cee73710", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT023.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB5499", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Elena Agostini <eagostini@nvidia.com>\n\nEnable the possibility to make a GPU memory area accessible from\nthe CPU.\n\nGPU memory has to be allocated via rte_gpu_mem_alloc().\n\nThis patch allows the gpudev library to pin, through the GPU driver,\na chunk of GPU memory and to return a memory pointer usable\nby the CPU to access the GPU memory area.\n\nSigned-off-by: Elena Agostini <eagostini@nvidia.com>\n---\n lib/gpudev/gpudev.c | 47 +++++++++++++++++++++++++++++++++++\n lib/gpudev/gpudev_driver.h | 6 +++++\n lib/gpudev/rte_gpudev.h | 50 ++++++++++++++++++++++++++++++++++++++\n lib/gpudev/version.map | 2 ++\n 4 files changed, 105 insertions(+)", "diff": "diff --git a/lib/gpudev/gpudev.c b/lib/gpudev/gpudev.c\nindex 9ae36dbae9..ca627e44b3 100644\n--- a/lib/gpudev/gpudev.c\n+++ b/lib/gpudev/gpudev.c\n@@ -634,6 +634,53 @@ rte_gpu_mem_unregister(int16_t dev_id, void *ptr)\n \treturn GPU_DRV_RET(dev->ops.mem_unregister(dev, ptr));\n }\n \n+int\n+rte_gpu_mem_pin(int16_t dev_id, size_t size, void *ptr)\n+{\n+\tstruct rte_gpu *dev;\n+\n+\tdev = gpu_get_by_id(dev_id);\n+\tif (dev == NULL) {\n+\t\tGPU_LOG(ERR, \"pin mem for invalid device ID %d\", dev_id);\n+\t\trte_errno = ENODEV;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tif (dev->ops.mem_pin == NULL) {\n+\t\tGPU_LOG(ERR, \"mem pinning not supported\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tif (ptr == NULL || size == 0) /* dry-run */\n+\t\treturn 0;\n+\n+\treturn GPU_DRV_RET(dev->ops.mem_pin(dev, size, ptr));\n+}\n+\n+int\n+rte_gpu_mem_unpin(int16_t dev_id, void *ptr)\n+{\n+\tstruct rte_gpu *dev;\n+\n+\tdev = gpu_get_by_id(dev_id);\n+\tif (dev == NULL) {\n+\t\tGPU_LOG(ERR, \"unpin mem for invalid device ID %d\", dev_id);\n+\t\trte_errno = ENODEV;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tif (dev->ops.mem_unpin == NULL) {\n+\t\trte_errno = ENOTSUP;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tif (ptr == NULL) /* dry-run */\n+\t\treturn 0;\n+\n+\treturn GPU_DRV_RET(dev->ops.mem_unpin(dev, ptr));\n+}\n+\n int\n rte_gpu_wmb(int16_t dev_id)\n {\ndiff --git a/lib/gpudev/gpudev_driver.h b/lib/gpudev/gpudev_driver.h\nindex cb7b101f2f..13dd8dac43 100644\n--- a/lib/gpudev/gpudev_driver.h\n+++ b/lib/gpudev/gpudev_driver.h\n@@ -31,6 +31,8 @@ typedef int (rte_gpu_mem_alloc_t)(struct rte_gpu *dev, size_t size, void **ptr);\n typedef int (rte_gpu_mem_free_t)(struct rte_gpu *dev, void *ptr);\n typedef int (rte_gpu_mem_register_t)(struct rte_gpu *dev, size_t size, void *ptr);\n typedef int (rte_gpu_mem_unregister_t)(struct rte_gpu *dev, void *ptr);\n+typedef int (rte_gpu_mem_pin_t)(struct rte_gpu *dev, size_t size, void *ptr);\n+typedef int (rte_gpu_mem_unpin_t)(struct rte_gpu *dev, void *ptr);\n typedef int (rte_gpu_wmb_t)(struct rte_gpu *dev);\n \n struct rte_gpu_ops {\n@@ -46,6 +48,10 @@ struct rte_gpu_ops {\n \trte_gpu_mem_register_t *mem_register;\n \t/* Unregister CPU memory from device. */\n \trte_gpu_mem_unregister_t *mem_unregister;\n+\t/* Pin GPU memory. */\n+\trte_gpu_mem_pin_t *mem_pin;\n+\t/* Unpin GPU memory. */\n+\trte_gpu_mem_unpin_t *mem_unpin;\n \t/* Enforce GPU write memory barrier. */\n \trte_gpu_wmb_t *wmb;\n };\ndiff --git a/lib/gpudev/rte_gpudev.h b/lib/gpudev/rte_gpudev.h\nindex fa3f3aad4f..0a9033c6e0 100644\n--- a/lib/gpudev/rte_gpudev.h\n+++ b/lib/gpudev/rte_gpudev.h\n@@ -447,6 +447,56 @@ int rte_gpu_mem_register(int16_t dev_id, size_t size, void *ptr);\n __rte_experimental\n int rte_gpu_mem_unregister(int16_t dev_id, void *ptr);\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Pin a chunk of GPU memory to make it accessible from the CPU\n+ * using the memory pointer returned by the function.\n+ * GPU memory has to be allocated via rte_gpu_mem_alloc().\n+ *\n+ * @param dev_id\n+ * Device ID requiring pinned memory.\n+ * @param size\n+ * Number of bytes to pin.\n+ * Requesting 0 will do nothing.\n+ * @param ptr\n+ * Pointer to the GPU memory area to be pinned.\n+ * NULL is a no-op accepted value.\n+\n+ * @return\n+ * A pointer to the pinned GPU memory usable by the CPU, otherwise NULL and rte_errno is set:\n+ * - ENODEV if invalid dev_id\n+ * - EINVAL if reserved flags\n+ * - ENOTSUP if operation not supported by the driver\n+ * - E2BIG if size is higher than limit\n+ * - ENOMEM if out of space\n+ * - EPERM if driver error\n+ */\n+__rte_experimental\n+int rte_gpu_mem_pin(int16_t dev_id, size_t size, void *ptr);\n+\n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ *\n+ * Unpin a chunk of GPU memory previously pinned with rte_gpu_mem_pin()\n+ *\n+ * @param dev_id\n+ * Reference device ID.\n+ * @param ptr\n+ * Pointer to the memory area to be unpinned.\n+ * NULL is a no-op accepted value.\n+ *\n+ * @return\n+ * 0 on success, -rte_errno otherwise:\n+ * - ENODEV if invalid dev_id\n+ * - ENOTSUP if operation not supported by the driver\n+ * - EPERM if driver error\n+ */\n+__rte_experimental\n+int rte_gpu_mem_unpin(int16_t dev_id, void *ptr);\n+\n /**\n * @warning\n * @b EXPERIMENTAL: this API may change without prior notice.\ndiff --git a/lib/gpudev/version.map b/lib/gpudev/version.map\nindex 2e414c65cc..8fb0f4623b 100644\n--- a/lib/gpudev/version.map\n+++ b/lib/gpudev/version.map\n@@ -21,7 +21,9 @@ EXPERIMENTAL {\n \trte_gpu_is_valid;\n \trte_gpu_mem_alloc;\n \trte_gpu_mem_free;\n+\trte_gpu_mem_pin;\n \trte_gpu_mem_register;\n+\trte_gpu_mem_unpin;\n \trte_gpu_mem_unregister;\n \trte_gpu_wmb;\n };\n", "prefixes": [ "v2" ] }