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GET /api/patches/105692/?format=api
{ "id": 105692, "url": "http://patchwork.dpdk.org/api/patches/105692/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220108002003.21153-3-eagostini@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220108002003.21153-3-eagostini@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220108002003.21153-3-eagostini@nvidia.com", "date": "2022-01-08T00:20:03", "name": "[v2,3/3] gpu/cuda: mem alloc aligned memory", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c539189f1fd53a75fecdb2e1f7e7b5efed85e896", "submitter": { "id": 1571, "url": "http://patchwork.dpdk.org/api/people/1571/?format=api", "name": "Elena Agostini", "email": "eagostini@nvidia.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220108002003.21153-3-eagostini@nvidia.com/mbox/", "series": [ { "id": 21096, "url": "http://patchwork.dpdk.org/api/series/21096/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=21096", "date": "2022-01-08T00:20:01", "name": "[v2,1/3] gpudev: mem alloc aligned memory", "version": 2, "mbox": "http://patchwork.dpdk.org/series/21096/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/105692/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/105692/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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SFS:(4636009)(46966006)(36840700001)(40470700002)(36756003)(2906002)(1076003)(7696005)(86362001)(508600001)(36860700001)(186003)(26005)(336012)(47076005)(2616005)(426003)(8676002)(8936002)(5660300002)(16526019)(83380400001)(356005)(6916009)(81166007)(55016003)(82310400004)(6666004)(6286002)(40460700001)(2876002)(4326008)(70586007)(70206006)(107886003)(316002)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Jan 2022 16:10:16.3322 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0d1e7347-2582-494d-2716-08d9d1f831a4", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT042.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB3894", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Elena Agostini <eagostini@nvidia.com>\n\nImplement aligned GPU memory allocation in GPU CUDA driver.\n\nChangelog:\n- cuda_mem_alloc parameters order\n\nSigned-off-by: Elena Agostini <eagostini@nvidia.com>\n---\n drivers/gpu/cuda/cuda.c | 21 ++++++++++++++++-----\n 1 file changed, 16 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/gpu/cuda/cuda.c b/drivers/gpu/cuda/cuda.c\nindex 882df08e56..dc8d3d3b5a 100644\n--- a/drivers/gpu/cuda/cuda.c\n+++ b/drivers/gpu/cuda/cuda.c\n@@ -139,8 +139,10 @@ typedef uintptr_t cuda_ptr_key;\n /* Single entry of the memory list */\n struct mem_entry {\n \tCUdeviceptr ptr_d;\n+\tCUdeviceptr ptr_orig_d;\n \tvoid *ptr_h;\n \tsize_t size;\n+\tsize_t size_orig;\n \tstruct rte_gpu *dev;\n \tCUcontext ctx;\n \tcuda_ptr_key pkey;\n@@ -569,7 +571,7 @@ cuda_dev_info_get(struct rte_gpu *dev, struct rte_gpu_info *info)\n */\n \n static int\n-cuda_mem_alloc(struct rte_gpu *dev, size_t size, void **ptr)\n+cuda_mem_alloc(struct rte_gpu *dev, size_t size, unsigned int align, void **ptr)\n {\n \tCUresult res;\n \tconst char *err_string;\n@@ -610,8 +612,10 @@ cuda_mem_alloc(struct rte_gpu *dev, size_t size, void **ptr)\n \n \t/* Allocate memory */\n \tmem_alloc_list_tail->size = size;\n-\tres = pfn_cuMemAlloc(&(mem_alloc_list_tail->ptr_d),\n-\t\t\tmem_alloc_list_tail->size);\n+\tmem_alloc_list_tail->size_orig = size + align;\n+\n+\tres = pfn_cuMemAlloc(&(mem_alloc_list_tail->ptr_orig_d),\n+\t\t\tmem_alloc_list_tail->size_orig);\n \tif (res != 0) {\n \t\tpfn_cuGetErrorString(res, &(err_string));\n \t\trte_cuda_log(ERR, \"cuCtxSetCurrent current failed with %s\",\n@@ -620,6 +624,13 @@ cuda_mem_alloc(struct rte_gpu *dev, size_t size, void **ptr)\n \t\treturn -rte_errno;\n \t}\n \n+\n+\t/* Align memory address */\n+\tmem_alloc_list_tail->ptr_d = mem_alloc_list_tail->ptr_orig_d;\n+\tif (align && ((uintptr_t)mem_alloc_list_tail->ptr_d) % align)\n+\t\tmem_alloc_list_tail->ptr_d += (align -\n+\t\t\t\t(((uintptr_t)mem_alloc_list_tail->ptr_d) % align));\n+\n \t/* GPUDirect RDMA attribute required */\n \tres = pfn_cuPointerSetAttribute(&flag,\n \t\t\tCU_POINTER_ATTRIBUTE_SYNC_MEMOPS,\n@@ -634,7 +645,6 @@ cuda_mem_alloc(struct rte_gpu *dev, size_t size, void **ptr)\n \n \tmem_alloc_list_tail->pkey = get_hash_from_ptr((void *)mem_alloc_list_tail->ptr_d);\n \tmem_alloc_list_tail->ptr_h = NULL;\n-\tmem_alloc_list_tail->size = size;\n \tmem_alloc_list_tail->dev = dev;\n \tmem_alloc_list_tail->ctx = (CUcontext)((uintptr_t)dev->mpshared->info.context);\n \tmem_alloc_list_tail->mtype = GPU_MEM;\n@@ -761,6 +771,7 @@ cuda_mem_register(struct rte_gpu *dev, size_t size, void *ptr)\n \tmem_alloc_list_tail->dev = dev;\n \tmem_alloc_list_tail->ctx = (CUcontext)((uintptr_t)dev->mpshared->info.context);\n \tmem_alloc_list_tail->mtype = CPU_REGISTERED;\n+\tmem_alloc_list_tail->ptr_orig_d = mem_alloc_list_tail->ptr_d;\n \n \t/* Restore original ctx as current ctx */\n \tres = pfn_cuCtxSetCurrent(current_ctx);\n@@ -796,7 +807,7 @@ cuda_mem_free(struct rte_gpu *dev, void *ptr)\n \t}\n \n \tif (mem_item->mtype == GPU_MEM) {\n-\t\tres = pfn_cuMemFree(mem_item->ptr_d);\n+\t\tres = pfn_cuMemFree(mem_item->ptr_orig_d);\n \t\tif (res != 0) {\n \t\t\tpfn_cuGetErrorString(res, &(err_string));\n \t\t\trte_cuda_log(ERR, \"cuMemFree current failed with %s\",\n", "prefixes": [ "v2", "3/3" ] }