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GET /api/patches/105713/?format=api
{ "id": 105713, "url": "http://patchwork.dpdk.org/api/patches/105713/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220110113509.553184-5-ssebasti@amd.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220110113509.553184-5-ssebasti@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220110113509.553184-5-ssebasti@amd.com", "date": "2022-01-10T11:35:07", "name": "[v1,4/6] net/axgbe: reset PHY Rx when mailbox command timeout", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "8aea5df3dabd4246bebd319b899737a6ef0de2b6", "submitter": { "id": 1604, "url": "http://patchwork.dpdk.org/api/people/1604/?format=api", "name": "Selwin Sebastian", "email": "ssebasti@amd.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220110113509.553184-5-ssebasti@amd.com/mbox/", "series": [ { "id": 21109, "url": "http://patchwork.dpdk.org/api/series/21109/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=21109", "date": "2022-01-10T11:35:04", "name": "[v1,1/6] net/axgbe: always attempt link training in KR mode", "version": 1, "mbox": "http://patchwork.dpdk.org/series/21109/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/105713/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/105713/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 480D7A034D;\n\tMon, 10 Jan 2022 12:36:07 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 605324118F;\n\tMon, 10 Jan 2022 12:35:42 +0100 (CET)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2052.outbound.protection.outlook.com [40.107.236.52])\n by mails.dpdk.org (Postfix) with ESMTP id 1458341174\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com;", "From": "<ssebasti@amd.com>", "To": "<dev@dpdk.org>", "Subject": "[PATCH v1 4/6] net/axgbe: reset PHY Rx when mailbox command timeout", "Date": "Mon, 10 Jan 2022 17:05:07 +0530", "Message-ID": "<20220110113509.553184-5-ssebasti@amd.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220110113509.553184-1-ssebasti@amd.com>", "References": "<20220110113509.553184-1-ssebasti@amd.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "259d0006-2b90-4cdb-05bd-08d9d42d5273", "X-MS-TrafficTypeDiagnostic": "DM6PR12MB2793:EE_", "X-Microsoft-Antispam-PRVS": "\n <DM6PR12MB279325625D0F930B1C50C2248D509@DM6PR12MB2793.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:3276;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n v7n/3ftlVAz2YRZkF5BdNZZsWtjAKc7pJLo/BfSZ3K0QoNZhiSaAnBv57uP8ZS+4IB3C+V/w7e1l1DuMfaAHz8kXw1++vr2GNg0yxRtN7k/5cgQ9QPSqlRRXmqJXR5LFG808kwYIOmD72DwArj5wORr22z5kSKGA+R0yA5BeK5CmqLiwENZAQtzx+2JBhADCUUIqZPk3edZPcpbZ69a4n9e9YvXAUtNv3hqZ+GLo8gm82TxbqyefmLvqYF2jrEKuVfpI63HBtD9pBKSo/4zXkCnLsC09gTRN+VEf0afWSK6jOtRSKEclRkFhWk5iaiw0qgT4o2GK5J9Tydyyk0PtL41QVL7SZVpGmA7IJNPsLGja8rPgWzN3VXNLiT65ZpUQxtBTohzI3BnSFsNoiqtt0nG0wt/W4gl4n6id9KLR7pA4d1/1YqqRUZmKyI+TE1MC+r3CHxLHCYU+ykO5loRJEAuxBIfJAYlWV59ZjfxPqoc0ezYlrohoBe2/cCfOfPLhpy9eUEfN1IpC/tt0D8C3fO4kzJ9N9bJ8uxjYHQHLGlopY9Vtugzjbjz4lnHMIV16sdLHsI0jrbc/6Kp65zs7I/HToMG9HL8EFWSVD5ExeUmojkYid/mzyR7DHyEJGOzCvIsobHsU8uB93HeB6VdrR3+zwZkJ0Qx6POlPiEGYkYn//77jXFM/HvEjOcj88KX8AqdAm/pgBFrzIUzoLn8lVwE4B1TOcti2MpTCkQfgpKqQobDZfk+r4ynhtXbKRdGFeTMODQA+ywTpz3FE7hSGd4YYxSLLGDUeRtX0nINZchQ=", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(4636009)(36840700001)(40470700002)(46966006)(1076003)(7696005)(82310400004)(40460700001)(426003)(2616005)(2906002)(508600001)(36756003)(336012)(2876002)(15650500001)(5660300002)(26005)(16526019)(186003)(70586007)(70206006)(316002)(81166007)(6666004)(356005)(83380400001)(8936002)(47076005)(6916009)(8676002)(36860700001)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "10 Jan 2022 11:35:36.9960 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 259d0006-2b90-4cdb-05bd-08d9d42d5273", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT021.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB2793", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Selwin Sebastian <selwin.sebastian@amd.com>\n\nSometimes mailbox commands timeout when the RX data path becomes\nunresponsive. This prevents the submission of new mailbox commands\nto DXIO. This patch identifies the timeout and resets the RX data\npath so that the next message can be submitted properly.\n\nSigned-off-by: Selwin Sebastian <selwin.sebastian@amd.com>\n---\n drivers/net/axgbe/axgbe_common.h | 14 ++++++++++++++\n drivers/net/axgbe/axgbe_phy_impl.c | 29 ++++++++++++++++++++++++++++-\n 2 files changed, 42 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h\nindex 5a7ac35b6a..a5431dd998 100644\n--- a/drivers/net/axgbe/axgbe_common.h\n+++ b/drivers/net/axgbe/axgbe_common.h\n@@ -1270,10 +1270,18 @@\n #define MDIO_PMA_10GBR_FECCTRL\t\t0x00ab\n #endif\n \n+#ifndef MDIO_PMA_RX_CTRL1\n+#define MDIO_PMA_RX_CTRL1\t\t0x8051\n+#endif\n+\n #ifndef MDIO_PCS_DIG_CTRL\n #define MDIO_PCS_DIG_CTRL\t\t0x8000\n #endif\n \n+#ifndef MDIO_PCS_DIGITAL_STAT\n+#define MDIO_PCS_DIGITAL_STAT\t\t0x8010\n+#endif\n+\n #ifndef MDIO_AN_XNP\n #define MDIO_AN_XNP\t\t\t0x0016\n #endif\n@@ -1354,6 +1362,8 @@\n #define AXGBE_KR_TRAINING_ENABLE\tBIT(1)\n \n #define AXGBE_PCS_CL37_BP\t\tBIT(12)\n+#define XGBE_PCS_PSEQ_STATE_MASK\t0x1c\n+#define XGBE_PCS_PSEQ_STATE_POWER_GOOD\t0x10\n \n #define AXGBE_AN_CL37_INT_CMPLT\t\tBIT(0)\n #define AXGBE_AN_CL37_INT_MASK\t\t0x01\n@@ -1401,6 +1411,10 @@ static inline uint32_t high32_value(uint64_t addr)\n #define XGBE_PMA_PLL_CTRL_SET BIT(15)\n #define XGBE_PMA_PLL_CTRL_CLEAR 0x0000\n \n+#define XGBE_PMA_RX_RST_0_MASK BIT(4)\n+#define XGBE_PMA_RX_RST_0_RESET_ON 0x10\n+#define XGBE_PMA_RX_RST_0_RESET_OFF 0x00\n+\n /*END*/\n \n /* Bit setting and getting macros\ndiff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c\nindex 0894dbf74b..e52dbb9585 100644\n--- a/drivers/net/axgbe/axgbe_phy_impl.c\n+++ b/drivers/net/axgbe/axgbe_phy_impl.c\n@@ -1196,6 +1196,28 @@ static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata)\n \taxgbe_phy_put_comm_ownership(pdata);\n }\n \n+static void axgbe_phy_rx_reset(struct axgbe_port *pdata)\n+{\n+\tint reg;\n+\n+\treg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT,\n+\t\t\t XGBE_PCS_PSEQ_STATE_MASK);\n+\tif (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) {\n+\t\t/* Mailbox command timed out, reset of RX block is required.\n+\t\t * This can be done by asseting the reset bit and wait for\n+\t\t * its compeletion.\n+\t\t */\n+\t\tXMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,\n+\t\t\t\t XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON);\n+\t\trte_delay_us(20);\n+\t\tXMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1,\n+\t\t\t\t XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF);\n+\t\trte_delay_us(45);\n+\t\tPMD_DRV_LOG(ERR, \"firmware mailbox reset performed\\n\");\n+\t}\n+}\n+\n+\n static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)\n {\n \tXMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,\n@@ -1216,8 +1238,10 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,\n \taxgbe_phy_pll_ctrl(pdata, false);\n \n \t/* Log if a previous command did not complete */\n-\tif (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))\n+\tif (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {\n \t\tPMD_DRV_LOG(NOTICE, \"firmware mailbox not ready for command\\n\");\n+\t\taxgbe_phy_rx_reset(pdata);\n+\t}\n \n \t/* Construct the command */\n \tXP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);\n@@ -1235,6 +1259,9 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,\n \t\t\tgoto reenable_pll;\n \t\trte_delay_us(1500);\n \t}\n+\tPMD_DRV_LOG(NOTICE, \"firmware mailbox command did not complete\\n\");\n+\t/* Reset on error */\n+\taxgbe_phy_rx_reset(pdata);\n \n reenable_pll:\n \t /* Re-enable the PLL control */\n", "prefixes": [ "v1", "4/6" ] }