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GET /api/patches/106629/?format=api
{ "id": 106629, "url": "http://patchwork.dpdk.org/api/patches/106629/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220127153950.812953-12-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220127153950.812953-12-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220127153950.812953-12-michaelba@nvidia.com", "date": "2022-01-27T15:39:41", "name": "[11/20] net/mlx5: share realtime timestamp configure", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5d2c2d8d92b83550db62da1a531dfc4a4ff18453", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220127153950.812953-12-michaelba@nvidia.com/mbox/", "series": [ { "id": 21402, "url": "http://patchwork.dpdk.org/api/series/21402/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=21402", "date": "2022-01-27T15:39:30", "name": "mlx5: refactor devargs management", "version": 1, "mbox": "http://patchwork.dpdk.org/series/21402/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/106629/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/106629/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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timestamp configure", "Date": "Thu, 27 Jan 2022 17:39:41 +0200", "Message-ID": "<20220127153950.812953-12-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220127153950.812953-1-michaelba@nvidia.com>", "References": "<20220127153950.812953-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "193df303-4c9d-4cd3-af4e-08d9e1ab5222", "X-MS-TrafficTypeDiagnostic": "CH0PR12MB5171:EE_", "X-Microsoft-Antispam-PRVS": "\n <CH0PR12MB5171B27CAA6B0F0859D2AF18CC219@CH0PR12MB5171.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:5797;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(86362001)(82310400004)(2906002)(508600001)(6666004)(7696005)(47076005)(40460700003)(316002)(54906003)(6916009)(5660300002)(8936002)(107886003)(356005)(81166007)(26005)(8676002)(4326008)(2616005)(36860700001)(6286002)(83380400001)(186003)(55016003)(36756003)(336012)(1076003)(426003)(70586007)(70206006)(36900700001)(20210929001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Jan 2022 15:40:18.1423 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 193df303-4c9d-4cd3-af4e-08d9e1ab5222", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT064.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH0PR12MB5171", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The realtime timestamp configure work for Linux as same as Windows.\nThis patch removes it to the function implemented in the folder shared\nbetween the operating systems, removing the duplication.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 23 ++-----------------\n drivers/net/mlx5/mlx5.c | 37 ++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h | 3 +++\n drivers/net/mlx5/windows/mlx5_os.c | 22 +-----------------\n 4 files changed, 43 insertions(+), 42 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 2fb91fec06..bb90cc4426 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1516,27 +1516,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\t\tpriv->dev_port);\n \t\t}\n \t}\n-\tif (sh->cdev->config.devx) {\n-\t\tuint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];\n-\n-\t\terr = hca_attr->access_register_user ?\n-\t\t\tmlx5_devx_cmd_register_read\n-\t\t\t\t(sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,\n-\t\t\t\treg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;\n-\t\tif (!err) {\n-\t\t\tuint32_t ts_mode;\n-\n-\t\t\t/* MTUTC register is read successfully. */\n-\t\t\tts_mode = MLX5_GET(register_mtutc, reg,\n-\t\t\t\t\t time_stamp_mode);\n-\t\t\tif (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)\n-\t\t\t\tconfig->rt_timestamp = 1;\n-\t\t} else {\n-\t\t\t/* Kernel does not support register reading. */\n-\t\t\tif (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))\n-\t\t\t\tconfig->rt_timestamp = 1;\n-\t\t}\n-\t}\n+\tif (sh->cdev->config.devx)\n+\t\tmlx5_rt_timestamp_config(sh, config, hca_attr);\n \t/*\n \t * If HW has bug working with tunnel packet decapsulation and\n \t * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex b371a87355..5146359100 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1129,6 +1129,43 @@ mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh)\n \treturn 0;\n }\n \n+/**\n+ * Configure realtime timestamp format.\n+ *\n+ * @param sh\n+ * Pointer to mlx5_dev_ctx_shared object.\n+ * @param config\n+ * Device configuration parameters.\n+ * @param hca_attr\n+ * Pointer to DevX HCA capabilities structure.\n+ */\n+void\n+mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,\n+\t\t\t struct mlx5_dev_config *config,\n+\t\t\t struct mlx5_hca_attr *hca_attr)\n+{\n+\tuint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc);\n+\tuint32_t reg[dw_cnt];\n+\tint ret = ENOTSUP;\n+\n+\tif (hca_attr->access_register_user)\n+\t\tret = mlx5_devx_cmd_register_read(sh->cdev->ctx,\n+\t\t\t\t\t\t MLX5_REGISTER_ID_MTUTC, 0,\n+\t\t\t\t\t\t reg, dw_cnt);\n+\tif (!ret) {\n+\t\tuint32_t ts_mode;\n+\n+\t\t/* MTUTC register is read successfully. */\n+\t\tts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode);\n+\t\tif (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)\n+\t\t\tconfig->rt_timestamp = 1;\n+\t} else {\n+\t\t/* Kernel does not support register reading. */\n+\t\tif (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))\n+\t\t\tconfig->rt_timestamp = 1;\n+\t}\n+}\n+\n /**\n * Allocate shared device context. If there is multiport device the\n * master and representors will share this context, if there is single\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 6bc7a34f60..0f90d757e9 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1517,6 +1517,9 @@ void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh);\n \t port_id < RTE_MAX_ETHPORTS; \\\n \t port_id = mlx5_eth_find_next(port_id + 1, dev))\n int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs);\n+void mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh,\n+\t\t\t struct mlx5_dev_config *config,\n+\t\t\t struct mlx5_hca_attr *hca_attr);\n struct mlx5_dev_ctx_shared *\n mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,\n \t\t\t const struct mlx5_dev_config *config);\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex 178e58b4d7..a9c7ba2a14 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -483,27 +483,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\tDRV_LOG(DEBUG, \"VLAN stripping is %ssupported\",\n \t\t\t(config->hw_vlan_strip ? \"\" : \"not \"));\n \t\tconfig->hw_fcs_strip = hca_attr->scatter_fcs;\n-\t}\n-\tif (sh->devx) {\n-\t\tuint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];\n-\n-\t\terr = hca_attr->access_register_user ?\n-\t\t\tmlx5_devx_cmd_register_read\n-\t\t\t\t(sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,\n-\t\t\t\treg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;\n-\t\tif (!err) {\n-\t\t\tuint32_t ts_mode;\n-\n-\t\t\t/* MTUTC register is read successfully. */\n-\t\t\tts_mode = MLX5_GET(register_mtutc, reg,\n-\t\t\t\t\t time_stamp_mode);\n-\t\t\tif (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)\n-\t\t\t\tconfig->rt_timestamp = 1;\n-\t\t} else {\n-\t\t\t/* Kernel does not support register reading. */\n-\t\t\tif (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S))\n-\t\t\t\tconfig->rt_timestamp = 1;\n-\t\t}\n+\t\tmlx5_rt_timestamp_config(sh, config, hca_attr);\n \t}\n \tif (config->mprq.enabled) {\n \t\tDRV_LOG(WARNING, \"Multi-Packet RQ isn't supported\");\n", "prefixes": [ "11/20" ] }