Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/106633/?format=api
{ "id": 106633, "url": "http://patchwork.dpdk.org/api/patches/106633/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220127153950.812953-13-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220127153950.812953-13-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220127153950.812953-13-michaelba@nvidia.com", "date": "2022-01-27T15:39:42", "name": "[12/20] net/mlx5: share counter config function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "29b647c6ea806ee2a0ffef5feee7c30a343f9eef", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220127153950.812953-13-michaelba@nvidia.com/mbox/", "series": [ { "id": 21402, "url": "http://patchwork.dpdk.org/api/series/21402/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=21402", "date": "2022-01-27T15:39:30", "name": "mlx5: refactor devargs management", "version": 1, "mbox": "http://patchwork.dpdk.org/series/21402/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/106633/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/106633/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CFB7DA04A6;\n\tThu, 27 Jan 2022 16:41:55 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 75963428EB;\n\tThu, 27 Jan 2022 16:40:28 +0100 (CET)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2043.outbound.protection.outlook.com [40.107.93.43])\n by mails.dpdk.org (Postfix) with ESMTP id 761AC428DE\n for <dev@dpdk.org>; Thu, 27 Jan 2022 16:40:26 +0100 (CET)", "from BN9PR03CA0845.namprd03.prod.outlook.com (2603:10b6:408:13d::10)\n by BY5PR12MB4292.namprd12.prod.outlook.com (2603:10b6:a03:212::12)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4930.15; Thu, 27 Jan\n 2022 15:40:23 +0000", "from BN8NAM11FT046.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:13d:cafe::10) by BN9PR03CA0845.outlook.office365.com\n (2603:10b6:408:13d::10) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4930.15 via Frontend\n Transport; Thu, 27 Jan 2022 15:40:23 +0000", "from mail.nvidia.com (12.22.5.234) by\n BN8NAM11FT046.mail.protection.outlook.com (10.13.177.127) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4930.15 via Frontend Transport; Thu, 27 Jan 2022 15:40:23 +0000", "from drhqmail203.nvidia.com (10.126.190.182) by\n DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id\n 15.0.1497.18; Thu, 27 Jan 2022 15:40:19 +0000", "from drhqmail202.nvidia.com (10.126.190.181) by\n drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9;\n Thu, 27 Jan 2022 07:40:18 -0800", "from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.181)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9 via Frontend\n Transport; Thu, 27 Jan 2022 07:40:17 -0800" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=AOqKX2W3UE2C/Fpu4m6eil/vrKizbWLejIMYkM4/qhX1P+uIpx6WbYDnbI2p8VOP3/stDKe1YRAJABkoxHLuWQeI6Ojo58FyZhU5lgvfRkqSBGf4LGQb1KTWHOF54KMCM4I/ULVvm6PiiekP8x584/amF9oo7NHOwREcfqI+A9fL4ommmussKgTNccOWh6oaKC5tnSP8MN9nsK8gFsU4FxW1Cu9mx+JliZv1g9H2Dn7AFEE05OgvRDA3GFvGFDCvPkzwMjfmVT2vgYjq6u03FHvvfNV8ey2KqMoySOceEGcCyhu1cKTroDDDVMAQOLOwwoYJJJDpgY8X/705na9qWQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=nOO3fpXBcInfQhVZMRC1l5idFk6trimTkDuMclZ2Lqw=;\n b=Y85pbVReC3VZgLXT1kdR0dXeImW5QNt1pTCHmdISSIvFVqHOIaAHcUS1gHQpSvNvd7BlCyyq2qEFNrFjWP91O3M8K7BPeWL9EZuiwSpLgwE0PGLo3rK0CK/1r1aacEy9dU06AxHT8+B/IRVfXw1WDxSeGxEvHBLNwpj5MPb+0PqRDMvrQRinfjEvJ1K/Ge/+bSquNXfJOZ98oFeP5NIL8ON5a1WztFjOoSbpeBq3guN05O2Wh+JK90VHSVvjua9xmhJo5V31SmezjALuXqeeqHxBuDYt0oa/fRwHNOfqIZy9wjk5WBMvPnCSXT5nf0kbbFT6dJNMtNIfaTs94610tQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 12.22.5.234) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass\n (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none\n (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=nOO3fpXBcInfQhVZMRC1l5idFk6trimTkDuMclZ2Lqw=;\n b=lPu94IONusrmPKzzumdN54skKE039BFb+wTpEk7gDc2HjwFtUo9bUbkI0zIdXdZjCgeGPwd2IwjTlQUqAH85wSSG6ggXlUtDkIgNMa+4NiGgfEeJDHk3UEWHOxpSMCoWToMPPGwwdPequ/0ZKsDTzw8dqT+oVPkAzUwaZmo/fkpEEymTU1gZm2VSRkDxt8+i590+qHi+NLjjm/uxF5Av7N/VH0szZ4oyM8QXLaq01myrvt3RfnYdPX4BVRTqeyUzZkQk1gNMMbpTYuex8+m/NSSZAWkiAl6mF2giugXq1HEs9m2QhrTUCNPpZK6MB4wgj4npt115dBNPR9VtY4nEiA==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 12.22.5.234)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 12.22.5.234 as permitted sender) receiver=protection.outlook.com;\n client-ip=12.22.5.234; helo=mail.nvidia.com;", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Subject": "[PATCH 12/20] net/mlx5: share counter config function", "Date": "Thu, 27 Jan 2022 17:39:42 +0200", "Message-ID": "<20220127153950.812953-13-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220127153950.812953-1-michaelba@nvidia.com>", "References": "<20220127153950.812953-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "96bb129c-2e77-4c9b-b28c-08d9e1ab555c", "X-MS-TrafficTypeDiagnostic": "BY5PR12MB4292:EE_", "X-Microsoft-Antispam-PRVS": "\n <BY5PR12MB4292A7527890F0E9008FF50CCC219@BY5PR12MB4292.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:9508;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n JR4SzaMyAq4j7Bat+Bv7F1ZRnHXHXlItj7K6wFlqTPJSTGEZeeruxoRdfOm+PuXH5Rr8Q7qEuoIN/Ed+lr6Q7jvxq9IFONPOkh/AriPYqZTD/1r7iLB/mfgjJOBRmJm8P6Q28t0jeBqaTR63H1+YvIFv4b2LVOzJ8iwNadgRo7Hw4ozWPafCib0usT2vjIyR0Bf4Zi+y+C04ieGoqpZ8Leugtwb613T86ZJN+03MjICaIfULUvw0S0gPA2epsowNzPWBQLkVherWmrzIxIFS3HPBjcgyyKNtdIsYXUuCGEC8SkZqhb4etIg6TqQUZKsgP1oo1VMgKVx/ba0kMnioviiPIF+jHEQY3OYPrWgLg2vwHvMLMem/4ikQrkrmnMghXFXvXhrDe98PrAgGNiZBnfecM+XNPiwOwKbjKMG6WAYo1tdpfRO/fMuuDc5rYyGd9dzAIGcPA+Y5uwapYgYq1FX6/1xhz3OwBazkbi9wyycfn0KA8Aat8gS8ECMkcyPRZC2yHIPFdPYWI478gqj5JLdeDYMrunp4mscs/X1V7p9IfUGQIvqxp+NBCRoOat5aWFJLOUZwEBLRblbzDezNvGUYmPtcvPg3G1WM2q0DKtfrBz+nDdws5zSx8l0nNjV/sdcBsvM9Odv09sxT9FK2Mgx4/3B0O/VHWt2ixoH/cyMSKVnJCsRSGsKZ7CipIiPKLPLcs1GhMer9aC46i1e+ZA==", "X-Forefront-Antispam-Report": "CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(4326008)(36860700001)(47076005)(83380400001)(5660300002)(36756003)(70586007)(70206006)(2906002)(8936002)(8676002)(40460700003)(107886003)(6916009)(508600001)(426003)(186003)(86362001)(26005)(336012)(54906003)(316002)(6286002)(2616005)(1076003)(82310400004)(81166007)(356005)(6666004)(7696005)(55016003)(36900700001)(20210929001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Jan 2022 15:40:23.5556 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 96bb129c-2e77-4c9b-b28c-08d9e1ab555c", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT046.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB4292", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The mlx5_flow_counter_mode_config function exists for both Linux and\nWindows with the same name and content.\nThis patch moves its implementation to the folder shared between the\noperating systems, removing the duplication.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 40 ------------------------------\n drivers/net/mlx5/mlx5.c | 40 ++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/windows/mlx5_os.c | 40 ------------------------------\n 4 files changed, 41 insertions(+), 80 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex bb90cc4426..9a05c1ba44 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -673,46 +673,6 @@ mlx5_init_once(void)\n \treturn ret;\n }\n \n-/**\n- * DV flow counter mode detect and config.\n- *\n- * @param dev\n- * Pointer to rte_eth_dev structure.\n- *\n- */\n-static void\n-mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)\n-{\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n-\tstruct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;\n-\tbool fallback;\n-\n-#ifndef HAVE_IBV_DEVX_ASYNC\n-\tfallback = true;\n-#else\n-\tfallback = false;\n-\tif (!sh->cdev->config.devx || !priv->config.dv_flow_en ||\n-\t !hca_attr->flow_counters_dump ||\n-\t !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||\n-\t (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))\n-\t\tfallback = true;\n-#endif\n-\tif (fallback)\n-\t\tDRV_LOG(INFO, \"Use fall-back DV counter management. Flow \"\n-\t\t\t\"counter dump:%d, bulk_alloc_bitmap:0x%hhx.\",\n-\t\t\thca_attr->flow_counters_dump,\n-\t\t\thca_attr->flow_counter_bulk_alloc_bitmap);\n-\t/* Initialize fallback mode only on the port initializes sh. */\n-\tif (sh->refcnt == 1)\n-\t\tsh->cmng.counter_fallback = fallback;\n-\telse if (fallback != sh->cmng.counter_fallback)\n-\t\tDRV_LOG(WARNING, \"Port %d in sh has different fallback mode \"\n-\t\t\t\"with others:%d.\", PORT_ID(priv), fallback);\n-#endif\n-}\n-\n /**\n * DR flow drop action support detect.\n *\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 5146359100..27bcca9012 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -513,6 +513,46 @@ mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)\n \t}\n }\n \n+/**\n+ * DV flow counter mode detect and config.\n+ *\n+ * @param dev\n+ * Pointer to rte_eth_dev structure.\n+ *\n+ */\n+void\n+mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)\n+{\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n+\tstruct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;\n+\tbool fallback;\n+\n+#ifndef HAVE_IBV_DEVX_ASYNC\n+\tfallback = true;\n+#else\n+\tfallback = false;\n+\tif (!sh->cdev->config.devx || !priv->config.dv_flow_en ||\n+\t !hca_attr->flow_counters_dump ||\n+\t !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||\n+\t (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))\n+\t\tfallback = true;\n+#endif\n+\tif (fallback)\n+\t\tDRV_LOG(INFO, \"Use fall-back DV counter management. Flow \"\n+\t\t\t\"counter dump:%d, bulk_alloc_bitmap:0x%hhx.\",\n+\t\t\thca_attr->flow_counters_dump,\n+\t\t\thca_attr->flow_counter_bulk_alloc_bitmap);\n+\t/* Initialize fallback mode only on the port initializes sh. */\n+\tif (sh->refcnt == 1)\n+\t\tsh->cmng.counter_fallback = fallback;\n+\telse if (fallback != sh->cmng.counter_fallback)\n+\t\tDRV_LOG(WARNING, \"Port %d in sh has different fallback mode \"\n+\t\t\t\"with others:%d.\", PORT_ID(priv), fallback);\n+#endif\n+}\n+\n /**\n * Initialize the counters management structure.\n *\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 0f90d757e9..d69b6a357b 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1535,6 +1535,7 @@ int mlx5_dev_check_sibling_config(struct mlx5_dev_ctx_shared *sh,\n \t\t\t\t struct rte_device *dpdk_dev);\n bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev);\n int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev);\n+void mlx5_flow_counter_mode_config(struct rte_eth_dev *dev);\n int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh);\n int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh);\n int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh);\ndiff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c\nindex a9c7ba2a14..eaa63ad50f 100644\n--- a/drivers/net/mlx5/windows/mlx5_os.c\n+++ b/drivers/net/mlx5/windows/mlx5_os.c\n@@ -255,46 +255,6 @@ mlx5_os_set_nonblock_channel_fd(int fd)\n \treturn -ENOTSUP;\n }\n \n-/**\n- * DV flow counter mode detect and config.\n- *\n- * @param dev\n- * Pointer to rte_eth_dev structure.\n- *\n- */\n-static void\n-mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)\n-{\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_dev_ctx_shared *sh = priv->sh;\n-\tstruct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr;\n-\tbool fallback;\n-\n-#ifndef HAVE_IBV_DEVX_ASYNC\n-\tfallback = true;\n-#else\n-\tfallback = false;\n-\tif (!sh->cdev->config.devx || !priv->config.dv_flow_en ||\n-\t !hca_attr->flow_counters_dump ||\n-\t !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) ||\n-\t (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))\n-\t\tfallback = true;\n-#endif\n-\tif (fallback)\n-\t\tDRV_LOG(INFO, \"Use fall-back DV counter management. Flow \"\n-\t\t\t\"counter dump:%d, bulk_alloc_bitmap:0x%hhx.\",\n-\t\t\thca_attr->flow_counters_dump,\n-\t\t\thca_attr->flow_counter_bulk_alloc_bitmap);\n-\t/* Initialize fallback mode only on the port initializes sh. */\n-\tif (sh->refcnt == 1)\n-\t\tsh->cmng.counter_fallback = fallback;\n-\telse if (fallback != sh->cmng.counter_fallback)\n-\t\tDRV_LOG(WARNING, \"Port %d in sh has different fallback mode \"\n-\t\t\t\"with others:%d.\", PORT_ID(priv), fallback);\n-#endif\n-}\n-\n /**\n * Spawn an Ethernet device from DevX information.\n *\n", "prefixes": [ "12/20" ] }