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GET /api/patches/107821/?format=api
{ "id": 107821, "url": "http://patchwork.dpdk.org/api/patches/107821/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220218171527.56719-5-kai.ji@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220218171527.56719-5-kai.ji@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220218171527.56719-5-kai.ji@intel.com", "date": "2022-02-18T17:15:22", "name": "[v9,4/9] crypto/qat: rework asymmetric op build operation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e9b0b2e21048264f2bccfaa220b5cca9a39477da", "submitter": { "id": 2202, "url": "http://patchwork.dpdk.org/api/people/2202/?format=api", "name": "Ji, Kai", "email": "kai.ji@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220218171527.56719-5-kai.ji@intel.com/mbox/", "series": [ { "id": 21741, "url": "http://patchwork.dpdk.org/api/series/21741/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=21741", "date": "2022-02-18T17:15:18", "name": "drivers/qat: QAT symmetric crypto datapatch rework", "version": 9, "mbox": "http://patchwork.dpdk.org/series/21741/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/107821/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/107821/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 92569A0032;\n\tFri, 18 Feb 2022 18:16:11 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 250E44115B;\n\tFri, 18 Feb 2022 18:15:53 +0100 (CET)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id C19034113F\n for <dev@dpdk.org>; Fri, 18 Feb 2022 18:15:48 +0100 (CET)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 18 Feb 2022 09:15:37 -0800", "from silpixa00400465.ir.intel.com ([10.55.128.22])\n by orsmga005.jf.intel.com with ESMTP; 18 Feb 2022 09:15:35 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1645204549; x=1676740549;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=vjUgdc06kCFt1n1IQ2zZQ7UHowwAsUUxtoOMUWF58eU=;\n b=VmKxacJlXXwwgdC3eGfJVh7bTkRmzvxkHZxMe/G0+klMW/n12ARoeNhc\n o7+SV/OMxwGk+BY8J9h2Dqz0vSwuj6p3d3Wtyif2ypcIaMyhJ0hve75dg\n Za3cS2FQVCl8fKOIHv5KYoFbnWAjSoVk+/QRrH39pLq5hNk5q5Z3XUwWv\n NWkvjlkOoZcD5yu2czr34nXcqguiGxueBU7XrBKbDn4/22Z//n4wwiINI\n 2ua34+xQol+eKzFxzDEXPu1rPNQNhRJpfbNcrchIrb1ic0CQXEWsyfnrv\n M8jyMof1yyGGUYh9xIQ9B6MensqOMw0VWhMJ3af+fy5YIJjCtDHU20A4a A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10262\"; a=\"238571899\"", "E=Sophos;i=\"5.88,379,1635231600\"; d=\"scan'208\";a=\"238571899\"", "E=Sophos;i=\"5.88,379,1635231600\"; d=\"scan'208\";a=\"705446230\"" ], "X-ExtLoop1": "1", "From": "Kai Ji <kai.ji@intel.com>", "To": "dev@dpdk.org", "Cc": "gakhil@marvell.com,\n\troy.fan.zhang@intel.com,\n\tKai Ji <kai.ji@intel.com>", "Subject": "[dpdk-dev v9 4/9] crypto/qat: rework asymmetric op build operation", "Date": "Sat, 19 Feb 2022 01:15:22 +0800", "Message-Id": "<20220218171527.56719-5-kai.ji@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20220218171527.56719-1-kai.ji@intel.com>", "References": "<20220217162909.22713-1-kai.ji@intel.com>\n <20220218171527.56719-1-kai.ji@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch reworks the asymmetric crypto data path\nimplementation in QAT driver. The changes include asymmetric\ncrypto data path separation for QAT hardware generations, and\ncode optimisation of the device capabilities declaration.\n\nSigned-off-by: Kai Ji <kai.ji@intel.com>\n---\n drivers/common/qat/qat_qp.c | 5 +-\n drivers/crypto/qat/qat_asym.c | 129 +++++++++++++++++++---------------\n drivers/crypto/qat/qat_asym.h | 63 +++++++++++++++--\n 3 files changed, 131 insertions(+), 66 deletions(-)", "diff": "diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c\nindex 56234ca1a4..7f2fdc53ce 100644\n--- a/drivers/common/qat/qat_qp.c\n+++ b/drivers/common/qat/qat_qp.c\n@@ -619,7 +619,7 @@ qat_enqueue_op_burst(void *qp,\n #ifdef BUILD_QAT_ASYM\n \t\t\tret = qat_asym_build_request(*ops, base_addr + tail,\n \t\t\t\ttmp_qp->op_cookies[tail >> queue->trailz],\n-\t\t\t\ttmp_qp->qat_dev_gen);\n+\t\t\t\tNULL, tmp_qp->qat_dev_gen);\n #endif\n \t\t}\n \t\tif (ret != 0) {\n@@ -847,7 +847,8 @@ qat_dequeue_op_burst(void *qp, void **ops,\n #ifdef BUILD_QAT_ASYM\n \t\telse if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC)\n \t\t\tqat_asym_process_response(ops, resp_msg,\n-\t\t\t\ttmp_qp->op_cookies[head >> rx_queue->trailz]);\n+\t\t\t\ttmp_qp->op_cookies[head >> rx_queue->trailz],\n+\t\t\t\tNULL);\n #endif\n \n \t\thead = adf_modulo(head + rx_queue->msg_size,\ndiff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c\nindex f46eefd4b3..845e905a89 100644\n--- a/drivers/crypto/qat/qat_asym.c\n+++ b/drivers/crypto/qat/qat_asym.c\n@@ -1,68 +1,36 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2019 Intel Corporation\n+ * Copyright(c) 2019 - 2022 Intel Corporation\n */\n \n #include <stdarg.h>\n \n-#include \"qat_asym.h\"\n+#include <cryptodev_pmd.h>\n+\n #include \"icp_qat_fw_pke.h\"\n #include \"icp_qat_fw.h\"\n #include \"qat_pke_functionality_arrays.h\"\n \n-#define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg))\n-\n-static int qat_asym_get_sz_and_func_id(const uint32_t arr[][2],\n-\t\tsize_t arr_sz, size_t *size, uint32_t *func_id)\n-{\n-\tsize_t i;\n-\n-\tfor (i = 0; i < arr_sz; i++) {\n-\t\tif (*size <= arr[i][0]) {\n-\t\t\t*size = arr[i][0];\n-\t\t\t*func_id = arr[i][1];\n-\t\t\treturn 0;\n-\t\t}\n-\t}\n-\treturn -1;\n-}\n-\n-static inline void qat_fill_req_tmpl(struct icp_qat_fw_pke_request *qat_req)\n-{\n-\tmemset(qat_req, 0, sizeof(*qat_req));\n-\tqat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;\n-\n-\tqat_req->pke_hdr.hdr_flags =\n-\t\t\tICP_QAT_FW_COMN_HDR_FLAGS_BUILD\n-\t\t\t(ICP_QAT_FW_COMN_REQ_FLAG_SET);\n-}\n-\n-static inline void qat_asym_build_req_tmpl(void *sess_private_data)\n-{\n-\tstruct icp_qat_fw_pke_request *qat_req;\n-\tstruct qat_asym_session *session = sess_private_data;\n+#include \"qat_device.h\"\n \n-\tqat_req = &session->req_tmpl;\n-\tqat_fill_req_tmpl(qat_req);\n-}\n+#include \"qat_logs.h\"\n+#include \"qat_asym.h\"\n \n-static size_t max_of(int n, ...)\n-{\n-\tva_list args;\n-\tsize_t len = 0, num;\n-\tint i;\n+uint8_t qat_asym_driver_id;\n \n-\tva_start(args, n);\n-\tlen = va_arg(args, size_t);\n+struct qat_crypto_gen_dev_ops qat_asym_gen_dev_ops[QAT_N_GENS];\n \n-\tfor (i = 0; i < n - 1; i++) {\n-\t\tnum = va_arg(args, size_t);\n-\t\tif (num > len)\n-\t\t\tlen = num;\n-\t}\n-\tva_end(args);\n+/* An rte_driver is needed in the registration of both the device and the driver\n+ * with cryptodev.\n+ * The actual qat pci's rte_driver can't be used as its name represents\n+ * the whole pci device with all services. Think of this as a holder for a name\n+ * for the crypto part of the pci device.\n+ */\n+static const char qat_asym_drv_name[] = RTE_STR(CRYPTODEV_NAME_QAT_ASYM_PMD);\n+static const struct rte_driver cryptodev_qat_asym_driver = {\n+\t.name = qat_asym_drv_name,\n+\t.alias = qat_asym_drv_name\n+};\n \n-\treturn len;\n-}\n \n static void qat_clear_arrays(struct qat_asym_op_cookie *cookie,\n \t\tint in_count, int out_count, int alg_size)\n@@ -106,7 +74,46 @@ static void qat_clear_arrays_by_alg(struct qat_asym_op_cookie *cookie,\n \t}\n }\n \n-static int qat_asym_check_nonzero(rte_crypto_param n)\n+#define qat_asym_sz_2param(arg) (arg, sizeof(arg)/sizeof(*arg))\n+\n+static int\n+qat_asym_get_sz_and_func_id(const uint32_t arr[][2],\n+\t\tsize_t arr_sz, size_t *size, uint32_t *func_id)\n+{\n+\tsize_t i;\n+\n+\tfor (i = 0; i < arr_sz; i++) {\n+\t\tif (*size <= arr[i][0]) {\n+\t\t\t*size = arr[i][0];\n+\t\t\t*func_id = arr[i][1];\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\treturn -1;\n+}\n+\n+static size_t\n+max_of(int n, ...)\n+{\n+\tva_list args;\n+\tsize_t len = 0, num;\n+\tint i;\n+\n+\tva_start(args, n);\n+\tlen = va_arg(args, size_t);\n+\n+\tfor (i = 0; i < n - 1; i++) {\n+\t\tnum = va_arg(args, size_t);\n+\t\tif (num > len)\n+\t\t\tlen = num;\n+\t}\n+\tva_end(args);\n+\n+\treturn len;\n+}\n+\n+static int\n+qat_asym_check_nonzero(rte_crypto_param n)\n {\n \tif (n.length < 8) {\n \t\t/* Not a case for any cryptographic function except for DH\n@@ -475,10 +482,9 @@ qat_asym_fill_arrays(struct rte_crypto_asym_op *asym_op,\n }\n \n int\n-qat_asym_build_request(void *in_op,\n-\t\t\tuint8_t *out_msg,\n-\t\t\tvoid *op_cookie,\n-\t\t\t__rte_unused enum qat_device_gen qat_dev_gen)\n+qat_asym_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,\n+\t\t__rte_unused uint64_t *opaque,\n+\t\t__rte_unused enum qat_device_gen dev_gen)\n {\n \tstruct qat_asym_session *ctx;\n \tstruct rte_crypto_op *op = (struct rte_crypto_op *)in_op;\n@@ -677,9 +683,9 @@ static void qat_asym_collect_response(struct rte_crypto_op *rx_op,\n \tqat_clear_arrays_by_alg(cookie, xform, alg_size_in_bytes);\n }\n \n-void\n+int\n qat_asym_process_response(void **op, uint8_t *resp,\n-\t\tvoid *op_cookie)\n+\t\tvoid *op_cookie, __rte_unused uint64_t *dequeue_err_count)\n {\n \tstruct qat_asym_session *ctx;\n \tstruct icp_qat_fw_pke_resp *resp_msg =\n@@ -722,6 +728,8 @@ qat_asym_process_response(void **op, uint8_t *resp,\n \tQAT_DP_HEXDUMP_LOG(DEBUG, \"resp_msg:\", resp_msg,\n \t\t\tsizeof(struct icp_qat_fw_pke_resp));\n #endif\n+\n+\treturn 1;\n }\n \n int\n@@ -779,3 +787,8 @@ qat_asym_session_clear(struct rte_cryptodev *dev,\n \tif (sess_priv)\n \t\tmemset(s, 0, qat_asym_session_get_private_size(dev));\n }\n+\n+static struct cryptodev_driver qat_crypto_drv;\n+RTE_PMD_REGISTER_CRYPTO_DRIVER(qat_crypto_drv,\n+\t\tcryptodev_qat_asym_driver,\n+\t\tqat_asym_driver_id);\ndiff --git a/drivers/crypto/qat/qat_asym.h b/drivers/crypto/qat/qat_asym.h\nindex c9242a12ca..3ae95f2e7b 100644\n--- a/drivers/crypto/qat/qat_asym.h\n+++ b/drivers/crypto/qat/qat_asym.h\n@@ -1,5 +1,5 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2019 Intel Corporation\n+ * Copyright(c) 2022 Intel Corporation\n */\n \n #ifndef _QAT_ASYM_H_\n@@ -8,10 +8,13 @@\n #include <cryptodev_pmd.h>\n #include <rte_crypto_asym.h>\n #include \"icp_qat_fw_pke.h\"\n-#include \"qat_common.h\"\n-#include \"qat_asym_pmd.h\"\n+#include \"qat_device.h\"\n+#include \"qat_crypto.h\"\n #include \"icp_qat_fw.h\"\n \n+/** Intel(R) QAT Asymmetric Crypto PMD driver name */\n+#define CRYPTODEV_NAME_QAT_ASYM_PMD\tcrypto_qat_asym\n+\n typedef uint64_t large_int_ptr;\n #define MAX_PKE_PARAMS\t8\n #define QAT_PKE_MAX_LN_SIZE 512\n@@ -26,6 +29,28 @@ typedef uint64_t large_int_ptr;\n #define QAT_ASYM_RSA_NUM_OUT_PARAMS\t\t1\n #define QAT_ASYM_RSA_QT_NUM_IN_PARAMS\t\t6\n \n+/**\n+ * helper function to add an asym capability\n+ * <name> <op type> <modlen (min, max, increment)>\n+ **/\n+#define QAT_ASYM_CAP(n, o, l, r, i)\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.op = RTE_CRYPTO_OP_TYPE_ASYMMETRIC,\t\t\t\\\n+\t\t{.asym = {\t\t\t\t\t\t\\\n+\t\t\t.xform_capa = {\t\t\t\t\t\\\n+\t\t\t\t.xform_type = RTE_CRYPTO_ASYM_XFORM_##n,\\\n+\t\t\t\t.op_types = o,\t\t\t\t\\\n+\t\t\t\t{\t\t\t\t\t\\\n+\t\t\t\t.modlen = {\t\t\t\t\\\n+\t\t\t\t.min = l,\t\t\t\t\\\n+\t\t\t\t.max = r,\t\t\t\t\\\n+\t\t\t\t.increment = i\t\t\t\t\\\n+\t\t\t\t}, }\t\t\t\t\t\\\n+\t\t\t}\t\t\t\t\t\t\\\n+\t\t},\t\t\t\t\t\t\t\\\n+\t\t}\t\t\t\t\t\t\t\\\n+\t}\n+\n struct qat_asym_op_cookie {\n \tsize_t alg_size;\n \tuint64_t error;\n@@ -45,6 +70,27 @@ struct qat_asym_session {\n \tstruct rte_crypto_asym_xform *xform;\n };\n \n+static inline void\n+qat_fill_req_tmpl(struct icp_qat_fw_pke_request *qat_req)\n+{\n+\tmemset(qat_req, 0, sizeof(*qat_req));\n+\tqat_req->pke_hdr.service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_PKE;\n+\n+\tqat_req->pke_hdr.hdr_flags =\n+\t\t\tICP_QAT_FW_COMN_HDR_FLAGS_BUILD\n+\t\t\t(ICP_QAT_FW_COMN_REQ_FLAG_SET);\n+}\n+\n+static inline void\n+qat_asym_build_req_tmpl(void *sess_private_data)\n+{\n+\tstruct icp_qat_fw_pke_request *qat_req;\n+\tstruct qat_asym_session *session = sess_private_data;\n+\n+\tqat_req = &session->req_tmpl;\n+\tqat_fill_req_tmpl(qat_req);\n+}\n+\n int\n qat_asym_session_configure(struct rte_cryptodev *dev __rte_unused,\n \t\tstruct rte_crypto_asym_xform *xform,\n@@ -75,7 +121,9 @@ qat_asym_session_clear(struct rte_cryptodev *dev,\n */\n int\n qat_asym_build_request(void *in_op, uint8_t *out_msg,\n-\t\tvoid *op_cookie, enum qat_device_gen qat_dev_gen);\n+\t\tvoid *op_cookie,\n+\t\t__rte_unused uint64_t *opaque,\n+\t\tenum qat_device_gen qat_dev_gen);\n \n /*\n * Process PKE response received from outgoing queue of QAT\n@@ -87,8 +135,11 @@ qat_asym_build_request(void *in_op, uint8_t *out_msg,\n * @param\top_cookie\tCookie pointer that holds private metadata\n *\n */\n+int\n+qat_asym_process_response(void **op, uint8_t *resp,\n+\t\tvoid *op_cookie, __rte_unused uint64_t *dequeue_err_count);\n+\n void\n-qat_asym_process_response(void __rte_unused **op, uint8_t *resp,\n-\t\tvoid *op_cookie);\n+qat_asym_init_op_cookie(void *cookie);\n \n #endif /* _QAT_ASYM_H_ */\n", "prefixes": [ "v9", "4/9" ] }