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GET /api/patches/109809/?format=api
{ "id": 109809, "url": "http://patchwork.dpdk.org/api/patches/109809/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220419055921.10566-5-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220419055921.10566-5-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220419055921.10566-5-ndabilpuram@marvell.com", "date": "2022-04-19T05:59:02", "name": "[05/24] common/cnxk: fix SQ flush sequence", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bd152ecec20504f5de9e8eb5fef910ce5f501c44", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220419055921.10566-5-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 22546, "url": "http://patchwork.dpdk.org/api/series/22546/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=22546", "date": "2022-04-19T05:58:58", "name": "[01/24] common/cnxk: add multi channel support for SDP send queues", "version": 1, "mbox": "http://patchwork.dpdk.org/series/22546/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/109809/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/109809/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3D002A00C3;\n\tTue, 19 Apr 2022 08:00:20 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A6949427EB;\n\tTue, 19 Apr 2022 08:00:15 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id D84034161A\n for <dev@dpdk.org>; Tue, 19 Apr 2022 08:00:13 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 23INEdMR010013\n for <dev@dpdk.org>; Mon, 18 Apr 2022 23:00:13 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ffwap25vx-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 18 Apr 2022 23:00:13 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 18 Apr 2022 23:00:08 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 18 Apr 2022 23:00:08 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 147A65B6948;\n Mon, 18 Apr 2022 23:00:05 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=oh9ulFqCrXavR6P50bNajDIYxph0gluleU/7JDh/3L0=;\n b=dh6utwsdFzb12HeZJQD1R8BZgPDLLhyE2gxXgVFBEAmp1+uLeljImtyJZU/OxYBeqjsA\n hKBvR8rrVcjKcgZ+5egttin6J7NXaggrxf1T7+ShFFMzaPuUuW5yg1R6a8xKm/s8xBuY\n IprQfC82zskQ2aITu+E/Pz9lNUixJFTQXwEfDm+fnLbUQxepdzXxKUeYeJYcBYXVD8ql\n Qy0Jv28ncaqan9BsWzo2wcEEw6o/v4YanB72HWRrMAGvVeFNwir9hoDo2kLBX52P4x6M\n b15NR590+w7yb3ZP+ab7WzWfd108g1+s+/wzuPt9dvVF8A2r6AcUmLAYLO9bK14c+bpM 1w==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 05/24] common/cnxk: fix SQ flush sequence", "Date": "Tue, 19 Apr 2022 11:29:02 +0530", "Message-ID": "<20220419055921.10566-5-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220419055921.10566-1-ndabilpuram@marvell.com>", "References": "<20220419055921.10566-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "buce07MlL3xGaugA6g1t8wGxcM48CFJx", "X-Proofpoint-ORIG-GUID": "buce07MlL3xGaugA6g1t8wGxcM48CFJx", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514\n definitions=2022-04-19_02,2022-04-15_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Satha Rao <skoteshwar@marvell.com>\n\nFix SQ flush sequence to issue NIX RX SW Sync after SMQ flush.\nThis sync ensures that all the packets that were inflight are\nflushed out of memory.\n\nThis patch also fixes NULL return issues reported by\nstatic analysis tool in Traffic Manager and sync's mbox\nto that of Kernel version.\n\nFixes: 05d727e8b14a (\"common/cnxk: support NIX traffic management\")\nFixes: 0b7e667ee303 (\"common/cnxk: enable packet marking\")\n\nSigned-off-by: Satha Rao <skoteshwar@marvell.com>\n---\n drivers/common/cnxk/roc_mbox.h | 35 +++++++++++++++++++++++++++++++++--\n drivers/common/cnxk/roc_nix_tm.c | 7 +++++++\n drivers/common/cnxk/roc_nix_tm_mark.c | 9 +++++++++\n 3 files changed, 49 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex b608f58..2c30f19 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -116,7 +116,7 @@ struct mbox_msghdr {\n \t msg_rsp) \\\n \tM(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \\\n \t sso_grp_priority) \\\n-\tM(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \\\n+\tM(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, ssow_lf_inv_req, msg_rsp) \\\n \tM(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \\\n \t msg_rsp) \\\n \tM(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \\\n@@ -125,6 +125,9 @@ struct mbox_msghdr {\n \t sso_hws_stats) \\\n \tM(SSO_HW_RELEASE_XAQ, 0x611, sso_hw_release_xaq_aura, \\\n \t sso_hw_xaq_release, msg_rsp) \\\n+\tM(SSO_CONFIG_LSW, 0x612, ssow_config_lsw, ssow_config_lsw, msg_rsp) \\\n+\tM(SSO_HWS_CHNG_MSHIP, 0x613, ssow_chng_mship, ssow_chng_mship, \\\n+\t msg_rsp) \\\n \t/* TIM mbox IDs (range 0x800 - 0x9FF) */ \\\n \tM(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \\\n \t tim_lf_alloc_rsp) \\\n@@ -259,7 +262,8 @@ struct mbox_msghdr {\n \tM(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \\\n \t nix_bp_cfg_rsp) \\\n \tM(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \\\n-\t msg_rsp)\n+\t msg_rsp) \\\n+\tM(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp)\n \n /* Messages initiated by AF (range 0xC00 - 0xDFF) */\n #define MBOX_UP_CGX_MESSAGES \\\n@@ -1268,6 +1272,33 @@ struct ssow_lf_free_req {\n \tuint16_t __io hws;\n };\n \n+#define SSOW_INVAL_SELECTIVE_VER 0x1000\n+struct ssow_lf_inv_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint16_t nb_hws;\t\t /* Number of HWS to invalidate*/\n+\tuint16_t hws[MAX_RVU_BLKLF_CNT]; /* Array of HWS */\n+};\n+\n+struct ssow_config_lsw {\n+\tstruct mbox_msghdr hdr;\n+#define SSOW_LSW_DIS\t 0\n+#define SSOW_LSW_GW_WAIT 1\n+#define SSOW_LSW_GW_IMM\t 2\n+\tuint8_t __io lsw_mode;\n+#define SSOW_WQE_REL_LSW_WAIT 0\n+#define SSOW_WQE_REL_IMM 1\n+\tuint8_t __io wqe_release;\n+};\n+\n+struct ssow_chng_mship {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io set;\t /* Membership set to modify. */\n+\tuint8_t __io enable;\t /* Enable/Disable the hwgrps. */\n+\tuint8_t __io hws;\t /* HWS to modify. */\n+\tuint16_t __io nb_hwgrps; /* Number of hwgrps in the array */\n+\tuint16_t __io hwgrps[MAX_RVU_BLKLF_CNT]; /* Array of hwgrps. */\n+};\n+\n struct sso_hw_setconfig {\n \tstruct mbox_msghdr hdr;\n \tuint32_t __io npa_aura_id;\ndiff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c\nindex 5b70c7b..42d3abd 100644\n--- a/drivers/common/cnxk/roc_nix_tm.c\n+++ b/drivers/common/cnxk/roc_nix_tm.c\n@@ -590,6 +590,7 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)\n \tstruct nix_tm_node *node, *sibling;\n \tstruct nix_tm_node_list *list;\n \tenum roc_nix_tm_tree tree;\n+\tstruct msg_req *req;\n \tstruct mbox *mbox;\n \tstruct nix *nix;\n \tuint16_t qid;\n@@ -679,6 +680,12 @@ nix_tm_sq_flush_pre(struct roc_nix_sq *sq)\n \t\t\trc);\n \t\tgoto cleanup;\n \t}\n+\n+\treq = mbox_alloc_msg_nix_rx_sw_sync(mbox);\n+\tif (!req)\n+\t\treturn -ENOSPC;\n+\n+\trc = mbox_process(mbox);\n cleanup:\n \t/* Restore cgx state */\n \tif (!roc_nix->io_enabled) {\ndiff --git a/drivers/common/cnxk/roc_nix_tm_mark.c b/drivers/common/cnxk/roc_nix_tm_mark.c\nindex 64cf679..d37292e 100644\n--- a/drivers/common/cnxk/roc_nix_tm_mark.c\n+++ b/drivers/common/cnxk/roc_nix_tm_mark.c\n@@ -110,6 +110,9 @@ nix_tm_update_red_algo(struct nix *nix, bool red_send)\n \n \t\t/* Update txschq config */\n \t\treq = mbox_alloc_msg_nix_txschq_cfg(mbox);\n+\t\tif (req == NULL)\n+\t\t\treturn -ENOSPC;\n+\n \t\treq->lvl = tm_node->hw_lvl;\n \t\tk = prepare_tm_shaper_red_algo(tm_node, req->reg, req->regval,\n \t\t\t\t\t req->regval_mask);\n@@ -208,6 +211,9 @@ nix_tm_mark_init(struct nix *nix)\n \n \t/* Null mark format */\n \treq = mbox_alloc_msg_nix_mark_format_cfg(mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\n \trc = mbox_process_msg(mbox, (void *)&rsp);\n \tif (rc) {\n \t\tplt_err(\"TM failed to alloc null mark format, rc=%d\", rc);\n@@ -220,6 +226,9 @@ nix_tm_mark_init(struct nix *nix)\n \tfor (i = 0; i < ROC_NIX_TM_MARK_MAX; i++) {\n \t\tfor (j = 0; j < ROC_NIX_TM_MARK_COLOR_MAX; j++) {\n \t\t\treq = mbox_alloc_msg_nix_mark_format_cfg(mbox);\n+\t\t\tif (req == NULL)\n+\t\t\t\treturn -ENOSPC;\n+\n \t\t\treq->offset = mark_off[i];\n \n \t\t\tswitch (j) {\n", "prefixes": [ "05/24" ] }