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GET /api/patches/109818/?format=api
{ "id": 109818, "url": "http://patchwork.dpdk.org/api/patches/109818/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220419055921.10566-13-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220419055921.10566-13-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220419055921.10566-13-ndabilpuram@marvell.com", "date": "2022-04-19T05:59:10", "name": "[13/24] net/cnxk: disable default inner chksum for outb inline", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ebccf9d79703083c6cb739876999d2ec01158f81", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220419055921.10566-13-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 22546, "url": "http://patchwork.dpdk.org/api/series/22546/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=22546", "date": "2022-04-19T05:58:58", "name": "[01/24] common/cnxk: add multi channel support for SDP send queues", "version": 1, "mbox": "http://patchwork.dpdk.org/series/22546/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/109818/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/109818/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8DD10A00C3;\n\tTue, 19 Apr 2022 08:01:30 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B05AE427FF;\n\tTue, 19 Apr 2022 08:00:33 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 80A76427ED\n for <dev@dpdk.org>; Tue, 19 Apr 2022 08:00:32 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 23INJ4ZZ009960\n for <dev@dpdk.org>; Mon, 18 Apr 2022 23:00:32 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ffwap25xc-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 18 Apr 2022 23:00:31 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 18 Apr 2022 23:00:29 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 18 Apr 2022 23:00:29 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id D6F795B6943;\n Mon, 18 Apr 2022 23:00:27 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=3hfSLoLJa01oxMl0BXgQasi/inHcb323KecGr9c0ffU=;\n b=D5eqZvIJRrJcCXYWrlqFi+6OVVvllQlHdB8f4TZWu78P/8AKJxPQRoF/BRgOygup9ccL\n 8yxK46qfDLh84OZFMzRKRK+etPvnwniBCwlm5rSS6d9V85GW7pwsWQqpqHUD8mB91gQ4\n J2okYmr4nAOTcaoVDNHIvzy1uvkhK85A8PJ/ecRxSmHeRfyaZ/0FDt/c+NfTOQf9py6+\n rUdIWHUKnS89fOWxetgGU5TgiqU/yYSLhjcNOKJifU2s+U2dnDgYr1iE35f/FLP7K0q9\n iXzDcpNnsVptG+lRMO1OquzEzgqeIxcuYWtvImRwpxfN/cDqMw3iV2yBVf4ngHyhKq21 qQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 13/24] net/cnxk: disable default inner chksum for outb inline", "Date": "Tue, 19 Apr 2022 11:29:10 +0530", "Message-ID": "<20220419055921.10566-13-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220419055921.10566-1-ndabilpuram@marvell.com>", "References": "<20220419055921.10566-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "Okf7tUPMTYqRUbDW3tvM0wsU4qYa0wij", "X-Proofpoint-ORIG-GUID": "Okf7tUPMTYqRUbDW3tvM0wsU4qYa0wij", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514\n definitions=2022-04-19_02,2022-04-15_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Disable default inner L3/L4 checksum generation for outbound inline\npath and enable based on SA options or RTE_MBUF flags as per\nthe spec. Though the checksum generation is not impacting much\nperformance, it is overwriting zero checksum for UDP packets\nwhich is not always good.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/net/cnxk/cn10k_ethdev.h | 4 +++-\n drivers/net/cnxk/cn10k_ethdev_sec.c | 3 +++\n drivers/net/cnxk/cn10k_tx.h | 44 ++++++++++++++++++++++++++++++-------\n 3 files changed, 42 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h\nindex 1e49d65..9642d6a 100644\n--- a/drivers/net/cnxk/cn10k_ethdev.h\n+++ b/drivers/net/cnxk/cn10k_ethdev.h\n@@ -71,7 +71,9 @@ struct cn10k_sec_sess_priv {\n \t\t\tuint8_t mode : 1;\n \t\t\tuint8_t roundup_byte : 5;\n \t\t\tuint8_t roundup_len;\n-\t\t\tuint16_t partial_len;\n+\t\t\tuint16_t partial_len : 10;\n+\t\t\tuint16_t chksum : 2;\n+\t\t\tuint16_t rsvd : 4;\n \t\t};\n \n \t\tuint64_t u64;\ndiff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c\nindex 87bb691..b307215 100644\n--- a/drivers/net/cnxk/cn10k_ethdev_sec.c\n+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c\n@@ -552,6 +552,9 @@ cn10k_eth_sec_session_create(void *device,\n \t\tsess_priv.partial_len = rlens->partial_len;\n \t\tsess_priv.mode = outb_sa_dptr->w2.s.ipsec_mode;\n \t\tsess_priv.outer_ip_ver = outb_sa_dptr->w2.s.outer_ip_ver;\n+\t\t/* Propagate inner checksum enable from SA to fast path */\n+\t\tsess_priv.chksum = (!ipsec->options.ip_csum_enable << 1 |\n+\t\t\t\t !ipsec->options.l4_csum_enable);\n \n \t\t/* Pointer from eth_sec -> outb_sa */\n \t\teth_sec->sa = outb_sa;\ndiff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h\nindex de88a21..981bc9b 100644\n--- a/drivers/net/cnxk/cn10k_tx.h\n+++ b/drivers/net/cnxk/cn10k_tx.h\n@@ -246,6 +246,7 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1,\n {\n \tstruct cn10k_sec_sess_priv sess_priv;\n \tuint32_t pkt_len, dlen_adj, rlen;\n+\tuint8_t l3l4type, chksum;\n \tuint64x2_t cmd01, cmd23;\n \tuintptr_t dptr, nixtx;\n \tuint64_t ucode_cmd[4];\n@@ -256,10 +257,23 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1,\n \n \tsess_priv.u64 = *rte_security_dynfield(m);\n \n-\tif (flags & NIX_TX_NEED_SEND_HDR_W1)\n+\tif (flags & NIX_TX_NEED_SEND_HDR_W1) {\n \t\tl2_len = vgetq_lane_u8(*cmd0, 8);\n-\telse\n+\t\t/* Extract l3l4type either from il3il4type or ol3ol4type */\n+\t\tif (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F &&\n+\t\t flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)\n+\t\t\tl3l4type = vgetq_lane_u8(*cmd0, 13);\n+\t\telse\n+\t\t\tl3l4type = vgetq_lane_u8(*cmd0, 12);\n+\n+\t\tchksum = (l3l4type & 0x1) << 1 | !!(l3l4type & 0x30);\n+\t\tchksum = ~chksum;\n+\t\tsess_priv.chksum = sess_priv.chksum & chksum;\n+\t\t/* Clear SEND header flags */\n+\t\t*cmd0 = vsetq_lane_u16(0, *cmd0, 6);\n+\t} else {\n \t\tl2_len = m->l2_len;\n+\t}\n \n \t/* Retrieve DPTR */\n \tdptr = vgetq_lane_u64(*cmd1, 1);\n@@ -291,8 +305,8 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1,\n \tsa_base &= ~0xFFFFUL;\n \tsa = (uintptr_t)roc_nix_inl_ot_ipsec_outb_sa(sa_base, sess_priv.sa_idx);\n \tucode_cmd[3] = (ROC_CPT_DFLT_ENG_GRP_SE_IE << 61 | 1UL << 60 | sa);\n-\tucode_cmd[0] =\n-\t\t(ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 | pkt_len);\n+\tucode_cmd[0] = (ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 |\n+\t\t\t((uint64_t)sess_priv.chksum) << 32 | pkt_len);\n \n \t/* CPT Word 0 and Word 1 */\n \tcmd01 = vdupq_n_u64((nixtx + 16) | (cn10k_nix_tx_ext_subs(flags) + 1));\n@@ -343,6 +357,7 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr,\n \tstruct cn10k_sec_sess_priv sess_priv;\n \tuint32_t pkt_len, dlen_adj, rlen;\n \tstruct nix_send_hdr_s *send_hdr;\n+\tuint8_t l3l4type, chksum;\n \tuint64x2_t cmd01, cmd23;\n \tunion nix_send_sg_s *sg;\n \tuintptr_t dptr, nixtx;\n@@ -360,10 +375,23 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr,\n \telse\n \t\tsg = (union nix_send_sg_s *)&cmd[2];\n \n-\tif (flags & NIX_TX_NEED_SEND_HDR_W1)\n+\tif (flags & NIX_TX_NEED_SEND_HDR_W1) {\n \t\tl2_len = cmd[1] & 0xFF;\n-\telse\n+\t\t/* Extract l3l4type either from il3il4type or ol3ol4type */\n+\t\tif (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F &&\n+\t\t flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)\n+\t\t\tl3l4type = (cmd[1] >> 40) & 0xFF;\n+\t\telse\n+\t\t\tl3l4type = (cmd[1] >> 32) & 0xFF;\n+\n+\t\tchksum = (l3l4type & 0x1) << 1 | !!(l3l4type & 0x30);\n+\t\tchksum = ~chksum;\n+\t\tsess_priv.chksum = sess_priv.chksum & chksum;\n+\t\t/* Clear SEND header flags */\n+\t\tcmd[1] &= ~(0xFFFFUL << 32);\n+\t} else {\n \t\tl2_len = m->l2_len;\n+\t}\n \n \t/* Retrieve DPTR */\n \tdptr = *(uint64_t *)(sg + 1);\n@@ -395,8 +423,8 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr,\n \tsa_base &= ~0xFFFFUL;\n \tsa = (uintptr_t)roc_nix_inl_ot_ipsec_outb_sa(sa_base, sess_priv.sa_idx);\n \tucode_cmd[3] = (ROC_CPT_DFLT_ENG_GRP_SE_IE << 61 | 1UL << 60 | sa);\n-\tucode_cmd[0] =\n-\t\t(ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 | pkt_len);\n+\tucode_cmd[0] = (ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 |\n+\t\t\t((uint64_t)sess_priv.chksum) << 32 | pkt_len);\n \n \t/* CPT Word 0 and Word 1. Assume no multi-seg support */\n \tcmd01 = vdupq_n_u64((nixtx + 16) | (cn10k_nix_tx_ext_subs(flags) + 1));\n", "prefixes": [ "13/24" ] }