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GET /api/patches/109825/?format=api
{ "id": 109825, "url": "http://patchwork.dpdk.org/api/patches/109825/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220419055921.10566-20-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220419055921.10566-20-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220419055921.10566-20-ndabilpuram@marvell.com", "date": "2022-04-19T05:59:17", "name": "[20/24] net/cnxk: update olflags with L3/L4 csum offload", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d0e0a35ad019ae79ff408fea1bd6d6339bf4c016", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220419055921.10566-20-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 22546, "url": "http://patchwork.dpdk.org/api/series/22546/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=22546", "date": "2022-04-19T05:58:58", "name": "[01/24] common/cnxk: add multi channel support for SDP send queues", "version": 1, "mbox": "http://patchwork.dpdk.org/series/22546/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/109825/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/109825/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3A474A00C3;\n\tTue, 19 Apr 2022 08:02:23 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0B6BE42835;\n\tTue, 19 Apr 2022 08:00:53 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 42C1742831\n for <dev@dpdk.org>; Tue, 19 Apr 2022 08:00:52 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 23IK05pV003352\n for <dev@dpdk.org>; Mon, 18 Apr 2022 23:00:51 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fhemwsryy-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 18 Apr 2022 23:00:51 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 18 Apr 2022 23:00:49 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 18 Apr 2022 23:00:49 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 982535B6923;\n Mon, 18 Apr 2022 23:00:47 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=8q0z1y/49aWWeBEB/kSTmFn9gleAJFCUF/jUDjO1gSc=;\n b=Ddsvj9lfTY/Yk+PHWYs4IMz0D1ZAc0Nj+7UwAaMSY8DShk39MSuSFCVQe8Grqp/IHFIT\n VfTc3iNavV+8fyUMGFfnlQRSYFiovbtkrMKx3NFyjveN1yjoLyADAMZY/xsQ6n2GP32T\n dJ0ySoEL2QPELPROx0Sz8YqdnPsGTHUYF7+mR3C8x/RaUW3JupiFwu2elVMTMJyFFShH\n jvUpaxq33hvEf+N82uX35ITfYuWRnrBHlAEcdlorCn9iry1qMvRvWi1kh0acUlINc5B4\n brsXLRxBK56jLc6qzQ9JWfazSoIj7q8eylYdBJTXBN5Fm5p5ny5kfdVbALA+4wVhWNRO 9A==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Akhil Goyal <gakhil@marvell.com>", "Subject": "[PATCH 20/24] net/cnxk: update olflags with L3/L4 csum offload", "Date": "Tue, 19 Apr 2022 11:29:17 +0530", "Message-ID": "<20220419055921.10566-20-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220419055921.10566-1-ndabilpuram@marvell.com>", "References": "<20220419055921.10566-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "1PBukLjykM5_QvYxDtpuMp5p1CHn6Pw5", "X-Proofpoint-GUID": "1PBukLjykM5_QvYxDtpuMp5p1CHn6Pw5", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514\n definitions=2022-04-19_02,2022-04-15_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Akhil Goyal <gakhil@marvell.com>\n\nWhen the packet is processed with inline IPsec offload,\nthe ol_flags were updated only with RTE_MBUF_F_RX_SEC_OFFLOAD.\nBut the hardware can also update the L3/L4 csum offload flags.\nHence, ol_flags are updated with RTE_MBUF_F_RX_IP_CKSUM_GOOD,\nRTE_MBUF_F_RX_L4_CKSUM_GOOD, etc based on the microcode completion\ncodes.\n\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/net/cnxk/cn10k_rx.h | 51 ++++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 50 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h\nindex db054c5..ae7d48f 100644\n--- a/drivers/net/cnxk/cn10k_rx.h\n+++ b/drivers/net/cnxk/cn10k_rx.h\n@@ -42,6 +42,18 @@\n \t\t (uint64_t *)(((uintptr_t)((uint64_t *)(b))[i]) - (o)) : \\\n \t\t (uint64_t *)(((uintptr_t)(b)) + CQE_SZ(i) - (o)))\n \n+#define NIX_RX_SEC_UCC_CONST \\\n+\t((RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1) << 8 | \\\n+\t ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \\\n+\t\t << 24 | \\\n+\t ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1) \\\n+\t\t << 32 | \\\n+\t ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \\\n+\t\t << 40 | \\\n+\t ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \\\n+\t\t << 48 | \\\n+\t (RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1) << 56)\n+\n #ifdef RTE_LIBRTE_MEMPOOL_DEBUG\n static inline void\n nix_mbuf_validate_next(struct rte_mbuf *m)\n@@ -467,6 +479,11 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, const uint64_t sa_base,\n \t\t\t\t\t RTE_MBUF_F_RX_SEC_OFFLOAD :\n \t\t\t\t\t (RTE_MBUF_F_RX_SEC_OFFLOAD |\n \t\t\t\t\t RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED));\n+\n+\t\t\tucc = hdr->w3.uc_ccode;\n+\t\t\tinner->ol_flags |= ((ucc & 0xF0) == 0xF0) ?\n+\t\t\t\t((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3))\n+\t\t\t\t & 0xFF) << 1 : 0;\n \t\t} else if (!(hdr->w0.err_sum) && !(hdr->w0.reas_sts)) {\n \t\t\t/* Reassembly success */\n \t\t\tinner = nix_sec_reassemble_frags(hdr, cq_w1, cq_w5,\n@@ -529,6 +546,11 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, const uint64_t sa_base,\n \t\t\t\t (RTE_MBUF_F_RX_SEC_OFFLOAD |\n \t\t\t\t RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED));\n \n+\t\tucc = hdr->w3.uc_ccode;\n+\t\tinner->ol_flags |= ((ucc & 0xF0) == 0xF0) ?\n+\t\t\t((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3))\n+\t\t\t & 0xFF) << 1 : 0;\n+\n \t\t/* Store meta in lmtline to free\n \t\t * Assume all meta's from same aura.\n \t\t */\n@@ -1313,7 +1335,26 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\tsa23 = vaddq_u64(sa23, vdupq_n_u64(sa_base));\n \n \t\t\tconst uint8x16_t tbl = {\n-\t\t\t\t0, 0, 0, 0, 0, 0, 0, 0,\n+\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST */\n+\t\t\t\t0,\n+\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM */\n+\t\t\t\tRTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,\n+\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_AGAIN */\n+\t\t\t\t0,\n+\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM */\n+\t\t\t\t(RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n+\t\t\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,\n+\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM */\n+\t\t\t\t(RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n+\t\t\t\t RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,\n+\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM */\n+\t\t\t\t(RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n+\t\t\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,\n+\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_UDP_ZEROCSUM */\n+\t\t\t\t(RTE_MBUF_F_RX_IP_CKSUM_GOOD |\n+\t\t\t\t RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,\n+\t\t\t\t/* ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM */\n+\t\t\t\tRTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1,\n \t\t\t\t/* HW_CCODE -> RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED */\n \t\t\t\t1, 0, 1, 1, 1, 1, 0, 1,\n \t\t\t};\n@@ -1418,6 +1459,8 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t\tnix_sec_meta_to_mbuf(cq0_w1, cq0_w5, sa, cpth0,\n \t\t\t\t\t\t mbuf0, &f0, &ol_flags0,\n \t\t\t\t\t\t flags, &rearm0);\n+\t\t\t\tol_flags0 |= ((uint64_t)vget_lane_u8(ucc, 0))\n+\t\t\t\t\t << 1;\n \t\t\t\tol_flags0 |= (RTE_MBUF_F_RX_SEC_OFFLOAD |\n \t\t\t\t\t(uint64_t)vget_lane_u8(ucc, 1) << 19);\n \t\t\t}\n@@ -1440,6 +1483,8 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t\tnix_sec_meta_to_mbuf(cq1_w1, cq1_w5, sa, cpth1,\n \t\t\t\t\t\t mbuf1, &f1, &ol_flags1,\n \t\t\t\t\t\t flags, &rearm1);\n+\t\t\t\tol_flags1 |= ((uint64_t)vget_lane_u8(ucc, 2))\n+\t\t\t\t\t << 1;\n \t\t\t\tol_flags1 |= (RTE_MBUF_F_RX_SEC_OFFLOAD |\n \t\t\t\t\t(uint64_t)vget_lane_u8(ucc, 3) << 19);\n \t\t\t}\n@@ -1462,6 +1507,8 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t\tnix_sec_meta_to_mbuf(cq2_w1, cq2_w5, sa, cpth2,\n \t\t\t\t\t\t mbuf2, &f2, &ol_flags2,\n \t\t\t\t\t\t flags, &rearm2);\n+\t\t\t\tol_flags2 |= ((uint64_t)vget_lane_u8(ucc, 4))\n+\t\t\t\t\t << 1;\n \t\t\t\tol_flags2 |= (RTE_MBUF_F_RX_SEC_OFFLOAD |\n \t\t\t\t\t(uint64_t)vget_lane_u8(ucc, 5) << 19);\n \t\t\t}\n@@ -1484,6 +1531,8 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,\n \t\t\t\tnix_sec_meta_to_mbuf(cq3_w1, cq3_w5, sa, cpth3,\n \t\t\t\t\t\t mbuf3, &f3, &ol_flags3,\n \t\t\t\t\t\t flags, &rearm3);\n+\t\t\t\tol_flags3 |= ((uint64_t)vget_lane_u8(ucc, 6))\n+\t\t\t\t\t << 1;\n \t\t\t\tol_flags3 |= (RTE_MBUF_F_RX_SEC_OFFLOAD |\n \t\t\t\t\t(uint64_t)vget_lane_u8(ucc, 7) << 19);\n \t\t\t}\n", "prefixes": [ "20/24" ] }