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GET /api/patches/110743/?format=api
{ "id": 110743, "url": "http://patchwork.dpdk.org/api/patches/110743/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220505173003.3242618-4-kda@semihalf.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220505173003.3242618-4-kda@semihalf.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220505173003.3242618-4-kda@semihalf.com", "date": "2022-05-05T17:29:55", "name": "[03/11] eal: add initial support for RISC-V architecture", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "874fe5c14964b8d309d3d3cb508d4c5c4f542a28", "submitter": { "id": 2179, "url": "http://patchwork.dpdk.org/api/people/2179/?format=api", "name": "Stanislaw Kardach", "email": "kda@semihalf.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220505173003.3242618-4-kda@semihalf.com/mbox/", "series": [ { "id": 22800, "url": "http://patchwork.dpdk.org/api/series/22800/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=22800", "date": "2022-05-05T17:29:52", "name": "Introduce support for RISC-V architecture", "version": 1, "mbox": "http://patchwork.dpdk.org/series/22800/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/110743/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/110743/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 32434A00C2;\n\tThu, 5 May 2022 19:30:54 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EA6AE42838;\n\tThu, 5 May 2022 19:30:32 +0200 (CEST)", "from mail-lj1-f182.google.com (mail-lj1-f182.google.com\n [209.85.208.182])\n by mails.dpdk.org (Postfix) with ESMTP id 1759942833\n for <dev@dpdk.org>; Thu, 5 May 2022 19:30:30 +0200 (CEST)", "by mail-lj1-f182.google.com with SMTP id g16so6493529lja.3\n for <dev@dpdk.org>; Thu, 05 May 2022 10:30:30 -0700 (PDT)", "from localhost.localdomain (89-73-146-138.dynamic.chello.pl.\n [89.73.146.138]) by smtp.gmail.com with ESMTPSA id\n z26-20020ac25dfa000000b0047255d21203sm289640lfq.306.2022.05.05.10.30.27\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 05 May 2022 10:30:28 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=semihalf-com.20210112.gappssmtp.com; s=20210112;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=/L84mA7V9g6tqXWgHeafxP0DfAq0Q8F7lHA6wwPy1+U=;\n b=8W+GAkVzQMAXDUWVYjLbcRByZ9D6tLAjZuxctGVogCJ7fm024o7AgHvHQJIyLF++my\n jutAPXYbgrSxhCeD4znQCXSi9f0UjI9YGadFN1/jociTUZkYJlcefXj3TueunH8Or8vl\n JhNhxAkJ2xi6OqbFhBeNU7t5G9oVb5GsTVdMVOI/Zd27FlkwuQZwweWaYBxxhK12maOq\n aAWj9fe0fIkaG8IUc84AiHDXKJiqJNEcFrWioJQJ3BUJz0V//ZFZlSAo6YT0ZDCndqVn\n Wzzv2CcMCtKj8NWU+qH/AUQynXlOwcIX5Au+NJc47vOqH0h5Jb7DPARso9R/ueZn5m6f\n mNaA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20210112;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=/L84mA7V9g6tqXWgHeafxP0DfAq0Q8F7lHA6wwPy1+U=;\n b=jL3bLyPXYsRNbNF1Ee5d49ESmTcQK0IcnMlHDLnzoE0lfQZGMe/MCrGA6cMnIY284D\n 5UmMhLV1IVVNJHrOkiPuL4rhMl5GszO9EM3CFEDZcG9K7yPUz7DCeMKLqzKhn8Ktz/qd\n 0ic0V/LCVJCrf85dGzVtlHbM/XWecs/TqJLF5uAIRaRoXdeA2Lw+arK74lhNbUEk4sEj\n JAUCTemS2iFGdw6GuD0ofRmP9/yBPOLTWockOWQh1aQWDNhfgtbwtTo8aQg9EYgQb+cw\n ceQOZ4qbfiXuwDs2X3SMG7Egr5puelzKGUT5bFS+EJWGAXT+LBk67IOp0LiZIbZlSsbd\n 5oZw==", "X-Gm-Message-State": "AOAM532TuUjiiXF3w+wkJN6N/9eH5Cg/Xg2OhELes5taNBHJKCqz5+Iu\n YYADYxBe+0sYf15uLhESyRVXRQ==", "X-Google-Smtp-Source": "\n ABdhPJyFQzBSXMtLVF6ZpSP4kw3JpiGi3mYzMFGUEWfbBGvol93xYm9zwUWkALz9UK3EJOLULeLf/w==", "X-Received": "by 2002:a05:651c:483:b0:24f:2ae0:61f3 with SMTP id\n s3-20020a05651c048300b0024f2ae061f3mr17444896ljc.229.1651771828851;\n Thu, 05 May 2022 10:30:28 -0700 (PDT)", "From": "Stanislaw Kardach <kda@semihalf.com>", "To": "Thomas Monjalon <thomas@monjalon.net>", "Cc": "Michal Mazurek <maz@semihalf.com>, dev@dpdk.org,\n Frank Zhao <Frank.Zhao@starfivetech.com>, Sam Grove <sam.grove@sifive.com>,\n mw@semihalf.com, upstream@semihalf.com,\n Stanislaw Kardach <kda@semihalf.com>", "Subject": "[PATCH 03/11] eal: add initial support for RISC-V architecture", "Date": "Thu, 5 May 2022 19:29:55 +0200", "Message-Id": "<20220505173003.3242618-4-kda@semihalf.com>", "X-Mailer": "git-send-email 2.30.2", "In-Reply-To": "<20220505173003.3242618-1-kda@semihalf.com>", "References": "<20220505173003.3242618-1-kda@semihalf.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Michal Mazurek <maz@semihalf.com>\n\nAdd all necessary elements for DPDK to compile and run EAL on SiFive\nFreedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)\ncore complex.\n\nThis includes:\n\n- EAL library implementation for rv64imafdc ISA.\n- meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define\n is added for architecture identification.\n- xmm_t structure operation stubs as there is no vector support in the\n U74 core.\n\nCompilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.\n\nTwo rte_rdtsc() schemes are provided: stable low-resolution using rdtime\n(default) and unstable high-resolution using rdcycle. User can override\nthe scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of\nboth DPDK and the application. The reasoning for this is as follows.\nThe RISC-V ISA mandates that clock read by rdtime has to be of constant\nperiod and synchronized between all hardware threads within 1 tick\n(chapter 10.1 in version 20191213 of RISC-V spec).\nHowever this clock may not be of high-enough frequency for dataplane\nuses. I.e. on HiFive Unmatched (FU740) it is 1MHz.\nThere is a high-resolution alternative in form of rdcycle which is\nclocked at the core clock frequency. The drawbacks are that it may be\ndisabled during sleep (WFI) and its frequency might change due to DVFS.\n\nThe platform is currently marked as linux-only because rte_cycles\nimplementation uses the timebase-frequency device-tree node read through\nthe proc file system. Such approach was chosen because Linux kernel\ndepends on the presence of this device-tree node.\n\nThe compilation of following modules has been disabled by this commit\nand will be re-enabled in later commits as fixes are introduced:\nnet/ixgbe, net/memif, net/tap, example/l3fwd.\n\nKnown checkpatch errors/warnings:\n\n- ERROR:COMPLEX_MACRO in rte_atomic.h and rte_cycles.h due to inline\n assembly declarations.\n- vector_size compiler attribute used in rte_vect.h directly.\n- rte_*mb() used directly in rte_atomic.h to reduce code duplication.\n- __atomic_thread_fence() used to implement rte_atomic_thread_fence().\n\nSigned-off-by: Michal Mazurek <maz@semihalf.com>\nSigned-off-by: Stanislaw Kardach <kda@semihalf.com>\nSponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>\nSponsored-by: Sam Grove <sam.grove@sifive.com>\n---\n MAINTAINERS | 6 +\n app/test/test_xmmt_ops.h | 16 ++\n config/meson.build | 2 +\n config/riscv/meson.build | 143 ++++++++++++++++++\n config/riscv/riscv64_linux_gcc | 17 +++\n config/riscv/riscv64_sifive_u740_linux_gcc | 19 +++\n doc/guides/contributing/design.rst | 2 +-\n .../linux_gsg/cross_build_dpdk_for_riscv.rst | 125 +++++++++++++++\n doc/guides/linux_gsg/index.rst | 1 +\n doc/guides/nics/features.rst | 5 +\n doc/guides/nics/features/default.ini | 1 +\n doc/guides/rel_notes/release_22_07.rst | 23 +++\n drivers/net/i40e/meson.build | 6 +\n drivers/net/ixgbe/meson.build | 6 +\n drivers/net/memif/meson.build | 5 +\n drivers/net/tap/meson.build | 5 +\n examples/l3fwd/meson.build | 6 +\n lib/eal/riscv/include/meson.build | 23 +++\n lib/eal/riscv/include/rte_atomic.h | 52 +++++++\n lib/eal/riscv/include/rte_byteorder.h | 44 ++++++\n lib/eal/riscv/include/rte_cpuflags.h | 55 +++++++\n lib/eal/riscv/include/rte_cycles.h | 103 +++++++++++++\n lib/eal/riscv/include/rte_io.h | 21 +++\n lib/eal/riscv/include/rte_mcslock.h | 18 +++\n lib/eal/riscv/include/rte_memcpy.h | 63 ++++++++\n lib/eal/riscv/include/rte_pause.h | 31 ++++\n lib/eal/riscv/include/rte_pflock.h | 17 +++\n lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++\n lib/eal/riscv/include/rte_prefetch.h | 50 ++++++\n lib/eal/riscv/include/rte_rwlock.h | 44 ++++++\n lib/eal/riscv/include/rte_spinlock.h | 67 ++++++++\n lib/eal/riscv/include/rte_ticketlock.h | 21 +++\n lib/eal/riscv/include/rte_vect.h | 55 +++++++\n lib/eal/riscv/meson.build | 11 ++\n lib/eal/riscv/rte_cpuflags.c | 122 +++++++++++++++\n lib/eal/riscv/rte_cycles.c | 77 ++++++++++\n lib/eal/riscv/rte_hypervisor.c | 13 ++\n lib/eal/riscv/rte_power_intrinsics.c | 56 +++++++\n meson.build | 2 +\n 39 files changed, 1354 insertions(+), 1 deletion(-)\n create mode 100644 config/riscv/meson.build\n create mode 100644 config/riscv/riscv64_linux_gcc\n create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc\n create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst\n create mode 100644 lib/eal/riscv/include/meson.build\n create mode 100644 lib/eal/riscv/include/rte_atomic.h\n create mode 100644 lib/eal/riscv/include/rte_byteorder.h\n create mode 100644 lib/eal/riscv/include/rte_cpuflags.h\n create mode 100644 lib/eal/riscv/include/rte_cycles.h\n create mode 100644 lib/eal/riscv/include/rte_io.h\n create mode 100644 lib/eal/riscv/include/rte_mcslock.h\n create mode 100644 lib/eal/riscv/include/rte_memcpy.h\n create mode 100644 lib/eal/riscv/include/rte_pause.h\n create mode 100644 lib/eal/riscv/include/rte_pflock.h\n create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h\n create mode 100644 lib/eal/riscv/include/rte_prefetch.h\n create mode 100644 lib/eal/riscv/include/rte_rwlock.h\n create mode 100644 lib/eal/riscv/include/rte_spinlock.h\n create mode 100644 lib/eal/riscv/include/rte_ticketlock.h\n create mode 100644 lib/eal/riscv/include/rte_vect.h\n create mode 100644 lib/eal/riscv/meson.build\n create mode 100644 lib/eal/riscv/rte_cpuflags.c\n create mode 100644 lib/eal/riscv/rte_cycles.c\n create mode 100644 lib/eal/riscv/rte_hypervisor.c\n create mode 100644 lib/eal/riscv/rte_power_intrinsics.c", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 7c4f541dba..2c732a1912 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -296,6 +296,12 @@ F: drivers/*/*/*_altivec.*\n F: app/*/*_altivec.*\n F: examples/*/*_altivec.*\n \n+RISC-V\n+M: Stanislaw Kardach <kda@semihalf.com>\n+F: config/riscv/\n+F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst\n+F: lib/eal/riscv/\n+\n Intel x86\n M: Bruce Richardson <bruce.richardson@intel.com>\n M: Konstantin Ananyev <konstantin.ananyev@intel.com>\ndiff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h\nindex 3a82d5ecac..55f256599e 100644\n--- a/app/test/test_xmmt_ops.h\n+++ b/app/test/test_xmmt_ops.h\n@@ -1,5 +1,8 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n * Copyright(c) 2015 Cavium, Inc\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n */\n \n #ifndef _TEST_XMMT_OPS_H_\n@@ -49,6 +52,19 @@ vect_set_epi32(int i3, int i2, int i1, int i0)\n \treturn data;\n }\n \n+#elif defined(RTE_ARCH_RISCV)\n+\n+#define vect_loadu_sil128(p) vect_load_128(p)\n+\n+/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */\n+static __rte_always_inline xmm_t\n+vect_set_epi32(int i3, int i2, int i1, int i0)\n+{\n+\txmm_t data = (xmm_t){i0, i1, i2, i3};\n+\n+\treturn data;\n+}\n+\n #endif\n \n #endif /* _TEST_XMMT_OPS_H_ */\ndiff --git a/config/meson.build b/config/meson.build\nindex 7134e80e8d..7f7b6c92fd 100644\n--- a/config/meson.build\n+++ b/config/meson.build\n@@ -121,6 +121,8 @@ if cpu_instruction_set == 'generic'\n cpu_instruction_set = 'generic'\n elif host_machine.cpu_family().startswith('ppc')\n cpu_instruction_set = 'power8'\n+ elif host_machine.cpu_family().startswith('riscv')\n+ cpu_instruction_set = 'riscv'\n endif\n endif\n \ndiff --git a/config/riscv/meson.build b/config/riscv/meson.build\nnew file mode 100644\nindex 0000000000..0c16c31fc2\n--- /dev/null\n+++ b/config/riscv/meson.build\n@@ -0,0 +1,143 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2017 Intel Corporation.\n+# Copyright(c) 2017 Cavium, Inc\n+# Copyright(c) 2021 PANTHEON.tech s.r.o.\n+# Copyright(c) 2022 StarFive\n+# Copyright(c) 2022 SiFive\n+# Copyright(c) 2022 Semihalf\n+\n+if not is_linux\n+ error('Only Linux is supported at this point in time.')\n+endif\n+\n+if not dpdk_conf.get('RTE_ARCH_64')\n+ error('Only 64-bit compiles are supported for this platform type')\n+endif\n+\n+dpdk_conf.set('RTE_ARCH', 'riscv')\n+dpdk_conf.set('RTE_ARCH_RISCV', 1)\n+dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)\n+\n+# common flags to all riscv builds, with lowest priority\n+flags_common = [\n+ ['RTE_ARCH_RISCV', true],\n+ ['RTE_CACHE_LINE_SIZE', 64],\n+ # Set this to true if target emulates U-mode TIME CSR via M or S mode trap.\n+ # This allows to remove a FENCE on rte_rdtsc_precise() as trap effectively\n+ # acts as one.\n+ ['RTE_RISCV_EMU_UTIME', false],\n+ # Set this to true if target emulates U-mode CYCLE CSR via M or S mode trap.\n+ # This allows to remove a FENCE on rte_rdtsc_precise() as trap effectively\n+ # acts as one.\n+ ['RTE_RISCV_EMU_UCYCLE', false],\n+ # Manually set wall time clock frequency for the target. If 0, then it is\n+ # read from /proc/device-tree/cpus/timebase-frequency. This property is\n+ # guaranteed on Linux, as riscv time_init() requires it.\n+ ['RTE_RISCV_TIME_FREQ', 0],\n+]\n+\n+## SoC-specific options.\n+# The priority is like this: arch > vendor > common.\n+#\n+# Note that currently there's no way of getting vendor/microarchitecture id\n+# values in userspace which is why the logic of choosing the right flag\n+# combination is strictly based on the values passed from a cross-file.\n+vendor_generic = {\n+ 'description': 'Generic RISC-V',\n+ 'flags': [\n+ ['RTE_MACHINE', '\"riscv\"'],\n+ ['RTE_USE_C11_MEM_MODEL', true],\n+ ['RTE_MAX_LCORE', 128],\n+ ['RTE_MAX_NUMA_NODES', 2]\n+ ],\n+ 'arch_config': {\n+ 'generic': {'machine_args': ['-march=rv64gc']}\n+ }\n+}\n+\n+arch_config_riscv = {\n+ '0x8000000000000007': {\n+ 'machine_args': ['-march=rv64gc', '-mtune=sifive-7-series'],\n+ 'flags': [\n+ ['RTE_RISCV_EMU_UTIME', true],\n+ ['RTE_RISCV_EMU_UCYCLE', true]\n+ ]\n+ },\n+}\n+\n+vendor_sifive = {\n+ 'description': 'SiFive',\n+ 'flags': [\n+ ['RTE_MACHINE', '\"riscv\"'],\n+ ['RTE_USE_C11_MEM_MODEL', true],\n+ ['RTE_MAX_LCORE', 4],\n+ ['RTE_MAX_NUMA_NODES', 1],\n+ ],\n+ 'arch_config': arch_config_riscv\n+}\n+\n+vendors = {\n+ 'generic': vendor_generic,\n+ '0x489': vendor_sifive\n+}\n+\n+# Native/cross vendor/arch detection\n+if not meson.is_cross_build()\n+ if machine == 'default'\n+ # default build\n+ vendor_id = 'generic'\n+ arch_id = 'generic'\n+ message('generic RISC-V')\n+ else\n+ vendor_id = 'generic'\n+ arch_id = 'generic'\n+ warning('RISC-V arch discovery not available, using generic!')\n+ endif\n+else\n+ # cross build\n+ vendor_id = meson.get_cross_property('vendor_id')\n+ arch_id = meson.get_cross_property('arch_id')\n+endif\n+\n+if vendors.has_key(vendor_id)\n+ vendor_config = vendors[vendor_id]\n+else\n+ error('Unsupported RISC-V vendor: @0@. '.format(vendor_id) +\n+ 'Please add support for it or use the generic ' +\n+ '(-Dmachine=generic) build.')\n+endif\n+\n+message('RISC-V vendor: ' + vendor_config['description'])\n+message('RISC-V architecture id: ' + arch_id)\n+\n+arch_config = vendor_config['arch_config']\n+if arch_config.has_key(arch_id)\n+ # use the specified arch_id machine args if found\n+ arch_config = arch_config[arch_id]\n+else\n+ # unknown micro-architecture id\n+ error('Unsupported architecture @0@ of vendor @1@. '\n+ .format(arch_id, vendor_id) +\n+ 'Please add support for it or use the generic ' +\n+ '(-Dmachine=generic) build.')\n+endif\n+\n+# Concatenate flags respecting priorities.\n+dpdk_flags = flags_common + vendor_config['flags'] + arch_config.get('flags', [])\n+\n+# apply supported machine args\n+machine_args = [] # Clear previous machine args\n+foreach flag: arch_config['machine_args']\n+ if cc.has_argument(flag)\n+ machine_args += flag\n+ endif\n+endforeach\n+\n+# apply flags\n+foreach flag: dpdk_flags\n+ if flag.length() > 0\n+ dpdk_conf.set(flag[0], flag[1])\n+ endif\n+endforeach\n+message('Using machine args: @0@'.format(machine_args))\n+\ndiff --git a/config/riscv/riscv64_linux_gcc b/config/riscv/riscv64_linux_gcc\nnew file mode 100644\nindex 0000000000..04248d7ecb\n--- /dev/null\n+++ b/config/riscv/riscv64_linux_gcc\n@@ -0,0 +1,17 @@\n+[binaries]\n+c = 'riscv64-linux-gnu-gcc'\n+cpp = 'riscv64-linux-gnu-g++'\n+ar = 'riscv64-linux-gnu-ar'\n+strip = 'riscv64-linux-gnu-strip'\n+pcap-config = ''\n+pkgconfig = 'riscv64-linux-gnu-pkg-config'\n+\n+[host_machine]\n+system = 'linux'\n+cpu_family = 'riscv64'\n+cpu = 'rv64gc'\n+endian = 'little'\n+\n+[properties]\n+vendor_id = 'generic'\n+arch_id = 'generic'\ndiff --git a/config/riscv/riscv64_sifive_u740_linux_gcc b/config/riscv/riscv64_sifive_u740_linux_gcc\nnew file mode 100644\nindex 0000000000..7b5ad2562d\n--- /dev/null\n+++ b/config/riscv/riscv64_sifive_u740_linux_gcc\n@@ -0,0 +1,19 @@\n+[binaries]\n+c = 'riscv64-unknown-linux-gnu-gcc'\n+cpp = 'riscv64-unknown-linux-gnu-g++'\n+ar = 'riscv64-unknown-linux-gnu-ar'\n+strip = 'riscv64-unknown-linux-gnu-strip'\n+pcap-config = ''\n+pkgconfig = 'riscv64-unknown-linux-gnu-pkg-config'\n+\n+[host_machine]\n+system = 'linux'\n+cpu_family = 'riscv64'\n+cpu = 'rv64gc'\n+endian = 'little'\n+\n+[properties]\n+vendor_id = '0x489'\n+arch_id = '0x8000000000000007'\n+max_lcores = 4\n+max_numa_nodes = 1\ndiff --git a/doc/guides/contributing/design.rst b/doc/guides/contributing/design.rst\nindex d5ca8b4d9c..0383afe5c8 100644\n--- a/doc/guides/contributing/design.rst\n+++ b/doc/guides/contributing/design.rst\n@@ -42,7 +42,7 @@ Per Architecture Sources\n The following macro options can be used:\n \n * ``RTE_ARCH`` is a string that contains the name of the architecture.\n-* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.\n+* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.\n \n Per Execution Environment Sources\n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\ndiff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst\nnew file mode 100644\nindex 0000000000..9907b35a1d\n--- /dev/null\n+++ b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst\n@@ -0,0 +1,125 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2020 ARM Corporation.\n+ Copyright(c) 2022 StarFive\n+ Copyright(c) 2022 SiFive\n+ Copyright(c) 2022 Semihalf\n+\n+Cross compiling DPDK for RISC-V\n+===============================\n+\n+This chapter describes how to cross compile DPDK for RISC-V from x86 build\n+hosts.\n+\n+.. note::\n+\n+ While it's possible to compile DPDK natively on a RISC-V host, it is\n+ currently recommended to cross-compile as Linux kernel does not offer any\n+ way for userspace to discover the vendor and architecture identifiers of the\n+ CPU and therefore any per-chip optimization options have to be chosen via\n+ a cross-file or ``c_args``.\n+\n+\n+Prerequisites\n+-------------\n+\n+\n+Linux kernel\n+~~~~~~~~~~~~\n+\n+It is recommended to use Linux kernel built from\n+`SiFive Freedom Unleashed SDK <https://github.com/sifive/freedom-u-sdk>`_.\n+\n+\n+Meson prerequisites\n+~~~~~~~~~~~~~~~~~~~\n+\n+Meson depends on pkgconfig to find the dependencies.\n+The package ``pkg-config-riscv64-linux-gnu`` is required for RISC-V.\n+To install it in Ubuntu::\n+\n+ sudo apt install pkg-config-riscv64-linux-gnu\n+\n+\n+GNU toolchain\n+-------------\n+\n+\n+Obtain the cross toolchain\n+~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+The build process was tested using:\n+\n+* Ubuntu toolchain (the ``crossbuild-essential-riscv64`` package).\n+\n+* Latest `RISC-V GNU toolchain\n+ <https://github.com/riscv/riscv-gnu-toolchain/releases>`_ on Ubuntu or Arch\n+ Linux.\n+\n+Alternatively the toolchain may be built straight from the source, to do that\n+follow the instructions on the riscv-gnu-toolchain github page.\n+\n+\n+Unzip and add into the PATH\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+This step is only required for the riscv-gnu-toolchain. The Ubuntu toolchain is\n+in the PATH already.\n+\n+.. code-block:: console\n+\n+ tar -xvf riscv64-glibc-ubuntu-20.04-<version>.tar.gz\n+ export PATH=$PATH:<cross_install_dir>/riscv/bin\n+\n+\n+Cross Compiling DPDK with GNU toolchain using Meson\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+To cross-compile DPDK for a desired target machine use the following command::\n+\n+ meson cross-build --cross-file <target_machine_configuration>\n+ ninja -C cross-build\n+\n+For example if the target machine is a generic rv64gc RISC-V, use the following\n+command::\n+\n+ meson riscv64-build-gcc --cross-file config/riscv/riscv64_linux_gcc\n+ ninja -C riscv64-build-gcc\n+\n+If riscv-gnu-toolchain is used, binary names should be updated to match. Update the following lines in the cross-file:\n+\n+.. code-block:: console\n+\n+ [binaries]\n+ c = 'riscv64-unknown-linux-gnu-gcc'\n+ cpp = 'riscv64-unknown-linux-gnu-g++'\n+ ar = 'riscv64-unknown-linux-gnu-ar'\n+ strip = 'riscv64-unknown-linux-gnu-strip'\n+ ...\n+\n+Some toolchains (such as freedom-u-sdk one) require also setting ``--sysroot``,\n+otherwise include paths might not be resolved. To do so, add the appropriate\n+paths to the cross-file:\n+\n+.. code-block:: console\n+\n+ [properties]\n+ ...\n+ c_args = ['--sysroot', '<path/to/toolchain/sysroot>']\n+ cpp_args = c_args\n+ c_link_args = ['--sysroot', '<path/to/toolchain/sysroot>']\n+ cpp_link_args = c_link_args\n+ ...\n+\n+\n+Supported cross-compilation targets\n+-----------------------------------\n+\n+Currently the following targets are supported:\n+\n+* Generic rv64gc ISA: ``config/riscv/riscv64_linux_gcc``\n+\n+* SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc``\n+\n+To add a new target support, ``config/riscv/meson.build`` has to be modified by\n+adding a new vendor/architecture id and a corresponding cross-file has to be\n+added to ``config/riscv`` directory.\ndiff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst\nindex 16a9a67260..747552c385 100644\n--- a/doc/guides/linux_gsg/index.rst\n+++ b/doc/guides/linux_gsg/index.rst\n@@ -14,6 +14,7 @@ Getting Started Guide for Linux\n sys_reqs\n build_dpdk\n cross_build_dpdk_for_arm64\n+ cross_build_dpdk_for_riscv\n linux_drivers\n build_sample_apps\n linux_eal_parameters\ndiff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst\nindex 21bedb743f..6c4fa74bc7 100644\n--- a/doc/guides/nics/features.rst\n+++ b/doc/guides/nics/features.rst\n@@ -855,6 +855,11 @@ x86-64\n \n Support 64bits x86 architecture.\n \n+rv64\n+----\n+\n+Support 64-bit RISC-V architecture.\n+\n \n .. _nic_features_usage_doc:\n \ndiff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini\nindex b1d18ac62c..02198682c6 100644\n--- a/doc/guides/nics/features/default.ini\n+++ b/doc/guides/nics/features/default.ini\n@@ -74,6 +74,7 @@ ARMv8 =\n Power8 =\n x86-32 =\n x86-64 =\n+rv64 =\n Usage doc =\n Design doc =\n Perf doc =\ndiff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst\nindex 067118174b..453591e568 100644\n--- a/doc/guides/rel_notes/release_22_07.rst\n+++ b/doc/guides/rel_notes/release_22_07.rst\n@@ -55,6 +55,29 @@ New Features\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* **Added initial RISC-V architecture support.***\n+\n+ Added EAL implementation for RISC-V architecture. The initial device the\n+ porting was tested on is a HiFive Unmatched development board based on the\n+ SiFive Freedom U740 SoC. In theory this implementation should work with any\n+ ``rv64gc`` ISA compatible implementation with MMU supporting a reasonable\n+ address space size (U740 uses sv39 MMU).\n+\n+ * Verified with meson tests. ``fast-tests`` suite passing with default config.\n+ * Verified PMD operation with Intel x520-DA2 NIC (``ixgbe``) and ``test-pmd``\n+ application. Packet transfer checked using all UIO drivers available for\n+ non-IOMMU platforms: ``uio_pci_generic``, ``vfio-pci noiommu`` and\n+ ``igb_uio``.\n+ * The ``i40e`` PMD driver is disabled on RISC-V as ``rv64gc`` ISA has no\n+ vector operations.\n+ * RISCV support is currently limited to Linux.\n+ * Clang compilation currently not supported due to issues with relocation\n+ relaxation.\n+ * Debug build of ``app/test/dpdk-test`` fails currently on RISC-V due to\n+ seemingly invalid loop and goto jump code generation by GCC in\n+ ``test_ring.c`` where extensive inlining increases the code size beyond the\n+ capability of the generated instruction (JAL: +/-1MB PC-relative).\n+\n * **Updated Intel iavf driver.**\n \n * Added Tx QoS queue rate limitation support.\ndiff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build\nindex efc5f93e35..a4c1c9079a 100644\n--- a/drivers/net/i40e/meson.build\n+++ b/drivers/net/i40e/meson.build\n@@ -1,6 +1,12 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2017 Intel Corporation\n \n+if arch_subdir == 'riscv'\n+\t\tbuild = false\n+\t\treason = 'riscv arch not supported'\n+\t\tsubdir_done()\n+endif\n+\n cflags += ['-DPF_DRIVER',\n '-DVF_DRIVER',\n '-DINTEGRATED_VF',\ndiff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build\nindex 162f8d5f46..88539e97d5 100644\n--- a/drivers/net/ixgbe/meson.build\n+++ b/drivers/net/ixgbe/meson.build\n@@ -1,6 +1,12 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2017 Intel Corporation\n \n+if arch_subdir == 'riscv'\n+\t\tbuild = false\n+\t\treason = 'riscv arch not supported'\n+\t\tsubdir_done()\n+endif\n+\n cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']\n \n subdir('base')\ndiff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build\nindex 680bc8631c..9afb495953 100644\n--- a/drivers/net/memif/meson.build\n+++ b/drivers/net/memif/meson.build\n@@ -5,6 +5,11 @@ if not is_linux\n build = false\n reason = 'only supported on Linux'\n endif\n+if arch_subdir == 'riscv'\n+\t\tbuild = false\n+\t\treason = 'riscv arch not supported'\n+\t\tsubdir_done()\n+endif\n \n sources = files(\n 'memif_socket.c',\ndiff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build\nindex c09713a67b..3efac9ac07 100644\n--- a/drivers/net/tap/meson.build\n+++ b/drivers/net/tap/meson.build\n@@ -5,6 +5,11 @@ if not is_linux\n build = false\n reason = 'only supported on Linux'\n endif\n+if arch_subdir == 'riscv'\n+\t\tbuild = false\n+\t\treason = 'riscv arch not supported'\n+\t\tsubdir_done()\n+endif\n sources = files(\n 'rte_eth_tap.c',\n 'tap_bpf_api.c',\ndiff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build\nindex 0830b3eb31..75fa19b7fe 100644\n--- a/examples/l3fwd/meson.build\n+++ b/examples/l3fwd/meson.build\n@@ -6,6 +6,12 @@\n # To build this example as a standalone application with an already-installed\n # DPDK instance, use 'make'\n \n+if dpdk_conf.has('RTE_ARCH_RISCV')\n+\t\tbuild = false\n+\t\treason = 'riscv arch not supported'\n+\t\tsubdir_done()\n+endif\n+\n allow_experimental_apis = true\n deps += ['hash', 'lpm', 'fib', 'eventdev']\n sources = files(\ndiff --git a/lib/eal/riscv/include/meson.build b/lib/eal/riscv/include/meson.build\nnew file mode 100644\nindex 0000000000..d290ed82ed\n--- /dev/null\n+++ b/lib/eal/riscv/include/meson.build\n@@ -0,0 +1,23 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2022 StarFive\n+# Copyright(c) 2022 SiFive\n+# Copyright(c) 2022 Semihalf\n+\n+arch_headers = files(\n+\t'rte_atomic.h',\n+\t'rte_byteorder.h',\n+\t'rte_cpuflags.h',\n+\t'rte_cycles.h',\n+\t'rte_io.h',\n+\t'rte_mcslock.h',\n+\t'rte_memcpy.h',\n+\t'rte_pause.h',\n+\t'rte_pflock.h',\n+\t'rte_power_intrinsics.h',\n+\t'rte_prefetch.h',\n+\t'rte_rwlock.h',\n+\t'rte_spinlock.h',\n+\t'rte_ticketlock.h',\n+\t'rte_vect.h'\n+)\n+install_headers(arch_headers, subdir: get_option('include_subdir_arch'))\ndiff --git a/lib/eal/riscv/include/rte_atomic.h b/lib/eal/riscv/include/rte_atomic.h\nnew file mode 100644\nindex 0000000000..4b4633c914\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_atomic.h\n@@ -0,0 +1,52 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ * All rights reserved.\n+ */\n+\n+#ifndef RTE_ATOMIC_RISCV_H\n+#define RTE_ATOMIC_RISCV_H\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+# error Platform must be built with RTE_FORCE_INTRINSICS\n+#endif\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <stdint.h>\n+#include <rte_common.h>\n+#include <rte_config.h>\n+#include \"generic/rte_atomic.h\"\n+\n+#define rte_mb()\tasm volatile(\"fence rw, rw\" : : : \"memory\")\n+\n+#define rte_wmb()\tasm volatile(\"fence w, w\" : : : \"memory\")\n+\n+#define rte_rmb()\tasm volatile(\"fence r, r\" : : : \"memory\")\n+\n+#define rte_smp_mb()\trte_mb()\n+\n+#define rte_smp_wmb()\trte_wmb()\n+\n+#define rte_smp_rmb()\trte_rmb()\n+\n+#define rte_io_mb()\tasm volatile(\"fence iorw, iorw\" : : : \"memory\")\n+\n+#define rte_io_wmb()\tasm volatile(\"fence orw, ow\" : : : \"memory\")\n+\n+#define rte_io_rmb()\tasm volatile(\"fence ir, ir\" : : : \"memory\")\n+\n+static __rte_always_inline void\n+rte_atomic_thread_fence(int memorder)\n+{\n+\t__atomic_thread_fence(memorder);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_ATOMIC_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_byteorder.h b/lib/eal/riscv/include/rte_byteorder.h\nnew file mode 100644\nindex 0000000000..21893505d6\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_byteorder.h\n@@ -0,0 +1,44 @@\n+/*\n+ * SPDX-License-Identifier: BSD-3-Clause\n+ * Inspired from FreeBSD src/sys/powerpc/include/endian.h\n+ * Copyright(c) 1987, 1991, 1993\n+ * The Regents of the University of California. All rights reserved.\n+ */\n+\n+#ifndef RTE_BYTEORDER_RISCV_H\n+#define RTE_BYTEORDER_RISCV_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <stdint.h>\n+#include <rte_common.h>\n+#include \"generic/rte_byteorder.h\"\n+\n+#ifndef RTE_BYTE_ORDER\n+#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN\n+#endif\n+\n+#define rte_cpu_to_le_16(x) (x)\n+#define rte_cpu_to_le_32(x) (x)\n+#define rte_cpu_to_le_64(x) (x)\n+\n+#define rte_cpu_to_be_16(x) rte_bswap16(x)\n+#define rte_cpu_to_be_32(x) rte_bswap32(x)\n+#define rte_cpu_to_be_64(x) rte_bswap64(x)\n+\n+#define rte_le_to_cpu_16(x) (x)\n+#define rte_le_to_cpu_32(x) (x)\n+#define rte_le_to_cpu_64(x) (x)\n+\n+#define rte_be_to_cpu_16(x) rte_bswap16(x)\n+#define rte_be_to_cpu_32(x) rte_bswap32(x)\n+#define rte_be_to_cpu_64(x) rte_bswap64(x)\n+\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_BYTEORDER_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_cpuflags.h b/lib/eal/riscv/include/rte_cpuflags.h\nnew file mode 100644\nindex 0000000000..66e787f898\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_cpuflags.h\n@@ -0,0 +1,55 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2014 IBM Corporation\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#ifndef RTE_CPUFLAGS_RISCV_H\n+#define RTE_CPUFLAGS_RISCV_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/**\n+ * Enumeration of all CPU features supported\n+ */\n+enum rte_cpu_flag_t {\n+\tRTE_CPUFLAG_RISCV_ISA_A, /* Atomic */\n+\tRTE_CPUFLAG_RISCV_ISA_B, /* Bit-Manipulation */\n+\tRTE_CPUFLAG_RISCV_ISA_C, /* Compressed instruction */\n+\tRTE_CPUFLAG_RISCV_ISA_D, /* Double precision floating-point */\n+\tRTE_CPUFLAG_RISCV_ISA_E, /* RV32E ISA */\n+\tRTE_CPUFLAG_RISCV_ISA_F, /* Single precision floating-point */\n+\tRTE_CPUFLAG_RISCV_ISA_G, /* Extension pack (IMAFD, Zicsr, Zifencei) */\n+\tRTE_CPUFLAG_RISCV_ISA_H, /* Hypervisor */\n+\tRTE_CPUFLAG_RISCV_ISA_I, /* RV32I/RV64I/IRV128I base ISA */\n+\tRTE_CPUFLAG_RISCV_ISA_J, /* Dynamic Translation Language */\n+\tRTE_CPUFLAG_RISCV_ISA_K, /* Reserved */\n+\tRTE_CPUFLAG_RISCV_ISA_L, /* Decimal Floating-Point */\n+\tRTE_CPUFLAG_RISCV_ISA_M, /* Integer Multiply/Divide */\n+\tRTE_CPUFLAG_RISCV_ISA_N, /* User-level interrupts */\n+\tRTE_CPUFLAG_RISCV_ISA_O, /* Reserved */\n+\tRTE_CPUFLAG_RISCV_ISA_P, /* Packed-SIMD */\n+\tRTE_CPUFLAG_RISCV_ISA_Q, /* Quad-precision floating-points */\n+\tRTE_CPUFLAG_RISCV_ISA_R, /* Reserved */\n+\tRTE_CPUFLAG_RISCV_ISA_S, /* Supervisor mode */\n+\tRTE_CPUFLAG_RISCV_ISA_T, /* Transactional memory */\n+\tRTE_CPUFLAG_RISCV_ISA_U, /* User mode */\n+\tRTE_CPUFLAG_RISCV_ISA_V, /* Vector */\n+\tRTE_CPUFLAG_RISCV_ISA_W, /* Reserved */\n+\tRTE_CPUFLAG_RISCV_ISA_X, /* Non-standard extension present */\n+\tRTE_CPUFLAG_RISCV_ISA_Y, /* Reserved */\n+\tRTE_CPUFLAG_RISCV_ISA_Z, /* Reserved */\n+\t/* The last item */\n+\tRTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */\n+};\n+\n+#include \"generic/rte_cpuflags.h\"\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_CPUFLAGS_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_cycles.h b/lib/eal/riscv/include/rte_cycles.h\nnew file mode 100644\nindex 0000000000..1eb6e2bad2\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_cycles.h\n@@ -0,0 +1,103 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2015 Cavium, Inc\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#ifndef RTE_CYCLES_RISCV_H\n+#define RTE_CYCLES_RISCV_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_cycles.h\"\n+\n+#ifndef RTE_RISCV_RDTSC_USE_HPM\n+#define RTE_RISCV_RDTSC_USE_HPM 0\n+#endif\n+\n+#define RV64_CSRR(reg, value) \\\n+\tasm volatile(\"csrr %0, \" #reg : \"=r\" (value) : : \"memory\")\n+\n+/** Read wall time counter */\n+static __rte_always_inline uint64_t\n+__rte_riscv_rdtime(void)\n+{\n+\tuint64_t tsc;\n+\tRV64_CSRR(time, tsc);\n+\treturn tsc;\n+}\n+\n+/** Read wall time counter ensuring no re-ordering */\n+static __rte_always_inline uint64_t\n+__rte_riscv_rdtime_precise(void)\n+{\n+#if !defined(RTE_RISCV_EMU_UTIME)\n+\tasm volatile(\"fence\" : : : \"memory\");\n+#endif\n+\treturn __rte_riscv_rdtime();\n+}\n+\n+/** Read hart cycle counter */\n+static __rte_always_inline uint64_t\n+__rte_riscv_rdcycle(void)\n+{\n+\tuint64_t tsc;\n+\tRV64_CSRR(cycle, tsc);\n+\treturn tsc;\n+}\n+\n+/** Read hart cycle counter ensuring no re-ordering */\n+static __rte_always_inline uint64_t\n+__rte_riscv_rdcycle_precise(void)\n+{\n+#if !defined(RTE_RISCV_EMU_UCYCLE)\n+\tasm volatile(\"fence\" : : : \"memory\");\n+#endif\n+\treturn __rte_riscv_rdcycle();\n+}\n+\n+/**\n+ * Read the time base register.\n+ *\n+ * @return\n+ * The time base for this lcore.\n+ */\n+static __rte_always_inline uint64_t\n+rte_rdtsc(void)\n+{\n+\t/**\n+\t * By default TIME userspace counter is used. Although it's frequency\n+\t * may not be enough for all applications.\n+\t */\n+\tif (!RTE_RISCV_RDTSC_USE_HPM)\n+\t\treturn __rte_riscv_rdtime();\n+\t/**\n+\t * Alternatively HPM's CYCLE counter may be used. However this counter\n+\t * is not guaranteed by ISA to either be stable frequency or always\n+\t * enabled for userspace access (it may trap to kernel or firmware).\n+\t */\n+\treturn __rte_riscv_rdcycle();\n+}\n+\n+static inline uint64_t\n+rte_rdtsc_precise(void)\n+{\n+\tif (!RTE_RISCV_RDTSC_USE_HPM)\n+\t\treturn __rte_riscv_rdtime_precise();\n+\treturn __rte_riscv_rdcycle_precise();\n+}\n+\n+static __rte_always_inline uint64_t\n+rte_get_tsc_cycles(void)\n+{\n+\treturn rte_rdtsc();\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_CYCLES_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_io.h b/lib/eal/riscv/include/rte_io.h\nnew file mode 100644\nindex 0000000000..29659c9590\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_io.h\n@@ -0,0 +1,21 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2016 Cavium, Inc\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#ifndef RTE_IO_RISCV_H\n+#define RTE_IO_RISCV_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_io.h\"\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_IO_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_mcslock.h b/lib/eal/riscv/include/rte_mcslock.h\nnew file mode 100644\nindex 0000000000..b517cd5fc5\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_mcslock.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Arm Limited\n+ */\n+\n+#ifndef RTE_MCSLOCK_RISCV_H\n+#define RTE_MCSLOCK_RISCV_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_mcslock.h\"\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_MCSLOCK_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_memcpy.h b/lib/eal/riscv/include/rte_memcpy.h\nnew file mode 100644\nindex 0000000000..e34f19396e\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_memcpy.h\n@@ -0,0 +1,63 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#ifndef RTE_MEMCPY_RISCV_H\n+#define RTE_MEMCPY_RISCV_H\n+\n+#include <stdint.h>\n+#include <string.h>\n+\n+#include \"rte_common.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_memcpy.h\"\n+\n+static inline void\n+rte_mov16(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 16);\n+}\n+\n+static inline void\n+rte_mov32(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 32);\n+}\n+\n+static inline void\n+rte_mov48(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 48);\n+}\n+\n+static inline void\n+rte_mov64(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 64);\n+}\n+\n+static inline void\n+rte_mov128(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 128);\n+}\n+\n+static inline void\n+rte_mov256(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 256);\n+}\n+\n+#define rte_memcpy(d, s, n)\tmemcpy((d), (s), (n))\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_MEMCPY_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_pause.h b/lib/eal/riscv/include/rte_pause.h\nnew file mode 100644\nindex 0000000000..c24c1f32e8\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_pause.h\n@@ -0,0 +1,31 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#ifndef RTE_PAUSE_RISCV_H\n+#define RTE_PAUSE_RISCV_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"rte_atomic.h\"\n+\n+#include \"generic/rte_pause.h\"\n+\n+static inline void rte_pause(void)\n+{\n+\t/* Insert pause hint directly to be compatible with old compilers.\n+\t * This will work even on platforms without Zihintpause extension\n+\t * because this is a FENCE hint instruction which evaluates to NOP then.\n+\t */\n+\tasm volatile(\".int 0x0100000F\"::: \"memory\");\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_PAUSE_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_pflock.h b/lib/eal/riscv/include/rte_pflock.h\nnew file mode 100644\nindex 0000000000..ce6ca02aca\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_pflock.h\n@@ -0,0 +1,17 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Microsoft Corporation\n+ */\n+#ifndef RTE_PFLOCK_RISCV_H\n+#define RTE_PFLOCK_RISCV_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_pflock.h\"\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_PFLOCK_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_power_intrinsics.h b/lib/eal/riscv/include/rte_power_intrinsics.h\nnew file mode 100644\nindex 0000000000..636e58e71f\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_power_intrinsics.h\n@@ -0,0 +1,22 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#ifndef RTE_POWER_INTRINSIC_RISCV_H\n+#define RTE_POWER_INTRINSIC_RISCV_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_common.h>\n+\n+#include \"generic/rte_power_intrinsics.h\"\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_POWER_INTRINSIC_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_prefetch.h b/lib/eal/riscv/include/rte_prefetch.h\nnew file mode 100644\nindex 0000000000..966d9e2687\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_prefetch.h\n@@ -0,0 +1,50 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2014 IBM Corporation\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#ifndef RTE_PREFETCH_RISCV_H\n+#define RTE_PREFETCH_RISCV_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_common.h>\n+#include \"generic/rte_prefetch.h\"\n+\n+static inline void rte_prefetch0(const volatile void *p)\n+{\n+\tRTE_SET_USED(p);\n+}\n+\n+static inline void rte_prefetch1(const volatile void *p)\n+{\n+\tRTE_SET_USED(p);\n+}\n+\n+static inline void rte_prefetch2(const volatile void *p)\n+{\n+\tRTE_SET_USED(p);\n+}\n+\n+static inline void rte_prefetch_non_temporal(const volatile void *p)\n+{\n+\t/* non-temporal version not available, fallback to rte_prefetch0 */\n+\trte_prefetch0(p);\n+}\n+\n+__rte_experimental\n+static inline void\n+rte_cldemote(const volatile void *p)\n+{\n+\tRTE_SET_USED(p);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_PREFETCH_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_rwlock.h b/lib/eal/riscv/include/rte_rwlock.h\nnew file mode 100644\nindex 0000000000..9cdaf1b0ef\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_rwlock.h\n@@ -0,0 +1,44 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#ifndef RTE_RWLOCK_RISCV_H\n+#define RTE_RWLOCK_RISCV_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_rwlock.h\"\n+\n+static inline void\n+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_read_lock(rwl);\n+}\n+\n+static inline void\n+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_read_unlock(rwl);\n+}\n+\n+static inline void\n+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_write_lock(rwl);\n+}\n+\n+static inline void\n+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_write_unlock(rwl);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_RWLOCK_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_spinlock.h b/lib/eal/riscv/include/rte_spinlock.h\nnew file mode 100644\nindex 0000000000..6af430735c\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_spinlock.h\n@@ -0,0 +1,67 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2015 RehiveTech. All rights reserved.\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#ifndef RTE_SPINLOCK_RISCV_H\n+#define RTE_SPINLOCK_RISCV_H\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+# error Platform must be built with RTE_FORCE_INTRINSICS\n+#endif\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_common.h>\n+#include \"generic/rte_spinlock.h\"\n+\n+static inline int rte_tm_supported(void)\n+{\n+\treturn 0;\n+}\n+\n+static inline void\n+rte_spinlock_lock_tm(rte_spinlock_t *sl)\n+{\n+\trte_spinlock_lock(sl); /* fall-back */\n+}\n+\n+static inline int\n+rte_spinlock_trylock_tm(rte_spinlock_t *sl)\n+{\n+\treturn rte_spinlock_trylock(sl);\n+}\n+\n+static inline void\n+rte_spinlock_unlock_tm(rte_spinlock_t *sl)\n+{\n+\trte_spinlock_unlock(sl);\n+}\n+\n+static inline void\n+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)\n+{\n+\trte_spinlock_recursive_lock(slr); /* fall-back */\n+}\n+\n+static inline void\n+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)\n+{\n+\trte_spinlock_recursive_unlock(slr);\n+}\n+\n+static inline int\n+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)\n+{\n+\treturn rte_spinlock_recursive_trylock(slr);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_SPINLOCK_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_ticketlock.h b/lib/eal/riscv/include/rte_ticketlock.h\nnew file mode 100644\nindex 0000000000..b8d2a4f937\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_ticketlock.h\n@@ -0,0 +1,21 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Arm Limited\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#ifndef RTE_TICKETLOCK_RISCV_H\n+#define RTE_TICKETLOCK_RISCV_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_ticketlock.h\"\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_TICKETLOCK_RISCV_H */\ndiff --git a/lib/eal/riscv/include/rte_vect.h b/lib/eal/riscv/include/rte_vect.h\nnew file mode 100644\nindex 0000000000..4600521c20\n--- /dev/null\n+++ b/lib/eal/riscv/include/rte_vect.h\n@@ -0,0 +1,55 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#ifndef RTE_VECT_RISCV_H\n+#define RTE_VECT_RISCV_H\n+\n+#include <stdint.h>\n+#include \"generic/rte_vect.h\"\n+#include \"rte_common.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED\n+\n+typedef int32_t\t\txmm_t __attribute__((vector_size(16)));\n+\n+#define XMM_SIZE\t(sizeof(xmm_t))\n+#define XMM_MASK\t(XMM_SIZE - 1)\n+\n+typedef union rte_xmm {\n+\txmm_t\t\tx;\n+\tuint8_t\t\tu8[XMM_SIZE / sizeof(uint8_t)];\n+\tuint16_t\tu16[XMM_SIZE / sizeof(uint16_t)];\n+\tuint32_t\tu32[XMM_SIZE / sizeof(uint32_t)];\n+\tuint64_t\tu64[XMM_SIZE / sizeof(uint64_t)];\n+\tdouble\t\tpd[XMM_SIZE / sizeof(double)];\n+} __rte_aligned(8) rte_xmm_t;\n+\n+static inline xmm_t\n+vect_load_128(void *p)\n+{\n+\txmm_t ret = *((xmm_t *)p);\n+\treturn ret;\n+}\n+\n+static inline xmm_t\n+vect_and(xmm_t data, xmm_t mask)\n+{\n+\trte_xmm_t ret = (rte_xmm_t)data;\n+\trte_xmm_t m = (rte_xmm_t)mask;\n+\tret.u64[0] &= m.u64[0];\n+\tret.u64[1] &= m.u64[1];\n+\treturn ret.x;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_VECT_RISCV_H */\ndiff --git a/lib/eal/riscv/meson.build b/lib/eal/riscv/meson.build\nnew file mode 100644\nindex 0000000000..6ec53ea03a\n--- /dev/null\n+++ b/lib/eal/riscv/meson.build\n@@ -0,0 +1,11 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2017 Intel Corporation.\n+\n+subdir('include')\n+\n+sources += files(\n+\t'rte_cpuflags.c',\n+\t'rte_cycles.c',\n+\t'rte_hypervisor.c',\n+\t'rte_power_intrinsics.c',\n+)\ndiff --git a/lib/eal/riscv/rte_cpuflags.c b/lib/eal/riscv/rte_cpuflags.c\nnew file mode 100644\nindex 0000000000..4f6d29b947\n--- /dev/null\n+++ b/lib/eal/riscv/rte_cpuflags.c\n@@ -0,0 +1,122 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#include \"rte_cpuflags.h\"\n+\n+#include <elf.h>\n+#include <fcntl.h>\n+#include <assert.h>\n+#include <unistd.h>\n+#include <string.h>\n+\n+#ifndef AT_HWCAP\n+#define AT_HWCAP 16\n+#endif\n+\n+#ifndef AT_HWCAP2\n+#define AT_HWCAP2 26\n+#endif\n+\n+#ifndef AT_PLATFORM\n+#define AT_PLATFORM 15\n+#endif\n+\n+enum cpu_register_t {\n+\tREG_NONE = 0,\n+\tREG_HWCAP,\n+\tREG_HWCAP2,\n+\tREG_PLATFORM,\n+\tREG_MAX\n+};\n+\n+typedef uint32_t hwcap_registers_t[REG_MAX];\n+\n+/**\n+ * Struct to hold a processor feature entry\n+ */\n+struct feature_entry {\n+\tuint32_t reg;\n+\tuint32_t bit;\n+#define CPU_FLAG_NAME_MAX_LEN 64\n+\tchar name[CPU_FLAG_NAME_MAX_LEN];\n+};\n+\n+#define FEAT_DEF(name, reg, bit) \\\n+\t[RTE_CPUFLAG_##name] = {reg, bit, #name},\n+\n+typedef Elf64_auxv_t _Elfx_auxv_t;\n+\n+const struct feature_entry rte_cpu_feature_table[] = {\n+\tFEAT_DEF(RISCV_ISA_A, REG_HWCAP, 0)\n+\tFEAT_DEF(RISCV_ISA_B, REG_HWCAP, 1)\n+\tFEAT_DEF(RISCV_ISA_C, REG_HWCAP, 2)\n+\tFEAT_DEF(RISCV_ISA_D, REG_HWCAP, 3)\n+\tFEAT_DEF(RISCV_ISA_E, REG_HWCAP, 4)\n+\tFEAT_DEF(RISCV_ISA_F, REG_HWCAP, 5)\n+\tFEAT_DEF(RISCV_ISA_G, REG_HWCAP, 6)\n+\tFEAT_DEF(RISCV_ISA_H, REG_HWCAP, 7)\n+\tFEAT_DEF(RISCV_ISA_I, REG_HWCAP, 8)\n+\tFEAT_DEF(RISCV_ISA_J, REG_HWCAP, 9)\n+\tFEAT_DEF(RISCV_ISA_K, REG_HWCAP, 10)\n+\tFEAT_DEF(RISCV_ISA_L, REG_HWCAP, 11)\n+\tFEAT_DEF(RISCV_ISA_M, REG_HWCAP, 12)\n+\tFEAT_DEF(RISCV_ISA_N, REG_HWCAP, 13)\n+\tFEAT_DEF(RISCV_ISA_O, REG_HWCAP, 14)\n+\tFEAT_DEF(RISCV_ISA_P, REG_HWCAP, 15)\n+\tFEAT_DEF(RISCV_ISA_Q, REG_HWCAP, 16)\n+\tFEAT_DEF(RISCV_ISA_R, REG_HWCAP, 17)\n+\tFEAT_DEF(RISCV_ISA_S, REG_HWCAP, 18)\n+\tFEAT_DEF(RISCV_ISA_T, REG_HWCAP, 19)\n+\tFEAT_DEF(RISCV_ISA_U, REG_HWCAP, 20)\n+\tFEAT_DEF(RISCV_ISA_V, REG_HWCAP, 21)\n+\tFEAT_DEF(RISCV_ISA_W, REG_HWCAP, 22)\n+\tFEAT_DEF(RISCV_ISA_X, REG_HWCAP, 23)\n+\tFEAT_DEF(RISCV_ISA_Y, REG_HWCAP, 24)\n+\tFEAT_DEF(RISCV_ISA_Z, REG_HWCAP, 25)\n+};\n+/*\n+ * Read AUXV software register and get cpu features for ARM\n+ */\n+static void\n+rte_cpu_get_features(hwcap_registers_t out)\n+{\n+\tout[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);\n+\tout[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2);\n+}\n+\n+/*\n+ * Checks if a particular flag is available on current machine.\n+ */\n+int\n+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)\n+{\n+\tconst struct feature_entry *feat;\n+\thwcap_registers_t regs = {0};\n+\n+\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n+\t\treturn -ENOENT;\n+\n+\tfeat = &rte_cpu_feature_table[feature];\n+\tif (feat->reg == REG_NONE)\n+\t\treturn -EFAULT;\n+\n+\trte_cpu_get_features(regs);\n+\treturn (regs[feat->reg] >> feat->bit) & 1;\n+}\n+\n+const char *\n+rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)\n+{\n+\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n+\t\treturn NULL;\n+\treturn rte_cpu_feature_table[feature].name;\n+}\n+\n+void\n+rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)\n+{\n+\tmemset(intrinsics, 0, sizeof(*intrinsics));\n+}\ndiff --git a/lib/eal/riscv/rte_cycles.c b/lib/eal/riscv/rte_cycles.c\nnew file mode 100644\nindex 0000000000..358f271311\n--- /dev/null\n+++ b/lib/eal/riscv/rte_cycles.c\n@@ -0,0 +1,77 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2015 Cavium, Inc\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#include <stdio.h>\n+\n+#include \"eal_private.h\"\n+#include \"rte_byteorder.h\"\n+#include \"rte_cycles.h\"\n+#include \"rte_log.h\"\n+\n+/** Read generic counter frequency */\n+static uint64_t\n+__rte_riscv_timefrq(void)\n+{\n+#define TIMEBASE_FREQ_SIZE\t8\n+\tif (RTE_RISCV_TIME_FREQ > 0)\n+\t\treturn RTE_RISCV_TIME_FREQ;\n+\tuint8_t buf[TIMEBASE_FREQ_SIZE];\n+\tssize_t cnt;\n+\tFILE *file;\n+\n+\tfile = fopen(\"/proc/device-tree/cpus/timebase-frequency\", \"rb\");\n+\tif (!file)\n+\t\tgoto fail;\n+\n+\tcnt = fread(buf, 1, TIMEBASE_FREQ_SIZE, file);\n+\tfclose(file);\n+\tswitch (cnt) {\n+\tcase 8:\n+\t\treturn rte_be_to_cpu_64(*(uint64_t *)buf);\n+\tcase 4:\n+\t\treturn rte_be_to_cpu_32(*(uint32_t *)buf);\n+\tdefault:\n+\t\tbreak;\n+\t}\n+fail:\n+\tRTE_LOG(WARNING, EAL, \"Unable to read timebase-frequency from FDT.\\n\");\n+\treturn 0;\n+}\n+\n+uint64_t\n+get_tsc_freq_arch(void)\n+{\n+\tRTE_LOG(NOTICE, EAL, \"TSC using RISC-V %s.\\n\",\n+\t\tRTE_RISCV_RDTSC_USE_HPM ? \"rdcycle\" : \"rdtime\");\n+\tif (!RTE_RISCV_RDTSC_USE_HPM)\n+\t\treturn __rte_riscv_timefrq();\n+#define CYC_PER_1MHZ 1E6\n+\t/*\n+\t * Use real time clock to estimate current cycle frequency\n+\t */\n+\tuint64_t ticks, frq;\n+\tuint64_t start_ticks, cur_ticks;\n+\tuint64_t start_cycle, end_cycle;\n+\n+\t/* Do not proceed unless clock frequency can be obtained. */\n+\tfrq = __rte_riscv_timefrq();\n+\tif (!frq)\n+\t\treturn 0;\n+\n+\t/* Number of ticks for 1/10 second */\n+\tticks = frq / 10;\n+\n+\tstart_ticks = __rte_riscv_rdtime_precise();\n+\tstart_cycle = rte_rdtsc_precise();\n+\tdo {\n+\t\tcur_ticks = __rte_riscv_rdtime();\n+\t} while ((cur_ticks - start_ticks) < ticks);\n+\tend_cycle = rte_rdtsc_precise();\n+\n+\t/* Adjust the cycles to next 1Mhz */\n+\treturn RTE_ALIGN_MUL_CEIL((end_cycle - start_cycle) * 10, CYC_PER_1MHZ);\n+}\ndiff --git a/lib/eal/riscv/rte_hypervisor.c b/lib/eal/riscv/rte_hypervisor.c\nnew file mode 100644\nindex 0000000000..92b5435993\n--- /dev/null\n+++ b/lib/eal/riscv/rte_hypervisor.c\n@@ -0,0 +1,13 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#include \"rte_hypervisor.h\"\n+\n+enum rte_hypervisor\n+rte_hypervisor_get(void)\n+{\n+\treturn RTE_HYPERVISOR_UNKNOWN;\n+}\ndiff --git a/lib/eal/riscv/rte_power_intrinsics.c b/lib/eal/riscv/rte_power_intrinsics.c\nnew file mode 100644\nindex 0000000000..240e7b6b87\n--- /dev/null\n+++ b/lib/eal/riscv/rte_power_intrinsics.c\n@@ -0,0 +1,56 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 StarFive\n+ * Copyright(c) 2022 SiFive\n+ * Copyright(c) 2022 Semihalf\n+ */\n+\n+#include \"rte_power_intrinsics.h\"\n+\n+/**\n+ * This function is not supported on RISC-V 64\n+ */\n+int\n+rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n+\t\t const uint64_t tsc_timestamp)\n+{\n+\tRTE_SET_USED(pmc);\n+\tRTE_SET_USED(tsc_timestamp);\n+\n+\treturn -ENOTSUP;\n+}\n+\n+/**\n+ * This function is not supported on RISC-V 64\n+ */\n+int\n+rte_power_pause(const uint64_t tsc_timestamp)\n+{\n+\tRTE_SET_USED(tsc_timestamp);\n+\n+\treturn -ENOTSUP;\n+}\n+\n+/**\n+ * This function is not supported on RISC-V 64\n+ */\n+int\n+rte_power_monitor_wakeup(const unsigned int lcore_id)\n+{\n+\tRTE_SET_USED(lcore_id);\n+\n+\treturn -ENOTSUP;\n+}\n+\n+/**\n+ * This function is not supported on RISC-V 64\n+ */\n+int\n+rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[],\n+\t\t\tconst uint32_t num, const uint64_t tsc_timestamp)\n+{\n+\tRTE_SET_USED(pmc);\n+\tRTE_SET_USED(num);\n+\tRTE_SET_USED(tsc_timestamp);\n+\n+\treturn -ENOTSUP;\n+}\ndiff --git a/meson.build b/meson.build\nindex 937f6110c0..a8db04a1ee 100644\n--- a/meson.build\n+++ b/meson.build\n@@ -50,6 +50,8 @@ elif host_machine.cpu_family().startswith('arm') or host_machine.cpu_family().st\n arch_subdir = 'arm'\n elif host_machine.cpu_family().startswith('ppc')\n arch_subdir = 'ppc'\n+elif host_machine.cpu_family().startswith('riscv')\n+ arch_subdir = 'riscv'\n endif\n \n # configure the build, and make sure configs here and in config folder are\n", "prefixes": [ "03/11" ] }