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{
    "id": 110747,
    "url": "http://patchwork.dpdk.org/api/patches/110747/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220505173003.3242618-9-kda@semihalf.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
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        "scm_url": "git://dpdk.org/dpdk",
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        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
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    "msgid": "<20220505173003.3242618-9-kda@semihalf.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220505173003.3242618-9-kda@semihalf.com",
    "date": "2022-05-05T17:30:00",
    "name": "[08/11] test/cpuflags: add test for RISC-V cpu flag",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "2342464055f86ecc78bd7f12aa4a2b15d2595510",
    "submitter": {
        "id": 2179,
        "url": "http://patchwork.dpdk.org/api/people/2179/?format=api",
        "name": "Stanislaw Kardach",
        "email": "kda@semihalf.com"
    },
    "delegate": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220505173003.3242618-9-kda@semihalf.com/mbox/",
    "series": [
        {
            "id": 22800,
            "url": "http://patchwork.dpdk.org/api/series/22800/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=22800",
            "date": "2022-05-05T17:29:52",
            "name": "Introduce support for RISC-V architecture",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/22800/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/110747/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/110747/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Stanislaw Kardach <kda@semihalf.com>",
        "To": "dev@dpdk.org",
        "Cc": "Michal Mazurek <maz@semihalf.com>,\n Frank Zhao <Frank.Zhao@starfivetech.com>, Sam Grove <sam.grove@sifive.com>,\n mw@semihalf.com, upstream@semihalf.com,\n Stanislaw Kardach <kda@semihalf.com>",
        "Subject": "[PATCH 08/11] test/cpuflags: add test for RISC-V cpu flag",
        "Date": "Thu,  5 May 2022 19:30:00 +0200",
        "Message-Id": "<20220505173003.3242618-9-kda@semihalf.com>",
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    "content": "From: Michal Mazurek <maz@semihalf.com>\n\nAdd checks for all flag values defined in the RISC-V misa CSR register.\n\nSigned-off-by: Michal Mazurek <maz@semihalf.com>\nSigned-off-by: Stanislaw Kardach <kda@semihalf.com>\nSponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>\nSponsored-by: Sam Grove <sam.grove@sifive.com>\n---\n app/test/test_cpuflags.c | 81 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 81 insertions(+)",
    "diff": "diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c\nindex 40f6ac7fca..98a99c2c7d 100644\n--- a/app/test/test_cpuflags.c\n+++ b/app/test/test_cpuflags.c\n@@ -200,6 +200,87 @@ test_cpuflags(void)\n \tCHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);\n #endif\n \n+#if defined(RTE_ARCH_RISCV)\n+\n+\tprintf(\"Check for RISCV_ISA_A:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A);\n+\n+\tprintf(\"Check for RISCV_ISA_B:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B);\n+\n+\tprintf(\"Check for RISCV_ISA_C:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C);\n+\n+\tprintf(\"Check for RISCV_ISA_D:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D);\n+\n+\tprintf(\"Check for RISCV_ISA_E:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E);\n+\n+\tprintf(\"Check for RISCV_ISA_F:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F);\n+\n+\tprintf(\"Check for RISCV_ISA_G:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G);\n+\n+\tprintf(\"Check for RISCV_ISA_H:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H);\n+\n+\tprintf(\"Check for RISCV_ISA_I:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I);\n+\n+\tprintf(\"Check for RISCV_ISA_J:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J);\n+\n+\tprintf(\"Check for RISCV_ISA_K:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K);\n+\n+\tprintf(\"Check for RISCV_ISA_L:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L);\n+\n+\tprintf(\"Check for RISCV_ISA_M:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M);\n+\n+\tprintf(\"Check for RISCV_ISA_N:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N);\n+\n+\tprintf(\"Check for RISCV_ISA_O:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O);\n+\n+\tprintf(\"Check for RISCV_ISA_P:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P);\n+\n+\tprintf(\"Check for RISCV_ISA_Q:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q);\n+\n+\tprintf(\"Check for RISCV_ISA_R:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R);\n+\n+\tprintf(\"Check for RISCV_ISA_S:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S);\n+\n+\tprintf(\"Check for RISCV_ISA_T:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T);\n+\n+\tprintf(\"Check for RISCV_ISA_U:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U);\n+\n+\tprintf(\"Check for RISCV_ISA_V:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V);\n+\n+\tprintf(\"Check for RISCV_ISA_W:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W);\n+\n+\tprintf(\"Check for RISCV_ISA_X:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X);\n+\n+\tprintf(\"Check for RISCV_ISA_Y:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y);\n+\n+\tprintf(\"Check for RISCV_ISA_Z:\\t\");\n+\tCHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z);\n+#endif\n+\n \t/*\n \t * Check if invalid data is handled properly\n \t */\n",
    "prefixes": [
        "08/11"
    ]
}