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GET /api/patches/112317/?format=api
{ "id": 112317, "url": "http://patchwork.dpdk.org/api/patches/112317/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220604162651.3503338-4-tduszynski@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220604162651.3503338-4-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220604162651.3503338-4-tduszynski@marvell.com", "date": "2022-06-04T16:26:44", "name": "[03/10] raw/cnxk_bphy: add doxygen comments", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "09e24e7516c13feadc28e9fde940eaf3e450a8fa", "submitter": { "id": 2215, "url": "http://patchwork.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220604162651.3503338-4-tduszynski@marvell.com/mbox/", "series": [ { "id": 23325, "url": "http://patchwork.dpdk.org/api/series/23325/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=23325", "date": "2022-06-04T16:26:41", "name": "Sync BPHY changes", "version": 1, "mbox": "http://patchwork.dpdk.org/series/23325/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/112317/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/112317/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 465E2A034C;\n\tSat, 4 Jun 2022 18:27:33 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AD8D64280D;\n\tSat, 4 Jun 2022 18:27:24 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 844E140041\n for <dev@dpdk.org>; Sat, 4 Jun 2022 18:27:22 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 254GRF5v032547;\n Sat, 4 Jun 2022 09:27:22 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gg6wq0dgy-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Sat, 04 Jun 2022 09:27:21 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 4 Jun 2022 09:27:19 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Sat, 4 Jun 2022 09:27:19 -0700", "from localhost.localdomain (unknown [10.28.34.39])\n by maili.marvell.com (Postfix) with ESMTP id 2E7DF5E6885;\n Sat, 4 Jun 2022 09:27:16 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=/A3Kk9+5f56kPV5q/KpwtcuwnBSm71MCYPTCk4aAmyE=;\n b=EnMBLbKqpMEMec9vNvOAd83Ty02j/lbWpVtJMGaDqkmmQGDcIEP8TAByIG17f9G9vmrO\n z0xU+F5pMQV2TJL4gdFpJ2UAQ1xqr5z8cnGn4WBp5UOT8tXRARVWMtigepEMawl+/r3L\n JI1x9OlbTC+S9s6TbTseiiKN/2uPDtU3StSQuudykwkQhAgOuVR+3t7vd440vqENdwKQ\n gIlrnZ+lX2VozbZl5YwlPAzj2qLrb/4weGjxZyArV+8yZmvcOZKA3OjYPCQqK2wuyzvq\n 1n0CFFh359mK94toA/z5F20YpKCRq9pi0zgSg7+Jk/G1L6Shk3lyaPe/9KS426hN6KRb QQ==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>, Jakub Palider <jpalider@marvell.com>, Tomasz Duszynski\n <tduszynski@marvell.com>", "CC": "<thomas@monjalon.net>, <jerinj@marvell.com>", "Subject": "[PATCH 03/10] raw/cnxk_bphy: add doxygen comments", "Date": "Sat, 4 Jun 2022 18:26:44 +0200", "Message-ID": "<20220604162651.3503338-4-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220604162651.3503338-1-tduszynski@marvell.com>", "References": "<20220604162651.3503338-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "dVJbrXD6TCtd553vpCMsR3wupG1hZp1E", "X-Proofpoint-GUID": "dVJbrXD6TCtd553vpCMsR3wupG1hZp1E", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514\n definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Jakub Palider <jpalider@marvell.com>\n\nDocumentation in doxygen format is important for API\nheaders used by end user. This patch fills BPHY and CGX\ninterface with missing bits.\n\nSigned-off-by: Jakub Palider <jpalider@marvell.com>\nReviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>\n---\n drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 339 +++++++++++++++++++++++++--\n 1 file changed, 318 insertions(+), 21 deletions(-)", "diff": "diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\nindex cc2372f719..db8a13a4f8 100644\n--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\n+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\n@@ -13,103 +13,169 @@\n #include <rte_memcpy.h>\n #include <rte_rawdev.h>\n \n+/**\n+ * @file rte_pmd_bphy.h\n+ *\n+ * Marvell CGX and BPHY PMD specific structures and interface\n+ *\n+ * This API allows applications to manage BPHY memory in user space along with\n+ * installing interrupt handlers for low latency signal processing.\n+ */\n+\n #ifdef __cplusplus\n extern \"C\" {\n #endif\n \n+/** Available message types */\n enum cnxk_bphy_cgx_msg_type {\n+\t/** Type used to obtain link information */\n \tCNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,\n+\t/** Type used to disable internal loopback */\n \tCNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,\n+\t/** Type used to enable loopback */\n \tCNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,\n+\t/** Type used to disable PTP on RX */\n \tCNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,\n+\t/** Type used to enable PTP on RX */\n \tCNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,\n+\t/** Type used to set link mode */\n \tCNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,\n+\t/** Type used to set link state */\n \tCNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,\n+\t/** Type used to start transmission and packet reception */\n \tCNXK_BPHY_CGX_MSG_TYPE_START_RXTX,\n+\t/** Type used to stop transmission and packet reception */\n \tCNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,\n+\t/** Type used to obtain supported FEC */\n \tCNXK_BPHY_CGX_MSG_TYPE_GET_SUPPORTED_FEC,\n+\t/** Type used to set FEC */\n \tCNXK_BPHY_CGX_MSG_TYPE_SET_FEC,\n };\n \n+/** Available link speeds */\n enum cnxk_bphy_cgx_eth_link_speed {\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_NONE,\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_10M,\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_100M,\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_1G,\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_2HG,\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_5G,\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_10G,\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_20G,\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_25G,\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_40G,\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_50G,\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_80G,\n-\tCNXK_BPHY_CGX_ETH_LINK_SPEED_100G,\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_NONE, /**< None */\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_10M, /**< 10 Mbps */\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_100M, /**< 100 Mbps */\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_1G, /**< 1 Gbps */\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_2HG, /**< 2.5 Gbps */\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_5G, /**< 5 Gbps */\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_10G, /**< 10 Gbps */\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_20G, /**< 20 Gbps */\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_25G, /**< 25 Gbps */\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_40G, /**< 40 Gbps */\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_50G, /**< 50 Gbps */\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_80G, /**< 80 Gbps */\n+\tCNXK_BPHY_CGX_ETH_LINK_SPEED_100G, /**< 100 Gbps */\n \t__CNXK_BPHY_CGX_ETH_LINK_SPEED_MAX\n };\n \n+/** Available FEC modes */\n enum cnxk_bphy_cgx_eth_link_fec {\n+\t/** Disable FEC */\n \tCNXK_BPHY_CGX_ETH_LINK_FEC_NONE,\n+\t/** Base FEC (IEEE 802.3 CLause 74) */\n \tCNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R,\n+\t/** Reed-Solomon FEC */\n \tCNXK_BPHY_CGX_ETH_LINK_FEC_RS,\n \t__CNXK_BPHY_CGX_ETH_LINK_FEC_MAX\n };\n \n+/** Available link modes */\n enum cnxk_bphy_cgx_eth_link_mode {\n+\t/** SGMII */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,\n+\t/** 1000BASE-X */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,\n+\t/** QSGMII */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,\n+\t/** 10GBASE-C2C */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,\n+\t/** 10GBASE-C2M */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,\n+\t/** 10GBASE-KR */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,\n+\t/** 20GBASE-C2C */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,\n+\t/** 25GBASE-C2C */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,\n+\t/** 25GBASE-C2M */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,\n+\t/** 25GBASE-2-C2M */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,\n+\t/** 25GBASE-CR */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,\n+\t/** 25GBASE-KR */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,\n+\t/** 40GBASE-C2C */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,\n+\t/** 40GBASE-C2M */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,\n+\t/** 40GBASE-CR4 */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,\n+\t/** 40GBASE-KR4 */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,\n+\t/** 40GAUI-C2C */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,\n+\t/** 50GBASE-C2C */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,\n+\t/** 50GBASE-C2M */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,\n+\t/** 50GBASE-4-C2C */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,\n+\t/** 50GBASE-CR */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,\n+\t/** 50GBASE-KR */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,\n+\t/** 80GAUI-C2C */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,\n+\t/** 100GBASE-C2C */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,\n+\t/** 100GBASE-C2M */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,\n+\t/** 100GBASE-CR4 */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,\n+\t/** 100GBASE-KR4 */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,\n \t__CNXK_BPHY_CGX_ETH_LINK_MODE_MAX\n };\n \n struct cnxk_bphy_cgx_msg_link_mode {\n+\t/** Setting for full-duplex */\n \tbool full_duplex;\n+\t/** Setting for automatic link negotiation */\n \tbool autoneg;\n+\t/** Link speed */\n \tenum cnxk_bphy_cgx_eth_link_speed speed;\n+\t/** Link mode */\n \tenum cnxk_bphy_cgx_eth_link_mode mode;\n };\n \n struct cnxk_bphy_cgx_msg_link_info {\n+\t/** Link state information */\n \tbool link_up;\n+\t/** Link full duplex state */\n \tbool full_duplex;\n+\t/** Link speed */\n \tenum cnxk_bphy_cgx_eth_link_speed speed;\n+\t/** Link auto-negotiation setting */\n \tbool autoneg;\n+\t/** FEC mode */\n \tenum cnxk_bphy_cgx_eth_link_fec fec;\n+\t/** Link configuration */\n \tenum cnxk_bphy_cgx_eth_link_mode mode;\n };\n \n struct cnxk_bphy_cgx_msg_set_link_state {\n+\t/** Defines link state result */\n \tbool state; /* up or down */\n };\n \n struct cnxk_bphy_cgx_msg {\n+\t/** Message type */\n \tenum cnxk_bphy_cgx_msg_type type;\n-\t/*\n-\t * data depends on message type and whether\n+\t/**\n+\t * Data depends on message type and whether\n \t * it's a request or a response\n \t */\n \tvoid *data;\n@@ -117,42 +183,63 @@ struct cnxk_bphy_cgx_msg {\n \n #define CNXK_BPHY_DEF_QUEUE 0\n \n+/**\n+ * BPHY interrupt handler\n+ *\n+ * @param irq_num\n+ * Zero-based interrupt number\n+ * @param isr_data\n+ * Cookie passed to interrupt handler\n+ */\n typedef void (*cnxk_bphy_intr_handler_t)(int irq_num, void *isr_data);\n \n struct cnxk_bphy_mem {\n+\t/** Memory for BAR0 */\n \tstruct rte_mem_resource res0;\n+\t/** Memory for BAR2 */\n \tstruct rte_mem_resource res2;\n };\n \n+/** Available IRQ configuration commands */\n enum cnxk_bphy_irq_msg_type {\n+\t/** Type used to initialize interrupts */\n \tCNXK_BPHY_IRQ_MSG_TYPE_INIT,\n+\t/** Type used to deinitialize interrupts */\n \tCNXK_BPHY_IRQ_MSG_TYPE_FINI,\n+\t/** Type used to register interrupt */\n \tCNXK_BPHY_IRQ_MSG_TYPE_REGISTER,\n+\t/** Type used to unregister interrupt */\n \tCNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,\n+\t/** Type used to retrieve BPHY memory */\n \tCNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,\n+\t/** Type used to retrieve NPA PF function */\n \tCNXK_BPHY_MSG_TYPE_NPA_PF_FUNC,\n+\t/** Type used to retrieve NPA SSO function */\n \tCNXK_BPHY_MSG_TYPE_SSO_PF_FUNC,\n };\n \n struct cnxk_bphy_irq_msg {\n+\t/** Message command type */\n \tenum cnxk_bphy_irq_msg_type type;\n-\t/*\n-\t * The data field, depending on message type, may point to\n-\t * - (enq) full struct cnxk_bphy_irq_info for registration request\n-\t * - (enq) struct cnxk_bphy_irq_info with irq_num set for unregistration\n-\t * - (deq) struct cnxk_bphy_mem for memory range request response\n-\t * - (xxx) NULL\n+\t/**\n+\t * Data depends on message type and whether\n+\t * it is a request or a response\n \t */\n \tvoid *data;\n };\n \n struct cnxk_bphy_irq_info {\n+\t/** Interrupt number */\n \tint irq_num;\n+\t/** Interrupt handler */\n \tcnxk_bphy_intr_handler_t handler;\n+\t/** Interrupt handler cookie */\n \tvoid *data;\n+\t/** CPU zero-based number for interrupt execution */\n \tint cpu;\n };\n \n+/** @internal helper routine for enqueuing/dequeuing messages */\n static __rte_always_inline int\n __rte_pmd_bphy_enq_deq(uint16_t dev_id, unsigned int queue, void *req,\n \t\t void *rsp, size_t rsp_size)\n@@ -187,6 +274,15 @@ __rte_pmd_bphy_enq_deq(uint16_t dev_id, unsigned int queue, void *req,\n \treturn 0;\n }\n \n+/**\n+ * Initialize BPHY subsystem\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_intr_init(uint16_t dev_id)\n {\n@@ -198,6 +294,15 @@ rte_pmd_bphy_intr_init(uint16_t dev_id)\n \t\t\t\t NULL, 0);\n }\n \n+/**\n+ * Deinitialize BPHY subsystem\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_intr_fini(uint16_t dev_id)\n {\n@@ -209,6 +314,23 @@ rte_pmd_bphy_intr_fini(uint16_t dev_id)\n \t\t\t\t NULL, 0);\n }\n \n+/**\n+ * Register BPHY interrupt handler\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param irq_num\n+ * Zero-based interrupt number\n+ * @param handler\n+ * Interrupt handler to be executed\n+ * @param data\n+ * Data to be passed to interrupt handler\n+ * @param cpu\n+ * CPU number which will be handling interrupt\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num,\n \t\t\t cnxk_bphy_intr_handler_t handler, void *data,\n@@ -229,6 +351,17 @@ rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num,\n \t\t\t\t NULL, 0);\n }\n \n+/**\n+ * Unregister BPHY interrupt handler\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param irq_num\n+ * Zero-based interrupt number used during registration\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num)\n {\n@@ -244,6 +377,17 @@ rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num)\n \t\t\t\t NULL, 0);\n }\n \n+/**\n+ * Obtain BPHY memory\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param mem\n+ * Memory structure which will be filled for memory access\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_intr_mem_get(uint16_t dev_id, struct cnxk_bphy_mem *mem)\n {\n@@ -255,6 +399,17 @@ rte_pmd_bphy_intr_mem_get(uint16_t dev_id, struct cnxk_bphy_mem *mem)\n \t\t\t\t mem, sizeof(*mem));\n }\n \n+/**\n+ * Obtain NPA PF func\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param pf_func\n+ * NPA PF function to obtain\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_npa_pf_func_get(uint16_t dev_id, uint16_t *pf_func)\n {\n@@ -266,6 +421,17 @@ rte_pmd_bphy_npa_pf_func_get(uint16_t dev_id, uint16_t *pf_func)\n \t\t\t\t pf_func, sizeof(*pf_func));\n }\n \n+/**\n+ * Obtain SSO PF func\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param pf_func\n+ * SSO PF function to obtain\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_sso_pf_func_get(uint16_t dev_id, uint16_t *pf_func)\n {\n@@ -277,6 +443,19 @@ rte_pmd_bphy_sso_pf_func_get(uint16_t dev_id, uint16_t *pf_func)\n \t\t\t\t pf_func, sizeof(*pf_func));\n }\n \n+/**\n+ * Obtain link information\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ * @param info\n+ * Link information structure\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_cgx_get_link_info(uint16_t dev_id, uint16_t lmac,\n \t\t\t struct cnxk_bphy_cgx_msg_link_info *info)\n@@ -288,6 +467,17 @@ rte_pmd_bphy_cgx_get_link_info(uint16_t dev_id, uint16_t lmac,\n \treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, info, sizeof(*info));\n }\n \n+/**\n+ * Disable loopback mode for an interface\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_cgx_intlbk_disable(uint16_t dev_id, uint16_t lmac)\n {\n@@ -298,6 +488,17 @@ rte_pmd_bphy_cgx_intlbk_disable(uint16_t dev_id, uint16_t lmac)\n \treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);\n }\n \n+/**\n+ * Enable loopback mode for an interface\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_cgx_intlbk_enable(uint16_t dev_id, uint16_t lmac)\n {\n@@ -308,6 +509,17 @@ rte_pmd_bphy_cgx_intlbk_enable(uint16_t dev_id, uint16_t lmac)\n \treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);\n }\n \n+/**\n+ * Disable PTP on RX path\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_cgx_ptp_rx_disable(uint16_t dev_id, uint16_t lmac)\n {\n@@ -318,6 +530,17 @@ rte_pmd_bphy_cgx_ptp_rx_disable(uint16_t dev_id, uint16_t lmac)\n \treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);\n }\n \n+/**\n+ * Enable PTP on RX path\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_cgx_ptp_rx_enable(uint16_t dev_id, uint16_t lmac)\n {\n@@ -328,6 +551,19 @@ rte_pmd_bphy_cgx_ptp_rx_enable(uint16_t dev_id, uint16_t lmac)\n \treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);\n }\n \n+/**\n+ * Set link mode for a CGX\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ * @param mode\n+ * Link mode to set\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_cgx_set_link_mode(uint16_t dev_id, uint16_t lmac,\n \t\t\t struct cnxk_bphy_cgx_msg_link_mode *mode)\n@@ -340,6 +576,19 @@ rte_pmd_bphy_cgx_set_link_mode(uint16_t dev_id, uint16_t lmac,\n \treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);\n }\n \n+/**\n+ * Set link state for a CGX\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ * @param up\n+ * Link state to set\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_cgx_set_link_state(uint16_t dev_id, uint16_t lmac, bool up)\n {\n@@ -354,6 +603,17 @@ rte_pmd_bphy_cgx_set_link_state(uint16_t dev_id, uint16_t lmac, bool up)\n \treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);\n }\n \n+/**\n+ * Start CGX\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_cgx_start_rxtx(uint16_t dev_id, uint16_t lmac)\n {\n@@ -364,6 +624,17 @@ rte_pmd_bphy_cgx_start_rxtx(uint16_t dev_id, uint16_t lmac)\n \treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);\n }\n \n+/**\n+ * Stop CGX\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_cgx_stop_rxtx(uint16_t dev_id, uint16_t lmac)\n {\n@@ -374,6 +645,19 @@ rte_pmd_bphy_cgx_stop_rxtx(uint16_t dev_id, uint16_t lmac)\n \treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);\n }\n \n+/**\n+ * Get supported list FEC mode\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ * @param fec\n+ * FEC structure which holds information\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_cgx_get_supported_fec(uint16_t dev_id, uint16_t lmac,\n \t\t\t\t enum cnxk_bphy_cgx_eth_link_fec *fec)\n@@ -385,6 +669,19 @@ rte_pmd_bphy_cgx_get_supported_fec(uint16_t dev_id, uint16_t lmac,\n \treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, fec, sizeof(*fec));\n }\n \n+/**\n+ * Set FEC mode for a device\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ * @param fec\n+ * FEC structure which holds information to set\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n static __rte_always_inline int\n rte_pmd_bphy_cgx_set_fec(uint16_t dev_id, uint16_t lmac,\n \t\t\t enum cnxk_bphy_cgx_eth_link_fec fec)\n", "prefixes": [ "03/10" ] }