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GET /api/patches/112320/?format=api
{ "id": 112320, "url": "http://patchwork.dpdk.org/api/patches/112320/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220604162651.3503338-10-tduszynski@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220604162651.3503338-10-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220604162651.3503338-10-tduszynski@marvell.com", "date": "2022-06-04T16:26:50", "name": "[09/10] common/cnxk: sync eth mode change command with firmware", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "4acfdb609dae80e74b6d0b21dc7469d6decbea95", "submitter": { "id": 2215, "url": "http://patchwork.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220604162651.3503338-10-tduszynski@marvell.com/mbox/", "series": [ { "id": 23325, "url": "http://patchwork.dpdk.org/api/series/23325/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=23325", "date": "2022-06-04T16:26:41", "name": "Sync BPHY changes", "version": 1, "mbox": "http://patchwork.dpdk.org/series/23325/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/112320/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/112320/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 45E0CA034C;\n\tSat, 4 Jun 2022 18:27:54 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 282DD42B79;\n\tSat, 4 Jun 2022 18:27:42 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id B868842B76\n for <dev@dpdk.org>; Sat, 4 Jun 2022 18:27:40 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 254FrqRj032131;\n Sat, 4 Jun 2022 09:27:40 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3gg9ndg4hc-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Sat, 04 Jun 2022 09:27:39 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Sat, 4 Jun 2022 09:27:38 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sat, 4 Jun 2022 09:27:38 -0700", "from localhost.localdomain (unknown [10.28.34.39])\n by maili.marvell.com (Postfix) with ESMTP id AE2E33F70AB;\n Sat, 4 Jun 2022 09:27:35 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=VUtZ4VxKZVQoAK4fpZRoQc0ITnRteO8IkPr9jnMqwbU=;\n b=HbuXiKrd1nuXWIPzJkc9npz3Nq5PqYxvDSZa5SciAu5xpPGn/Tn2a8nxTVAxHbko2Urj\n AMvPgkID6C4ch4R8UouOC3Hnb1tCRMPmvkUrFPdzjMCl0/82S2Sfbx7KKpxcmK5ggWMB\n BjL20qOVU5lQU+e8iT9teqrecYMa5cmKAeqx4ITtklKcF2h8iECEXSKc/Fe1kNWB4Sua\n R8CoZKdw7c3Sdh9SXYo0syRVcM2h9XUf2/L6TqAYuXQOXSzRtZive22vpxeh4pn96DOy\n V0kVgeKLQvHdYDE66j1r9ploFWnzlxHBnWBADRywSDrtgWH73A/OnU7jowDCE7WTnH4X kg==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Jakub Palider <jpalider@marvell.com>, \"Tomasz\n Duszynski\" <tduszynski@marvell.com>", "CC": "<thomas@monjalon.net>, <jerinj@marvell.com>", "Subject": "[PATCH 09/10] common/cnxk: sync eth mode change command with firmware", "Date": "Sat, 4 Jun 2022 18:26:50 +0200", "Message-ID": "<20220604162651.3503338-10-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220604162651.3503338-1-tduszynski@marvell.com>", "References": "<20220604162651.3503338-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "inFZzCT0MH2QUQzKnT_INerRlCIhsQxw", "X-Proofpoint-GUID": "inFZzCT0MH2QUQzKnT_INerRlCIhsQxw", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514\n definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Layout of eth mode change command defined by firmware has been changed\nrecently. So in order to retain compatibility between ROC and firmware\nupdate existing codebase.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nReviewed-by: Jakub Palider <jpalider@marvell.com>\nReviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>\n---\n drivers/common/cnxk/roc_bphy_cgx.c | 11 +++++++--\n drivers/common/cnxk/roc_bphy_cgx.h | 19 +++++++++++++-\n drivers/common/cnxk/roc_bphy_cgx_priv.h | 12 +++++----\n drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 4 +++\n drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 33 +++++++++++++++++++++++++\n 5 files changed, 71 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c\nindex 4b62905164..a5df104088 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx.c\n+++ b/drivers/common/cnxk/roc_bphy_cgx.c\n@@ -367,8 +367,10 @@ roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n {\n \tuint64_t scr1, scr0;\n \n-\tif (roc_model_is_cn10k())\n+\tif (roc_model_is_cn9k() &&\n+\t (mode->use_portm_idx || mode->portm_idx || mode->mode_group_idx)) {\n \t\treturn -ENOTSUP;\n+\t}\n \n \tif (!roc_cgx)\n \t\treturn -EINVAL;\n@@ -383,7 +385,12 @@ roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n \t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |\n \t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) |\n \t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |\n-\t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) |\n+\t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_USE_PORTM_IDX,\n+\t\t\t mode->use_portm_idx) |\n+\t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORTM_IDX,\n+\t\t\t mode->portm_idx) |\n+\t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE_GROUP_IDX,\n+\t\t\t mode->mode_group_idx) |\n \t FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode));\n \n \treturn roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h\nindex 3b645eb130..4ce1316513 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx.h\n+++ b/drivers/common/cnxk/roc_bphy_cgx.h\n@@ -72,13 +72,30 @@ enum roc_bphy_cgx_eth_link_mode {\n \tROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,\n \tROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,\n \tROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2M_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_50GBASE_CR2_C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_50GBASE_KR2_C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2M_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_100GBASE_CR2_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_100GBASE_KR2_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_SFI_1G_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_25GBASE_CR_C_BIT,\n+\tROC_BPHY_CGX_ETH_LINK_MODE_25GBASE_KR_C_BIT,\n \t__ROC_BPHY_CGX_ETH_LINK_MODE_MAX\n };\n \n+enum roc_bphy_cgx_mode_group {\n+\tROC_BPHY_CGX_MODE_GROUP_ETH,\n+};\n+\n struct roc_bphy_cgx_link_mode {\n \tbool full_duplex;\n \tbool an;\n-\tunsigned int port;\n+\tbool use_portm_idx;\n+\tunsigned int portm_idx;\n+\tenum roc_bphy_cgx_mode_group mode_group_idx;\n \tenum roc_bphy_cgx_eth_link_speed speed;\n \tenum roc_bphy_cgx_eth_link_mode mode;\n };\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h\nindex c8c406439c..78fa1eaa6b 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h\n+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h\n@@ -74,11 +74,13 @@ enum eth_cmd_own {\n #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)\n \n /* struct eth_mode_change_args */\n-#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED\t GENMASK_ULL(11, 8)\n-#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)\n-#define SCR1_ETH_MODE_CHANGE_ARGS_AN\t BIT_ULL(13)\n-#define SCR1_ETH_MODE_CHANGE_ARGS_PORT\t GENMASK_ULL(21, 14)\n-#define SCR1_ETH_MODE_CHANGE_ARGS_MODE\t GENMASK_ULL(63, 22)\n+#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED GENMASK_ULL(11, 8)\n+#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)\n+#define SCR1_ETH_MODE_CHANGE_ARGS_AN\t BIT_ULL(13)\n+#define SCR1_ETH_MODE_CHANGE_ARGS_USE_PORTM_IDX BIT_ULL(14)\n+#define SCR1_ETH_MODE_CHANGE_ARGS_PORTM_IDX GENMASK_ULL(19, 15)\n+#define SCR1_ETH_MODE_CHANGE_ARGS_MODE_GROUP_IDX GENMASK_ULL(21, 20)\n+#define SCR1_ETH_MODE_CHANGE_ARGS_MODE\t GENMASK_ULL(63, 22)\n \n /* struct eth_set_fec_args */\n #define SCR1_ETH_SET_FEC_ARGS GENMASK_ULL(9, 8)\ndiff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\nindex de1c372334..f839a70f04 100644\n--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\n+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\n@@ -112,6 +112,10 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,\n \t\tmemset(&rlink_mode, 0, sizeof(rlink_mode));\n \t\trlink_mode.full_duplex = link_mode->full_duplex;\n \t\trlink_mode.an = link_mode->autoneg;\n+\t\trlink_mode.use_portm_idx = link_mode->use_portm_idx;\n+\t\trlink_mode.portm_idx = link_mode->portm_idx;\n+\t\trlink_mode.mode_group_idx =\n+\t\t\t(enum roc_bphy_cgx_mode_group)link_mode->mode_group_idx;\n \t\trlink_mode.speed =\n \t\t\t(enum roc_bphy_cgx_eth_link_speed)link_mode->speed;\n \t\trlink_mode.mode =\ndiff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\nindex 86e58e4756..7f326e3643 100644\n--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\n+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\n@@ -143,14 +143,47 @@ enum cnxk_bphy_cgx_eth_link_mode {\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,\n \t/** 100GBASE-KR4 */\n \tCNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,\n+\t/** 50GAUI-2-C2C */\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2C_BIT,\n+\t/** 50GAUI-2-C2M */\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_50GAUI_2_C2M_BIT,\n+\t/** 50GBASE-CR2-C */\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_50GBASE_CR2_C_BIT,\n+\t/** 50GBASE-KR2-C */\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_50GBASE_KR2_C_BIT,\n+\t/** 100GAUI-2-C2C */\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2C_BIT,\n+\t/** 100GAUI-2-C2M */\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_100GAUI_2_C2M_BIT,\n+\t/** 100GBASE-CR2 */\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_100GBASE_CR2_BIT,\n+\t/** 100GBASE-KR2 */\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_100GBASE_KR2_BIT,\n+\t/** SFI-1G */\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_SFI_1G_BIT,\n+\t/** 25GBASE-CR-C */\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_25GBASE_CR_C_BIT,\n+\t/** 25GBASE-KR-C */\n+\tCNXK_BPHY_CGX_ETH_LINK_MODE_25GBASE_KR_C_BIT,\n \t__CNXK_BPHY_CGX_ETH_LINK_MODE_MAX\n };\n \n+enum cnxk_bphy_cgx_mode_group {\n+\t/** ETH group */\n+\tCNXK_BPHY_CGX_MODE_GROUP_ETH,\n+};\n+\n struct cnxk_bphy_cgx_msg_link_mode {\n \t/** Setting for full-duplex */\n \tbool full_duplex;\n \t/** Setting for automatic link negotiation */\n \tbool autoneg;\n+\t/** Set to true to use port index */\n+\tbool use_portm_idx;\n+\t/** Port index */\n+\tunsigned int portm_idx;\n+\t/** Mode group */\n+\tenum cnxk_bphy_cgx_mode_group mode_group_idx;\n \t/** Link speed */\n \tenum cnxk_bphy_cgx_eth_link_speed speed;\n \t/** Link mode */\n", "prefixes": [ "09/10" ] }