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GET /api/patches/112323/?format=api
{ "id": 112323, "url": "http://patchwork.dpdk.org/api/patches/112323/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220604162651.3503338-7-tduszynski@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220604162651.3503338-7-tduszynski@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220604162651.3503338-7-tduszynski@marvell.com", "date": "2022-06-04T16:26:47", "name": "[06/10] raw/cnxk_bphy: support enabling TX for CPRI SERDES", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "7e97939578eabc5f370a56d2ee7be791eb24d911", "submitter": { "id": 2215, "url": "http://patchwork.dpdk.org/api/people/2215/?format=api", "name": "Tomasz Duszynski", "email": "tduszynski@marvell.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220604162651.3503338-7-tduszynski@marvell.com/mbox/", "series": [ { "id": 23325, "url": "http://patchwork.dpdk.org/api/series/23325/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=23325", "date": "2022-06-04T16:26:41", "name": "Sync BPHY changes", "version": 1, "mbox": "http://patchwork.dpdk.org/series/23325/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/112323/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/112323/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C06E9A034C;\n\tSat, 4 Jun 2022 18:29:35 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 631CA415D7;\n\tSat, 4 Jun 2022 18:29:35 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 5F3A8415D7\n for <dev@dpdk.org>; Sat, 4 Jun 2022 18:29:33 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 254GMx3o022379;\n Sat, 4 Jun 2022 09:27:30 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gg6wq0dh8-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Sat, 04 Jun 2022 09:27:30 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Sat, 4 Jun 2022 09:27:28 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sat, 4 Jun 2022 09:27:28 -0700", "from localhost.localdomain (unknown [10.28.34.39])\n by maili.marvell.com (Postfix) with ESMTP id D909C3F7097;\n Sat, 4 Jun 2022 09:27:25 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=zqHD4uf/nFhrewhNI0e/iMp2JzeHyf7rUoAAnn8rOYk=;\n b=AVmU4lUiAjDm5M3vOtmhnGThQ6Ri8jDHwa5UCcK/y6EYtN6r0YMAfkEX1GmI/r9XOCn7\n qvc6JRPljVGT+qWQ6JMjLou6j2xJsRCBsJb3ZW0sougNiI4NMLFRwyKW+rzVs1NB81i3\n 0rSEF4P20LbJOPgXAytWMvSo2cf1qAgca150O03HSNMDqkWp+ZB9o+A2N/MmjTnpb8uf\n Va1owl7DYtU/ifzkVfIAml9HTLr+/bauO2PXR4oLzqD6w0tnzaJe/9c3TRZODbWvb2//\n Yu9oilQTgky2I/WIrm/tcwbYbiaN5JtpW4lbWsbuXOlf734+B3ILnvMwtPaE1RJq7I2F IA==", "From": "Tomasz Duszynski <tduszynski@marvell.com>", "To": "<dev@dpdk.org>, Jakub Palider <jpalider@marvell.com>, Tomasz Duszynski\n <tduszynski@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>,\n \"Kiran Kumar K\" <kirankumark@marvell.com>,\n Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<thomas@monjalon.net>, <jerinj@marvell.com>", "Subject": "[PATCH 06/10] raw/cnxk_bphy: support enabling TX for CPRI SERDES", "Date": "Sat, 4 Jun 2022 18:26:47 +0200", "Message-ID": "<20220604162651.3503338-7-tduszynski@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220604162651.3503338-1-tduszynski@marvell.com>", "References": "<20220604162651.3503338-1-tduszynski@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "YRjzlJR8n7RwumgCkiF52kWToToe1Q5n", "X-Proofpoint-GUID": "YRjzlJR8n7RwumgCkiF52kWToToe1Q5n", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514\n definitions=2022-06-04_05,2022-06-03_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for enabling or disablig TX for SERDES\nconfigured in CPRI mode.\n\nSigned-off-by: Tomasz Duszynski <tduszynski@marvell.com>\nReviewed-by: Jakub Palider <jpalider@marvell.com>\nReviewed-by: Jerin Jacob Kollanukkaran <jerinj@marvell.com>\n---\n doc/guides/rawdevs/cnxk_bphy.rst | 10 +++++++\n drivers/common/cnxk/roc_bphy_cgx.c | 31 +++++++++++++++++++++\n drivers/common/cnxk/roc_bphy_cgx.h | 8 ++++++\n drivers/common/cnxk/roc_bphy_cgx_priv.h | 6 +++++\n drivers/common/cnxk/version.map | 1 +\n drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 11 ++++++++\n drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 36 +++++++++++++++++++++++++\n 7 files changed, 103 insertions(+)", "diff": "diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst\nindex 7f55e9eac6..50ee9bdaa6 100644\n--- a/doc/guides/rawdevs/cnxk_bphy.rst\n+++ b/doc/guides/rawdevs/cnxk_bphy.rst\n@@ -111,6 +111,16 @@ Prior to sending actual message payload i.e\n ``struct cnxk_bphy_cgx_msg_cpri_mode_change`` needs to be filled with relevant\n information.\n \n+Enable TX for CPRI SERDES\n+~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+Message is used to enable TX for SERDES configured in CPRI mode.\n+\n+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL``.\n+Prior to sending actual message payload i.e\n+``struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl`` needs to be filled with relevant\n+information.\n+\n BPHY PMD\n --------\n \ndiff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c\nindex 223bd313fa..ee0198924e 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx.c\n+++ b/drivers/common/cnxk/roc_bphy_cgx.c\n@@ -488,3 +488,34 @@ roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n \n \treturn roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);\n }\n+\n+int\n+roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx,\n+\t\t\t\t unsigned int lmac,\n+\t\t\t\t struct roc_bphy_cgx_cpri_mode_tx_ctrl *mode)\n+{\n+\tuint64_t scr1, scr0;\n+\n+\tif (!(roc_model_is_cnf95xxn_a0() ||\n+\t roc_model_is_cnf95xxn_a1() ||\n+\t roc_model_is_cnf95xxn_b0()))\n+\t\treturn -ENOTSUP;\n+\n+\tif (!roc_cgx)\n+\t\treturn -EINVAL;\n+\n+\tif (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))\n+\t\treturn -ENODEV;\n+\n+\tif (!mode)\n+\t\treturn -EINVAL;\n+\n+\tscr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_CPRI_TX_CONTROL) |\n+\t FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_GSERC_IDX,\n+\t\t\t mode->gserc_idx) |\n+\t FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX,\n+\t\t\t mode->lane_idx) |\n+\t FIELD_PREP(SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE, mode->enable);\n+\n+\treturn roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);\n+}\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h\nindex 59adddd420..b8023cce88 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx.h\n+++ b/drivers/common/cnxk/roc_bphy_cgx.h\n@@ -100,6 +100,12 @@ struct roc_bphy_cgx_cpri_mode_change {\n \tbool disable_dfe;\n };\n \n+struct roc_bphy_cgx_cpri_mode_tx_ctrl {\n+\tint gserc_idx;\n+\tint lane_idx;\n+\tbool enable;\n+};\n+\n __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);\n __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);\n \n@@ -130,5 +136,7 @@ __roc_api int roc_bphy_cgx_fec_supported_get(struct roc_bphy_cgx *roc_cgx, unsig\n \t\t\t\t\t enum roc_bphy_cgx_eth_link_fec *fec);\n __roc_api int roc_bphy_cgx_cpri_mode_change(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n \t\t\t\t\t struct roc_bphy_cgx_cpri_mode_change *mode);\n+__roc_api int roc_bphy_cgx_cpri_mode_tx_control(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,\n+\t\t\t\t\t\tstruct roc_bphy_cgx_cpri_mode_tx_ctrl *mode);\n \n #endif /* _ROC_BPHY_CGX_H_ */\ndiff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h\nindex cdd94989c8..96db34f6a1 100644\n--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h\n+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h\n@@ -70,6 +70,7 @@ enum eth_cmd_id {\n \tETH_CMD_SET_FEC = 19,\n \tETH_CMD_SET_PTP_MODE = 34,\n \tETH_CMD_CPRI_MODE_CHANGE = 35,\n+\tETH_CMD_CPRI_TX_CONTROL = 36,\n };\n \n /* event types - cause of interrupt */\n@@ -141,6 +142,11 @@ enum eth_cmd_own {\n #define SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_LEQ BIT_ULL(32)\n #define SCR1_CPRI_MODE_CHANGE_ARGS_DISABLE_DFE BIT_ULL(33)\n \n+/* struct cpri_mode_tx_ctrl_args */\n+#define SCR1_CPRI_MODE_TX_CTRL_ARGS_GSERC_IDX GENMASK_ULL(11, 8)\n+#define SCR1_CPRI_MODE_TX_CTRL_ARGS_LANE_IDX GENMASK_ULL(15, 12)\n+#define SCR1_CPRI_MODE_TX_CTRL_ARGS_ENABLE BIT_ULL(16)\n+\n #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)\n \n #endif /* _ROC_BPHY_CGX_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 720cad61ea..a6183799a9 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -29,6 +29,7 @@ INTERNAL {\n \troc_ae_fpm_put;\n \troc_aes_xcbc_key_derive;\n \troc_bphy_cgx_cpri_mode_change;\n+\troc_bphy_cgx_cpri_mode_tx_control;\n \troc_bphy_cgx_dev_fini;\n \troc_bphy_cgx_dev_init;\n \troc_bphy_cgx_fec_set;\ndiff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\nindex 803b245c78..bdc65a7f2a 100644\n--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\n+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c\n@@ -58,10 +58,12 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,\n \tstruct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue];\n \tstruct cnxk_bphy_cgx_msg_cpri_mode_change *cpri_mode;\n \tstruct cnxk_bphy_cgx_msg_set_link_state *link_state;\n+\tstruct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *tx_ctrl;\n \tstruct cnxk_bphy_cgx_msg *msg = buf->buf_addr;\n \tstruct cnxk_bphy_cgx_msg_link_mode *link_mode;\n \tstruct cnxk_bphy_cgx_msg_link_info *link_info;\n \tstruct roc_bphy_cgx_cpri_mode_change rcpri_mode;\n+\tstruct roc_bphy_cgx_cpri_mode_tx_ctrl rtx_ctrl;\n \tstruct roc_bphy_cgx_link_info rlink_info;\n \tstruct roc_bphy_cgx_link_mode rlink_mode;\n \tenum roc_bphy_cgx_eth_link_fec *fec;\n@@ -148,6 +150,15 @@ cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,\n \t\tret = roc_bphy_cgx_cpri_mode_change(cgx->rcgx, lmac,\n \t\t\t\t\t\t &rcpri_mode);\n \t\tbreak;\n+\tcase CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL:\n+\t\ttx_ctrl = msg->data;\n+\t\tmemset(&rtx_ctrl, 0, sizeof(rtx_ctrl));\n+\t\trtx_ctrl.gserc_idx = tx_ctrl->gserc_idx;\n+\t\trtx_ctrl.lane_idx = tx_ctrl->lane_idx;\n+\t\trtx_ctrl.enable = tx_ctrl->enable;\n+\t\tret = roc_bphy_cgx_cpri_mode_tx_control(cgx->rcgx, lmac,\n+\t\t\t\t\t\t\t&rtx_ctrl);\n+\t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\n \t}\ndiff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\nindex 36b75aa385..79bb2233bc 100644\n--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\n+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h\n@@ -52,6 +52,8 @@ enum cnxk_bphy_cgx_msg_type {\n \tCNXK_BPHY_CGX_MSG_TYPE_SET_FEC,\n \t/** Type used to switch from eCPRI to CPRI */\n \tCNXK_BPHY_CGX_MSG_TYPE_CPRI_MODE_CHANGE,\n+\t/** Type used to enable TX for CPRI SERDES */\n+\tCNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL,\n };\n \n /** Available link speeds */\n@@ -186,6 +188,15 @@ struct cnxk_bphy_cgx_msg_cpri_mode_change {\n \tbool disable_dfe;\n };\n \n+struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl {\n+\t/** SERDES index (0 - 4) */\n+\tint gserc_idx;\n+\t/** Lane index (0 - 1) */\n+\tint lane_idx;\n+\t/** Disable or enable SERDES */\n+\tbool enable;\n+};\n+\n struct cnxk_bphy_cgx_msg {\n \t/** Message type */\n \tenum cnxk_bphy_cgx_msg_type type;\n@@ -734,6 +745,31 @@ rte_pmd_bphy_cgx_cpri_mode_change(uint16_t dev_id, uint16_t lmac,\n \treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);\n }\n \n+/**\n+ * Enable TX for SERDES configured in CPRI mode\n+ *\n+ * @param dev_id\n+ * The identifier of the device\n+ * @param lmac\n+ * LMAC number for operation\n+ * @param mode\n+ * CPRI TX control structure holding control data\n+ *\n+ * @return\n+ * Returns 0 on success, negative error code otherwise\n+ */\n+static __rte_always_inline int\n+rte_pmd_bphy_cgx_cpri_tx_control(uint16_t dev_id, uint16_t lmac,\n+\t\t\t\t struct cnxk_bphy_cgx_msg_cpri_mode_tx_ctrl *mode)\n+{\n+\tstruct cnxk_bphy_cgx_msg msg = {\n+\t\t.type = CNXK_BPHY_CGX_MSG_TYPE_CPRI_TX_CONTROL,\n+\t\t.data = mode,\n+\t};\n+\n+\treturn __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);\n+}\n+\n #ifdef __cplusplus\n }\n #endif\n", "prefixes": [ "06/10" ] }