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GET /api/patches/112777/?format=api
{ "id": 112777, "url": "http://patchwork.dpdk.org/api/patches/112777/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220615144341.399152-5-spiked@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220615144341.399152-5-spiked@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220615144341.399152-5-spiked@nvidia.com", "date": "2022-06-15T14:43:39", "name": "[v9,4/6] net/mlx5: support Rx queue based available descriptor threshold", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "20b3c36ed01e616fcc181a47662bd98e09fffc72", "submitter": { "id": 2637, "url": "http://patchwork.dpdk.org/api/people/2637/?format=api", "name": "Spike Du", "email": "spiked@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220615144341.399152-5-spiked@nvidia.com/mbox/", "series": [ { "id": 23541, "url": "http://patchwork.dpdk.org/api/series/23541/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=23541", "date": "2022-06-15T14:43:36", "name": "introduce per-queue available descriptor threshold and host shaper", "version": 9, "mbox": "http://patchwork.dpdk.org/series/23541/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/112777/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/112777/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8ECC9A0548;\n\tWed, 15 Jun 2022 16:44:36 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6F6BC42B95;\n\tWed, 15 Jun 2022 16:44:17 +0200 (CEST)", "from NAM02-BN1-obe.outbound.protection.outlook.com\n (mail-bn1nam07on2064.outbound.protection.outlook.com [40.107.212.64])\n by mails.dpdk.org (Postfix) with ESMTP id 79C3C42B8E\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Spike Du <spiked@nvidia.com>", "To": "<matan@nvidia.com>, <viacheslavo@nvidia.com>, <orika@nvidia.com>,\n <thomas@monjalon.net>, Shahaf Shuler <shahafs@nvidia.com>", "CC": "<andrew.rybchenko@oktetlabs.ru>, <stephen@networkplumber.org>,\n <mb@smartsharesystems.com>, <dev@dpdk.org>, <rasland@nvidia.com>", "Subject": "[PATCH v9 4/6] net/mlx5: support Rx queue based available descriptor\n threshold", "Date": "Wed, 15 Jun 2022 17:43:39 +0300", "Message-ID": "<20220615144341.399152-5-spiked@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20220615144341.399152-1-spiked@nvidia.com>", "References": "<20220615125836.391771-2-spiked@nvidia.com>\n <20220615144341.399152-1-spiked@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "3662084c-b6c7-4df4-e8e2-08da4edd8376", "X-MS-TrafficTypeDiagnostic": "BL0PR12MB2354:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BL0PR12MB2354DED6579E7D3D61C7E99BA8AD9@BL0PR12MB2354.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n tVJhzQ7wCblIxVh6cgImdU7a1dohi/X5OVJtHHagfx2LNNzEkCoO2HRp4y0E88fGl1gnGg5oeCg1O7dHiqqcPKsXIh8NbICk2Z1G6XV2V+48XOrWJtc9cq802NzyBMFXIKD0ciZrau5YEa77BJh7qdxk6eT0Kp/WxGLPJovUYB9UssmkJp8NXy8c/OJP93Jm6ezfThxoWM9YTpm/fajo9mccXHPN15UznmnoRmKPy297G78wwNO5/Aiu7wPtMfw74YsiQOZMRalqB/g0KGtXJCOO6RSmJyidU15zW0JQkILmAUntoA/Ci7lY7LC0yYD8dK/9WGbDMUXoCP0SV+rjrFA+kSf2KIkOn/lump6kA3kdliPmPDEBmYQxlNMq8Hdwo6NVGEO5v13ah4IjkgGem/derMVBB/5+Zta292H7LZJrT7CDeC95ddTw43iNBrv8WoNY0hVvJ23b6aLYzMB5FmNtmWYrGcm5LwmNuCH9peR+QXFWhjyuqrDpea4Myq5fEAZBFe5xQwBDzC8ekyMV8ExNSuhCSs1GJ1DIRQjo2D3/z5Y4I9EA2UwK7jq4E2+UATt8xCynndHLrDGONqfNdstzgw5TTMDTAuRbGQntVV0ZdM0UKGv5ZBueO6ciiYeohNP9qX2uk4/X8O4LMw2d5JeHhLT3rxSqj4fFo1ToZgU89484RILJdw5eNwnUC4TmyA2cwD03NQlY/UonMYf6oQ==", "X-Forefront-Antispam-Report": "CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230016)(4636009)(46966006)(36840700001)(40470700004)(356005)(70206006)(70586007)(4326008)(8676002)(86362001)(54906003)(81166007)(508600001)(6636002)(316002)(426003)(47076005)(36860700001)(2616005)(336012)(16526019)(107886003)(186003)(36756003)(7696005)(26005)(83380400001)(6666004)(6286002)(55016003)(2906002)(40460700003)(8936002)(110136005)(1076003)(5660300002)(82310400005)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Jun 2022 14:44:12.4974 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3662084c-b6c7-4df4-e8e2-08da4edd8376", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT029.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL0PR12MB2354", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add mlx5 specific available descriptor threshold configuration\nand query handler.\nIn mlx5 PMD, available descriptor threshold is also called\nLWM(limit watermark).\nWhile the Rx queue fullness reaches the LWM limit, the driver catches\nan HW event and invokes the user callback.\nThe query handler finds the next RX queue with pending LWM event\nif any, starting from the given RX queue index.\n\nSigned-off-by: Spike Du <spiked@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 12 +++\n doc/guides/rel_notes/release_22_07.rst | 1 +\n drivers/common/mlx5/mlx5_prm.h | 1 +\n drivers/net/mlx5/mlx5.c | 2 +\n drivers/net/mlx5/mlx5_rx.c | 151 +++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_rx.h | 5 ++\n 6 files changed, 172 insertions(+)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex d83c56d..cceaddf 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -93,6 +93,7 @@ Features\n - Connection tracking.\n - Sub-Function representors.\n - Sub-Function.\n+- Rx queue available descriptor threshold configuration.\n \n \n Limitations\n@@ -520,6 +521,9 @@ Limitations\n \n - The NIC egress flow rules on representor port are not supported.\n \n+- Available descriptor threshold:\n+\n+ - Doesn't support shared Rx queue and Hairpin Rx queue.\n \n Statistics\n ----------\n@@ -1680,3 +1684,11 @@ The procedure below is an example of using a ConnectX-5 adapter card (pf0) with\n #. For each VF PCIe, using the following command to bind the driver::\n \n $ echo \"0000:82:00.2\" >> /sys/bus/pci/drivers/mlx5_core/bind\n+\n+Available descriptor threshold introduction\n+-------------------------------------------\n+\n+Available descriptor threshold is a per Rx queue attribute, it should be configured as\n+a percentage of the Rx queue size.\n+When Rx queue available descriptors for hardware are below the threshold, an event is sent to PMD.\n+\ndiff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst\nindex 6fc044e..7fb98cd 100644\n--- a/doc/guides/rel_notes/release_22_07.rst\n+++ b/doc/guides/rel_notes/release_22_07.rst\n@@ -151,6 +151,7 @@ New Features\n * Added support for promiscuous mode on Windows.\n * Added support for MTU on Windows.\n * Added matching and RSS on IPsec ESP.\n+ * Added Rx queue available descriptor threshold support.\n \n * **Updated VMware vmxnet3 networking driver.**\n \ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 654e5f4..7c4030a 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3294,6 +3294,7 @@ struct mlx5_aso_wqe {\n \n enum {\n \tMLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,\n+\tMLX5_EVENT_TYPE_SRQ_LIMIT_REACHED = 0x14,\n };\n \n enum {\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex e04a666..998846a 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -2071,6 +2071,8 @@ struct mlx5_dev_ctx_shared *\n \t.dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,\n \t.vlan_filter_set = mlx5_vlan_filter_set,\n \t.rx_queue_setup = mlx5_rx_queue_setup,\n+\t.rx_queue_avail_thresh_set = mlx5_rx_queue_lwm_set,\n+\t.rx_queue_avail_thresh_query = mlx5_rx_queue_lwm_query,\n \t.rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,\n \t.tx_queue_setup = mlx5_tx_queue_setup,\n \t.tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,\ndiff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c\nindex 197d708..2cb7006 100644\n--- a/drivers/net/mlx5/mlx5_rx.c\n+++ b/drivers/net/mlx5/mlx5_rx.c\n@@ -25,6 +25,7 @@\n #include \"mlx5.h\"\n #include \"mlx5_utils.h\"\n #include \"mlx5_rxtx.h\"\n+#include \"mlx5_devx.h\"\n #include \"mlx5_rx.h\"\n \n \n@@ -128,6 +129,16 @@\n \treturn RTE_ETH_RX_DESC_AVAIL;\n }\n \n+/* Get rxq lwm percentage according to lwm number. */\n+static uint8_t\n+mlx5_rxq_lwm_to_percentage(struct mlx5_rxq_priv *rxq)\n+{\n+\tstruct mlx5_rxq_data *rxq_data = &rxq->ctrl->rxq;\n+\tuint32_t wqe_cnt = 1 << (rxq_data->elts_n - rxq_data->sges_n);\n+\n+\treturn rxq->lwm * 100 / wqe_cnt;\n+}\n+\n /**\n * DPDK callback to get the RX queue information.\n *\n@@ -150,6 +161,7 @@\n {\n \tstruct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, rx_queue_id);\n \tstruct mlx5_rxq_data *rxq = mlx5_rxq_data_get(dev, rx_queue_id);\n+\tstruct mlx5_rxq_priv *rxq_priv = mlx5_rxq_get(dev, rx_queue_id);\n \n \tif (!rxq)\n \t\treturn;\n@@ -169,6 +181,8 @@\n \tqinfo->nb_desc = mlx5_rxq_mprq_enabled(rxq) ?\n \t\tRTE_BIT32(rxq->elts_n) * RTE_BIT32(rxq->log_strd_num) :\n \t\tRTE_BIT32(rxq->elts_n);\n+\tqinfo->avail_thresh = rxq_priv ?\n+\t\tmlx5_rxq_lwm_to_percentage(rxq_priv) : 0;\n }\n \n /**\n@@ -1188,6 +1202,34 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)\n \treturn -ENOTSUP;\n }\n \n+int\n+mlx5_rx_queue_lwm_query(struct rte_eth_dev *dev,\n+\t\t\tuint16_t *queue_id, uint8_t *lwm)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tunsigned int rxq_id, found = 0, n;\n+\tstruct mlx5_rxq_priv *rxq;\n+\n+\tif (!queue_id)\n+\t\treturn -EINVAL;\n+\t/* Query all the Rx queues of the port in a circular way. */\n+\tfor (rxq_id = *queue_id, n = 0; n < priv->rxqs_n; n++) {\n+\t\trxq = mlx5_rxq_get(dev, rxq_id);\n+\t\tif (rxq && rxq->lwm_event_pending) {\n+\t\t\tpthread_mutex_lock(&priv->sh->lwm_config_lock);\n+\t\t\trxq->lwm_event_pending = 0;\n+\t\t\tpthread_mutex_unlock(&priv->sh->lwm_config_lock);\n+\t\t\t*queue_id = rxq_id;\n+\t\t\tfound = 1;\n+\t\t\tif (lwm)\n+\t\t\t\t*lwm = mlx5_rxq_lwm_to_percentage(rxq);\n+\t\t\tbreak;\n+\t\t}\n+\t\trxq_id = (rxq_id + 1) % priv->rxqs_n;\n+\t}\n+\treturn found;\n+}\n+\n /**\n * Rte interrupt handler for LWM event.\n * It first checks if the event arrives, if so process the callback for\n@@ -1220,3 +1262,112 @@ int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)\n \t}\n \trte_eth_dev_callback_process(dev, RTE_ETH_EVENT_RX_AVAIL_THRESH, NULL);\n }\n+\n+/**\n+ * DPDK callback to arm an Rx queue LWM(limit watermark) event.\n+ * While the Rx queue fullness reaches the LWM limit, the driver catches\n+ * an HW event and invokes the user event callback.\n+ * After the last event handling, the user needs to call this API again\n+ * to arm an additional event.\n+ *\n+ * @param dev\n+ * Pointer to the device structure.\n+ * @param[in] rx_queue_id\n+ * Rx queue identificator.\n+ * @param[in] lwm\n+ * The LWM value, is defined by a percentage of the Rx queue size.\n+ * [1-99] to set a new LWM (update the old value).\n+ * 0 to unarm the event.\n+ *\n+ * @return\n+ * 0 : operation success.\n+ * Otherwise:\n+ * - ENOMEM - not enough memory to create LWM event channel.\n+ * - EINVAL - the input Rxq is not created by devx.\n+ * - E2BIG - lwm is bigger than 99.\n+ */\n+int\n+mlx5_rx_queue_lwm_set(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n+\t\t uint8_t lwm)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tuint16_t port_id = PORT_ID(priv);\n+\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, rx_queue_id);\n+\tuint16_t event_nums[1] = {MLX5_EVENT_TYPE_SRQ_LIMIT_REACHED};\n+\tstruct mlx5_rxq_data *rxq_data;\n+\tuint32_t wqe_cnt;\n+\tuint64_t cookie;\n+\tint ret = 0;\n+\n+\tif (!rxq) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\trxq_data = &rxq->ctrl->rxq;\n+\t/* Ensure the Rq is created by devx. */\n+\tif (priv->obj_ops.rxq_obj_new != devx_obj_ops.rxq_obj_new) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\tif (lwm > 99) {\n+\t\tDRV_LOG(WARNING, \"Too big LWM configuration.\");\n+\t\trte_errno = E2BIG;\n+\t\treturn -rte_errno;\n+\t}\n+\t/* Start config LWM. */\n+\tpthread_mutex_lock(&priv->sh->lwm_config_lock);\n+\tif (rxq->lwm == 0 && lwm == 0) {\n+\t\t/* Both old/new values are 0, do nothing. */\n+\t\tret = 0;\n+\t\tgoto end;\n+\t}\n+\twqe_cnt = 1 << (rxq_data->elts_n - rxq_data->sges_n);\n+\tif (lwm) {\n+\t\tif (!priv->sh->devx_channel_lwm) {\n+\t\t\tret = mlx5_lwm_setup(priv);\n+\t\t\tif (ret) {\n+\t\t\t\tDRV_LOG(WARNING,\n+\t\t\t\t\t\"Failed to create shared_lwm.\");\n+\t\t\t\trte_errno = ENOMEM;\n+\t\t\t\tret = -rte_errno;\n+\t\t\t\tgoto end;\n+\t\t\t}\n+\t\t}\n+\t\tif (!rxq->lwm_devx_subscribed) {\n+\t\t\tcookie = ((uint32_t)\n+\t\t\t\t (port_id << LWM_COOKIE_PORTID_OFFSET)) |\n+\t\t\t\t(rx_queue_id << LWM_COOKIE_RXQID_OFFSET);\n+\t\t\tret = mlx5_os_devx_subscribe_devx_event\n+\t\t\t\t(priv->sh->devx_channel_lwm,\n+\t\t\t\t rxq->devx_rq.rq->obj,\n+\t\t\t\t sizeof(event_nums),\n+\t\t\t\t event_nums,\n+\t\t\t\t cookie);\n+\t\t\tif (ret) {\n+\t\t\t\trte_errno = rte_errno ? rte_errno : EINVAL;\n+\t\t\t\tret = -rte_errno;\n+\t\t\t\tgoto end;\n+\t\t\t}\n+\t\t\trxq->lwm_devx_subscribed = 1;\n+\t\t}\n+\t}\n+\t/* Save LWM to rxq and send modify_rq devx command. */\n+\trxq->lwm = lwm * wqe_cnt / 100;\n+\t/* Prevent integer division loss when switch lwm number to percentage. */\n+\tif (lwm && (lwm * wqe_cnt % 100)) {\n+\t\trxq->lwm = ((uint32_t)(rxq->lwm + 1) >= wqe_cnt) ?\n+\t\t\trxq->lwm : (rxq->lwm + 1);\n+\t}\n+\tif (lwm && !rxq->lwm) {\n+\t\t/* With mprq, wqe_cnt may be < 100. */\n+\t\tDRV_LOG(WARNING, \"Too small LWM configuration.\");\n+\t\trte_errno = EINVAL;\n+\t\tret = -rte_errno;\n+\t\tgoto end;\n+\t}\n+\tret = mlx5_devx_modify_rq(rxq, MLX5_RXQ_MOD_RDY2RDY);\n+end:\n+\tpthread_mutex_unlock(&priv->sh->lwm_config_lock);\n+\treturn ret;\n+}\n+\ndiff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex 068dff5..e078aaf 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -177,6 +177,7 @@ struct mlx5_rxq_priv {\n \tuint32_t hairpin_status; /* Hairpin binding status. */\n \tuint32_t lwm:16;\n \tuint32_t lwm_event_pending:1;\n+\tuint32_t lwm_devx_subscribed:1;\n };\n \n /* External RX queue descriptor. */\n@@ -297,6 +298,10 @@ int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n \t\t\t struct rte_eth_burst_mode *mode);\n int mlx5_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);\n void mlx5_dev_interrupt_handler_lwm(void *args);\n+int mlx5_rx_queue_lwm_set(struct rte_eth_dev *dev, uint16_t rx_queue_id,\n+\t\t\t uint8_t lwm);\n+int mlx5_rx_queue_lwm_query(struct rte_eth_dev *dev, uint16_t *rx_queue_id,\n+\t\t\t uint8_t *lwm);\n \n /* Vectorized version of mlx5_rx.c */\n int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);\n", "prefixes": [ "v9", "4/6" ] }