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GET /api/patches/112839/?format=api
{ "id": 112839, "url": "http://patchwork.dpdk.org/api/patches/112839/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220616070743.30658-10-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220616070743.30658-10-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220616070743.30658-10-ndabilpuram@marvell.com", "date": "2022-06-16T07:07:41", "name": "[10/12] net/cnxk: resize CQ for Rx security for errata", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "bd2af4795ba0e06866d3f00d6f9c43deb6c18ee3", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220616070743.30658-10-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 23552, "url": "http://patchwork.dpdk.org/api/series/23552/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=23552", "date": "2022-06-16T07:07:32", "name": "[01/12] common/cnxk: use computed value for wqe skip", "version": 1, "mbox": "http://patchwork.dpdk.org/series/23552/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/112839/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/112839/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6D39FA00C3;\n\tThu, 16 Jun 2022 09:10:04 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EA73442BD8;\n\tThu, 16 Jun 2022 09:10:01 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id D6F0742BE3\n for <dev@dpdk.org>; Thu, 16 Jun 2022 09:10:00 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 25G2AMlr013083\n for <dev@dpdk.org>; Thu, 16 Jun 2022 00:10:00 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gq83yx51q-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 16 Jun 2022 00:10:00 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 16 Jun 2022 00:09:58 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 16 Jun 2022 00:09:58 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 1D5433F709B;\n Thu, 16 Jun 2022 00:09:55 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=J3cRSMPOaNN1/Ji955//zFMxfYhgoBVhEULJvhEFKTg=;\n b=R/81Vou+ZsptMajs+2575lKwM/5MzncLbtVa46opv9HtKyHHahJk92LOPdkWd8H55ZgP\n KF8rU9xfEuQ5mNpHr17/ix6mXh2Zb/eFask2ULMKyjCr4W1msdjHLQ07/kpOO2qgAP84\n qA4a6SnDhU2ijYhYjdW+AHhxVZT07vp1S94AFr2WK7Kpr8mKhIpfVQAGLhU0mUYrhJEd\n qjblwk0sKTlvO3UPDIi8AfI4T9ZKFkL0Y9aPBZWpkzgq4i/0/qR0cNbSSctC2n8+wzSU\n y8mmo141b+Sby1ykfZ7+AZ/7AS+RDHtUwsfy2fEyScyInrgkzyB32Vwla1+02qFDAMxz yw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 10/12] net/cnxk: resize CQ for Rx security for errata", "Date": "Thu, 16 Jun 2022 12:37:41 +0530", "Message-ID": "<20220616070743.30658-10-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220616070743.30658-1-ndabilpuram@marvell.com>", "References": "<20220616070743.30658-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "CjgoRxai79ob7d-M7WnNHc76g-rgXozJ", "X-Proofpoint-GUID": "CjgoRxai79ob7d-M7WnNHc76g-rgXozJ", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514\n definitions=2022-06-16_03,2022-06-15_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Resize CQ for Rx security offload in case of HW errata.\n\nci: skip_checkpatch skip_klocwork\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/net/cnxk/cnxk_ethdev.c | 43 +++++++++++++++++++++++++++++++++++++++++-\n drivers/net/cnxk/cnxk_ethdev.h | 2 +-\n 2 files changed, 43 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 4ea1617..2418290 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -5,6 +5,8 @@\n \n #include <rte_eventdev.h>\n \n+#define CNXK_NIX_CQ_INL_CLAMP_MAX (64UL * 1024UL)\n+\n static inline uint64_t\n nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)\n {\n@@ -40,6 +42,39 @@ nix_get_speed_capa(struct cnxk_eth_dev *dev)\n \treturn speed_capa;\n }\n \n+static uint32_t\n+nix_inl_cq_sz_clamp_up(struct roc_nix *nix, struct rte_mempool *mp,\n+\t\t uint32_t nb_desc)\n+{\n+\tstruct roc_nix_rq *inl_rq;\n+\tuint64_t limit;\n+\n+\tif (!roc_errata_cpt_hang_on_x2p_bp())\n+\t\treturn nb_desc;\n+\n+\t/* CQ should be able to hold all buffers in first pass RQ's aura\n+\t * this RQ's aura.\n+\t */\n+\tinl_rq = roc_nix_inl_dev_rq(nix);\n+\tif (!inl_rq) {\n+\t\t/* This itself is going to be inline RQ's aura */\n+\t\tlimit = roc_npa_aura_op_limit_get(mp->pool_id);\n+\t} else {\n+\t\tlimit = roc_npa_aura_op_limit_get(inl_rq->aura_handle);\n+\t\t/* Also add this RQ's aura if it is different */\n+\t\tif (inl_rq->aura_handle != mp->pool_id)\n+\t\t\tlimit += roc_npa_aura_op_limit_get(mp->pool_id);\n+\t}\n+\tnb_desc = PLT_MAX(limit + 1, nb_desc);\n+\tif (nb_desc > CNXK_NIX_CQ_INL_CLAMP_MAX) {\n+\t\tplt_warn(\"Could not setup CQ size to accommodate\"\n+\t\t\t \" all buffers in related auras (%\" PRIu64 \")\",\n+\t\t\t limit);\n+\t\tnb_desc = CNXK_NIX_CQ_INL_CLAMP_MAX;\n+\t}\n+\treturn nb_desc;\n+}\n+\n int\n cnxk_nix_inb_mode_set(struct cnxk_eth_dev *dev, bool use_inl_dev)\n {\n@@ -504,7 +539,7 @@ cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)\n \n int\n cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n-\t\t\tuint16_t nb_desc, uint16_t fp_rx_q_sz,\n+\t\t\tuint32_t nb_desc, uint16_t fp_rx_q_sz,\n \t\t\tconst struct rte_eth_rxconf *rx_conf,\n \t\t\tstruct rte_mempool *mp)\n {\n@@ -552,6 +587,12 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)\n \t\troc_nix_inl_dev_xaq_realloc(mp->pool_id);\n \n+\t/* Increase CQ size to Aura size to avoid CQ overflow and\n+\t * then CPT buffer leak.\n+\t */\n+\tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)\n+\t\tnb_desc = nix_inl_cq_sz_clamp_up(nix, mp, nb_desc);\n+\n \t/* Setup ROC CQ */\n \tcq = &dev->cqs[qid];\n \tcq->qid = qid;\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex a4e96f0..4cb7c9e 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -530,7 +530,7 @@ int cnxk_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\t\t uint16_t nb_desc, uint16_t fp_tx_q_sz,\n \t\t\t const struct rte_eth_txconf *tx_conf);\n int cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n-\t\t\t uint16_t nb_desc, uint16_t fp_rx_q_sz,\n+\t\t\t uint32_t nb_desc, uint16_t fp_rx_q_sz,\n \t\t\t const struct rte_eth_rxconf *rx_conf,\n \t\t\t struct rte_mempool *mp);\n int cnxk_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qid);\n", "prefixes": [ "10/12" ] }