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GET /api/patches/112968/?format=api
{ "id": 112968, "url": "http://patchwork.dpdk.org/api/patches/112968/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220617073604.889403-4-ktejasree@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220617073604.889403-4-ktejasree@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220617073604.889403-4-ktejasree@marvell.com", "date": "2022-06-17T07:36:03", "name": "[3/4] crypto/cnxk: support scatter gather mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "14c216b210f11f081004f48c0c86875ef1f0e519", "submitter": { "id": 1789, "url": "http://patchwork.dpdk.org/api/people/1789/?format=api", "name": "Tejasree Kondoj", "email": "ktejasree@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220617073604.889403-4-ktejasree@marvell.com/mbox/", "series": [ { "id": 23602, "url": "http://patchwork.dpdk.org/api/series/23602/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=23602", "date": "2022-06-17T07:36:00", "name": "support stream cipher chained operations", "version": 1, "mbox": "http://patchwork.dpdk.org/series/23602/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/112968/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/112968/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 89ACBA0093;\n\tFri, 17 Jun 2022 09:36:37 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AE4A74281C;\n\tFri, 17 Jun 2022 09:36:19 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 9400842905\n for <dev@dpdk.org>; Fri, 17 Jun 2022 09:36:16 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 25H3kwvC022796\n for <dev@dpdk.org>; Fri, 17 Jun 2022 00:36:16 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3grj05rrrb-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 17 Jun 2022 00:36:15 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Fri, 17 Jun 2022 00:36:13 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 17 Jun 2022 00:36:13 -0700", "from hyd1554.marvell.com (unknown [10.29.57.11])\n by maili.marvell.com (Postfix) with ESMTP id 3D85B3F7051;\n Fri, 17 Jun 2022 00:36:12 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=ZXOnC/RUQf3VW+XAI8PhTHD5xBY6XiKintcEPTeq0oM=;\n b=WJn/eJiw9THxS4ybYgrlkLiK7E4MmrI8IT5Y/EireCKut8cqDYBZU31kJrDaSjZ07at+\n JaUsp8rvH2rkRAFu7H3HBwlw/emICEzWBauG8Z/qYc1E0qxU30anzojXnhYOwVPS7j67\n BuQZEgbAVVw0pdcLIGlM85KS09U/bICs5z0W+AomwUMPmJwO5HCrtc/EAIx4Jb/ddcOB\n 0LIHKFTiJyGbmNlH9sfSgTzb+qQlIwM4VAODveXFb0E/kj80CQbcT/WJA9X7R+ZW7aRO\n 6bqjgHR0NVtTr4Xx5CwPwZytDxl3bTr/kcih6VRVE7bfi4omPX6fT82fjR/VBEDviUpa hQ==", "From": "Tejasree Kondoj <ktejasree@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>", "CC": "Anoob Joseph <anoobj@marvell.com>, Ankur Dwivedi <adwivedi@marvell.com>,\n <dev@dpdk.org>", "Subject": "[PATCH 3/4] crypto/cnxk: support scatter gather mode", "Date": "Fri, 17 Jun 2022 13:06:03 +0530", "Message-ID": "<20220617073604.889403-4-ktejasree@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220617073604.889403-1-ktejasree@marvell.com>", "References": "<20220617073604.889403-1-ktejasree@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "suW-4_9OiLAYv5BRFPjq3CGK7s5DK30y", "X-Proofpoint-ORIG-GUID": "suW-4_9OiLAYv5BRFPjq3CGK7s5DK30y", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.64.514\n definitions=2022-06-17_06,2022-06-16_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adding scatter gather support for zuc, snow3g\nand aes-ctr-cmac chained operations on cn9k.\n\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/crypto/cnxk/cnxk_se.h | 149 +++++++++++++++++++++++++++++-----\n 1 file changed, 128 insertions(+), 21 deletions(-)", "diff": "diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h\nindex 7429d66314..a2a97aa88f 100644\n--- a/drivers/crypto/cnxk/cnxk_se.h\n+++ b/drivers/crypto/cnxk/cnxk_se.h\n@@ -1027,12 +1027,6 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n \tvoid *dm_vaddr;\n \tuint8_t *iv_d;\n \n-\tif (unlikely((!(req_flags & ROC_SE_SINGLE_BUF_INPLACE)) ||\n-\t\t (!(req_flags & ROC_SE_SINGLE_BUF_HEADROOM)))) {\n-\t\tplt_dp_err(\"Scatter gather mode is not supported\");\n-\t\treturn -1;\n-\t}\n-\n \tencr_offset = ROC_SE_ENCR_OFFSET(d_offs);\n \tauth_offset = ROC_SE_AUTH_OFFSET(d_offs);\n \n@@ -1084,28 +1078,141 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,\n \telse\n \t\tinputlen = encr_offset + encr_data_len;\n \n-\tdm_vaddr = params->bufs[0].vaddr;\n+\tif (likely(((req_flags & ROC_SE_SINGLE_BUF_INPLACE)) &&\n+\t\t ((req_flags & ROC_SE_SINGLE_BUF_HEADROOM)))) {\n+\n+\t\tdm_vaddr = params->bufs[0].vaddr;\n \n-\t/* Use Direct mode */\n+\t\t/* Use Direct mode */\n+\n+\t\toffset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -\n+\t\t\t\t\t ROC_SE_OFF_CTRL_LEN - iv_len);\n \n-\toffset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr - ROC_SE_OFF_CTRL_LEN -\n-\t\t\t\t iv_len);\n+\t\t/* DPTR */\n+\t\tinst->dptr = (uint64_t)offset_vaddr;\n+\t\t/* RPTR should just exclude offset control word */\n+\t\tinst->rptr = (uint64_t)dm_vaddr - iv_len;\n \n-\t/* DPTR */\n-\tinst->dptr = (uint64_t)offset_vaddr;\n-\t/* RPTR should just exclude offset control word */\n-\tinst->rptr = (uint64_t)dm_vaddr - iv_len;\n+\t\tcpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;\n \n-\tcpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;\n+\t\t*(uint64_t *)offset_vaddr =\n+\t\t\trte_cpu_to_be_64(((uint64_t)(iv_offset) << 16) |\n+\t\t\t\t\t ((uint64_t)(encr_offset)));\n \n-\t*(uint64_t *)offset_vaddr = rte_cpu_to_be_64(\n-\t\t((uint64_t)(iv_offset) << 16) | ((uint64_t)(encr_offset)));\n+\t\tiv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN);\n+\t\tpdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv);\n+\n+\t\tiv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16);\n+\t\tpdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv);\n+\n+\t} else {\n+\n+\t\tstruct roc_se_sglist_comp *scatter_comp, *gather_comp;\n+\t\tvoid *m_vaddr = params->meta_buf.vaddr;\n+\t\tuint32_t i, g_size_bytes, s_size_bytes;\n+\t\tuint8_t *in_buffer;\n+\t\tuint32_t size;\n+\n+\t\t/* save space for IV */\n+\t\toffset_vaddr = m_vaddr;\n+\n+\t\tm_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN +\n+\t\t\t RTE_ALIGN_CEIL(iv_len, 8);\n+\n+\t\tcpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;\n+\n+\t\t/* DPTR has SG list */\n+\t\tin_buffer = m_vaddr;\n+\n+\t\t((uint16_t *)in_buffer)[0] = 0;\n+\t\t((uint16_t *)in_buffer)[1] = 0;\n+\n+\t\tgather_comp =\n+\t\t\t(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);\n+\n+\t\t/* Input Gather List */\n+\t\ti = 0;\n+\n+\t\t/* Offset control word followed by iv */\n+\n+\t\ti = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,\n+\t\t\t\t ROC_SE_OFF_CTRL_LEN + iv_len);\n+\n+\t\t*(uint64_t *)offset_vaddr =\n+\t\t\trte_cpu_to_be_64(((uint64_t)(iv_offset) << 16) |\n+\t\t\t\t\t ((uint64_t)(encr_offset)));\n+\n+\t\tiv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN);\n+\t\tpdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv);\n+\n+\t\tiv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16);\n+\t\tpdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv);\n+\n+\t\t/* input data */\n+\t\tsize = inputlen - iv_len;\n+\t\tif (size) {\n+\t\t\ti = fill_sg_comp_from_iov(gather_comp, i,\n+\t\t\t\t\t\t params->src_iov, 0, &size,\n+\t\t\t\t\t\t NULL, 0);\n+\t\t\tif (unlikely(size)) {\n+\t\t\t\tplt_dp_err(\"Insufficient buffer space,\"\n+\t\t\t\t\t \" size %d needed\",\n+\t\t\t\t\t size);\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\t\t((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);\n+\t\tg_size_bytes =\n+\t\t\t((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);\n+\n+\t\t/*\n+\t\t * Output Scatter List\n+\t\t */\n \n-\tiv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN);\n-\tpdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv);\n+\t\ti = 0;\n+\t\tscatter_comp =\n+\t\t\t(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +\n+\t\t\t\t\t\t g_size_bytes);\n+\n+\t\tif (iv_len) {\n+\t\t\ti = fill_sg_comp(scatter_comp, i,\n+\t\t\t\t\t (uint64_t)offset_vaddr +\n+\t\t\t\t\t\t ROC_SE_OFF_CTRL_LEN,\n+\t\t\t\t\t iv_len);\n+\t\t}\n \n-\tiv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16);\n-\tpdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv);\n+\t\t/* Add output data */\n+\t\tif (se_ctx->ciph_then_auth &&\n+\t\t (req_flags & ROC_SE_VALID_MAC_BUF))\n+\t\t\tsize = inputlen - iv_len;\n+\t\telse\n+\t\t\t/* Output including mac */\n+\t\t\tsize = inputlen - iv_len + mac_len;\n+\n+\t\tif (size) {\n+\t\t\ti = fill_sg_comp_from_iov(scatter_comp, i,\n+\t\t\t\t\t\t params->dst_iov, 0, &size,\n+\t\t\t\t\t\t NULL, 0);\n+\n+\t\t\tif (unlikely(size)) {\n+\t\t\t\tplt_dp_err(\"Insufficient buffer space,\"\n+\t\t\t\t\t \" size %d needed\",\n+\t\t\t\t\t size);\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t}\n+\n+\t\t((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);\n+\t\ts_size_bytes =\n+\t\t\t((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);\n+\n+\t\tsize = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;\n+\n+\t\t/* This is DPTR len in case of SG mode */\n+\t\tcpt_inst_w4.s.dlen = size;\n+\n+\t\tinst->dptr = (uint64_t)in_buffer;\n+\t}\n \n \tinst->w4.u64 = cpt_inst_w4.u64;\n \n", "prefixes": [ "3/4" ] }