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GET /api/patches/113084/?format=api
{ "id": 113084, "url": "http://patchwork.dpdk.org/api/patches/113084/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220620071807.951128-3-ktejasree@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220620071807.951128-3-ktejasree@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220620071807.951128-3-ktejasree@marvell.com", "date": "2022-06-20T07:18:06", "name": "[2/3] crypto/cnxk: improvements to fastpath handling", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "2582eeb96184446b819e6e0dc272144bea973c5f", "submitter": { "id": 1789, "url": "http://patchwork.dpdk.org/api/people/1789/?format=api", "name": "Tejasree Kondoj", "email": "ktejasree@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220620071807.951128-3-ktejasree@marvell.com/mbox/", "series": [ { "id": 23627, "url": "http://patchwork.dpdk.org/api/series/23627/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=23627", "date": "2022-06-20T07:18:04", "name": "support new full context firmware", "version": 1, "mbox": "http://patchwork.dpdk.org/series/23627/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/113084/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/113084/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EF3C3A0545;\n\tMon, 20 Jun 2022 09:18:30 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0058D427F7;\n\tMon, 20 Jun 2022 09:18:25 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 1366840150\n for <dev@dpdk.org>; Mon, 20 Jun 2022 09:18:23 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 25JNE48a011897\n for <dev@dpdk.org>; Mon, 20 Jun 2022 00:18:23 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3gsc2p5u2n-6\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 20 Jun 2022 00:18:23 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Mon, 20 Jun 2022 00:18:19 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 20 Jun 2022 00:18:19 -0700", "from hyd1554.marvell.com (unknown [10.29.57.11])\n by maili.marvell.com (Postfix) with ESMTP id D15D55E686D;\n Mon, 20 Jun 2022 00:18:15 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=xDpTHy2DBt8s0CxvCfVUjTT3INZKukJYWXetwlmR0u0=;\n b=UR6Uqdtqegdrlc0L8qn5YWa/JRbttc2sUEm+HEbrv7kieyZC+/PQKDDIHg2Ac5m8oeYh\n T1DF9fyngZ8IO4Ky1ayx5MSBjX73KqkUcmUTattErxJwfgkKNRYy45SFWhIk5zpFV2ae\n zE2HCXGQCvckDogWIalKOtXpSW0911s7iVMtNrIbp2ye0BeRAowjD0xuUL6db8qK6S/g\n 22HCIatIvje0edatw9SWnzgmKq6yLduSv0m1bZXusaMZU5c5xEemSfL3ihx/zqDnTZtH\n /DT+Afhz/ZKWDBZO5MvUy28JQWY3H6q571KeFYbZML0XIF4JYz6xUoScv+gM2RamuBgP Sg==", "From": "Tejasree Kondoj <ktejasree@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>", "CC": "Anoob Joseph <anoobj@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n Nithin Dabilpuram <ndabilpuram@marvell.com>, Vidya Sagar Velumuri\n <vvelumuri@marvell.com>, Archana Muniganti <marchana@marvell.com>, \"Ankur\n Dwivedi\" <adwivedi@marvell.com>, Kiran Kumar K <kirankumark@marvell.com>,\n Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 2/3] crypto/cnxk: improvements to fastpath handling", "Date": "Mon, 20 Jun 2022 12:48:06 +0530", "Message-ID": "<20220620071807.951128-3-ktejasree@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220620071807.951128-1-ktejasree@marvell.com>", "References": "<20220620071807.951128-1-ktejasree@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "GszV2m3gjX-ESrcZfrhgxGVqL9LMnS-3", "X-Proofpoint-GUID": "GszV2m3gjX-ESrcZfrhgxGVqL9LMnS-3", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.64.514\n definitions=2022-06-20_05,2022-06-17_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Anoob Joseph <anoobj@marvell.com>\n\nRemove SA & packet accesses in dequeue path by adjusting the headers in\nthe enqueue path for outbound packets. For inbound packets, add extra\nesn_en flag in the SA to minimize cache line accesses in the datapath.\n\nAlso, use seq_lo for IPID. IPID just need to be unique. Instead of\nincrementing per packet, use ESN low bits.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\n---\n drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 69 ++++++++++++++----------\n drivers/crypto/cnxk/cn9k_ipsec.c | 11 ++--\n drivers/crypto/cnxk/cn9k_ipsec.h | 7 ++-\n drivers/crypto/cnxk/cn9k_ipsec_la_ops.h | 55 +++++++++++--------\n drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 12 ++---\n 5 files changed, 87 insertions(+), 67 deletions(-)", "diff": "diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\nindex 7720730120..8aab9c9f60 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n@@ -43,10 +43,12 @@ cn9k_cpt_sec_inst_fill(struct rte_crypto_op *op,\n \t\t struct cpt_inst_s *inst)\n {\n \tstruct rte_crypto_sym_op *sym_op = op->sym;\n-\tstruct roc_ie_on_common_sa *common_sa;\n \tstruct cn9k_sec_session *priv;\n-\tstruct roc_ie_on_sa_ctl *ctl;\n \tstruct cn9k_ipsec_sa *sa;\n+\tint ret;\n+\n+\tpriv = get_sec_session_private_data(op->sym->sec_session);\n+\tsa = &priv->sa;\n \n \tif (unlikely(sym_op->m_dst && sym_op->m_dst != sym_op->m_src)) {\n \t\tplt_dp_err(\"Out of place is not supported\");\n@@ -58,21 +60,17 @@ cn9k_cpt_sec_inst_fill(struct rte_crypto_op *op,\n \t\treturn -ENOTSUP;\n \t}\n \n-\tpriv = get_sec_session_private_data(op->sym->sec_session);\n-\tsa = &priv->sa;\n-\n \tif (sa->dir == RTE_SECURITY_IPSEC_SA_DIR_EGRESS)\n-\t\treturn process_outb_sa(op, sa, inst);\n-\n-\tinfl_req->op_flags |= CPT_OP_FLAGS_IPSEC_DIR_INBOUND;\n-\n-\tcommon_sa = &sa->in_sa.common_sa;\n-\tctl = &common_sa->ctl;\n-\n-\tif (ctl->esn_en)\n-\t\tinfl_req->op_flags |= CPT_OP_FLAGS_IPSEC_INB_ESN;\n+\t\tret = process_outb_sa(op, sa, inst);\n+\telse {\n+\t\tinfl_req->op_flags |= CPT_OP_FLAGS_IPSEC_DIR_INBOUND;\n+\t\tprocess_inb_sa(op, sa, inst);\n+\t\tif (unlikely(sa->esn_en))\n+\t\t\tinfl_req->op_flags |= CPT_OP_FLAGS_IPSEC_INB_ESN;\n+\t\tret = 0;\n+\t}\n \n-\treturn process_inb_sa(op, sa, inst);\n+\treturn ret;\n }\n \n static inline struct cnxk_se_sess *\n@@ -234,19 +232,29 @@ cn9k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \t};\n \n \tpend_q = &qp->pend_q;\n-\n-\tconst uint64_t lmt_base = qp->lf.lmt_base;\n-\tconst uint64_t io_addr = qp->lf.io_addr;\n-\tconst uint64_t pq_mask = pend_q->pq_mask;\n+\trte_prefetch2(pend_q);\n \n \t/* Clear w0, w2, w3 of both inst */\n \n+#if defined(RTE_ARCH_ARM64)\n+\tuint64x2_t zero = vdupq_n_u64(0);\n+\n+\tvst1q_u64(&inst[0].w0.u64, zero);\n+\tvst1q_u64(&inst[1].w0.u64, zero);\n+\tvst1q_u64(&inst[0].w2.u64, zero);\n+\tvst1q_u64(&inst[1].w2.u64, zero);\n+#else\n \tinst[0].w0.u64 = 0;\n \tinst[0].w2.u64 = 0;\n \tinst[0].w3.u64 = 0;\n \tinst[1].w0.u64 = 0;\n \tinst[1].w2.u64 = 0;\n \tinst[1].w3.u64 = 0;\n+#endif\n+\n+\tconst uint64_t lmt_base = qp->lf.lmt_base;\n+\tconst uint64_t io_addr = qp->lf.io_addr;\n+\tconst uint64_t pq_mask = pend_q->pq_mask;\n \n \thead = pend_q->head;\n \tnb_allowed = pending_queue_free_cnt(head, pend_q->tail, pq_mask);\n@@ -506,21 +514,26 @@ cn9k_cpt_sec_post_process(struct rte_crypto_op *cop,\n \tuint16_t m_len = 0;\n \tchar *data;\n \n-\tpriv = get_sec_session_private_data(cop->sym->sec_session);\n-\tsa = &priv->sa;\n-\n \tif (infl_req->op_flags & CPT_OP_FLAGS_IPSEC_DIR_INBOUND) {\n-\t\tstruct roc_ie_on_common_sa *common_sa = &sa->in_sa.common_sa;\n+\t\tstruct roc_ie_on_common_sa *common_sa;\n \n \t\tdata = rte_pktmbuf_mtod(m, char *);\n-\t\tif (infl_req->op_flags == CPT_OP_FLAGS_IPSEC_INB_ESN) {\n-\t\t\tstruct roc_ie_on_inb_hdr *inb_hdr =\n-\t\t\t\t(struct roc_ie_on_inb_hdr *)data;\n-\t\t\tuint64_t seq = rte_be_to_cpu_64(inb_hdr->seq);\n+\t\tif (unlikely(infl_req->op_flags & CPT_OP_FLAGS_IPSEC_INB_ESN)) {\n+\t\t\tstruct roc_ie_on_inb_hdr *inb_hdr;\n+\t\t\tuint64_t seq;\n+\n+\t\t\tpriv = get_sec_session_private_data(\n+\t\t\t\tsym_op->sec_session);\n+\t\t\tsa = &priv->sa;\n+\t\t\tcommon_sa = &sa->in_sa.common_sa;\n+\n+\t\t\tinb_hdr = (struct roc_ie_on_inb_hdr *)data;\n+\t\t\tseq = rte_be_to_cpu_64(inb_hdr->seq);\n \n \t\t\tif (seq > common_sa->seq_t.u64)\n \t\t\t\tcommon_sa->seq_t.u64 = seq;\n \t\t}\n+\n \t\tip = (struct rte_ipv4_hdr *)(data + ROC_IE_ON_INB_RPTR_HDR);\n \n \t\tif (((ip->version_ihl & 0xf0) >> RTE_IPV4_IHL_MULTIPLIER) ==\n@@ -537,8 +550,6 @@ cn9k_cpt_sec_post_process(struct rte_crypto_op *cop,\n \t\tm->data_len = m_len;\n \t\tm->pkt_len = m_len;\n \t\tm->data_off += ROC_IE_ON_INB_RPTR_HDR;\n-\t} else {\n-\t\trte_pktmbuf_adj(m, sa->custom_hdr_len);\n \t}\n }\n \ndiff --git a/drivers/crypto/cnxk/cn9k_ipsec.c b/drivers/crypto/cnxk/cn9k_ipsec.c\nindex 85f3f26c32..49a775eb7f 100644\n--- a/drivers/crypto/cnxk/cn9k_ipsec.c\n+++ b/drivers/crypto/cnxk/cn9k_ipsec.c\n@@ -40,13 +40,8 @@ cn9k_ipsec_outb_sa_create(struct cnxk_cpt_qp *qp,\n \n \t/* Initialize lookaside IPsec private data */\n \tsa->dir = RTE_SECURITY_IPSEC_SA_DIR_EGRESS;\n-\t/* Start ip id from 1 */\n-\tsa->ip_id = 1;\n-\tsa->seq_lo = 1;\n-\tsa->seq_hi = 0;\n \n-\tif (ipsec->esn.value)\n-\t\tsa->esn = ipsec->esn.value;\n+\tsa->esn = ipsec->esn.value;\n \n \tret = cnxk_ipsec_outb_rlens_get(&sa->rlens, ipsec, crypto_xform);\n \tif (ret)\n@@ -166,10 +161,12 @@ cn9k_ipsec_inb_sa_create(struct cnxk_cpt_qp *qp,\n \t}\n \n \tret = cnxk_on_ipsec_inb_sa_create(ipsec, crypto_xform, &sa->in_sa);\n-\n \tif (ret < 0)\n \t\treturn ret;\n \n+\tif (sa->in_sa.common_sa.ctl.esn_en)\n+\t\tsa->esn_en = 1;\n+\n \tctx_len = ret;\n \topcode = ROC_IE_ON_MAJOR_OP_WRITE_IPSEC_INBOUND;\n \tegrp = roc_cpt->eng_grp[CPT_ENG_TYPE_IE];\ndiff --git a/drivers/crypto/cnxk/cn9k_ipsec.h b/drivers/crypto/cnxk/cn9k_ipsec.h\nindex 499dbc2782..bed5976096 100644\n--- a/drivers/crypto/cnxk/cn9k_ipsec.h\n+++ b/drivers/crypto/cnxk/cn9k_ipsec.h\n@@ -28,8 +28,6 @@ struct cn9k_ipsec_sa {\n \tuint8_t custom_hdr_len;\n \t/** Response length calculation data */\n \tstruct cnxk_ipsec_outb_rlens rlens;\n-\t/** Outbound IP-ID */\n-\tuint16_t ip_id;\n \t/** ESN */\n \tunion {\n \t\tuint64_t esn;\n@@ -42,6 +40,11 @@ struct cn9k_ipsec_sa {\n \tstruct cnxk_on_ipsec_ar ar;\n \t/** Anti replay window size */\n \tuint32_t replay_win_sz;\n+\t/*\n+\t * ESN enable flag. Copy of in_sa ctl.esn_en to have single cache line\n+\t * access in the non-esn fastpath.\n+\t */\n+\tuint8_t esn_en;\n \t/** Queue pair */\n \tstruct cnxk_cpt_qp *qp;\n };\ndiff --git a/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h b/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h\nindex bbb4404a89..65dbb629b1 100644\n--- a/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h\n+++ b/drivers/crypto/cnxk/cn9k_ipsec_la_ops.h\n@@ -77,29 +77,36 @@ process_outb_sa(struct rte_crypto_op *cop, struct cn9k_ipsec_sa *sa,\n \tconst unsigned int hdr_len = sa->custom_hdr_len;\n \tstruct rte_crypto_sym_op *sym_op = cop->sym;\n \tstruct rte_mbuf *m_src = sym_op->m_src;\n+\tuint32_t dlen, rlen, pkt_len, seq_lo;\n+\tuint16_t data_off = m_src->data_off;\n \tstruct roc_ie_on_outb_hdr *hdr;\n-\tuint32_t dlen, rlen;\n \tint32_t extend_tail;\n+\tuint64_t esn;\n \n-\tdlen = rte_pktmbuf_pkt_len(m_src) + hdr_len;\n-\trlen = ipsec_po_out_rlen_get(sa, dlen - hdr_len);\n+\tpkt_len = rte_pktmbuf_pkt_len(m_src);\n+\tdlen = pkt_len + hdr_len;\n+\trlen = ipsec_po_out_rlen_get(sa, pkt_len);\n \n \textend_tail = rlen - dlen;\n \tif (unlikely(extend_tail > rte_pktmbuf_tailroom(m_src))) {\n-\t\tplt_dp_err(\"Not enough tail room (required: %d, available: %d\",\n+\t\tplt_dp_err(\"Not enough tail room (required: %d, available: %d)\",\n \t\t\t extend_tail, rte_pktmbuf_tailroom(m_src));\n \t\treturn -ENOMEM;\n \t}\n \n-\tm_src->data_len += extend_tail;\n-\tm_src->pkt_len += extend_tail;\n-\n-\thdr = (struct roc_ie_on_outb_hdr *)rte_pktmbuf_prepend(m_src, hdr_len);\n-\tif (unlikely(hdr == NULL)) {\n-\t\tplt_dp_err(\"Not enough head room\");\n+\tif (unlikely(hdr_len > data_off)) {\n+\t\tplt_dp_err(\"Not enough head room (required: %d, available: %d)\",\n+\t\t\t hdr_len, rte_pktmbuf_headroom(m_src));\n \t\treturn -ENOMEM;\n \t}\n \n+\tpkt_len += extend_tail;\n+\n+\tm_src->data_len = pkt_len;\n+\tm_src->pkt_len = pkt_len;\n+\n+\thdr = PLT_PTR_ADD(m_src->buf_addr, data_off - hdr_len);\n+\n #ifdef LA_IPSEC_DEBUG\n \tif (sa->inst.w4 & ROC_IE_ON_PER_PKT_IV) {\n \t\tmemcpy(&hdr->iv[0],\n@@ -109,23 +116,28 @@ process_outb_sa(struct rte_crypto_op *cop, struct cn9k_ipsec_sa *sa,\n \t}\n #endif\n \n-\thdr->seq = rte_cpu_to_be_32(sa->seq_lo);\n-\thdr->ip_id = rte_cpu_to_be_32(sa->ip_id);\n-\thdr->esn = rte_cpu_to_be_32(sa->seq_hi);\n+\tesn = ++sa->esn;\n+\n+\t/* Set ESN seq hi */\n+\thdr->esn = rte_cpu_to_be_32(esn >> 32);\n \n-\tsa->ip_id++;\n-\tsa->esn++;\n+\t/* Set ESN seq lo */\n+\tseq_lo = rte_cpu_to_be_32(esn & (BIT_ULL(32) - 1));\n+\thdr->seq = seq_lo;\n+\n+\t/* Set IPID same as seq_lo */\n+\thdr->ip_id = seq_lo;\n \n \t/* Prepare CPT instruction */\n \tinst->w4.u64 = sa->inst.w4 | dlen;\n-\tinst->dptr = rte_pktmbuf_iova(m_src);\n-\tinst->rptr = inst->dptr;\n+\tinst->dptr = PLT_U64_CAST(hdr);\n+\tinst->rptr = PLT_U64_CAST(hdr);\n \tinst->w7.u64 = sa->inst.w7;\n \n \treturn 0;\n }\n \n-static __rte_always_inline int\n+static __rte_always_inline void\n process_inb_sa(struct rte_crypto_op *cop, struct cn9k_ipsec_sa *sa,\n \t struct cpt_inst_s *inst)\n {\n@@ -149,16 +161,13 @@ process_inb_sa(struct rte_crypto_op *cop, struct cn9k_ipsec_sa *sa,\n \t\t\tinst->dptr = rte_pktmbuf_iova(m_src);\n \t\t\tinst->rptr = inst->dptr;\n \t\t\tinst->w7.u64 = sa->inst.w7;\n-\t\t\treturn 0;\n+\t\t\treturn;\n \t\t}\n \t}\n \n \t/* Prepare CPT instruction */\n \tinst->w4.u64 = sa->inst.w4 | rte_pktmbuf_pkt_len(m_src);\n-\tinst->dptr = rte_pktmbuf_iova(m_src);\n-\tinst->rptr = inst->dptr;\n+\tinst->dptr = inst->rptr = rte_pktmbuf_iova(m_src);\n \tinst->w7.u64 = sa->inst.w7;\n-\n-\treturn 0;\n }\n #endif /* __CN9K_IPSEC_LA_OPS_H__ */\ndiff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\nindex ec99e6d660..0b41d47de9 100644\n--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h\n@@ -70,16 +70,16 @@ struct cnxk_cpt_qp {\n \t/**< Crypto LF */\n \tstruct pending_queue pend_q;\n \t/**< Pending queue */\n-\tstruct rte_mempool *sess_mp;\n-\t/**< Session mempool */\n-\tstruct rte_mempool *sess_mp_priv;\n-\t/**< Session private data mempool */\n-\tstruct cpt_qp_meta_info meta_info;\n-\t/**< Metabuf info required to support operations on the queue pair */\n \tstruct roc_cpt_lmtline lmtline;\n \t/**< Lmtline information */\n+\tstruct cpt_qp_meta_info meta_info;\n+\t/**< Metabuf info required to support operations on the queue pair */\n \tstruct crypto_adpter_info ca;\n \t/**< Crypto adapter related info */\n+\tstruct rte_mempool *sess_mp;\n+\t/**< Session mempool */\n+\tstruct rte_mempool *sess_mp_priv;\n+\t/**< Session private data mempool */\n };\n \n int cnxk_cpt_dev_config(struct rte_cryptodev *dev,\n", "prefixes": [ "2/3" ] }