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{
    "id": 114769,
    "url": "http://patchwork.dpdk.org/api/patches/114769/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220809184908.24030-5-ndabilpuram@marvell.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
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    "msgid": "<20220809184908.24030-5-ndabilpuram@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220809184908.24030-5-ndabilpuram@marvell.com",
    "date": "2022-08-09T18:48:49",
    "name": "[05/23] common/cnxk: limit meta aura workaround to CN10K A0",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "4fc1009a7ef92a1732bf7fb62c5ce89c562fda08",
    "submitter": {
        "id": 1202,
        "url": "http://patchwork.dpdk.org/api/people/1202/?format=api",
        "name": "Nithin Dabilpuram",
        "email": "ndabilpuram@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "http://patchwork.dpdk.org/api/users/310/?format=api",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerinj@marvell.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220809184908.24030-5-ndabilpuram@marvell.com/mbox/",
    "series": [
        {
            "id": 24239,
            "url": "http://patchwork.dpdk.org/api/series/24239/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=24239",
            "date": "2022-08-09T18:48:45",
            "name": "[01/23] common/cnxk: fix part value for cn10k",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/24239/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/114769/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/114769/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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        ],
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        "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>",
        "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>",
        "CC": "<jerinj@marvell.com>, <dev@dpdk.org>",
        "Subject": "[PATCH 05/23] common/cnxk: limit meta aura workaround to CN10K A0",
        "Date": "Wed, 10 Aug 2022 00:18:49 +0530",
        "Message-ID": "<20220809184908.24030-5-ndabilpuram@marvell.com>",
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        "References": "<20220809184908.24030-1-ndabilpuram@marvell.com>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Limit meta aura workaround to CN10K A0.\nAlso other NIX and Inline related Erratas applicable\nfor CN10K A1.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_errata.h  |  7 +++++++\n drivers/common/cnxk/roc_nix_inl.c | 10 ++++++----\n drivers/net/cnxk/cnxk_ethdev.c    |  3 ++-\n 3 files changed, 15 insertions(+), 5 deletions(-)",
    "diff": "diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h\nindex f048297..8dc372f 100644\n--- a/drivers/common/cnxk/roc_errata.h\n+++ b/drivers/common/cnxk/roc_errata.h\n@@ -81,6 +81,13 @@ roc_errata_nix_has_perf_issue_on_stats_update(void)\n static inline bool\n roc_errata_cpt_hang_on_x2p_bp(void)\n {\n+\treturn roc_model_is_cn10ka_a0() || roc_model_is_cn10ka_a1();\n+}\n+\n+/* IPBUNIXRX-40400 */\n+static inline bool\n+roc_errata_nix_no_meta_aura(void)\n+{\n \treturn roc_model_is_cn10ka_a0();\n }\n \ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex 7da8938..603551b 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -627,18 +627,18 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)\n \tinl_rq->first_skip = rq->first_skip;\n \tinl_rq->later_skip = rq->later_skip;\n \tinl_rq->lpb_size = rq->lpb_size;\n-\tinl_rq->lpb_drop_ena = true;\n \tinl_rq->spb_ena = rq->spb_ena;\n \tinl_rq->spb_aura_handle = rq->spb_aura_handle;\n \tinl_rq->spb_size = rq->spb_size;\n-\tinl_rq->spb_drop_ena = !!rq->spb_ena;\n \n-\tif (!roc_model_is_cn9k()) {\n+\tif (roc_errata_nix_no_meta_aura()) {\n \t\tuint64_t aura_limit =\n \t\t\troc_npa_aura_op_limit_get(inl_rq->aura_handle);\n \t\tuint64_t aura_shift = plt_log2_u32(aura_limit);\n \t\tuint64_t aura_drop, drop_pc;\n \n+\t\tinl_rq->lpb_drop_ena = true;\n+\n \t\tif (aura_shift < 8)\n \t\t\taura_shift = 0;\n \t\telse\n@@ -653,12 +653,14 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)\n \t\troc_npa_aura_drop_set(inl_rq->aura_handle, aura_drop, true);\n \t}\n \n-\tif (inl_rq->spb_ena) {\n+\tif (roc_errata_nix_no_meta_aura() && inl_rq->spb_ena) {\n \t\tuint64_t aura_limit =\n \t\t\troc_npa_aura_op_limit_get(inl_rq->spb_aura_handle);\n \t\tuint64_t aura_shift = plt_log2_u32(aura_limit);\n \t\tuint64_t aura_drop, drop_pc;\n \n+\t\tinl_rq->spb_drop_ena = true;\n+\n \t\tif (aura_shift < 8)\n \t\t\taura_shift = 0;\n \t\telse\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 2418290..df20f27 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -617,7 +617,8 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \trq->first_skip = first_skip;\n \trq->later_skip = sizeof(struct rte_mbuf);\n \trq->lpb_size = mp->elt_size;\n-\trq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);\n+\tif (roc_errata_nix_no_meta_aura())\n+\t\trq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);\n \n \t/* Enable Inline IPSec on RQ, will not be used for Poll mode */\n \tif (roc_nix_inl_inb_is_enabled(nix))\n",
    "prefixes": [
        "05/23"
    ]
}