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GET /api/patches/114781/?format=api
{ "id": 114781, "url": "http://patchwork.dpdk.org/api/patches/114781/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220809184908.24030-21-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220809184908.24030-21-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220809184908.24030-21-ndabilpuram@marvell.com", "date": "2022-08-09T18:49:05", "name": "[21/23] common/cnxk: add support for CPT second pass", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "ef5c203b6eeefcea7d94f6813550347e327a3567", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220809184908.24030-21-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 24239, "url": "http://patchwork.dpdk.org/api/series/24239/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=24239", "date": "2022-08-09T18:48:45", "name": "[01/23] common/cnxk: fix part value for cn10k", "version": 1, "mbox": "http://patchwork.dpdk.org/series/24239/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/114781/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/114781/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 336D7A04FD;\n\tTue, 9 Aug 2022 20:51:30 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2371542C4E;\n\tTue, 9 Aug 2022 20:50:50 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 7E0AA42BEB\n for <dev@dpdk.org>; Tue, 9 Aug 2022 20:50:47 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 279D8wcl015744\n for <dev@dpdk.org>; Tue, 9 Aug 2022 11:50:46 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3huds2ukxf-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 09 Aug 2022 11:50:46 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 9 Aug 2022 11:50:45 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 9 Aug 2022 11:50:44 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id B9FAC3F7085;\n Tue, 9 Aug 2022 11:50:42 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=VgXDgKWi8IMKUAHJ3X7nCCreSiGrkS+UvI+iJevgDak=;\n b=ewpcsRXQJMitUHWKgBFlg34Iyuwwn822fCyT/B4XkAT9YS8EOh+wBSLq45K8b3oqBNu0\n ugQjJO+21UuRfYQ3aNNErTRWzv3KkAP8VU0Lh6vDv6LYjDOvo14qlBmbXuzA1TMXm8ik\n ouxyecuyW3yC5tgOIrzgD54mszB9+l3GMwgFprIboLEc5Kv+aZoPBcD8roR63P6izWQ/\n NJGkycoJYwDLYODdfNGOUTMEKKXHpjtpMsnMgSedrQjU3h39uXMDT2jKpDZIpj9u64uo\n GMy/hf4teOwvPuXicWaWSyWV6NYZ42q/iflFxQGue+p0ZSJ/ytGCXo7qZ0m96P5SNwq1 XQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>, Rakesh Kudurumalla\n <rkudurumalla@marvell.com>", "Subject": "[PATCH 21/23] common/cnxk: add support for CPT second pass", "Date": "Wed, 10 Aug 2022 00:19:05 +0530", "Message-ID": "<20220809184908.24030-21-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220809184908.24030-1-ndabilpuram@marvell.com>", "References": "<20220809184908.24030-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "jmqMGyNd4APkzgj7WY0H0impayvLoVun", "X-Proofpoint-GUID": "jmqMGyNd4APkzgj7WY0H0impayvLoVun", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1\n definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Rakesh Kudurumalla <rkudurumalla@marvell.com>\n\nAdded mailbox for masking and setting nix_rq_ctx\nparameters and enabling rq masking in ipsec_cfg1\nso second pass is applied to all rq's\n\nSigned-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>\n---\n drivers/common/cnxk/hw/nix.h | 4 +-\n drivers/common/cnxk/roc_mbox.h | 23 ++++++++++-\n drivers/common/cnxk/roc_nix_inl.c | 81 +++++++++++++++++++++++++++++++++++++++\n 3 files changed, 106 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h\nindex 5863e35..a535264 100644\n--- a/drivers/common/cnxk/hw/nix.h\n+++ b/drivers/common/cnxk/hw/nix.h\n@@ -1242,7 +1242,9 @@ struct nix_cn10k_rq_ctx_s {\n \tuint64_t ipsech_ena : 1;\n \tuint64_t ena_wqwd : 1;\n \tuint64_t cq : 20;\n-\tuint64_t rsvd_36_24 : 13;\n+\tuint64_t rsvd_34_24 : 11;\n+\tuint64_t port_ol4_dis : 1;\n+\tuint64_t port_il4_dis : 1;\n \tuint64_t lenerr_dis : 1;\n \tuint64_t csum_il4_dis : 1;\n \tuint64_t csum_ol4_dis : 1;\ndiff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex 912de11..688c70b 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -265,7 +265,9 @@ struct mbox_msghdr {\n \t msg_rsp) \\\n \tM(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp) \\\n \tM(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \\\n-\t msg_req, nix_inline_ipsec_cfg)\n+\t msg_req, nix_inline_ipsec_cfg)\t\t\t\t \\\n+\tM(NIX_LF_INLINE_RQ_CFG, 0x8024, nix_lf_inline_rq_cfg, \\\n+\t nix_rq_cpt_field_mask_cfg_req, msg_rsp)\n \n /* Messages initiated by AF (range 0xC00 - 0xDFF) */\n #define MBOX_UP_CGX_MESSAGES \\\n@@ -1088,6 +1090,25 @@ struct nix_mark_format_cfg_rsp {\n \tuint8_t __io mark_format_idx;\n };\n \n+struct nix_rq_cpt_field_mask_cfg_req {\n+\tstruct mbox_msghdr hdr;\n+#define RQ_CTX_MASK_MAX 6\n+\tunion {\n+\t\tuint64_t __io rq_ctx_word_set[RQ_CTX_MASK_MAX];\n+\t\tstruct nix_cn10k_rq_ctx_s rq_set;\n+\t};\n+\tunion {\n+\t\tuint64_t __io rq_ctx_word_mask[RQ_CTX_MASK_MAX];\n+\t\tstruct nix_cn10k_rq_ctx_s rq_mask;\n+\t};\n+\tstruct nix_lf_rx_ipec_cfg1_req {\n+\t\tuint32_t __io spb_cpt_aura;\n+\t\tuint8_t __io rq_mask_enable;\n+\t\tuint8_t __io spb_cpt_sizem1;\n+\t\tuint8_t __io spb_cpt_enable;\n+\t} ipsec_cfg1;\n+};\n+\n struct nix_lso_format_cfg {\n \tstruct mbox_msghdr hdr;\n \tuint64_t __io field_mask;\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex be0b806..cdf31b1 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -416,6 +416,70 @@ roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags)\n \treturn roc_cpt_rxc_time_cfg(roc_cpt, &cfg);\n }\n \n+static int\n+nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct nix_rq_cpt_field_mask_cfg_req *msk_req;\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct mbox *mbox = (&nix->dev)->mbox;\n+\tstruct idev_nix_inl_cfg *inl_cfg;\n+\tuint64_t aura_handle;\n+\tint rc = -ENOSPC;\n+\tint i;\n+\n+\tif (!idev)\n+\t\treturn rc;\n+\n+\tinl_cfg = &idev->inl_cfg;\n+\tmsk_req = mbox_alloc_msg_nix_lf_inline_rq_cfg(mbox);\n+\tif (msk_req == NULL)\n+\t\treturn rc;\n+\n+\tfor (i = 0; i < RQ_CTX_MASK_MAX; i++)\n+\t\tmsk_req->rq_ctx_word_mask[i] = 0xFFFFFFFFFFFFFFFF;\n+\n+\tmsk_req->rq_set.len_ol3_dis = 1;\n+\tmsk_req->rq_set.len_ol4_dis = 1;\n+\tmsk_req->rq_set.len_il3_dis = 1;\n+\n+\tmsk_req->rq_set.len_il4_dis = 1;\n+\tmsk_req->rq_set.csum_ol4_dis = 1;\n+\tmsk_req->rq_set.csum_il4_dis = 1;\n+\n+\tmsk_req->rq_set.lenerr_dis = 1;\n+\tmsk_req->rq_set.port_ol4_dis = 1;\n+\tmsk_req->rq_set.port_il4_dis = 1;\n+\n+\tmsk_req->rq_set.lpb_drop_ena = 0;\n+\tmsk_req->rq_set.spb_drop_ena = 0;\n+\tmsk_req->rq_set.xqe_drop_ena = 0;\n+\n+\tmsk_req->rq_mask.len_ol3_dis = ~(msk_req->rq_set.len_ol3_dis);\n+\tmsk_req->rq_mask.len_ol4_dis = ~(msk_req->rq_set.len_ol4_dis);\n+\tmsk_req->rq_mask.len_il3_dis = ~(msk_req->rq_set.len_il3_dis);\n+\n+\tmsk_req->rq_mask.len_il4_dis = ~(msk_req->rq_set.len_il4_dis);\n+\tmsk_req->rq_mask.csum_ol4_dis = ~(msk_req->rq_set.csum_ol4_dis);\n+\tmsk_req->rq_mask.csum_il4_dis = ~(msk_req->rq_set.csum_il4_dis);\n+\n+\tmsk_req->rq_mask.lenerr_dis = ~(msk_req->rq_set.lenerr_dis);\n+\tmsk_req->rq_mask.port_ol4_dis = ~(msk_req->rq_set.port_ol4_dis);\n+\tmsk_req->rq_mask.port_il4_dis = ~(msk_req->rq_set.port_il4_dis);\n+\n+\tmsk_req->rq_mask.lpb_drop_ena = ~(msk_req->rq_set.lpb_drop_ena);\n+\tmsk_req->rq_mask.spb_drop_ena = ~(msk_req->rq_set.spb_drop_ena);\n+\tmsk_req->rq_mask.xqe_drop_ena = ~(msk_req->rq_set.xqe_drop_ena);\n+\n+\taura_handle = roc_npa_zero_aura_handle();\n+\tmsk_req->ipsec_cfg1.spb_cpt_aura = roc_npa_aura_handle_to_aura(aura_handle);\n+\tmsk_req->ipsec_cfg1.rq_mask_enable = enable;\n+\tmsk_req->ipsec_cfg1.spb_cpt_sizem1 = inl_cfg->buf_sz;\n+\tmsk_req->ipsec_cfg1.spb_cpt_enable = enable;\n+\n+\treturn mbox_process(mbox);\n+}\n+\n int\n roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n {\n@@ -472,6 +536,14 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n \t\tnix->need_meta_aura = true;\n \t\tidev->inl_cfg.refs++;\n \t}\n+\n+\tif (roc_model_is_cn10kb_a0()) {\n+\t\trc = nix_inl_rq_mask_cfg(roc_nix, true);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to get rq mask rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t}\n \tnix->inl_inb_ena = true;\n \treturn 0;\n }\n@@ -481,6 +553,7 @@ roc_nix_inl_inb_fini(struct roc_nix *roc_nix)\n {\n \tstruct idev_cfg *idev = idev_get_cfg();\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tint rc;\n \n \tif (!nix->inl_inb_ena)\n \t\treturn 0;\n@@ -496,6 +569,14 @@ roc_nix_inl_inb_fini(struct roc_nix *roc_nix)\n \t\t\tnix_inl_meta_aura_destroy();\n \t}\n \n+\tif (roc_model_is_cn10kb_a0()) {\n+\t\trc = nix_inl_rq_mask_cfg(roc_nix, false);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to get rq mask rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t}\n+\n \t/* Flush Inbound CTX cache entries */\n \troc_nix_cpt_ctx_cache_sync(roc_nix);\n \n", "prefixes": [ "21/23" ] }