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GET /api/patches/116327/?format=api
{ "id": 116327, "url": "http://patchwork.dpdk.org/api/patches/116327/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220915070732.182542-3-hpothula@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220915070732.182542-3-hpothula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220915070732.182542-3-hpothula@marvell.com", "date": "2022-09-15T07:07:32", "name": "[v4,3/3] net/cnxk: Add support for mulitiple mbuf pools", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "8d2a0e30e6a0ffa037244dafdc3641434154ce05", "submitter": { "id": 2319, "url": "http://patchwork.dpdk.org/api/people/2319/?format=api", "name": "Hanumanth Pothula", "email": "hpothula@marvell.com" }, "delegate": { "id": 3961, "url": "http://patchwork.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220915070732.182542-3-hpothula@marvell.com/mbox/", "series": [ { "id": 24672, "url": "http://patchwork.dpdk.org/api/series/24672/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=24672", "date": "2022-09-15T07:07:30", "name": "[v4,1/3] ethdev: Add support for mulitiple mbuf pools per Rx queue", "version": 4, "mbox": "http://patchwork.dpdk.org/series/24672/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/116327/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/116327/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1646CA034C;\n\tThu, 15 Sep 2022 09:10:07 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 09E33427F4;\n\tThu, 15 Sep 2022 09:10:07 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 809DC40223\n for <dev@dpdk.org>; Thu, 15 Sep 2022 09:10:05 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 28ENmODh023168;\n Thu, 15 Sep 2022 00:07:58 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3jjy0272yf-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 15 Sep 2022 00:07:58 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 15 Sep 2022 00:07:56 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 15 Sep 2022 00:07:56 -0700", "from localhost.localdomain (unknown [10.28.36.155])\n by maili.marvell.com (Postfix) with ESMTP id 726DB3F70A2;\n Thu, 15 Sep 2022 00:07:51 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=Pymx5j8OuSeL6y3/zmmcT5pZ1GleZySiQYfezYGcffs=;\n b=bgB7JGYvTAPdjj46cbZb88Jrn3eMHO8lUvhbzT1GdvXvLFR1oLGxYj7ixVG1n8gQFOYv\n Qoght8XipS7c3vhLkkxzX4nBSC3sG/ekDKlYFR+XovuVMtHdYT6O4f9CPZocJk2zF+nP\n GlKxGFLWyHIDGlyn+lNwpfSWUMfMxBMCyFXSi7eD0TESDMXO6Jmz9tpt2+ByNU6dwdwQ\n HHTeUvEavGmOGtO1ibOcBpUzFk885r2UskTPEO0DxiqLFjZkjZkfQRy6BOP2+2BuMJCX\n j+sszy6x2l+FjQNbNqZVYokhMznJkQhkAOt0CRX8/A8bsuFJHRJ2UzM4gE/D2XFuOdPb Jw==", "From": "Hanumanth Pothula <hpothula@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, <andrew.rybchenko@oktetlabs.ru>, <xuan.ding@intel.com>,\n <wenxuanx.wu@intel.com>, <thomas@monjalon.net>, <xiaoyun.li@intel.com>,\n <stephen@networkplumber.org>, <yuanx.wang@intel.com>, <mdr@ashroe.eu>,\n <ferruh.yigit@xilinx.com>, <yuying.zhang@intel.com>,\n <qi.z.zhang@intel.com>, <viacheslavo@nvidia.com>, <jerinj@marvell.com>,\n Hanumanth Pothula <hpothula@marvell.com>", "Subject": "[PATCH v4 3/3] net/cnxk: Add support for mulitiple mbuf pools", "Date": "Thu, 15 Sep 2022 12:37:32 +0530", "Message-ID": "<20220915070732.182542-3-hpothula@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220915070732.182542-1-hpothula@marvell.com>", "References": "<20220902070047.2812906-1-hpothula@marvell.com>\n <20220915070732.182542-1-hpothula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "WsQ9l2BmSGsd0jgx4HcFacnNTzRvmSvH", "X-Proofpoint-ORIG-GUID": "WsQ9l2BmSGsd0jgx4HcFacnNTzRvmSvH", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1\n definitions=2022-09-15_03,2022-09-14_04,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Presently, HW is programmed only to receive packets from LPB pool.\nMaking all packets received from LPB pool.\n\nBut, CNXK HW supports two pools,\n - SPB -> packets with smaller size (less than 4K)\n - LPB -> packets with bigger size (greater than 4K)\n\nPatch enables multiple mempool capability, pool is selected based\non the packet's length. So, basically, PMD programs HW for receiving\npackets from both SPB and LPB pools based on the packet's length.\n\nThis is achieved by enabling rx multiple mempool offload,\nRTE_ETH_RX_OFFLOAD_MUL_MEMPOOL. This allows the application to send\nmore than one pool(in our case two) to the driver, with different\nsegment(packet) lengths, which helps the driver to configure both\npools based on segment lengths.\n\nThis is often useful for saving the memory where the application\ncan create a different pool to steer the specific size of the\npacket, thus enabling effective use of memory.\n\nSigned-off-by: Hanumanth Pothula <hpothula@marvell.com>\n---\n doc/guides/nics/features/cnxk.ini | 1 +\n doc/guides/nics/features/cnxk_vec.ini | 1 +\n drivers/net/cnxk/cnxk_ethdev.c | 77 +++++++++++++++++++++++----\n drivers/net/cnxk/cnxk_ethdev.h | 4 +-\n drivers/net/cnxk/cnxk_ethdev_ops.c | 3 ++\n 5 files changed, 76 insertions(+), 10 deletions(-)", "diff": "diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini\nindex 1876fe86c7..ed778ba398 100644\n--- a/doc/guides/nics/features/cnxk.ini\n+++ b/doc/guides/nics/features/cnxk.ini\n@@ -4,6 +4,7 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+multiple mempools = Y\n Speed capabilities = Y\n Rx interrupt = Y\n Lock-free Tx queue = Y\ndiff --git a/doc/guides/nics/features/cnxk_vec.ini b/doc/guides/nics/features/cnxk_vec.ini\nindex 5d0976e6ce..c2270fe338 100644\n--- a/doc/guides/nics/features/cnxk_vec.ini\n+++ b/doc/guides/nics/features/cnxk_vec.ini\n@@ -4,6 +4,7 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+multiple mempools = Y\n Speed capabilities = Y\n Rx interrupt = Y\n Lock-free Tx queue = Y\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex a089cc463b..5c962d6388 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -537,6 +537,51 @@ cnxk_nix_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid)\n \tplt_free(txq_sp);\n }\n \n+static int\n+cnxk_nix_process_rx_conf(const struct rte_eth_rxconf *rx_conf,\n+\t\t\t struct rte_mempool **lpb_pool, struct rte_mempool **spb_pool)\n+{\n+\tstruct rte_mempool *pool0;\n+\tstruct rte_mempool *pool1;\n+\tconst char *platform_ops;\n+\tstruct rte_mempool_ops *ops;\n+\n+\tif (*lpb_pool || !rx_conf->rx_mempool ||\n+\t rx_conf->rx_npool != CNXK_NIX_NUM_POOLS_MAX) {\n+\t\tplt_err(\"invalid arguments\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpool0 = rx_conf->rx_mempool[0].mp;\n+\tpool1 = rx_conf->rx_mempool[1].mp;\n+\n+\tif (pool0->elt_size > pool1->elt_size) {\n+\t\t*lpb_pool = pool0;\n+\t\t*spb_pool = pool1;\n+\n+\t} else {\n+\t\t*lpb_pool = pool1;\n+\t\t*spb_pool = pool0;\n+\t}\n+\n+\tif ((*spb_pool)->pool_id == 0) {\n+\t\tplt_err(\"Invalid pool_id\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tplatform_ops = rte_mbuf_platform_mempool_ops();\n+\tops = rte_mempool_get_ops((*spb_pool)->ops_index);\n+\tif (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {\n+\t\tplt_err(\"mempool ops should be of cnxk_npa type\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tplt_info(\"spb_pool:%s lpb_pool:%s lpb_len:%u spb_len:%u\\n\", (*spb_pool)->name,\n+\t\t (*lpb_pool)->name, (*lpb_pool)->elt_size, (*spb_pool)->elt_size);\n+\n+\treturn 0;\n+}\n+\n int\n cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\t\tuint32_t nb_desc, uint16_t fp_rx_q_sz,\n@@ -553,6 +598,8 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tuint16_t first_skip;\n \tint rc = -EINVAL;\n \tsize_t rxq_sz;\n+\tstruct rte_mempool *lpb_pool = mp;\n+\tstruct rte_mempool *spb_pool = NULL;\n \n \t/* Sanity checks */\n \tif (rx_conf->rx_deferred_start == 1) {\n@@ -560,15 +607,21 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\tgoto fail;\n \t}\n \n+\tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_MUL_MEMPOOL) {\n+\t\trc = cnxk_nix_process_rx_conf(rx_conf, &lpb_pool, &spb_pool);\n+\t\tif (rc)\n+\t\t\tgoto fail;\n+\t}\n+\n \tplatform_ops = rte_mbuf_platform_mempool_ops();\n \t/* This driver needs cnxk_npa mempool ops to work */\n-\tops = rte_mempool_get_ops(mp->ops_index);\n+\tops = rte_mempool_get_ops(lpb_pool->ops_index);\n \tif (strncmp(ops->name, platform_ops, RTE_MEMPOOL_OPS_NAMESIZE)) {\n \t\tplt_err(\"mempool ops should be of cnxk_npa type\");\n \t\tgoto fail;\n \t}\n \n-\tif (mp->pool_id == 0) {\n+\tif (lpb_pool->pool_id == 0) {\n \t\tplt_err(\"Invalid pool_id\");\n \t\tgoto fail;\n \t}\n@@ -585,13 +638,13 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t/* Its a no-op when inline device is not used */\n \tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY ||\n \t dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)\n-\t\troc_nix_inl_dev_xaq_realloc(mp->pool_id);\n+\t\troc_nix_inl_dev_xaq_realloc(lpb_pool->pool_id);\n \n \t/* Increase CQ size to Aura size to avoid CQ overflow and\n \t * then CPT buffer leak.\n \t */\n \tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)\n-\t\tnb_desc = nix_inl_cq_sz_clamp_up(nix, mp, nb_desc);\n+\t\tnb_desc = nix_inl_cq_sz_clamp_up(nix, lpb_pool, nb_desc);\n \n \t/* Setup ROC CQ */\n \tcq = &dev->cqs[qid];\n@@ -606,23 +659,29 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t/* Setup ROC RQ */\n \trq = &dev->rqs[qid];\n \trq->qid = qid;\n-\trq->aura_handle = mp->pool_id;\n+\trq->aura_handle = lpb_pool->pool_id;\n \trq->flow_tag_width = 32;\n \trq->sso_ena = false;\n \n \t/* Calculate first mbuf skip */\n \tfirst_skip = (sizeof(struct rte_mbuf));\n \tfirst_skip += RTE_PKTMBUF_HEADROOM;\n-\tfirst_skip += rte_pktmbuf_priv_size(mp);\n+\tfirst_skip += rte_pktmbuf_priv_size(lpb_pool);\n \trq->first_skip = first_skip;\n \trq->later_skip = sizeof(struct rte_mbuf);\n-\trq->lpb_size = mp->elt_size;\n+\trq->lpb_size = lpb_pool->elt_size;\n \trq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);\n \n \t/* Enable Inline IPSec on RQ, will not be used for Poll mode */\n \tif (roc_nix_inl_inb_is_enabled(nix))\n \t\trq->ipsech_ena = true;\n \n+\tif (spb_pool) {\n+\t\trq->spb_ena = 1;\n+\t\trq->spb_aura_handle = spb_pool->pool_id;\n+\t\trq->spb_size = spb_pool->elt_size;\n+\t}\n+\n \trc = roc_nix_rq_init(&dev->nix, rq, !!eth_dev->data->dev_started);\n \tif (rc) {\n \t\tplt_err(\"Failed to init roc rq for rq=%d, rc=%d\", qid, rc);\n@@ -645,7 +704,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t/* Queue config should reflect global offloads */\n \trxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;\n \trxq_sp->qconf.nb_desc = nb_desc;\n-\trxq_sp->qconf.mp = mp;\n+\trxq_sp->qconf.mp = lpb_pool;\n \trxq_sp->tc = 0;\n \trxq_sp->tx_pause = (dev->fc_cfg.mode == RTE_ETH_FC_FULL ||\n \t\t\t dev->fc_cfg.mode == RTE_ETH_FC_TX_PAUSE);\n@@ -664,7 +723,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\t\tgoto free_mem;\n \t}\n \n-\tplt_nix_dbg(\"rq=%d pool=%s nb_desc=%d->%d\", qid, mp->name, nb_desc,\n+\tplt_nix_dbg(\"rq=%d pool=%s nb_desc=%d->%d\", qid, lpb_pool->name, nb_desc,\n \t\t cq->nb_desc);\n \n \t/* Store start of fast path area */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex f11a9a0b63..194619e7b3 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -44,6 +44,8 @@\n #define CNXK_NIX_RX_DEFAULT_RING_SZ 4096\n /* Max supported SQB count */\n #define CNXK_NIX_TX_MAX_SQB 512\n+/* LPB & SPB */\n+#define CNXK_NIX_NUM_POOLS_MAX 2\n \n /* If PTP is enabled additional SEND MEM DESC is required which\n * takes 2 words, hence max 7 iova address are possible\n@@ -83,7 +85,7 @@\n \t RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | RTE_ETH_RX_OFFLOAD_SCATTER | \\\n \t RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | RTE_ETH_RX_OFFLOAD_RSS_HASH | \\\n \t RTE_ETH_RX_OFFLOAD_TIMESTAMP | RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \\\n-\t RTE_ETH_RX_OFFLOAD_SECURITY)\n+\t RTE_ETH_RX_OFFLOAD_MUL_MEMPOOL | RTE_ETH_RX_OFFLOAD_SECURITY)\n \n #define RSS_IPV4_ENABLE \\\n \t(RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | \\\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c\nindex 1592971073..49ca7a90f1 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_ops.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c\n@@ -69,6 +69,9 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)\n \tdevinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |\n \t\t\t RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP |\n \t\t\t RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;\n+\n+\tdevinfo->max_pools = CNXK_NIX_NUM_POOLS_MAX;\n+\n \treturn 0;\n }\n \n", "prefixes": [ "v4", "3/3" ] }