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GET /api/patches/116445/?format=api
{ "id": 116445, "url": "http://patchwork.dpdk.org/api/patches/116445/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20220919163731.1540454-8-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220919163731.1540454-8-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220919163731.1540454-8-dsosnowski@nvidia.com", "date": "2022-09-19T16:37:30", "name": "[7/7] app/flow-perf: add hairpin queue memory config", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "53efd240aabc127bc5563f2b8d173f12402ac4be", "submitter": { "id": 2386, "url": "http://patchwork.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20220919163731.1540454-8-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 24715, "url": "http://patchwork.dpdk.org/api/series/24715/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=24715", "date": "2022-09-19T16:37:23", "name": "ethdev: introduce hairpin memory capabilities", "version": 1, "mbox": "http://patchwork.dpdk.org/series/24715/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/116445/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/116445/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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b=kVO4ww9AFZaSFj2qJe1WNGY7Uj28qHEMhUHW4lo4fIT5QLlgmbSGlh+SQXBjZnlSO6N26eDVP+TR9N2jEW30lMko31zubOJjJlTqazrHncswyOf6/cdu4nkHQyR+BFroorE+HFO83AiIagY9n3CzofsFammvDp8uDYCUM4HYyclx/t2oSOCZ60jrPdPztLq/pmnbWJJr3eyQbLpKYp5XmxF3LYgia0vwkDQY0z1Yb65dk3wpX/aoTbw3XqJIrxUwmfivQjnu5cfjRd8uROOsmBTBSHd0gco5mdP9w5TSNoveAS4w8vL3sqPI6t/2xVQyORUI1gXWJBLFkbROOcawrQ==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Wisam Jaddo <wisamm@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 7/7] app/flow-perf: add hairpin queue memory config", "Date": "Mon, 19 Sep 2022 16:37:30 +0000", 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SFS:(13230022)(4636009)(346002)(39860400002)(376002)(136003)(396003)(451199015)(40470700004)(36840700001)(46966006)(36860700001)(8676002)(478600001)(36756003)(186003)(6636002)(70206006)(70586007)(37006003)(41300700001)(7696005)(6862004)(86362001)(7636003)(4326008)(8936002)(356005)(82310400005)(26005)(40460700003)(40480700001)(83380400001)(336012)(82740400003)(16526019)(55016003)(5660300002)(2616005)(6286002)(316002)(1076003)(47076005)(426003)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "19 Sep 2022 16:39:41.0058 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ed32985f-6ef1-4cfa-feba-08da9a5d8cd2", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT020.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB5000", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds the hairpin-conf command line parameter to flow-perf\napplication. hairpin-conf parameter takes a hexadecimal bitmask with\nbits having the following meaning:\n\n- Bit 0 - Force memory settings of hairpin RX queue.\n- Bit 1 - Force memory settings of hairpin TX queue.\n- Bit 4 - Use locked device memory for hairpin RX queue.\n- Bit 5 - Use RTE memory for hairpin RX queue.\n- Bit 8 - Use locked device memory for hairpin TX queue.\n- Bit 9 - Use RTE memory for hairpin TX queue.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n app/test-flow-perf/main.c | 32 ++++++++++++++++++++++++++++++++\n 1 file changed, 32 insertions(+)", "diff": "diff --git a/app/test-flow-perf/main.c b/app/test-flow-perf/main.c\nindex f375097028..4a9206803a 100644\n--- a/app/test-flow-perf/main.c\n+++ b/app/test-flow-perf/main.c\n@@ -46,6 +46,15 @@\n #define DEFAULT_RULES_BATCH 100000\n #define DEFAULT_GROUP 0\n \n+#define HAIRPIN_RX_CONF_FORCE_MEMORY (0x0001)\n+#define HAIRPIN_TX_CONF_FORCE_MEMORY (0x0002)\n+\n+#define HAIRPIN_RX_CONF_LOCKED_MEMORY (0x0010)\n+#define HAIRPIN_RX_CONF_RTE_MEMORY (0x0020)\n+\n+#define HAIRPIN_TX_CONF_LOCKED_MEMORY (0x0100)\n+#define HAIRPIN_TX_CONF_RTE_MEMORY (0x0200)\n+\n struct rte_flow *flow;\n static uint8_t flow_group;\n \n@@ -61,6 +70,7 @@ static uint32_t policy_id[MAX_PORTS];\n static uint8_t items_idx, actions_idx, attrs_idx;\n \n static uint64_t ports_mask;\n+static uint64_t hairpin_conf_mask;\n static uint16_t dst_ports[RTE_MAX_ETHPORTS];\n static volatile bool force_quit;\n static bool dump_iterations;\n@@ -482,6 +492,7 @@ usage(char *progname)\n \tprintf(\" --enable-fwd: To enable packets forwarding\"\n \t\t\" after insertion\\n\");\n \tprintf(\" --portmask=N: hexadecimal bitmask of ports used\\n\");\n+\tprintf(\" --hairpin-conf=0xXXXX: hexadecimal bitmask of hairpin queue configuration\\n\");\n \tprintf(\" --random-priority=N,S: use random priority levels \"\n \t\t\"from 0 to (N - 1) for flows \"\n \t\t\"and S as seed for pseudo-random number generator\\n\");\n@@ -629,6 +640,7 @@ static void\n args_parse(int argc, char **argv)\n {\n \tuint64_t pm, seed;\n+\tuint64_t hp_conf;\n \tchar **argvopt;\n \tuint32_t prio;\n \tchar *token;\n@@ -648,6 +660,7 @@ args_parse(int argc, char **argv)\n \t\t{ \"enable-fwd\", 0, 0, 0 },\n \t\t{ \"unique-data\", 0, 0, 0 },\n \t\t{ \"portmask\", 1, 0, 0 },\n+\t\t{ \"hairpin-conf\", 1, 0, 0 },\n \t\t{ \"cores\", 1, 0, 0 },\n \t\t{ \"random-priority\", 1, 0, 0 },\n \t\t{ \"meter-profile-alg\", 1, 0, 0 },\n@@ -880,6 +893,13 @@ args_parse(int argc, char **argv)\n \t\t\t\t\trte_exit(EXIT_FAILURE, \"Invalid fwd port mask\\n\");\n \t\t\t\tports_mask = pm;\n \t\t\t}\n+\t\t\tif (strcmp(lgopts[opt_idx].name, \"hairpin-conf\") == 0) {\n+\t\t\t\tend = NULL;\n+\t\t\t\thp_conf = strtoull(optarg, &end, 16);\n+\t\t\t\tif ((optarg[0] == '\\0') || (end == NULL) || (*end != '\\0'))\n+\t\t\t\t\trte_exit(EXIT_FAILURE, \"Invalid hairpin config mask\\n\");\n+\t\t\t\thairpin_conf_mask = hp_conf;\n+\t\t\t}\n \t\t\tif (strcmp(lgopts[opt_idx].name,\n \t\t\t\t\t\"port-id\") == 0) {\n \t\t\t\tuint16_t port_idx = 0;\n@@ -2035,6 +2055,12 @@ init_port(void)\n \t\t\t\thairpin_conf.peers[0].port = port_id;\n \t\t\t\thairpin_conf.peers[0].queue =\n \t\t\t\t\tstd_queue + tx_queues_count;\n+\t\t\t\thairpin_conf.use_locked_device_memory =\n+\t\t\t\t\t!!(hairpin_conf_mask & HAIRPIN_RX_CONF_LOCKED_MEMORY);\n+\t\t\t\thairpin_conf.use_rte_memory =\n+\t\t\t\t\t!!(hairpin_conf_mask & HAIRPIN_RX_CONF_RTE_MEMORY);\n+\t\t\t\thairpin_conf.force_memory =\n+\t\t\t\t\t!!(hairpin_conf_mask & HAIRPIN_RX_CONF_FORCE_MEMORY);\n \t\t\t\tret = rte_eth_rx_hairpin_queue_setup(\n \t\t\t\t\t\tport_id, hairpin_queue,\n \t\t\t\t\t\trxd_count, &hairpin_conf);\n@@ -2050,6 +2076,12 @@ init_port(void)\n \t\t\t\thairpin_conf.peers[0].port = port_id;\n \t\t\t\thairpin_conf.peers[0].queue =\n \t\t\t\t\tstd_queue + rx_queues_count;\n+\t\t\t\thairpin_conf.use_locked_device_memory =\n+\t\t\t\t\t!!(hairpin_conf_mask & HAIRPIN_TX_CONF_LOCKED_MEMORY);\n+\t\t\t\thairpin_conf.use_rte_memory =\n+\t\t\t\t\t!!(hairpin_conf_mask & HAIRPIN_TX_CONF_RTE_MEMORY);\n+\t\t\t\thairpin_conf.force_memory =\n+\t\t\t\t\t!!(hairpin_conf_mask & HAIRPIN_TX_CONF_FORCE_MEMORY);\n \t\t\t\tret = rte_eth_tx_hairpin_queue_setup(\n \t\t\t\t\t\tport_id, hairpin_queue,\n \t\t\t\t\t\ttxd_count, &hairpin_conf);\n", "prefixes": [ "7/7" ] }