Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/117321/?format=api
{ "id": 117321, "url": "http://patchwork.dpdk.org/api/patches/117321/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221004154047.35276-2-zhoumin@loongson.cn/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221004154047.35276-2-zhoumin@loongson.cn>", "list_archive_url": "https://inbox.dpdk.org/dev/20221004154047.35276-2-zhoumin@loongson.cn", "date": "2022-10-04T15:40:42", "name": "[v8,1/6] eal/loongarch: support LoongArch architecture", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c20e80965deea6448f3268ff6cef5cee01fafae8", "submitter": { "id": 2394, "url": "http://patchwork.dpdk.org/api/people/2394/?format=api", "name": "zhoumin", "email": "zhoumin@loongson.cn" }, "delegate": { "id": 24651, "url": "http://patchwork.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221004154047.35276-2-zhoumin@loongson.cn/mbox/", "series": [ { "id": 24969, "url": "http://patchwork.dpdk.org/api/series/24969/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=24969", "date": "2022-10-04T15:40:44", "name": "Introduce support for LoongArch architecture", "version": 8, "mbox": "http://patchwork.dpdk.org/series/24969/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/117321/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/117321/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8872EA00C4;\n\tTue, 4 Oct 2022 17:51:47 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4FEA54282D;\n\tTue, 4 Oct 2022 17:51:29 +0200 (CEST)", "from loongson.cn (mail.loongson.cn [114.242.206.163])\n by mails.dpdk.org (Postfix) with ESMTP id CDE0C410F2\n for <dev@dpdk.org>; Tue, 4 Oct 2022 17:51:24 +0200 (CEST)", "from localhost (unknown [114.241.48.130])\n by localhost.localdomain (Coremail) with SMTP id\n AQAAf8CxT+ADVDxjxfQlAA--.10361S2;\n Tue, 04 Oct 2022 23:40:51 +0800 (CST)" ], "From": "Min Zhou <zhoumin@loongson.cn>", "To": "thomas@monjalon.net, david.marchand@redhat.com,\n bruce.richardson@intel.com,\n anatoly.burakov@intel.com, qiming.yang@intel.com, Yuying.Zhang@intel.com,\n jgrajcia@cisco.com, konstantin.v.ananyev@yandex.ru, zhoumin@loongson.cn", "Cc": "dev@dpdk.org,\n\tmaobibo@loongson.cn", "Subject": "[PATCH v8 1/6] eal/loongarch: support LoongArch architecture", "Date": "Tue, 4 Oct 2022 23:40:42 +0800", "Message-Id": "<20221004154047.35276-2-zhoumin@loongson.cn>", "X-Mailer": "git-send-email 2.32.1 (Apple Git-133)", "In-Reply-To": "<20221004154047.35276-1-zhoumin@loongson.cn>", "References": "<20221004154047.35276-1-zhoumin@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "AQAAf8CxT+ADVDxjxfQlAA--.10361S2", "X-Coremail-Antispam": "1UD129KBjvAXoWfXFWDtF17Gw48Xw4DZF45GFg_yoWrXr4DJo\n WSqF43uw4kCrWUu3sYkr9xJ3yUWr92kan8AF1fCr4rGF1Sy3s8JFykKw4YvF43ArZ5Ja45\n C3y8KFZ3JrW7Jr4kn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3\n AaLaJ3UjIYCTnIWjp_UUUY67AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E6xAIw20EY4v20xva\n j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2\n x7M28EF7xvwVC0I7IYx2IY67AKxVWUJVWUCwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8\n JVWxJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r\n 4UJVWxJr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2Wl\n Yx0E2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbV\n WUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7Cj\n xVA2Y2ka0xkIwI1lc2xSY4AK67AK6ryrMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4\n AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE\n 17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMI\n IF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4l\n IxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvf\n C2KfnxnUUI43ZEXa7VUbOB_UUUUUU==", "X-CM-SenderInfo": "52kr3ztlq6z05rqj20fqof0/", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add all necessary elements for DPDK to compile and run EAL on\nLoongArch64 Soc.\n\nThis includes:\n\n- EAL library implementation for LoongArch ISA.\n- meson build structure for 'loongarch' architecture.\n RTE_ARCH_LOONGARCH define is added for architecture identification.\n- xmm_t structure operation stubs as there is no vector support in\n the current version for LoongArch.\n\nCompilation was tested on Debian and CentOS using loongarch64\ncross-compile toolchain from x86 build hosts. Functions were tested\non Loongnix and Kylin which are two Linux distributions supported\nLoongArch host based on Linux 4.19 maintained by Loongson\nCorporation.\n\nWe also tested DPDK on LoongArch with some external applications,\nincluding: Pktgen-DPDK, OVS, VPP.\n\nThe platform is currently marked as linux-only because there is no\nother OS than Linux support LoongArch host currently.\n\nThe i40e PMD driver is disabled on LoongArch because of the absence\nof vector support in the current version.\n\nSimilar to RISC-V, the compilation of following modules has been\ndisabled by this commit and will be re-enabled in later commits as\nfixes are introduced:\nnet/ixgbe, net/memif, net/tap, example/l3fwd.\n\nSigned-off-by: Min Zhou <zhoumin@loongson.cn>\n---\n MAINTAINERS | 6 ++\n app/test/test_xmmt_ops.h | 12 +++\n .../loongarch/loongarch_loongarch64_linux_gcc | 16 +++\n config/loongarch/meson.build | 43 ++++++++\n devtools/test-meson-builds.sh | 4 +\n doc/guides/contributing/design.rst | 2 +-\n .../cross_build_dpdk_for_loongarch.rst | 97 +++++++++++++++++++\n doc/guides/linux_gsg/index.rst | 1 +\n doc/guides/nics/features.rst | 8 ++\n doc/guides/nics/features/default.ini | 1 +\n doc/guides/rel_notes/release_22_11.rst | 7 ++\n drivers/net/i40e/meson.build | 6 ++\n drivers/net/ixgbe/meson.build | 6 ++\n drivers/net/memif/meson.build | 6 ++\n drivers/net/tap/meson.build | 6 ++\n examples/l3fwd/meson.build | 6 ++\n lib/eal/linux/eal_memory.c | 4 +\n lib/eal/loongarch/include/meson.build | 18 ++++\n lib/eal/loongarch/include/rte_atomic.h | 47 +++++++++\n lib/eal/loongarch/include/rte_byteorder.h | 40 ++++++++\n lib/eal/loongarch/include/rte_cpuflags.h | 39 ++++++++\n lib/eal/loongarch/include/rte_cycles.h | 47 +++++++++\n lib/eal/loongarch/include/rte_io.h | 18 ++++\n lib/eal/loongarch/include/rte_memcpy.h | 61 ++++++++++++\n lib/eal/loongarch/include/rte_pause.h | 24 +++++\n .../loongarch/include/rte_power_intrinsics.h | 20 ++++\n lib/eal/loongarch/include/rte_prefetch.h | 47 +++++++++\n lib/eal/loongarch/include/rte_rwlock.h | 42 ++++++++\n lib/eal/loongarch/include/rte_spinlock.h | 64 ++++++++++++\n lib/eal/loongarch/include/rte_vect.h | 65 +++++++++++++\n lib/eal/loongarch/meson.build | 11 +++\n lib/eal/loongarch/rte_cpuflags.c | 93 ++++++++++++++++++\n lib/eal/loongarch/rte_cycles.c | 45 +++++++++\n lib/eal/loongarch/rte_hypervisor.c | 11 +++\n lib/eal/loongarch/rte_power_intrinsics.c | 53 ++++++++++\n meson.build | 2 +\n 36 files changed, 977 insertions(+), 1 deletion(-)\n create mode 100644 config/loongarch/loongarch_loongarch64_linux_gcc\n create mode 100644 config/loongarch/meson.build\n create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst\n create mode 100644 lib/eal/loongarch/include/meson.build\n create mode 100644 lib/eal/loongarch/include/rte_atomic.h\n create mode 100644 lib/eal/loongarch/include/rte_byteorder.h\n create mode 100644 lib/eal/loongarch/include/rte_cpuflags.h\n create mode 100644 lib/eal/loongarch/include/rte_cycles.h\n create mode 100644 lib/eal/loongarch/include/rte_io.h\n create mode 100644 lib/eal/loongarch/include/rte_memcpy.h\n create mode 100644 lib/eal/loongarch/include/rte_pause.h\n create mode 100644 lib/eal/loongarch/include/rte_power_intrinsics.h\n create mode 100644 lib/eal/loongarch/include/rte_prefetch.h\n create mode 100644 lib/eal/loongarch/include/rte_rwlock.h\n create mode 100644 lib/eal/loongarch/include/rte_spinlock.h\n create mode 100644 lib/eal/loongarch/include/rte_vect.h\n create mode 100644 lib/eal/loongarch/meson.build\n create mode 100644 lib/eal/loongarch/rte_cpuflags.c\n create mode 100644 lib/eal/loongarch/rte_cycles.c\n create mode 100644 lib/eal/loongarch/rte_hypervisor.c\n create mode 100644 lib/eal/loongarch/rte_power_intrinsics.c", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex a55b379d73..5472fccf61 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -294,6 +294,12 @@ F: app/*/*_neon.*\n F: examples/*/*_neon.*\n F: examples/common/neon/\n \n+LoongArch\n+M: Min Zhou <zhoumin@loongson.cn>\n+F: config/loongarch/\n+F: doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst\n+F: lib/eal/loongarch/\n+\n IBM POWER (alpha)\n M: David Christensen <drc@linux.vnet.ibm.com>\n F: config/ppc/\ndiff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h\nindex 55f256599e..626aa9bcba 100644\n--- a/app/test/test_xmmt_ops.h\n+++ b/app/test/test_xmmt_ops.h\n@@ -65,6 +65,18 @@ vect_set_epi32(int i3, int i2, int i1, int i0)\n \treturn data;\n }\n \n+#elif defined(RTE_ARCH_LOONGARCH)\n+\n+#define vect_loadu_sil128(p) vect_load_128(p)\n+\n+/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */\n+static __rte_always_inline xmm_t\n+vect_set_epi32(int i3, int i2, int i1, int i0)\n+{\n+\txmm_t data = (xmm_t){.u32 = {i0, i1, i2, i3}};\n+\n+\treturn data;\n+}\n #endif\n \n #endif /* _TEST_XMMT_OPS_H_ */\ndiff --git a/config/loongarch/loongarch_loongarch64_linux_gcc b/config/loongarch/loongarch_loongarch64_linux_gcc\nnew file mode 100644\nindex 0000000000..c9330223ad\n--- /dev/null\n+++ b/config/loongarch/loongarch_loongarch64_linux_gcc\n@@ -0,0 +1,16 @@\n+[binaries]\n+c = ['ccache', 'loongarch64-unknown-linux-gnu-gcc']\n+cpp = ['ccache', 'loongarch64-unknown-linux-gnu-g++']\n+ar = 'loongarch64-unknown-linux-gnu-gcc-ar'\n+strip = 'loongarch64-unknown-linux-gnu-strip'\n+pcap-config = ''\n+\n+[host_machine]\n+system = 'linux'\n+cpu_family = 'loongarch64'\n+cpu = '3a5000'\n+endian = 'little'\n+\n+[properties]\n+implementor_id = 'generic'\n+implementor_pn = 'default'\ndiff --git a/config/loongarch/meson.build b/config/loongarch/meson.build\nnew file mode 100644\nindex 0000000000..99dabef203\n--- /dev/null\n+++ b/config/loongarch/meson.build\n@@ -0,0 +1,43 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2022 Loongson Technology Corporation Limited\n+\n+if not dpdk_conf.get('RTE_ARCH_64')\n+ error('Only 64-bit compiles are supported for this platform type')\n+endif\n+dpdk_conf.set('RTE_ARCH', 'loongarch')\n+dpdk_conf.set('RTE_ARCH_LOONGARCH', 1)\n+dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)\n+\n+machine_args_generic = [\n+ ['default', ['-march=loongarch64']],\n+]\n+\n+flags_generic = [\n+ ['RTE_MACHINE', '\"loongarch64\"'],\n+ ['RTE_MAX_LCORE', 64],\n+ ['RTE_MAX_NUMA_NODES', 16],\n+ ['RTE_CACHE_LINE_SIZE', 64]]\n+\n+impl_generic = ['Generic loongarch', flags_generic, machine_args_generic]\n+\n+machine = []\n+machine_args = []\n+\n+machine = impl_generic\n+impl_pn = 'default'\n+\n+message('Implementer : ' + machine[0])\n+foreach flag: machine[1]\n+ if flag.length() > 0\n+ dpdk_conf.set(flag[0], flag[1])\n+ endif\n+endforeach\n+\n+foreach marg: machine[2]\n+ if marg[0] == impl_pn\n+ foreach f: marg[1]\n+ machine_args += f\n+ endforeach\n+ endif\n+endforeach\n+message(machine_args)\ndiff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh\nindex 04a85fe987..e20a1c1df3 100755\n--- a/devtools/test-meson-builds.sh\n+++ b/devtools/test-meson-builds.sh\n@@ -260,6 +260,10 @@ build build-x86-mingw $f skipABI -Dexamples=helloworld\n f=$srcdir/config/arm/arm64_armv8_linux_gcc\n build build-arm64-generic-gcc $f ABI $use_shared\n \n+# generic LoongArch\n+f=$srcdir/config/loongarch/loongarch_loongarch64_linux_gcc\n+build build-loongarch64-generic-gcc $f ABI $use_shared\n+\n # IBM POWER\n f=$srcdir/config/ppc/ppc64le-power8-linux-gcc\n build build-ppc64-power8-gcc $f ABI $use_shared\ndiff --git a/doc/guides/contributing/design.rst b/doc/guides/contributing/design.rst\nindex 0383afe5c8..d24a7ff6a0 100644\n--- a/doc/guides/contributing/design.rst\n+++ b/doc/guides/contributing/design.rst\n@@ -42,7 +42,7 @@ Per Architecture Sources\n The following macro options can be used:\n \n * ``RTE_ARCH`` is a string that contains the name of the architecture.\n-* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.\n+* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_LOONGARCH``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.\n \n Per Execution Environment Sources\n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\ndiff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst\nnew file mode 100644\nindex 0000000000..979d075a90\n--- /dev/null\n+++ b/doc/guides/linux_gsg/cross_build_dpdk_for_loongarch.rst\n@@ -0,0 +1,97 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2022 Loongson Technology Corporation Limited\n+\n+Cross compiling DPDK for LoongArch\n+==================================\n+\n+This chapter describes how to cross compile DPDK for LoongArch from x86 build\n+hosts.\n+\n+.. note::\n+\n+ Due to some of the code under review, the current Linux 5.19 cannot boot\n+ on LoongArch system. There are still some Linux distributions that have\n+ supported LoongArch host, such as Anolis OS, Kylin, Loongnix and UOS. These\n+ distributions base on Linux kernel 4.19 supported by Loongson Corporation.\n+ Because LoongArch is such a new platform with many fundamental pieces of\n+ software still under development, it is currently recommended to cross\n+ compile DPDK on x86 for LoongArch.\n+\n+\n+Prerequisites\n+-------------\n+\n+Ensure that you have all pre-requisites for building DPDK natively as those\n+will be required also for cross-compilation.\n+\n+Linux kernel\n+~~~~~~~~~~~~\n+\n+Make sure that LoongArch host is running Linux kernel 4.19 or newer supported\n+by Loongson Corporation. The support for LoongArch in the current Linux 5.19\n+is not complete because it still misses some patches to add for other\n+subsystems.\n+\n+GNU toolchain\n+-------------\n+\n+Obtain the cross toolchain\n+~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+The build process was tested using:\n+\n+* Latest `LoongArch GNU toolchain\n+ <https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz>`_\n+ on Debian 10.4 or CentOS 8.\n+\n+Alternatively the toolchain may be built straight from the source. There is a\n+script to do that. But adding the whole script in this documentation is too\n+much. If you want to generate your own cross toolchain, you can refer to this\n+thread `Introduce support for LoongArch architecture\n+<https://inbox.dpdk.org/dev/53b50799-cb29-7ee6-be89-4fe21566e127@loongson.cn/T/#m1da99578f85894a4ddcd8e39d8239869e6a501d1>`_.\n+Before you start running the script, you may need to install some dependencies.\n+For instance, if you want to run this script in a RHEL 8 system, you can use\n+the following command to install these packages:\n+\n+.. code-block:: console\n+\n+ subscription-manager repos --enable codeready-builder-for-rhel-8-x86_64-rpms\n+ dnf install bison diffutils file flex gcc gcc-c++ git gmp-devel libtool make python3 rsync texinfo wget xz zlib-devel ccache\n+\n+To download cross tools from github we can use the following command:\n+\n+.. code-block:: console\n+\n+ wget -P /tmp/ https://github.com/loongson/build-tools/releases/download/2022.08.11/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz\n+\n+Unzip and add into the PATH\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+After downloading the cross-tools file, we need unzip and add those executable\n+binaries into the PATH as follows:\n+\n+.. code-block:: console\n+\n+ tar -xvf /tmp/loongarch64-clfs-5.1-cross-tools-gcc-glibc.tar.xz -C <cross_tool_install_dir> --strip-components 1\n+ export PATH=$PATH:<cross_tool_install_dir>/bin\n+\n+\n+Cross Compiling DPDK with GNU toolchain using Meson\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+To cross-compile DPDK for generic LoongArch we can use the following command:\n+\n+.. code-block:: console\n+\n+ meson cross-build --cross-file config/loongarch/loongarch_loongarch64_linux_gcc\n+ ninja -C cross-build\n+\n+Supported cross-compilation targets\n+-----------------------------------\n+\n+Currently the following target is supported:\n+\n+* Generic LoongArch64 ISA: ``config/loongarch/loongarch_loongarch64_linux_gcc``\n+\n+To add a new target support, a corresponding cross-file has to be added to\n+``config/loongarch`` directory.\ndiff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst\nindex 747552c385..c3e67bf9ec 100644\n--- a/doc/guides/linux_gsg/index.rst\n+++ b/doc/guides/linux_gsg/index.rst\n@@ -14,6 +14,7 @@ Getting Started Guide for Linux\n sys_reqs\n build_dpdk\n cross_build_dpdk_for_arm64\n+ cross_build_dpdk_for_loongarch\n cross_build_dpdk_for_riscv\n linux_drivers\n build_sample_apps\ndiff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst\nindex b0bc4c79b0..c4ab65adf8 100644\n--- a/doc/guides/nics/features.rst\n+++ b/doc/guides/nics/features.rst\n@@ -832,6 +832,14 @@ ARMv8\n Support armv8a (64bit) architecture.\n \n \n+.. _nic_features_loongarch64:\n+\n+LoongArch64\n+-----------\n+\n+Support 64-bit LoongArch architecture.\n+\n+\n .. _nic_features_power8:\n \n Power8\ndiff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini\nindex f7192cb0da..cbc17c0434 100644\n--- a/doc/guides/nics/features/default.ini\n+++ b/doc/guides/nics/features/default.ini\n@@ -71,6 +71,7 @@ Linux =\n Windows =\n ARMv7 =\n ARMv8 =\n+LoongArch64 =\n Power8 =\n rv64 =\n x86-32 =\ndiff --git a/doc/guides/rel_notes/release_22_11.rst b/doc/guides/rel_notes/release_22_11.rst\nindex 5d8ef669b8..dab08d58cf 100644\n--- a/doc/guides/rel_notes/release_22_11.rst\n+++ b/doc/guides/rel_notes/release_22_11.rst\n@@ -55,6 +55,13 @@ New Features\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* **Added initial LoongArch architecture support.**\n+\n+ * Added EAL implementation for LoongArch architecture. The initial devices\n+ the porting was tested on included Loongson 3A5000, Loongson 3C5000 and\n+ Loongson 3C5000L. In theory this implementation should work with any target\n+ based on ``LoongArch`` ISA.\n+\n * **Added configuration for asynchronous flow connection tracking.**\n \n Added connection tracking action number hint to ``rte_flow_configure``\ndiff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build\nindex 84fd42754e..e00c1a9ef9 100644\n--- a/drivers/net/i40e/meson.build\n+++ b/drivers/net/i40e/meson.build\n@@ -1,6 +1,12 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2017 Intel Corporation\n \n+if arch_subdir == 'loongarch'\n+ build = false\n+ reason = 'not supported on LoongArch'\n+ subdir_done()\n+endif\n+\n if arch_subdir == 'riscv'\n build = false\n reason = 'not supported on RISC-V'\ndiff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build\nindex a18908ef7c..80ab012448 100644\n--- a/drivers/net/ixgbe/meson.build\n+++ b/drivers/net/ixgbe/meson.build\n@@ -1,6 +1,12 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2017 Intel Corporation\n \n+if arch_subdir == 'loongarch'\n+ build = false\n+ reason = 'not supported on LoongArch'\n+ subdir_done()\n+endif\n+\n cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']\n \n subdir('base')\ndiff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build\nindex 680bc8631c..30c0fbc798 100644\n--- a/drivers/net/memif/meson.build\n+++ b/drivers/net/memif/meson.build\n@@ -1,6 +1,12 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright 2018-2019 Cisco Systems, Inc. All rights reserved.\n \n+if arch_subdir == 'loongarch'\n+ build = false\n+ reason = 'not supported on LoongArch'\n+ subdir_done()\n+endif\n+\n if not is_linux\n build = false\n reason = 'only supported on Linux'\ndiff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build\nindex c09713a67b..f0d03069cd 100644\n--- a/drivers/net/tap/meson.build\n+++ b/drivers/net/tap/meson.build\n@@ -1,6 +1,12 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright 2018 Luca Boccassi <bluca@debian.org>\n \n+if arch_subdir == 'loongarch'\n+ build = false\n+ reason = 'not supported on LoongArch'\n+ subdir_done()\n+endif\n+\n if not is_linux\n build = false\n reason = 'only supported on Linux'\ndiff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build\nindex b40244a941..d2f2d96099 100644\n--- a/examples/l3fwd/meson.build\n+++ b/examples/l3fwd/meson.build\n@@ -6,6 +6,12 @@\n # To build this example as a standalone application with an already-installed\n # DPDK instance, use 'make'\n \n+if arch_subdir == 'loongarch'\n+ build = false\n+ reason = 'not supported on LoongArch'\n+ subdir_done()\n+endif\n+\n allow_experimental_apis = true\n deps += ['acl', 'hash', 'lpm', 'fib', 'eventdev']\n sources = files(\ndiff --git a/lib/eal/linux/eal_memory.c b/lib/eal/linux/eal_memory.c\nindex c890c42106..60fc8cc6ca 100644\n--- a/lib/eal/linux/eal_memory.c\n+++ b/lib/eal/linux/eal_memory.c\n@@ -77,7 +77,11 @@ uint64_t eal_get_baseaddr(void)\n \t * rte_mem_check_dma_mask for ensuring all memory is within supported\n \t * range.\n \t */\n+#if defined(RTE_ARCH_LOONGARCH)\n+\treturn 0x7000000000ULL;\n+#else\n \treturn 0x100000000ULL;\n+#endif\n }\n \n /*\ndiff --git a/lib/eal/loongarch/include/meson.build b/lib/eal/loongarch/include/meson.build\nnew file mode 100644\nindex 0000000000..6e8d12601a\n--- /dev/null\n+++ b/lib/eal/loongarch/include/meson.build\n@@ -0,0 +1,18 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2022 Loongson Technology Corporation Limited\n+\n+arch_headers = files(\n+ 'rte_atomic.h',\n+ 'rte_byteorder.h',\n+ 'rte_cpuflags.h',\n+ 'rte_cycles.h',\n+ 'rte_io.h',\n+ 'rte_memcpy.h',\n+ 'rte_pause.h',\n+ 'rte_power_intrinsics.h',\n+ 'rte_prefetch.h',\n+ 'rte_rwlock.h',\n+ 'rte_spinlock.h',\n+ 'rte_vect.h',\n+)\n+install_headers(arch_headers, subdir: get_option('include_subdir_arch'))\ndiff --git a/lib/eal/loongarch/include/rte_atomic.h b/lib/eal/loongarch/include/rte_atomic.h\nnew file mode 100644\nindex 0000000000..3c8284517e\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_atomic.h\n@@ -0,0 +1,47 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef RTE_ATOMIC_LOONGARCH_H\n+#define RTE_ATOMIC_LOONGARCH_H\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+# error Platform must be built with RTE_FORCE_INTRINSICS\n+#endif\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_common.h>\n+#include \"generic/rte_atomic.h\"\n+\n+#define rte_mb()\tdo { asm volatile(\"dbar 0\":::\"memory\"); } while (0)\n+\n+#define rte_wmb()\trte_mb()\n+\n+#define rte_rmb()\trte_mb()\n+\n+#define rte_smp_mb()\trte_mb()\n+\n+#define rte_smp_wmb()\trte_mb()\n+\n+#define rte_smp_rmb()\trte_mb()\n+\n+#define rte_io_mb()\trte_mb()\n+\n+#define rte_io_wmb()\trte_mb()\n+\n+#define rte_io_rmb()\trte_mb()\n+\n+static __rte_always_inline void\n+rte_atomic_thread_fence(int memorder)\n+{\n+\t__atomic_thread_fence(memorder);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_ATOMIC_LOONGARCH_H */\ndiff --git a/lib/eal/loongarch/include/rte_byteorder.h b/lib/eal/loongarch/include/rte_byteorder.h\nnew file mode 100644\nindex 0000000000..0da6097a4f\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_byteorder.h\n@@ -0,0 +1,40 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef RTE_BYTEORDER_LOONGARCH_H\n+#define RTE_BYTEORDER_LOONGARCH_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_byteorder.h\"\n+\n+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n+\n+#define rte_cpu_to_le_16(x) (x)\n+#define rte_cpu_to_le_32(x) (x)\n+#define rte_cpu_to_le_64(x) (x)\n+\n+#define rte_cpu_to_be_16(x) rte_bswap16(x)\n+#define rte_cpu_to_be_32(x) rte_bswap32(x)\n+#define rte_cpu_to_be_64(x) rte_bswap64(x)\n+\n+#define rte_le_to_cpu_16(x) (x)\n+#define rte_le_to_cpu_32(x) (x)\n+#define rte_le_to_cpu_64(x) (x)\n+\n+#define rte_be_to_cpu_16(x) rte_bswap16(x)\n+#define rte_be_to_cpu_32(x) rte_bswap32(x)\n+#define rte_be_to_cpu_64(x) rte_bswap64(x)\n+\n+#else /* RTE_BIG_ENDIAN */\n+#error \"LoongArch not support big endian!\"\n+#endif\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_BYTEORDER_LOONGARCH_H */\ndiff --git a/lib/eal/loongarch/include/rte_cpuflags.h b/lib/eal/loongarch/include/rte_cpuflags.h\nnew file mode 100644\nindex 0000000000..1c80779262\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_cpuflags.h\n@@ -0,0 +1,39 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef RTE_CPUFLAGS_LOONGARCH_H\n+#define RTE_CPUFLAGS_LOONGARCH_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/**\n+ * Enumeration of all CPU features supported\n+ */\n+enum rte_cpu_flag_t {\n+\tRTE_CPUFLAG_CPUCFG = 0,\n+\tRTE_CPUFLAG_LAM,\n+\tRTE_CPUFLAG_UAL,\n+\tRTE_CPUFLAG_FPU,\n+\tRTE_CPUFLAG_LSX,\n+\tRTE_CPUFLAG_LASX,\n+\tRTE_CPUFLAG_CRC32,\n+\tRTE_CPUFLAG_COMPLEX,\n+\tRTE_CPUFLAG_CRYPTO,\n+\tRTE_CPUFLAG_LVZ,\n+\tRTE_CPUFLAG_LBT_X86,\n+\tRTE_CPUFLAG_LBT_ARM,\n+\tRTE_CPUFLAG_LBT_MIPS,\n+\t/* The last item */\n+\tRTE_CPUFLAG_NUMFLAGS /**< This should always be the last! */\n+};\n+\n+#include \"generic/rte_cpuflags.h\"\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_CPUFLAGS_LOONGARCH_H */\ndiff --git a/lib/eal/loongarch/include/rte_cycles.h b/lib/eal/loongarch/include/rte_cycles.h\nnew file mode 100644\nindex 0000000000..f612d1ad10\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_cycles.h\n@@ -0,0 +1,47 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef RTE_CYCLES_LOONGARCH_H\n+#define RTE_CYCLES_LOONGARCH_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_cycles.h\"\n+\n+/**\n+ * Read the time base register.\n+ *\n+ * @return\n+ * The time base for this lcore.\n+ */\n+static inline uint64_t\n+rte_rdtsc(void)\n+{\n+\tuint64_t count;\n+\n+\t__asm__ __volatile__ (\n+\t\t\"rdtime.d %[cycles], $zero\\n\"\n+\t\t: [cycles] \"=r\" (count)\n+\t\t::\n+\t\t);\n+\treturn count;\n+}\n+\n+static inline uint64_t\n+rte_rdtsc_precise(void)\n+{\n+\trte_mb();\n+\treturn rte_rdtsc();\n+}\n+\n+static inline uint64_t\n+rte_get_tsc_cycles(void) { return rte_rdtsc(); }\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_CYCLES_LOONGARCH_H */\ndiff --git a/lib/eal/loongarch/include/rte_io.h b/lib/eal/loongarch/include/rte_io.h\nnew file mode 100644\nindex 0000000000..40e40efa86\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_io.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef RTE_IO_LOONGARCH_H\n+#define RTE_IO_LOONGARCH_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_io.h\"\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_IO_LOONGARCH_H */\ndiff --git a/lib/eal/loongarch/include/rte_memcpy.h b/lib/eal/loongarch/include/rte_memcpy.h\nnew file mode 100644\nindex 0000000000..22578d40f4\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_memcpy.h\n@@ -0,0 +1,61 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef RTE_MEMCPY_LOONGARCH_H\n+#define RTE_MEMCPY_LOONGARCH_H\n+\n+#include <stdint.h>\n+#include <string.h>\n+\n+#include \"rte_common.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_memcpy.h\"\n+\n+static inline void\n+rte_mov16(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 16);\n+}\n+\n+static inline void\n+rte_mov32(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 32);\n+}\n+\n+static inline void\n+rte_mov48(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 48);\n+}\n+\n+static inline void\n+rte_mov64(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 64);\n+}\n+\n+static inline void\n+rte_mov128(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 128);\n+}\n+\n+static inline void\n+rte_mov256(uint8_t *dst, const uint8_t *src)\n+{\n+\tmemcpy(dst, src, 256);\n+}\n+\n+#define rte_memcpy(d, s, n)\tmemcpy((d), (s), (n))\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_MEMCPY_LOONGARCH_H */\ndiff --git a/lib/eal/loongarch/include/rte_pause.h b/lib/eal/loongarch/include/rte_pause.h\nnew file mode 100644\nindex 0000000000..4302e1b9be\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_pause.h\n@@ -0,0 +1,24 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef RTE_PAUSE_LOONGARCH_H\n+#define RTE_PAUSE_LOONGARCH_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"rte_atomic.h\"\n+\n+#include \"generic/rte_pause.h\"\n+\n+static inline void rte_pause(void)\n+{\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_PAUSE_LOONGARCH_H */\ndiff --git a/lib/eal/loongarch/include/rte_power_intrinsics.h b/lib/eal/loongarch/include/rte_power_intrinsics.h\nnew file mode 100644\nindex 0000000000..d5dbd94567\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_power_intrinsics.h\n@@ -0,0 +1,20 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef RTE_POWER_INTRINSIC_LOONGARCH_H\n+#define RTE_POWER_INTRINSIC_LOONGARCH_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_common.h>\n+\n+#include \"generic/rte_power_intrinsics.h\"\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_POWER_INTRINSIC_LOONGARCH_H */\ndiff --git a/lib/eal/loongarch/include/rte_prefetch.h b/lib/eal/loongarch/include/rte_prefetch.h\nnew file mode 100644\nindex 0000000000..ac18318fe4\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_prefetch.h\n@@ -0,0 +1,47 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef RTE_PREFETCH_LOONGARCH_H\n+#define RTE_PREFETCH_LOONGARCH_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_common.h>\n+#include \"generic/rte_prefetch.h\"\n+\n+static inline void rte_prefetch0(const volatile void *p)\n+{\n+\t__builtin_prefetch((const void *)(uintptr_t)p, 0, 3);\n+}\n+\n+static inline void rte_prefetch1(const volatile void *p)\n+{\n+\t__builtin_prefetch((const void *)(uintptr_t)p, 0, 2);\n+}\n+\n+static inline void rte_prefetch2(const volatile void *p)\n+{\n+\t__builtin_prefetch((const void *)(uintptr_t)p, 0, 1);\n+}\n+\n+static inline void rte_prefetch_non_temporal(const volatile void *p)\n+{\n+\t/* non-temporal version not available, fallback to rte_prefetch0 */\n+\trte_prefetch0(p);\n+}\n+\n+__rte_experimental\n+static inline void\n+rte_cldemote(const volatile void *p)\n+{\n+\tRTE_SET_USED(p);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_PREFETCH_LOONGARCH_H */\ndiff --git a/lib/eal/loongarch/include/rte_rwlock.h b/lib/eal/loongarch/include/rte_rwlock.h\nnew file mode 100644\nindex 0000000000..aedc6f3349\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_rwlock.h\n@@ -0,0 +1,42 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef RTE_RWLOCK_LOONGARCH_H\n+#define RTE_RWLOCK_LOONGARCH_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"generic/rte_rwlock.h\"\n+\n+static inline void\n+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_read_lock(rwl);\n+}\n+\n+static inline void\n+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_read_unlock(rwl);\n+}\n+\n+static inline void\n+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_write_lock(rwl);\n+}\n+\n+static inline void\n+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)\n+{\n+\trte_rwlock_write_unlock(rwl);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_RWLOCK_LOONGARCH_H */\ndiff --git a/lib/eal/loongarch/include/rte_spinlock.h b/lib/eal/loongarch/include/rte_spinlock.h\nnew file mode 100644\nindex 0000000000..e8d34e9728\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_spinlock.h\n@@ -0,0 +1,64 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef RTE_SPINLOCK_LOONGARCH_H\n+#define RTE_SPINLOCK_LOONGARCH_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <rte_common.h>\n+#include \"generic/rte_spinlock.h\"\n+\n+#ifndef RTE_FORCE_INTRINSICS\n+# error Platform must be built with RTE_FORCE_INTRINSICS\n+#endif\n+\n+static inline int rte_tm_supported(void)\n+{\n+\treturn 0;\n+}\n+\n+static inline void\n+rte_spinlock_lock_tm(rte_spinlock_t *sl)\n+{\n+\trte_spinlock_lock(sl); /* fall-back */\n+}\n+\n+static inline int\n+rte_spinlock_trylock_tm(rte_spinlock_t *sl)\n+{\n+\treturn rte_spinlock_trylock(sl);\n+}\n+\n+static inline void\n+rte_spinlock_unlock_tm(rte_spinlock_t *sl)\n+{\n+\trte_spinlock_unlock(sl);\n+}\n+\n+static inline void\n+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)\n+{\n+\trte_spinlock_recursive_lock(slr); /* fall-back */\n+}\n+\n+static inline void\n+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)\n+{\n+\trte_spinlock_recursive_unlock(slr);\n+}\n+\n+static inline int\n+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)\n+{\n+\treturn rte_spinlock_recursive_trylock(slr);\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_SPINLOCK_LOONGARCH_H */\ndiff --git a/lib/eal/loongarch/include/rte_vect.h b/lib/eal/loongarch/include/rte_vect.h\nnew file mode 100644\nindex 0000000000..15465151e1\n--- /dev/null\n+++ b/lib/eal/loongarch/include/rte_vect.h\n@@ -0,0 +1,65 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#ifndef RTE_VECT_LOONGARCH_H\n+#define RTE_VECT_LOONGARCH_H\n+\n+#include <stdint.h>\n+#include \"generic/rte_vect.h\"\n+#include \"rte_common.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED\n+\n+typedef union xmm {\n+\tint8_t i8[16];\n+\tint16_t i16[8];\n+\tint32_t i32[4];\n+\tint64_t i64[2];\n+\tuint8_t u8[16];\n+\tuint16_t u16[8];\n+\tuint32_t u32[4];\n+\tuint64_t u64[2];\n+\tdouble pd[2];\n+} __rte_aligned(16) xmm_t;\n+\n+#define XMM_SIZE (sizeof(xmm_t))\n+#define XMM_MASK (XMM_SIZE - 1)\n+\n+typedef union rte_xmm {\n+\txmm_t\t x;\n+\tuint8_t\t u8[XMM_SIZE / sizeof(uint8_t)];\n+\tuint16_t u16[XMM_SIZE / sizeof(uint16_t)];\n+\tuint32_t u32[XMM_SIZE / sizeof(uint32_t)];\n+\tuint64_t u64[XMM_SIZE / sizeof(uint64_t)];\n+\tdouble pd[XMM_SIZE / sizeof(double)];\n+} __rte_aligned(16) rte_xmm_t;\n+\n+static inline xmm_t\n+vect_load_128(void *p)\n+{\n+\txmm_t ret = *((xmm_t *)p);\n+\n+\treturn ret;\n+}\n+\n+static inline xmm_t\n+vect_and(xmm_t data, xmm_t mask)\n+{\n+\trte_xmm_t ret = {.x = data };\n+\trte_xmm_t m = {.x = mask };\n+\tret.u64[0] &= m.u64[0];\n+\tret.u64[1] &= m.u64[1];\n+\n+\treturn ret.x;\n+}\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_VECT_LOONGARCH_H */\ndiff --git a/lib/eal/loongarch/meson.build b/lib/eal/loongarch/meson.build\nnew file mode 100644\nindex 0000000000..4dcc27babb\n--- /dev/null\n+++ b/lib/eal/loongarch/meson.build\n@@ -0,0 +1,11 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2022 Loongson Technology Corporation Limited\n+\n+subdir('include')\n+\n+sources += files(\n+ 'rte_cpuflags.c',\n+ 'rte_cycles.c',\n+ 'rte_hypervisor.c',\n+ 'rte_power_intrinsics.c',\n+)\ndiff --git a/lib/eal/loongarch/rte_cpuflags.c b/lib/eal/loongarch/rte_cpuflags.c\nnew file mode 100644\nindex 0000000000..0a75ca58d4\n--- /dev/null\n+++ b/lib/eal/loongarch/rte_cpuflags.c\n@@ -0,0 +1,93 @@\n+/*\n+ * SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#include \"rte_cpuflags.h\"\n+\n+#include <elf.h>\n+#include <fcntl.h>\n+#include <assert.h>\n+#include <unistd.h>\n+#include <string.h>\n+\n+/* Symbolic values for the entries in the auxiliary table */\n+#define AT_HWCAP 16\n+\n+/* software based registers */\n+enum cpu_register_t {\n+\tREG_NONE = 0,\n+\tREG_HWCAP,\n+\tREG_MAX\n+};\n+\n+typedef uint32_t hwcap_registers_t[REG_MAX];\n+\n+struct feature_entry {\n+\tuint32_t reg;\n+\tuint32_t bit;\n+#define CPU_FLAG_NAME_MAX_LEN 64\n+\tchar name[CPU_FLAG_NAME_MAX_LEN];\n+};\n+\n+#define FEAT_DEF(name, reg, bit) \\\n+\t[RTE_CPUFLAG_##name] = {reg, bit, #name},\n+\n+const struct feature_entry rte_cpu_feature_table[] = {\n+\tFEAT_DEF(CPUCFG, REG_HWCAP, 0)\n+\tFEAT_DEF(LAM, REG_HWCAP, 1)\n+\tFEAT_DEF(UAL, REG_HWCAP, 2)\n+\tFEAT_DEF(FPU, REG_HWCAP, 3)\n+\tFEAT_DEF(LSX, REG_HWCAP, 4)\n+\tFEAT_DEF(LASX, REG_HWCAP, 5)\n+\tFEAT_DEF(CRC32, REG_HWCAP, 6)\n+\tFEAT_DEF(COMPLEX, REG_HWCAP, 7)\n+\tFEAT_DEF(CRYPTO, REG_HWCAP, 8)\n+\tFEAT_DEF(LVZ, REG_HWCAP, 9)\n+\tFEAT_DEF(LBT_X86, REG_HWCAP, 10)\n+\tFEAT_DEF(LBT_ARM, REG_HWCAP, 11)\n+\tFEAT_DEF(LBT_MIPS, REG_HWCAP, 12)\n+};\n+\n+/*\n+ * Read AUXV software register and get cpu features for LoongArch\n+ */\n+static void\n+rte_cpu_get_features(hwcap_registers_t out)\n+{\n+\tout[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);\n+}\n+\n+/*\n+ * Checks if a particular flag is available on current machine.\n+ */\n+int\n+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)\n+{\n+\tconst struct feature_entry *feat;\n+\thwcap_registers_t regs = {0};\n+\n+\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n+\t\treturn -ENOENT;\n+\n+\tfeat = &rte_cpu_feature_table[feature];\n+\tif (feat->reg == REG_NONE)\n+\t\treturn -EFAULT;\n+\n+\trte_cpu_get_features(regs);\n+\treturn (regs[feat->reg] >> feat->bit) & 1;\n+}\n+\n+const char *\n+rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)\n+{\n+\tif (feature >= RTE_CPUFLAG_NUMFLAGS)\n+\t\treturn NULL;\n+\treturn rte_cpu_feature_table[feature].name;\n+}\n+\n+void\n+rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)\n+{\n+\tmemset(intrinsics, 0, sizeof(*intrinsics));\n+}\ndiff --git a/lib/eal/loongarch/rte_cycles.c b/lib/eal/loongarch/rte_cycles.c\nnew file mode 100644\nindex 0000000000..582601d335\n--- /dev/null\n+++ b/lib/eal/loongarch/rte_cycles.c\n@@ -0,0 +1,45 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#include \"eal_private.h\"\n+\n+#define LOONGARCH_CPUCFG4\t0x4\n+#define CPUCFG4_CCFREQ_MASK\t0xFFFFFFFF\n+#define CPUCFG4_CCFREQ_SHIFT\t0\n+\n+#define LOONGARCH_CPUCFG5\t0x5\n+#define CPUCFG5_CCMUL_MASK\t0xFFFF\n+#define CPUCFG5_CCMUL_SHIFT\t0\n+\n+#define CPUCFG5_CCDIV_MASK\t0xFFFF0000\n+#define CPUCFG5_CCDIV_SHIFT\t16\n+\n+static __rte_noinline uint32_t\n+read_cpucfg(int arg)\n+{\n+\tint ret = 0;\n+\n+\t__asm__ __volatile__ (\n+\t\t\"cpucfg %[var], %[index]\\n\"\n+\t\t: [var]\"=r\"(ret)\n+\t\t: [index]\"r\"(arg)\n+\t\t:\n+\t\t);\n+\n+\treturn ret;\n+}\n+\n+uint64_t\n+get_tsc_freq_arch(void)\n+{\n+\tuint32_t base_freq, mul_factor, div_factor;\n+\n+\tbase_freq = read_cpucfg(LOONGARCH_CPUCFG4);\n+\tmul_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCMUL_MASK) >>\n+\t\tCPUCFG5_CCMUL_SHIFT;\n+\tdiv_factor = (read_cpucfg(LOONGARCH_CPUCFG5) & CPUCFG5_CCDIV_MASK) >>\n+\t\tCPUCFG5_CCDIV_SHIFT;\n+\n+\treturn base_freq * mul_factor / div_factor;\n+}\ndiff --git a/lib/eal/loongarch/rte_hypervisor.c b/lib/eal/loongarch/rte_hypervisor.c\nnew file mode 100644\nindex 0000000000..d044906f71\n--- /dev/null\n+++ b/lib/eal/loongarch/rte_hypervisor.c\n@@ -0,0 +1,11 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#include \"rte_hypervisor.h\"\n+\n+enum rte_hypervisor\n+rte_hypervisor_get(void)\n+{\n+\treturn RTE_HYPERVISOR_UNKNOWN;\n+}\ndiff --git a/lib/eal/loongarch/rte_power_intrinsics.c b/lib/eal/loongarch/rte_power_intrinsics.c\nnew file mode 100644\nindex 0000000000..a8969c260e\n--- /dev/null\n+++ b/lib/eal/loongarch/rte_power_intrinsics.c\n@@ -0,0 +1,53 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Loongson Technology Corporation Limited\n+ */\n+\n+#include <errno.h>\n+\n+#include \"rte_power_intrinsics.h\"\n+\n+/**\n+ * This function is not supported on LOONGARCH.\n+ */\n+int\n+rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n+\t\tconst uint64_t tsc_timestamp)\n+{\n+\tRTE_SET_USED(pmc);\n+\tRTE_SET_USED(tsc_timestamp);\n+\n+\treturn -ENOTSUP;\n+}\n+\n+/**\n+ * This function is not supported on LOONGARCH.\n+ */\n+int\n+rte_power_pause(const uint64_t tsc_timestamp)\n+{\n+\tRTE_SET_USED(tsc_timestamp);\n+\n+\treturn -ENOTSUP;\n+}\n+\n+/**\n+ * This function is not supported on LOONGARCH.\n+ */\n+int\n+rte_power_monitor_wakeup(const unsigned int lcore_id)\n+{\n+\tRTE_SET_USED(lcore_id);\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[],\n+\t\tconst uint32_t num, const uint64_t tsc_timestamp)\n+{\n+\tRTE_SET_USED(pmc);\n+\tRTE_SET_USED(num);\n+\tRTE_SET_USED(tsc_timestamp);\n+\n+\treturn -ENOTSUP;\n+}\ndiff --git a/meson.build b/meson.build\nindex 7d6643da3a..8b1b09ead5 100644\n--- a/meson.build\n+++ b/meson.build\n@@ -52,6 +52,8 @@ if host_machine.cpu_family().startswith('x86')\n arch_subdir = 'x86'\n elif host_machine.cpu_family().startswith('arm') or host_machine.cpu_family().startswith('aarch')\n arch_subdir = 'arm'\n+elif host_machine.cpu_family().startswith('loongarch')\n+ arch_subdir = 'loongarch'\n elif host_machine.cpu_family().startswith('ppc')\n arch_subdir = 'ppc'\n elif host_machine.cpu_family().startswith('riscv')\n", "prefixes": [ "v8", "1/6" ] }