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GET /api/patches/118776/?format=api
{ "id": 118776, "url": "http://patchwork.dpdk.org/api/patches/118776/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221020103656.1068036-7-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221020103656.1068036-7-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221020103656.1068036-7-junfeng.guo@intel.com", "date": "2022-10-20T10:36:54", "name": "[v6,6/8] net/gve: add support for dev info get and dev configure", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d6d81b5311c120157c7aaa932497232621e20b28", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221020103656.1068036-7-junfeng.guo@intel.com/mbox/", "series": [ { "id": 25340, "url": "http://patchwork.dpdk.org/api/series/25340/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25340", "date": "2022-10-20T10:36:48", "name": "introduce GVE PMD", "version": 6, "mbox": "http://patchwork.dpdk.org/series/25340/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/118776/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/118776/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C4D2EA0581;\n\tThu, 20 Oct 2022 12:39:10 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1CB9742D45;\n\tThu, 20 Oct 2022 12:38:52 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id A78D942D3A\n for <dev@dpdk.org>; Thu, 20 Oct 2022 12:38:49 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 20 Oct 2022 03:38:49 -0700", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by fmsmga004.fm.intel.com with ESMTP; 20 Oct 2022 03:38:46 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1666262329; x=1697798329;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=+ftQCRhTVozVP7bcdM+MfqRffvLXfBxLiszsPb0xGEQ=;\n b=Wg0r4kLlLF54QQrGwWeoYUhgh2YJHr8gDzMxDItpbr6X+V0/YCiJ3MHG\n jqkdqrBD77tDvlVYzYJtOT1AJIEZQDx4tC13xk5lhiGVlrjDMk2Xt2I5y\n mkkz1YOXjs63y7+oP/I46cP5KFS92OUYn2OA+bEtN3Ik6Xfsr3HkIQAbK\n QutoEwbSNoCKlc4BOHFJxaOdmMsuBabey8PfgBQr250+8OcClz9UoRe61\n YbjwrW9SdCjDkVP8oaJbyqfGcI9RfKQJnzydUwhAyhOlItKfYmE8y7WaF\n rx9BR2fgs3yocTsRJI9oJ1oiU42AbdxtcDK13nYZZi5nVlTQI3Rv6FFhV w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10505\"; a=\"308354925\"", "E=Sophos;i=\"5.95,198,1661842800\"; d=\"scan'208\";a=\"308354925\"", "E=McAfee;i=\"6500,9779,10505\"; a=\"698582908\"", "E=Sophos;i=\"5.95,198,1661842800\"; d=\"scan'208\";a=\"698582908\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@xilinx.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, xiaoyun.li@intel.com, awogbemila@google.com,\n bruce.richardson@intel.com, hemant.agrawal@nxp.com,\n stephen@networkplumber.org, chenbo.xia@intel.com, helin.zhang@intel.com,\n Junfeng Guo <junfeng.guo@intel.com>", "Subject": "[PATCH v6 6/8] net/gve: add support for dev info get and dev\n configure", "Date": "Thu, 20 Oct 2022 18:36:54 +0800", "Message-Id": "<20221020103656.1068036-7-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20221020103656.1068036-1-junfeng.guo@intel.com>", "References": "<20221010101757.878317-2-junfeng.guo@intel.com>\n <20221020103656.1068036-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add dev_ops dev_infos_get.\nComplete dev_configure with RX offloads configuration.\n\nSigned-off-by: Xiaoyun Li <xiaoyun.li@intel.com>\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n doc/guides/nics/features/gve.ini | 2 ++\n doc/guides/nics/gve.rst | 1 +\n drivers/net/gve/gve_ethdev.c | 56 +++++++++++++++++++++++++++++++-\n 3 files changed, 58 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/nics/features/gve.ini b/doc/guides/nics/features/gve.ini\nindex d1703d8dab..986df7f94a 100644\n--- a/doc/guides/nics/features/gve.ini\n+++ b/doc/guides/nics/features/gve.ini\n@@ -4,8 +4,10 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+Speed capabilities = Y\n Link status = Y\n MTU update = Y\n+RSS hash = Y\n Linux = Y\n x86-32 = Y\n x86-64 = Y\ndiff --git a/doc/guides/nics/gve.rst b/doc/guides/nics/gve.rst\nindex c42ff23841..8c09a5a7fa 100644\n--- a/doc/guides/nics/gve.rst\n+++ b/doc/guides/nics/gve.rst\n@@ -62,6 +62,7 @@ In this release, the GVE PMD provides the basic functionality of packet\n reception and transmission.\n Supported features of the GVE PMD are:\n \n+- Receiver Side Scaling (RSS)\n - Link state information\n \n Currently, only GQI_QPL and GQI_RDA queue format are supported in PMD.\ndiff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex 1968f38eb6..5be8d664f3 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -29,8 +29,13 @@ gve_write_version(uint8_t *driver_version_register)\n }\n \n static int\n-gve_dev_configure(__rte_unused struct rte_eth_dev *dev)\n+gve_dev_configure(struct rte_eth_dev *dev)\n {\n+\tstruct gve_priv *priv = dev->data->dev_private;\n+\n+\tif (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO)\n+\t\tpriv->enable_rsc = 1;\n+\n \treturn 0;\n }\n \n@@ -94,6 +99,54 @@ gve_dev_close(struct rte_eth_dev *dev)\n \treturn err;\n }\n \n+static int\n+gve_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n+{\n+\tstruct gve_priv *priv = dev->data->dev_private;\n+\n+\tdev_info->device = dev->device;\n+\tdev_info->max_mac_addrs = 1;\n+\tdev_info->max_rx_queues = priv->max_nb_rxq;\n+\tdev_info->max_tx_queues = priv->max_nb_txq;\n+\tdev_info->min_rx_bufsize = GVE_MIN_BUF_SIZE;\n+\tdev_info->max_rx_pktlen = GVE_MAX_RX_PKTLEN;\n+\tdev_info->max_mtu = RTE_ETHER_MTU;\n+\tdev_info->min_mtu = RTE_ETHER_MIN_MTU;\n+\n+\tdev_info->rx_offload_capa = 0;\n+\tdev_info->tx_offload_capa = 0;\n+\n+\tif (priv->queue_format == GVE_DQO_RDA_FORMAT)\n+\t\tdev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TCP_LRO;\n+\n+\tdev_info->default_rxconf = (struct rte_eth_rxconf) {\n+\t\t.rx_free_thresh = GVE_DEFAULT_RX_FREE_THRESH,\n+\t\t.rx_drop_en = 0,\n+\t\t.offloads = 0,\n+\t};\n+\n+\tdev_info->default_txconf = (struct rte_eth_txconf) {\n+\t\t.tx_free_thresh = GVE_DEFAULT_TX_FREE_THRESH,\n+\t\t.offloads = 0,\n+\t};\n+\n+\tdev_info->default_rxportconf.ring_size = priv->rx_desc_cnt;\n+\tdev_info->rx_desc_lim = (struct rte_eth_desc_lim) {\n+\t\t.nb_max = priv->rx_desc_cnt,\n+\t\t.nb_min = priv->rx_desc_cnt,\n+\t\t.nb_align = 1,\n+\t};\n+\n+\tdev_info->default_txportconf.ring_size = priv->tx_desc_cnt;\n+\tdev_info->tx_desc_lim = (struct rte_eth_desc_lim) {\n+\t\t.nb_max = priv->tx_desc_cnt,\n+\t\t.nb_min = priv->tx_desc_cnt,\n+\t\t.nb_align = 1,\n+\t};\n+\n+\treturn 0;\n+}\n+\n static int\n gve_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)\n {\n@@ -125,6 +178,7 @@ static const struct eth_dev_ops gve_eth_dev_ops = {\n \t.dev_start = gve_dev_start,\n \t.dev_stop = gve_dev_stop,\n \t.dev_close = gve_dev_close,\n+\t.dev_infos_get = gve_dev_info_get,\n \t.link_update = gve_link_update,\n \t.mtu_set = gve_dev_mtu_set,\n };\n", "prefixes": [ "v6", "6/8" ] }