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GET /api/patches/119004/?format=api
{ "id": 119004, "url": "http://patchwork.dpdk.org/api/patches/119004/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221024130134.1046536-15-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221024130134.1046536-15-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221024130134.1046536-15-junfeng.guo@intel.com", "date": "2022-10-24T13:01:34", "name": "[v10,14/14] net/idpf: add support for timestamp offload", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "53c75d08dcf78417b9004a4ec22dbbb7f166dd9f", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221024130134.1046536-15-junfeng.guo@intel.com/mbox/", "series": [ { "id": 25385, "url": "http://patchwork.dpdk.org/api/series/25385/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25385", "date": "2022-10-24T13:01:20", "name": "add support for idpf PMD in DPDK", "version": 10, "mbox": "http://patchwork.dpdk.org/series/25385/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/119004/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/119004/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 774D4A034C;\n\tMon, 24 Oct 2022 15:05:37 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EF07342BB9;\n\tMon, 24 Oct 2022 15:04:57 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 4031E42B8E\n for <dev@dpdk.org>; Mon, 24 Oct 2022 15:04:54 +0200 (CEST)", "from orsmga002.jf.intel.com ([10.7.209.21])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 24 Oct 2022 06:03:43 -0700", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by orsmga002.jf.intel.com with ESMTP; 24 Oct 2022 06:03:40 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1666616694; x=1698152694;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=VhJvx0pGpx3HVYR4cZYRjx8EnojXaUiG0rnziT7m9xg=;\n b=HafcKWP9/DiQgB9/W49asdcdUiJx0LaebqkoBDNxhYJV4Sp7YnDSqpt4\n zZg0Mum0gA+1DoY5M238XyIk5uCRV54c1z1EmDu/Ufs8bH3F4iGL9tD6A\n NbbM2nFgPK8/rCAEylAMgR7/gzWZ7QDlIlasrED3yqpKM/pKNOg9jhyLz\n Cm57KCcDj19dpMMFJ+T4yij75ty42ctyrziVHdwz/8w8E7HVLzvQJ7yX2\n b8xY2oxyHheHOFo7RCDZnmRlnNHFLSQN0ff4QEkbdYWBPpqtW4XFgmKLs\n 7tRuZtDFGhL7CNw9iMWjArUMYgooSD5RBVUJvl8oshLpp00Gy53NtBTgk g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10510\"; a=\"305018962\"", "E=Sophos;i=\"5.95,209,1661842800\"; d=\"scan'208\";a=\"305018962\"", "E=McAfee;i=\"6500,9779,10510\"; a=\"631248537\"", "E=Sophos;i=\"5.95,209,1661842800\"; d=\"scan'208\";a=\"631248537\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "andrew.rybchenko@oktetlabs.ru, qi.z.zhang@intel.com,\n jingjing.wu@intel.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, Junfeng Guo <junfeng.guo@intel.com>,\n Wenjing Qiao <wenjing.qiao@intel.com>", "Subject": "[PATCH v10 14/14] net/idpf: add support for timestamp offload", "Date": "Mon, 24 Oct 2022 21:01:34 +0800", "Message-Id": "<20221024130134.1046536-15-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20221024130134.1046536-1-junfeng.guo@intel.com>", "References": "<20221021051821.2164939-2-junfeng.guo@intel.com>\n <20221024130134.1046536-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for timestamp offload.\n\nSigned-off-by: Wenjing Qiao <wenjing.qiao@intel.com>\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n doc/guides/nics/features/idpf.ini | 1 +\n drivers/net/idpf/idpf_ethdev.c | 5 +-\n drivers/net/idpf/idpf_ethdev.h | 3 ++\n drivers/net/idpf/idpf_rxtx.c | 65 ++++++++++++++++++++++\n drivers/net/idpf/idpf_rxtx.h | 90 +++++++++++++++++++++++++++++++\n 5 files changed, 163 insertions(+), 1 deletion(-)", "diff": "diff --git a/doc/guides/nics/features/idpf.ini b/doc/guides/nics/features/idpf.ini\nindex 47c686762d..0a0ffc2c29 100644\n--- a/doc/guides/nics/features/idpf.ini\n+++ b/doc/guides/nics/features/idpf.ini\n@@ -12,5 +12,6 @@ MTU update = Y\n TSO = P\n L3 checksum offload = P\n L4 checksum offload = P\n+Timestamp offload = P\n Packet type parsing = Y\n Linux = Y\ndiff --git a/drivers/net/idpf/idpf_ethdev.c b/drivers/net/idpf/idpf_ethdev.c\nindex 21315866bf..bd33fd1797 100644\n--- a/drivers/net/idpf/idpf_ethdev.c\n+++ b/drivers/net/idpf/idpf_ethdev.c\n@@ -21,6 +21,8 @@ rte_spinlock_t idpf_adapter_lock;\n struct idpf_adapter_list idpf_adapter_list;\n bool idpf_adapter_list_init;\n \n+uint64_t idpf_timestamp_dynflag;\n+\n static const char * const idpf_valid_args[] = {\n \tIDPF_TX_SINGLE_Q,\n \tIDPF_RX_SINGLE_Q,\n@@ -100,7 +102,8 @@ idpf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\tRTE_ETH_RX_OFFLOAD_UDP_CKSUM\t\t|\n \t\tRTE_ETH_RX_OFFLOAD_TCP_CKSUM\t\t|\n \t\tRTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM\t|\n-\t\tRTE_ETH_RX_OFFLOAD_RSS_HASH;\n+\t\tRTE_ETH_RX_OFFLOAD_RSS_HASH\t\t|\n+\t\tRTE_ETH_RX_OFFLOAD_TIMESTAMP;\n \n \tdev_info->tx_offload_capa =\n \t\tRTE_ETH_TX_OFFLOAD_TCP_TSO\t\t|\ndiff --git a/drivers/net/idpf/idpf_ethdev.h b/drivers/net/idpf/idpf_ethdev.h\nindex 2485b3a784..d6080aff81 100644\n--- a/drivers/net/idpf/idpf_ethdev.h\n+++ b/drivers/net/idpf/idpf_ethdev.h\n@@ -185,6 +185,9 @@ struct idpf_adapter {\n \tbool tx_vec_allowed;\n \tbool rx_use_avx512;\n \tbool tx_use_avx512;\n+\n+\t/* For PTP */\n+\tuint64_t time_hw;\n };\n \n TAILQ_HEAD(idpf_adapter_list, idpf_adapter);\ndiff --git a/drivers/net/idpf/idpf_rxtx.c b/drivers/net/idpf/idpf_rxtx.c\nindex abef84b3b0..90b2111781 100644\n--- a/drivers/net/idpf/idpf_rxtx.c\n+++ b/drivers/net/idpf/idpf_rxtx.c\n@@ -10,6 +10,8 @@\n #include \"idpf_rxtx.h\"\n #include \"idpf_rxtx_vec_common.h\"\n \n+static int idpf_timestamp_dynfield_offset = -1;\n+\n const uint32_t *\n idpf_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)\n {\n@@ -941,6 +943,24 @@ idpf_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \t\treturn idpf_tx_split_queue_setup(dev, queue_idx, nb_desc,\n \t\t\t\t\t\t socket_id, tx_conf);\n }\n+\n+static int\n+idpf_register_ts_mbuf(struct idpf_rx_queue *rxq)\n+{\n+\tint err;\n+\tif ((rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) != 0) {\n+\t\t/* Register mbuf field and flag for Rx timestamp */\n+\t\terr = rte_mbuf_dyn_rx_timestamp_register(&idpf_timestamp_dynfield_offset,\n+\t\t\t\t\t\t\t &idpf_timestamp_dynflag);\n+\t\tif (err != 0) {\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t\"Cannot register mbuf field/flag for timestamp\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\treturn 0;\n+}\n+\n static int\n idpf_alloc_single_rxq_mbufs(struct idpf_rx_queue *rxq)\n {\n@@ -1034,6 +1054,13 @@ idpf_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \t\treturn -EINVAL;\n \t}\n \n+\terr = idpf_register_ts_mbuf(rxq);\n+\tif (err != 0) {\n+\t\tPMD_DRV_LOG(ERR, \"fail to regidter timestamp mbuf %u\",\n+\t\t\t\t\trx_queue_id);\n+\t\treturn -EIO;\n+\t}\n+\n \tif (rxq->bufq1 == NULL) {\n \t\t/* Single queue */\n \t\terr = idpf_alloc_single_rxq_mbufs(rxq);\n@@ -1396,6 +1423,7 @@ idpf_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \tstruct idpf_rx_queue *rxq;\n \tconst uint32_t *ptype_tbl;\n \tuint8_t status_err0_qw1;\n+\tstruct idpf_adapter *ad;\n \tstruct rte_mbuf *rxm;\n \tuint16_t rx_id_bufq1;\n \tuint16_t rx_id_bufq2;\n@@ -1405,9 +1433,11 @@ idpf_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \tuint16_t gen_id;\n \tuint16_t rx_id;\n \tuint16_t nb_rx;\n+\tuint64_t ts_ns;\n \n \tnb_rx = 0;\n \trxq = (struct idpf_rx_queue *)rx_queue;\n+\tad = rxq->adapter;\n \n \tif (unlikely(rxq == NULL) || unlikely(!rxq->q_started))\n \t\treturn nb_rx;\n@@ -1419,6 +1449,9 @@ idpf_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t (volatile struct virtchnl2_rx_flex_desc_adv_nic_3 *)rxq->rx_ring;\n \tptype_tbl = rxq->adapter->ptype_tbl;\n \n+\tif ((rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) != 0)\n+\t\trxq->hw_register_set = 1;\n+\n \twhile (nb_rx < nb_pkts) {\n \t\trx_desc = &rx_desc_ring[rx_id];\n \n@@ -1474,6 +1507,18 @@ idpf_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\tstatus_err0_qw1 = rx_desc->status_err0_qw1;\n \t\tpkt_flags = idpf_splitq_rx_csum_offload(status_err0_qw1);\n \t\tpkt_flags |= idpf_splitq_rx_rss_offload(rxm, rx_desc);\n+\t\tif (idpf_timestamp_dynflag > 0 &&\n+\t\t (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)) {\n+\t\t\t/* timestamp */\n+\t\t\tts_ns = idpf_tstamp_convert_32b_64b(ad,\n+\t\t\t\trxq->hw_register_set,\n+\t\t\t\trte_le_to_cpu_32(rx_desc->ts_high));\n+\t\t\trxq->hw_register_set = 0;\n+\t\t\t*RTE_MBUF_DYNFIELD(rxm,\n+\t\t\t\t\t idpf_timestamp_dynfield_offset,\n+\t\t\t\t\t rte_mbuf_timestamp_t *) = ts_ns;\n+\t\t\trxm->ol_flags |= idpf_timestamp_dynflag;\n+\t\t}\n \n \t\trxm->ol_flags |= pkt_flags;\n \n@@ -1775,18 +1820,22 @@ idpf_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \tconst uint32_t *ptype_tbl;\n \tuint16_t rx_id, nb_hold;\n \tstruct rte_eth_dev *dev;\n+\tstruct idpf_adapter *ad;\n \tuint16_t rx_packet_len;\n \tstruct rte_mbuf *rxm;\n \tstruct rte_mbuf *nmb;\n \tuint16_t rx_status0;\n \tuint64_t pkt_flags;\n \tuint64_t dma_addr;\n+\tuint64_t ts_ns;\n \tuint16_t nb_rx;\n \n \tnb_rx = 0;\n \tnb_hold = 0;\n \trxq = rx_queue;\n \n+\tad = rxq->adapter;\n+\n \tif (unlikely(rxq == NULL) || unlikely(!rxq->q_started))\n \t\treturn nb_rx;\n \n@@ -1794,6 +1843,9 @@ idpf_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \trx_ring = rxq->rx_ring;\n \tptype_tbl = rxq->adapter->ptype_tbl;\n \n+\tif ((rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) != 0)\n+\t\trxq->hw_register_set = 1;\n+\n \twhile (nb_rx < nb_pkts) {\n \t\trxdp = &rx_ring[rx_id];\n \t\trx_status0 = rte_le_to_cpu_16(rxdp->flex_nic_wb.status_error0);\n@@ -1853,6 +1905,19 @@ idpf_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,\n \n \t\trxm->ol_flags |= pkt_flags;\n \n+\t\tif (idpf_timestamp_dynflag > 0 &&\n+\t\t (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) != 0) {\n+\t\t\t/* timestamp */\n+\t\t\tts_ns = idpf_tstamp_convert_32b_64b(ad,\n+\t\t\t\trxq->hw_register_set,\n+\t\t\t\trte_le_to_cpu_32(rxd.flex_nic_wb.flex_ts.ts_high));\n+\t\t\trxq->hw_register_set = 0;\n+\t\t\t*RTE_MBUF_DYNFIELD(rxm,\n+\t\t\t\t\t idpf_timestamp_dynfield_offset,\n+\t\t\t\t\t rte_mbuf_timestamp_t *) = ts_ns;\n+\t\t\trxm->ol_flags |= idpf_timestamp_dynflag;\n+\t\t}\n+\n \t\trx_pkts[nb_rx++] = rxm;\n \t}\n \trxq->rx_tail = rx_id;\ndiff --git a/drivers/net/idpf/idpf_rxtx.h b/drivers/net/idpf/idpf_rxtx.h\nindex e808710b41..6e7fbaf7ef 100644\n--- a/drivers/net/idpf/idpf_rxtx.h\n+++ b/drivers/net/idpf/idpf_rxtx.h\n@@ -7,6 +7,41 @@\n \n #include \"idpf_ethdev.h\"\n \n+/* MTS */\n+#define GLTSYN_CMD_SYNC_0_0\t(PF_TIMESYNC_BASE + 0x0)\n+#define PF_GLTSYN_SHTIME_0_0\t(PF_TIMESYNC_BASE + 0x4)\n+#define PF_GLTSYN_SHTIME_L_0\t(PF_TIMESYNC_BASE + 0x8)\n+#define PF_GLTSYN_SHTIME_H_0\t(PF_TIMESYNC_BASE + 0xC)\n+#define GLTSYN_ART_L_0\t\t(PF_TIMESYNC_BASE + 0x10)\n+#define GLTSYN_ART_H_0\t\t(PF_TIMESYNC_BASE + 0x14)\n+#define PF_GLTSYN_SHTIME_0_1\t(PF_TIMESYNC_BASE + 0x24)\n+#define PF_GLTSYN_SHTIME_L_1\t(PF_TIMESYNC_BASE + 0x28)\n+#define PF_GLTSYN_SHTIME_H_1\t(PF_TIMESYNC_BASE + 0x2C)\n+#define PF_GLTSYN_SHTIME_0_2\t(PF_TIMESYNC_BASE + 0x44)\n+#define PF_GLTSYN_SHTIME_L_2\t(PF_TIMESYNC_BASE + 0x48)\n+#define PF_GLTSYN_SHTIME_H_2\t(PF_TIMESYNC_BASE + 0x4C)\n+#define PF_GLTSYN_SHTIME_0_3\t(PF_TIMESYNC_BASE + 0x64)\n+#define PF_GLTSYN_SHTIME_L_3\t(PF_TIMESYNC_BASE + 0x68)\n+#define PF_GLTSYN_SHTIME_H_3\t(PF_TIMESYNC_BASE + 0x6C)\n+\n+#define PF_TIMESYNC_BAR4_BASE\t0x0E400000\n+#define GLTSYN_ENA\t\t(PF_TIMESYNC_BAR4_BASE + 0x90)\n+#define GLTSYN_CMD\t\t(PF_TIMESYNC_BAR4_BASE + 0x94)\n+#define GLTSYC_TIME_L\t\t(PF_TIMESYNC_BAR4_BASE + 0x104)\n+#define GLTSYC_TIME_H\t\t(PF_TIMESYNC_BAR4_BASE + 0x108)\n+\n+#define GLTSYN_CMD_SYNC_0_4\t(PF_TIMESYNC_BAR4_BASE + 0x110)\n+#define PF_GLTSYN_SHTIME_L_4\t(PF_TIMESYNC_BAR4_BASE + 0x118)\n+#define PF_GLTSYN_SHTIME_H_4\t(PF_TIMESYNC_BAR4_BASE + 0x11C)\n+#define GLTSYN_INCVAL_L\t\t(PF_TIMESYNC_BAR4_BASE + 0x150)\n+#define GLTSYN_INCVAL_H\t\t(PF_TIMESYNC_BAR4_BASE + 0x154)\n+#define GLTSYN_SHADJ_L\t\t(PF_TIMESYNC_BAR4_BASE + 0x158)\n+#define GLTSYN_SHADJ_H\t\t(PF_TIMESYNC_BAR4_BASE + 0x15C)\n+\n+#define GLTSYN_CMD_SYNC_0_5\t(PF_TIMESYNC_BAR4_BASE + 0x130)\n+#define PF_GLTSYN_SHTIME_L_5\t(PF_TIMESYNC_BAR4_BASE + 0x138)\n+#define PF_GLTSYN_SHTIME_H_5\t(PF_TIMESYNC_BAR4_BASE + 0x13C)\n+\n /* In QLEN must be whole number of 32 descriptors. */\n #define IDPF_ALIGN_RING_DESC\t32\n #define IDPF_MIN_RING_DESC\t32\n@@ -41,6 +76,8 @@\n \t(sizeof(struct virtchnl2_ptype) + \\\n \t(((p)->proto_id_count ? ((p)->proto_id_count - 1) : 0) * sizeof((p)->proto_id[0])))\n \n+extern uint64_t idpf_timestamp_dynflag;\n+\n struct idpf_rx_queue {\n \tstruct idpf_adapter *adapter;\t/* the adapter this queue belongs to */\n \tstruct rte_mempool *mp;\t\t/* mbuf pool to populate Rx ring */\n@@ -201,4 +238,57 @@ void idpf_set_tx_function(struct rte_eth_dev *dev);\n \n const uint32_t *idpf_dev_supported_ptypes_get(struct rte_eth_dev *dev);\n \n+#define IDPF_TIMESYNC_REG_WRAP_GUARD_BAND 10000\n+/* Helper function to convert a 32b nanoseconds timestamp to 64b. */\n+static inline uint64_t\n+\n+idpf_tstamp_convert_32b_64b(struct idpf_adapter *ad, uint32_t flag,\n+\t\t\t uint32_t in_timestamp)\n+{\n+#ifdef RTE_ARCH_X86_64\n+\tstruct idpf_hw *hw = &ad->hw;\n+\tconst uint64_t mask = 0xFFFFFFFF;\n+\tuint32_t hi, lo, lo2, delta;\n+\tuint64_t ns;\n+\n+\tif (flag != 0) {\n+\t\tIDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);\n+\t\tIDPF_WRITE_REG(hw, GLTSYN_CMD_SYNC_0_0, PF_GLTSYN_CMD_SYNC_EXEC_CMD_M |\n+\t\t\t PF_GLTSYN_CMD_SYNC_SHTIME_EN_M);\n+\t\tlo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n+\t\thi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);\n+\t\t/*\n+\t\t * On typical system, the delta between lo and lo2 is ~1000ns,\n+\t\t * so 10000 seems a large-enough but not overly-big guard band.\n+\t\t */\n+\t\tif (lo > (UINT32_MAX - IDPF_TIMESYNC_REG_WRAP_GUARD_BAND))\n+\t\t\tlo2 = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n+\t\telse\n+\t\t\tlo2 = lo;\n+\n+\t\tif (lo2 < lo) {\n+\t\t\tlo = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_L_0);\n+\t\t\thi = IDPF_READ_REG(hw, PF_GLTSYN_SHTIME_H_0);\n+\t\t}\n+\n+\t\tad->time_hw = ((uint64_t)hi << 32) | lo;\n+\t}\n+\n+\tdelta = (in_timestamp - (uint32_t)(ad->time_hw & mask));\n+\tif (delta > (mask / 2)) {\n+\t\tdelta = ((uint32_t)(ad->time_hw & mask) - in_timestamp);\n+\t\tns = ad->time_hw - delta;\n+\t} else {\n+\t\tns = ad->time_hw + delta;\n+\t}\n+\n+\treturn ns;\n+#else /* !RTE_ARCH_X86_64 */\n+\tRTE_SET_USED(ad);\n+\tRTE_SET_USED(flag);\n+\tRTE_SET_USED(in_timestamp);\n+\treturn 0;\n+#endif /* RTE_ARCH_X86_64 */\n+}\n+\n #endif /* _IDPF_RXTX_H_ */\n", "prefixes": [ "v10", "14/14" ] }