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GET /api/patches/119130/?format=api
{ "id": 119130, "url": "http://patchwork.dpdk.org/api/patches/119130/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221026084244.22083-1-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221026084244.22083-1-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221026084244.22083-1-junfeng.guo@intel.com", "date": "2022-10-26T08:42:44", "name": "net/gve: fix meson build failure on non-Linux platforms", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2e0fc391c346779d8dfbf870ca3ebf9bbc4bb435", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221026084244.22083-1-junfeng.guo@intel.com/mbox/", "series": [ { "id": 25433, "url": "http://patchwork.dpdk.org/api/series/25433/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25433", "date": "2022-10-26T08:42:44", "name": "net/gve: fix meson build failure on non-Linux platforms", "version": 1, "mbox": "http://patchwork.dpdk.org/series/25433/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/119130/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/119130/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C5288A0542;\n\tWed, 26 Oct 2022 10:44:30 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2F8E142BB0;\n\tWed, 26 Oct 2022 10:44:30 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id 212C4400D6;\n Wed, 26 Oct 2022 10:44:27 +0200 (CEST)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Oct 2022 01:44:27 -0700", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by fmsmga004.fm.intel.com with ESMTP; 26 Oct 2022 01:44:23 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1666773868; x=1698309868;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=0ZMWMNiFdCY2DJud+qbHZbxmtqqErnte5bVN6LBL7S0=;\n b=abVp/Z//De49xlUjw3JU3sWDPvr+9zgGDxjutUr0aDBHe4gAE9tHJNBH\n qbkb02z/k56rna5478a6P80AjQ5y5dbfVRVe1o69DfjkfzYt5vu+6onxq\n 9Ii+SWL7VEEwjesd1UkKL/l97WMtgbvEUsopVYxwq1FeRnuFkhS2r/od+\n TJP4KpVCw/ksM/RYFyzjSIj/8NIXUw4LM0sDq0hf3PLYv2tybxDW6wTho\n wLQzX/T8KZOQmzZEQUf8jBQNTxPHBP7+dBwjy9mE9t3KwEF4AvngKSVZq\n pGDgeZVvPAUdzF83UuHdli9d16ujjrMj2peXckWmZRo64ZOU3wRLPDxsT w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10511\"; a=\"307889523\"", "E=Sophos;i=\"5.95,214,1661842800\"; d=\"scan'208\";a=\"307889523\"", "E=McAfee;i=\"6500,9779,10511\"; a=\"700847033\"", "E=Sophos;i=\"5.95,214,1661842800\"; d=\"scan'208\";a=\"700847033\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@xilinx.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, xiaoyun.li@intel.com, awogbemila@google.com,\n bruce.richardson@intel.com, hemant.agrawal@nxp.com,\n stephen@networkplumber.org, chenbo.xia@intel.com, helin.zhang@intel.com,\n Junfeng Guo <junfeng.guo@intel.com>, stable@dpdk.org", "Subject": "[PATCH] net/gve: fix meson build failure on non-Linux platforms", "Date": "Wed, 26 Oct 2022 16:42:44 +0800", "Message-Id": "<20221026084244.22083-1-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Meson build may fail on FreeBSD with gcc and clang, due to missing\nthe header file linux/pci_regs.h on non-Linux platform. Thus, in\nthis patch, we removed the file include and added the used Macros\nderived from linux/pci_regs.h.\n\nFixes: 3047a5ac8e66 (\"net/gve: add support for device initialization\")\nCc: stable@dpdk.org\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\n---\n drivers/net/gve/gve_ethdev.c | 14 +++++++++++++-\n 1 file changed, 13 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex b0f7b98daa..e968317737 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -1,12 +1,24 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n * Copyright(C) 2022 Intel Corporation\n */\n-#include <linux/pci_regs.h>\n \n #include \"gve_ethdev.h\"\n #include \"base/gve_adminq.h\"\n #include \"base/gve_register.h\"\n \n+/*\n+ * Following macros are derived from linux/pci_regs.h, however,\n+ * we can't simply include that header here, as there is no such\n+ * file for non-Linux platform.\n+ */\n+#define PCI_CFG_SPACE_SIZE\t256\n+#define PCI_CAPABILITY_LIST\t0x34\t/* Offset of first capability list entry */\n+#define PCI_STD_HEADER_SIZEOF\t64\n+#define PCI_CAP_SIZEOF\t\t4\n+#define PCI_CAP_ID_MSIX\t\t0x11\t/* MSI-X */\n+#define PCI_MSIX_FLAGS\t\t2\t/* Message Control */\n+#define PCI_MSIX_FLAGS_QSIZE\t0x07FF\t/* Table size */\n+\n const char gve_version_str[] = GVE_VERSION;\n static const char gve_version_prefix[] = GVE_VERSION_PREFIX;\n \n", "prefixes": [] }