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GET /api/patches/120203/?format=api
{ "id": 120203, "url": "http://patchwork.dpdk.org/api/patches/120203/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221128095442.3185112-7-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221128095442.3185112-7-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221128095442.3185112-7-ndabilpuram@marvell.com", "date": "2022-11-28T09:54:38", "name": "[07/11] net/cnxk: add late backpressure support for cn10kb", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3f5f4ef2b7c28d26f44dec0a1feafca94ce4e2ac", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221128095442.3185112-7-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 25906, "url": "http://patchwork.dpdk.org/api/series/25906/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25906", "date": "2022-11-28T09:54:32", "name": "[01/11] common/cnxk: free pending sqe buffers", "version": 1, "mbox": "http://patchwork.dpdk.org/series/25906/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/120203/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/120203/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 886EAA00C3;\n\tMon, 28 Nov 2022 10:55:34 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AF00542D25;\n\tMon, 28 Nov 2022 10:55:12 +0100 (CET)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id B3CFF42D35\n for <dev@dpdk.org>; Mon, 28 Nov 2022 10:55:10 +0100 (CET)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 2AS5jW1M026598 for <dev@dpdk.org>; Mon, 28 Nov 2022 01:55:09 -0800", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3m4q3srsfu-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Mon, 28 Nov 2022 01:55:09 -0800", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 28 Nov 2022 01:55:08 -0800", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Mon, 28 Nov 2022 01:55:08 -0800", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 0D8B63F704A;\n Mon, 28 Nov 2022 01:55:05 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=w12dMbtgdVQ2fIThJq3a56iWtBKrnIGoYgbNPXav3/k=;\n b=RLXyFi0Vozys1lArmp27Zi9Y0UPYgf9KTSOj57RvjlPrLw+XlsopJnmrhUxEMsLuRxi7\n /IU78oxaTneMPHW5/50+q6gVSpnGLyGMrak4430V44YMITz43LM64Ktkm+WQIL00hM3P\n dmIMEjuNrCPH+p5oKfTPkWdM1zpr7L9Kq8ld4G6RHLYOO28rUWiAfIxUM7oIUa31Zczm\n 1TzJjtdygCeB4yJHIRC2hgeIb3j4T28/spnBdoTjPMkG30+PiYNopWBPNm6mjWRgJjdx\n eq36kUtNnFyWKX/bkO+lO+Z6gzREVYEp3YRpabi498gK9IMuQrokXX0+18aELyWLWXCr 1g==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 07/11] net/cnxk: add late backpressure support for cn10kb", "Date": "Mon, 28 Nov 2022 15:24:38 +0530", "Message-ID": "<20221128095442.3185112-7-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221128095442.3185112-1-ndabilpuram@marvell.com>", "References": "<20221128095442.3185112-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "7w6g75PntvcudKSAcGT2POz_ViCvTcme", "X-Proofpoint-GUID": "7w6g75PntvcudKSAcGT2POz_ViCvTcme", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-11-28_07,2022-11-25_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add late backpressure support for cn10kb and set it up\nto backpressure CPT.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/hw/nix.h | 18 ++++++++++++------\n drivers/common/cnxk/roc_model.h | 6 ++++++\n drivers/common/cnxk/roc_nix_debug.c | 10 ++++++++--\n drivers/common/cnxk/roc_nix_irq.c | 3 +++\n drivers/common/cnxk/roc_nix_priv.h | 3 +++\n drivers/common/cnxk/roc_nix_queue.c | 14 +++++++++++++-\n drivers/net/cnxk/cnxk_ethdev.c | 5 +++--\n 7 files changed, 48 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h\nindex 425c335bf3..0d8f2a5e9b 100644\n--- a/drivers/common/cnxk/hw/nix.h\n+++ b/drivers/common/cnxk/hw/nix.h\n@@ -861,6 +861,7 @@\n #define NIX_CQERRINT_DOOR_ERR (0x0ull)\n #define NIX_CQERRINT_WR_FULL (0x1ull)\n #define NIX_CQERRINT_CQE_FAULT (0x2ull)\n+#define NIX_CQERRINT_CPT_DROP (0x3ull) /* [CN10KB, .) */\n \n #define NIX_LINK_SDP (0xdull) /* [CN10K, .) */\n #define NIX_LINK_CPT (0xeull) /* [CN10K, .) */\n@@ -1009,11 +1010,12 @@ struct nix_cqe_hdr_s {\n /* NIX completion queue context structure */\n struct nix_cq_ctx_s {\n \tuint64_t base : 64; /* W0 */\n-\tuint64_t rsvd_67_64 : 4;\n+\tuint64_t lbp_ena : 1;\n+\tuint64_t lbpid_low : 3;\n \tuint64_t bp_ena : 1;\n-\tuint64_t rsvd_71_69 : 3;\n+\tuint64_t lbpid_med : 3;\n \tuint64_t bpid : 9;\n-\tuint64_t rsvd_83_81 : 3;\n+\tuint64_t lbpid_high : 3;\n \tuint64_t qint_idx : 7;\n \tuint64_t cq_err : 1;\n \tuint64_t cint_idx : 7;\n@@ -1027,10 +1029,14 @@ struct nix_cq_ctx_s {\n \tuint64_t drop : 8;\n \tuint64_t drop_ena : 1;\n \tuint64_t ena : 1;\n-\tuint64_t rsvd_211_210 : 2;\n-\tuint64_t substream : 20;\n+\tuint64_t cpt_drop_err_en : 1;\n+\tuint64_t rsvd_211 : 1;\n+\tuint64_t substream : 12;\n+\tuint64_t stash_thresh : 4;\n+\tuint64_t lbp_frac : 4;\n \tuint64_t caching : 1;\n-\tuint64_t rsvd_235_233 : 3;\n+\tuint64_t stashing : 1;\n+\tuint64_t rsvd_235_234 : 2;\n \tuint64_t qsize : 4;\n \tuint64_t cq_err_int : 8;\n \tuint64_t cq_err_int_ena : 8;\ndiff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h\nindex 1985dd771d..848609eb35 100644\n--- a/drivers/common/cnxk/roc_model.h\n+++ b/drivers/common/cnxk/roc_model.h\n@@ -236,6 +236,12 @@ roc_model_is_cnf10kb_a0(void)\n \treturn roc_model->flag & ROC_MODEL_CNF105xxN_A0;\n }\n \n+static inline uint64_t\n+roc_model_is_cn10kb(void)\n+{\n+\treturn roc_model->flag & ROC_MODEL_CN103xx;\n+}\n+\n static inline bool\n roc_env_is_hw(void)\n {\ndiff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c\nindex 6f82350b53..e491060765 100644\n--- a/drivers/common/cnxk/roc_nix_debug.c\n+++ b/drivers/common/cnxk/roc_nix_debug.c\n@@ -665,8 +665,14 @@ nix_lf_cq_dump(__io struct nix_cq_ctx_s *ctx, FILE *file)\n \t\t ctx->cq_err_int_ena, ctx->cq_err_int);\n \tnix_dump(file, \"W3: qsize \\t\\t\\t%d\\nW3: caching \\t\\t\\t%d\", ctx->qsize,\n \t\t ctx->caching);\n-\tnix_dump(file, \"W3: substream \\t\\t\\t0x%03x\\nW3: ena \\t\\t\\t%d\", ctx->substream,\n-\t\t ctx->ena);\n+\tnix_dump(file, \"W3: substream \\t\\t\\t0x%03x\\nW3: ena \\t\\t\\t%d\\nW3: lbp_ena \\t\\t\\t%d\",\n+\t\t ctx->substream, ctx->ena, ctx->lbp_ena);\n+\tnix_dump(file,\n+\t\t \"W3: lbpid_high \\t\\t\\t0x%03x\\nW3: lbpid_med \\t\\t\\t0x%03x\\n\"\n+\t\t \"W3: lbpid_low \\t\\t\\t0x%03x\\n(W3: lbpid) \\t\\t\\t0x%03x\",\n+\t\t ctx->lbpid_high, ctx->lbpid_med, ctx->lbpid_low,\n+\t\t ctx->lbpid_high << 6 | ctx->lbpid_med << 3 | ctx->lbpid_low);\n+\tnix_dump(file, \"W3: lbp_frac \\t\\t\\t%d\\n\", ctx->lbp_frac);\n \tnix_dump(file, \"W3: drop_ena \\t\\t\\t%d\\nW3: drop \\t\\t\\t%d\", ctx->drop_ena,\n \t\t ctx->drop);\n \tnix_dump(file, \"W3: bp \\t\\t\\t\\t%d\\n\", ctx->bp);\ndiff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c\nindex 661af79193..2e4bccb713 100644\n--- a/drivers/common/cnxk/roc_nix_irq.c\n+++ b/drivers/common/cnxk/roc_nix_irq.c\n@@ -287,6 +287,9 @@ nix_lf_q_irq(void *param)\n \n \t\tif (irq & BIT_ULL(NIX_CQERRINT_CQE_FAULT))\n \t\t\tplt_err(\"CQ=%d NIX_CQERRINT_CQE_FAULT\", cq);\n+\n+\t\tif (irq & BIT_ULL(NIX_CQERRINT_CPT_DROP))\n+\t\t\tplt_err(\"CQ=%d NIX_CQERRINT_CPT_DROP\", cq);\n \t}\n \n \t/* Handle SQ interrupts */\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex 02290a1b86..0a9461c856 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -16,6 +16,9 @@\n \n /* Apply BP/DROP when CQ is 95% full */\n #define NIX_CQ_THRESH_LEVEL\t(5 * 256 / 100)\n+#define NIX_CQ_SEC_THRESH_LEVEL (25 * 256 / 100)\n+/* Apply LBP at 75% of actual BP */\n+#define NIX_CQ_LPB_THRESH_FRAC\t(75 * 16 / 100)\n #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)\n #define NIX_RQ_AURA_THRESH(x)\t(((x)*95) / 100)\n \ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 0dd3c8d4df..5fad8e4543 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -743,6 +743,8 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct mbox *mbox = (&nix->dev)->mbox;\n \tvolatile struct nix_cq_ctx_s *cq_ctx;\n+\tuint16_t drop_thresh = NIX_CQ_THRESH_LEVEL;\n+\tuint16_t cpt_lbpid = nix->bpid[0];\n \tenum nix_q_size qsize;\n \tsize_t desc_sz;\n \tint rc;\n@@ -797,6 +799,16 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)\n \tcq_ctx->avg_level = 0xff;\n \tcq_ctx->cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);\n \tcq_ctx->cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);\n+\tif (roc_model_is_cn10kb() && roc_nix_inl_inb_is_enabled(roc_nix)) {\n+\t\tcq_ctx->cq_err_int_ena |= BIT(NIX_CQERRINT_CPT_DROP);\n+\t\tcq_ctx->cpt_drop_err_en = 1;\n+\t\tcq_ctx->lbp_ena = 1;\n+\t\tcq_ctx->lbpid_low = cpt_lbpid & 0x7;\n+\t\tcq_ctx->lbpid_med = (cpt_lbpid >> 3) & 0x7;\n+\t\tcq_ctx->lbpid_high = (cpt_lbpid >> 6) & 0x7;\n+\t\tcq_ctx->lbp_frac = NIX_CQ_LPB_THRESH_FRAC;\n+\t\tdrop_thresh = NIX_CQ_SEC_THRESH_LEVEL;\n+\t}\n \n \t/* Many to one reduction */\n \tcq_ctx->qint_idx = cq->qid % nix->qints;\n@@ -812,7 +824,7 @@ roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)\n \t\tcq_ctx->drop_ena = 1;\n \t\tcq->drop_thresh = min_rx_drop;\n \t} else {\n-\t\tcq->drop_thresh = NIX_CQ_THRESH_LEVEL;\n+\t\tcq->drop_thresh = drop_thresh;\n \t\t/* Drop processing or red drop cannot be enabled due to\n \t\t * due to packets coming for second pass from CPT.\n \t\t */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 1be2e9e776..d711eb6b27 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -49,8 +49,9 @@ nix_inl_cq_sz_clamp_up(struct roc_nix *nix, struct rte_mempool *mp,\n \tstruct roc_nix_rq *inl_rq;\n \tuint64_t limit;\n \n+\t/* For CN10KB and above, LBP needs minimum CQ size */\n \tif (!roc_errata_cpt_hang_on_x2p_bp())\n-\t\treturn nb_desc;\n+\t\treturn RTE_MAX(nb_desc, (uint32_t)4096);\n \n \t/* CQ should be able to hold all buffers in first pass RQ's aura\n \t * this RQ's aura.\n@@ -695,7 +696,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \tfirst_skip += RTE_PKTMBUF_HEADROOM;\n \tfirst_skip += rte_pktmbuf_priv_size(lpb_pool);\n \trq->first_skip = first_skip;\n-\trq->later_skip = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mp);\n+\trq->later_skip = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(lpb_pool);\n \trq->lpb_size = lpb_pool->elt_size;\n \tif (roc_errata_nix_no_meta_aura())\n \t\trq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);\n", "prefixes": [ "07/11" ] }