Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/122230/?format=api
{ "id": 122230, "url": "http://patchwork.dpdk.org/api/patches/122230/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230118025347.1567078-6-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230118025347.1567078-6-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230118025347.1567078-6-junfeng.guo@intel.com", "date": "2023-01-18T02:53:44", "name": "[RFC,5/8] net/gve: support basic Rx data path for DQO", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "781553a3564d17c50757064c78f0e11fd761d245", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230118025347.1567078-6-junfeng.guo@intel.com/mbox/", "series": [ { "id": 26583, "url": "http://patchwork.dpdk.org/api/series/26583/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=26583", "date": "2023-01-18T02:53:39", "name": "gve PMD enhancement", "version": 1, "mbox": "http://patchwork.dpdk.org/series/26583/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/122230/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/122230/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 533D242407;\n\tWed, 18 Jan 2023 03:59:32 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B3A0442D4E;\n\tWed, 18 Jan 2023 03:59:15 +0100 (CET)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 1DDD542D4E\n for <dev@dpdk.org>; Wed, 18 Jan 2023 03:59:13 +0100 (CET)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 17 Jan 2023 18:59:13 -0800", "from dpdk-jf-ntb-one.sh.intel.com ([10.67.111.104])\n by fmsmga008.fm.intel.com with ESMTP; 17 Jan 2023 18:59:09 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1674010754; x=1705546754;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=O38K76eBW3merUeeJh5bJMfWxVYmsi4XflBS3s7dgQ8=;\n b=N4/KYlbNPCXhqx9o0yTuQvs1q2vimtCS6qT2wRhUYcshs32ilsSL2/yZ\n QmFQr3ttwrZOJHvy9PHr5lBz4RacUen6lp4QIibFGbMi5One0DFxSJY3l\n 5TFHnN0x+SkazuPN6taJSsnm0BzGDzXyiUCowlyaml7++IsYUbNAke4Bg\n 5LVKcbgFHsFumZaqbfAAvvxj3+oRd1SaVZiYvi+LAJ5T/nQfchoYTw7sL\n WfLv2uHo/20bCU/UY3+lps4JFXnm2Ph807EwRY9RpdfutxoMgd+bXJgJV\n bDnvuZZUvN+Pdy+WQ00j5u/QRLU2VpUdOZQIVSpvAXpDrDc2iBl1gtpWj w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10593\"; a=\"322575513\"", "E=Sophos;i=\"5.97,224,1669104000\"; d=\"scan'208\";a=\"322575513\"", "E=McAfee;i=\"6500,9779,10593\"; a=\"722911192\"", "E=Sophos;i=\"5.97,224,1669104000\"; d=\"scan'208\";a=\"722911192\"" ], "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com, jingjing.wu@intel.com, ferruh.yigit@amd.com,\n beilei.xing@intel.com", "Cc": "dev@dpdk.org, xiaoyun.li@intel.com, helin.zhang@intel.com,\n Junfeng Guo <junfeng.guo@intel.com>, Rushil Gupta <rushilg@google.com>,\n Jordan Kimbrough <jrkim@google.com>, Jeroen de Borst <jeroendb@google.com>", "Subject": "[RFC 5/8] net/gve: support basic Rx data path for DQO", "Date": "Wed, 18 Jan 2023 10:53:44 +0800", "Message-Id": "<20230118025347.1567078-6-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20230118025347.1567078-1-junfeng.guo@intel.com>", "References": "<20230118025347.1567078-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add basic Rx data path support for DQO.\n\nSigned-off-by: Junfeng Guo <junfeng.guo@intel.com>\nSigned-off-by: Rushil Gupta <rushilg@google.com>\nSigned-off-by: Jordan Kimbrough <jrkim@google.com>\nSigned-off-by: Jeroen de Borst <jeroendb@google.com>\n---\n drivers/net/gve/gve_ethdev.c | 1 +\n drivers/net/gve/gve_ethdev.h | 3 +\n drivers/net/gve/gve_rx_dqo.c | 128 +++++++++++++++++++++++++++++++++++\n 3 files changed, 132 insertions(+)", "diff": "diff --git a/drivers/net/gve/gve_ethdev.c b/drivers/net/gve/gve_ethdev.c\nindex 512a038968..89e3f09c37 100644\n--- a/drivers/net/gve/gve_ethdev.c\n+++ b/drivers/net/gve/gve_ethdev.c\n@@ -703,6 +703,7 @@ gve_dev_init(struct rte_eth_dev *eth_dev)\n \t} else {\n \t\t/* override Tx/Rx setup/release eth_dev ops */\n \t\tgve_eth_dev_ops_override(&gve_local_eth_dev_ops);\n+\t\teth_dev->rx_pkt_burst = gve_rx_burst_dqo;\n \t\teth_dev->tx_pkt_burst = gve_tx_burst_dqo;\n \t}\n \ndiff --git a/drivers/net/gve/gve_ethdev.h b/drivers/net/gve/gve_ethdev.h\nindex ba657dd6c1..d434f9babe 100644\n--- a/drivers/net/gve/gve_ethdev.h\n+++ b/drivers/net/gve/gve_ethdev.h\n@@ -366,6 +366,9 @@ gve_stop_tx_queues_dqo(struct rte_eth_dev *dev);\n void\n gve_stop_rx_queues_dqo(struct rte_eth_dev *dev);\n \n+uint16_t\n+gve_rx_burst_dqo(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts);\n+\n uint16_t\n gve_tx_burst_dqo(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts);\n \ndiff --git a/drivers/net/gve/gve_rx_dqo.c b/drivers/net/gve/gve_rx_dqo.c\nindex aca6f8ea2d..244517ce5d 100644\n--- a/drivers/net/gve/gve_rx_dqo.c\n+++ b/drivers/net/gve/gve_rx_dqo.c\n@@ -5,6 +5,134 @@\n #include \"gve_ethdev.h\"\n #include \"base/gve_adminq.h\"\n \n+static inline void\n+gve_rx_refill_dqo(struct gve_rx_queue *rxq)\n+{\n+\tvolatile struct gve_rx_desc_dqo *rx_buf_ring;\n+\tvolatile struct gve_rx_desc_dqo *rx_buf_desc;\n+\tstruct rte_mbuf *nmb[rxq->free_thresh];\n+\tuint16_t nb_refill = rxq->free_thresh;\n+\tuint16_t nb_desc = rxq->nb_rx_desc;\n+\tuint16_t next_avail = rxq->bufq_tail;\n+\tstruct rte_eth_dev *dev;\n+\tuint64_t dma_addr;\n+\tuint16_t delta;\n+\tint i;\n+\n+\tif (rxq->nb_rx_hold < rxq->free_thresh)\n+\t\treturn;\n+\n+\trx_buf_ring = rxq->rx_ring;\n+\tdelta = nb_desc - next_avail;\n+\tif (unlikely(delta < nb_refill)) {\n+\t\tif (likely(rte_pktmbuf_alloc_bulk(rxq->mpool, nmb, delta) == 0)) {\n+\t\t\tfor (i = 0; i < delta; i++) {\n+\t\t\t\trx_buf_desc = &rx_buf_ring[next_avail + i];\n+\t\t\t\trxq->sw_ring[next_avail + i] = nmb[i];\n+\t\t\t\tdma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb[i]));\n+\t\t\t\trx_buf_desc->header_buf_addr = 0;\n+\t\t\t\trx_buf_desc->buf_addr = dma_addr;\n+\t\t\t}\n+\t\t\tnb_refill -= delta;\n+\t\t\tnext_avail = 0;\n+\t\t\trxq->nb_rx_hold -= delta;\n+\t\t} else {\n+\t\t\tdev = &rte_eth_devices[rxq->port_id];\n+\t\t\tdev->data->rx_mbuf_alloc_failed += nb_desc - next_avail;\n+\t\t\tPMD_DRV_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u queue_id=%u\",\n+\t\t\t\t rxq->port_id, rxq->queue_id);\n+\t\t\treturn;\n+\t\t}\n+\t}\n+\n+\tif (nb_desc - next_avail >= nb_refill) {\n+\t\tif (likely(rte_pktmbuf_alloc_bulk(rxq->mpool, nmb, nb_refill) == 0)) {\n+\t\t\tfor (i = 0; i < nb_refill; i++) {\n+\t\t\t\trx_buf_desc = &rx_buf_ring[next_avail + i];\n+\t\t\t\trxq->sw_ring[next_avail + i] = nmb[i];\n+\t\t\t\tdma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb[i]));\n+\t\t\t\trx_buf_desc->header_buf_addr = 0;\n+\t\t\t\trx_buf_desc->buf_addr = dma_addr;\n+\t\t\t}\n+\t\t\tnext_avail += nb_refill;\n+\t\t\trxq->nb_rx_hold -= nb_refill;\n+\t\t} else {\n+\t\t\tdev = &rte_eth_devices[rxq->port_id];\n+\t\t\tdev->data->rx_mbuf_alloc_failed += nb_desc - next_avail;\n+\t\t\tPMD_DRV_LOG(DEBUG, \"RX mbuf alloc failed port_id=%u queue_id=%u\",\n+\t\t\t\t rxq->port_id, rxq->queue_id);\n+\t\t}\n+\t}\n+\n+\trte_write32(next_avail, rxq->qrx_tail);\n+\n+\trxq->bufq_tail = next_avail;\n+}\n+\n+uint16_t\n+gve_rx_burst_dqo(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n+{\n+\tvolatile struct gve_rx_compl_desc_dqo *rx_compl_ring;\n+\tvolatile struct gve_rx_compl_desc_dqo *rx_desc;\n+\tstruct gve_rx_queue *rxq;\n+\tstruct rte_mbuf *rxm;\n+\tuint16_t rx_id_bufq;\n+\tuint16_t pkt_len;\n+\tuint16_t rx_id;\n+\tuint16_t nb_rx;\n+\n+\tnb_rx = 0;\n+\trxq = rx_queue;\n+\trx_id = rxq->rx_tail;\n+\trx_id_bufq = rxq->next_avail;\n+\trx_compl_ring = rxq->compl_ring;\n+\n+\twhile (nb_rx < nb_pkts) {\n+\t\trx_desc = &rx_compl_ring[rx_id];\n+\n+\t\t/* check status */\n+\t\tif (rx_desc->generation != rxq->cur_gen_bit)\n+\t\t\tbreak;\n+\n+\t\tif (unlikely(rx_desc->rx_error))\n+\t\t\tcontinue;\n+\n+\t\tpkt_len = rx_desc->packet_len;\n+\n+\t\trx_id++;\n+\t\tif (rx_id == rxq->nb_rx_desc) {\n+\t\t\trx_id = 0;\n+\t\t\trxq->cur_gen_bit ^= 1;\n+\t\t}\n+\n+\t\trxm = rxq->sw_ring[rx_id_bufq];\n+\t\trx_id_bufq++;\n+\t\tif (rx_id_bufq == rxq->nb_rx_desc)\n+\t\t\trx_id_bufq = 0;\n+\t\trxq->nb_rx_hold++;\n+\n+\t\trxm->pkt_len = pkt_len;\n+\t\trxm->data_len = pkt_len;\n+\t\trxm->port = rxq->port_id;\n+\t\trxm->ol_flags = 0;\n+\n+\t\trxm->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;\n+\t\trxm->hash.rss = rte_be_to_cpu_32(rx_desc->hash);\n+\n+\t\trx_pkts[nb_rx++] = rxm;\n+\t}\n+\n+\tif (nb_rx > 0) {\n+\t\trxq->rx_tail = rx_id;\n+\t\tif (rx_id_bufq != rxq->next_avail)\n+\t\t\trxq->next_avail = rx_id_bufq;\n+\n+\t\tgve_rx_refill_dqo(rxq);\n+\t}\n+\n+\treturn nb_rx;\n+}\n+\n static inline void\n gve_release_rxq_mbufs_dqo(struct gve_rx_queue *rxq)\n {\n", "prefixes": [ "RFC", "5/8" ] }