Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/122724/?format=api
{ "id": 122724, "url": "http://patchwork.dpdk.org/api/patches/122724/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230131093346.1261066-6-valex@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230131093346.1261066-6-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230131093346.1261066-6-valex@nvidia.com", "date": "2023-01-31T09:33:34", "name": "[v1,05/16] net/mlx5/hws: align RTC create command with PRM format", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "5a1ed27738269314034a53f5ac234080359a002b", "submitter": { "id": 2858, "url": "http://patchwork.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230131093346.1261066-6-valex@nvidia.com/mbox/", "series": [ { "id": 26709, "url": "http://patchwork.dpdk.org/api/series/26709/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=26709", "date": "2023-01-31T09:33:29", "name": "net/mlx5/hws: support range and partial hash matching", "version": 1, "mbox": "http://patchwork.dpdk.org/series/26709/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/122724/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/122724/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6EB1F41B8D;\n\tTue, 31 Jan 2023 10:34:48 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3086942D0C;\n\tTue, 31 Jan 2023 10:34:40 +0100 (CET)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2053.outbound.protection.outlook.com [40.107.237.53])\n by mails.dpdk.org (Postfix) with ESMTP id 08C4642D0C\n for <dev@dpdk.org>; Tue, 31 Jan 2023 10:34:38 +0100 (CET)", "from MW4PR02CA0018.namprd02.prod.outlook.com (2603:10b6:303:16d::17)\n by SN7PR12MB6910.namprd12.prod.outlook.com (2603:10b6:806:262::21)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6043.36; Tue, 31 Jan\n 2023 09:34:36 +0000", "from CO1NAM11FT073.eop-nam11.prod.protection.outlook.com\n (2603:10b6:303:16d:cafe::53) by MW4PR02CA0018.outlook.office365.com\n (2603:10b6:303:16d::17) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6043.38 via Frontend\n Transport; Tue, 31 Jan 2023 09:34:36 +0000", "from mail.nvidia.com (216.228.117.160) by\n CO1NAM11FT073.mail.protection.outlook.com (10.13.174.196) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.6043.22 via Frontend Transport; Tue, 31 Jan 2023 09:34:35 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 31 Jan\n 2023 01:34:16 -0800", "from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 31 Jan\n 2023 01:34:14 -0800" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=SEiQSCs8ORRPr04iyyGoT9W8lVOctk+be0J6WyzuChiRu+75gZRPXajbwcLWgQr+E9DxAQUaEDMWx+sNRoOAeBVsQXEZQznS7GT6s2eF9oWwCDAT0VJuzrpnc//hZ3r2Dhf13fAgcpHmZYak2QydoMDv97bDmnkE3mBRWdmxRNKD51poUbMytySCZWMty12T3sCj3Bj0dpIOjI+za5RlfebM2QulnNlWCYOTsYKcQqFknyqdj88ja5Qnd5nBK8e9EigqrDneRHWHKzVh8/zfd+gq2lTyFd6lhK1RzzLVOkZnwfI7qIgEYGGNnpIPTzHsKL1rqmSU2pSg8ykW3fiGrA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=mY0pkgaUbUGWjJWj33X8+HQ5AIhEdsWSCsZVeW0C9uE=;\n b=NjauA/3b7m7G+E7LcH8eZrv15S5HZyL0bkz0pWDBx5imeD2mzSMCIQdLRWV/I+zdKPT//ITl5GzUkOKRzHUUcorzDQN55HqSjNrymsNwS8HAnbbUHLYBUtq4s2YPY+DDD3Gu8pWvDBpVnnQV4QA0ALDAJNBTlQQbB0OzLegtqM92UnS4UCfGsE9PVh0tktIY+SZAQWD2LHt1fWoD1uZpTUnaxnKOF/e3PbyEHv8gDWpsmkamuhjx9adSz4hf+cuXTlDbYe1NxD36Dl0Xidtw5Q27tdPkLYfwPgoOqGjk1CJ/Pm94AY2FT37XMVOljR5JNzX6ckBc8QRZCau78xRSDw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=mY0pkgaUbUGWjJWj33X8+HQ5AIhEdsWSCsZVeW0C9uE=;\n b=YMeRBV2/rQvIDP/gE7uXSHVv9BepGFHtFtbVtH/tlHt48h9OGJpjYxK1W0PPGVY1mSoeqU9aLXIrw6ptxu4tF/X1eieIRnLw8mmLo58PtPkFK3C/zJL3Mcg+fEYmlUsHzmsqbqVJfJ1Dupt0B6DhOYOzlPF51HScJ6Y3ApyJ+cOeAXtrdzI31sZ0Tw6yGbpwN1f4xaLSHqjtAUSDzFinSVpW2yKEQkR4Gprpgjbw6BdYvuJiQ3T6QLolD7EdyTeIsqiCFK3jcVrFnVp3Day+nsOZeCE2ceNf3wGLUBKzt3GtC5jNUQU15OwnUoo5OGS47rkv6NoiugbNVUMsATAEOA==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n \"Matan Azrad\" <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v1 05/16] net/mlx5/hws: align RTC create command with PRM format", "Date": "Tue, 31 Jan 2023 11:33:34 +0200", "Message-ID": "<20230131093346.1261066-6-valex@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230131093346.1261066-1-valex@nvidia.com>", "References": "<20230131093346.1261066-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT073:EE_|SN7PR12MB6910:EE_", "X-MS-Office365-Filtering-Correlation-Id": "cfdb5b4a-5d5e-488d-7337-08db036e5df4", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 4SYYzxqwrS7G+hOK400l9xWwLYQFwCYJ8lzO34zfo416C2/bw0vKCdUxmAhVElIY/5g/nY/JiB6tHeYjR+ssKSFaq0m3L5BZYCcuFm4vzd/R24J+n7ujEHiaDsVZYQcbKhXkhFOEwanqje4vh+wlCDUnbill0PY0kdofMqA33lyUOolEs8b4agprdHxhLteClbjxADAtBMbuDAsrpmtcbZhl8iYma9QstXfrubPTk9XNOOPr/XFjnq+oKcrgwbXkovyaGQ/ZAUZUBvrn/pvtcU+wkepoF4vBzERTTzQmkedOxoaonu1p2kDwHCONxMHNLFtC2BSJuzYljgNg6J1eIa/uxAt8bppjFGng097d2kxFaPrm4rqtpTk9NpE8vVatmGhGDDDSudwlBdjzSfRyCFiiB/OcBdzyj8NxrUcp5QabxKJ5Z3GJ3o14EqfR3gCBgVoHJsMP9KnXtEa/7TYJN9xbntAWsysg0KcL1jXPd+NOKDRhYIIoiYl5gVYqjFTf/yfH6e7RzcHxDsGV3j/s2DioDWDLQo6FP3oh8Voc+yOP039M+kqNqOvbh04JDdjzEnmbfP0fdUfObJxdEHEqmMRJVQmNA8fbk9H6LIa8O5noyAJf6nL2N8d1yrZiLL+h33LezJC4Qdaksy/3kYX38ayH59LNyEtsJ38xm+08xRMsluQ9+1lE8lxQ9eZXqMDKG67jAtQfqArhOFcvPE1oIw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(136003)(376002)(346002)(39860400002)(396003)(451199018)(40470700004)(36840700001)(46966006)(4326008)(8676002)(70206006)(70586007)(8936002)(6636002)(316002)(54906003)(110136005)(5660300002)(41300700001)(1076003)(2906002)(7696005)(478600001)(6666004)(107886003)(26005)(2616005)(36756003)(40460700003)(186003)(16526019)(6286002)(336012)(83380400001)(426003)(47076005)(356005)(36860700001)(55016003)(82310400005)(82740400003)(40480700001)(86362001)(7636003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Jan 2023 09:34:35.9550 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n cfdb5b4a-5d5e-488d-7337-08db036e5df4", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT073.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB6910", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Rename rtc params create for new format.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 16 ++++++++++------\n drivers/net/mlx5/hws/mlx5dr_cmd.c | 13 +++++++++++--\n drivers/net/mlx5/hws/mlx5dr_cmd.h | 11 +++++++----\n drivers/net/mlx5/hws/mlx5dr_matcher.c | 19 ++++++++++++-------\n 4 files changed, 40 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 6d0b5e640c..cf46296afb 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3237,6 +3237,7 @@ enum mlx5_ifc_rtc_access_mode {\n enum mlx5_ifc_rtc_ste_format {\n \tMLX5_IFC_RTC_STE_FORMAT_8DW = 0x4,\n \tMLX5_IFC_RTC_STE_FORMAT_11DW = 0x5,\n+\tMLX5_IFC_RTC_STE_FORMAT_RANGE = 0x7,\n };\n \n enum mlx5_ifc_rtc_reparse_mode {\n@@ -3251,24 +3252,27 @@ struct mlx5_ifc_rtc_bits {\n \tu8 reserved_at_40[0x40];\n \tu8 update_index_mode[0x2];\n \tu8 reparse_mode[0x2];\n-\tu8 reserved_at_84[0x4];\n+\tu8 num_match_ste[0x4];\n \tu8 pd[0x18];\n \tu8 reserved_at_a0[0x9];\n \tu8 access_index_mode[0x3];\n \tu8 num_hash_definer[0x4];\n-\tu8 reserved_at_b0[0x3];\n+\tu8 update_method[0x1];\n+\tu8 reserved_at_b1[0x2];\n \tu8 log_depth[0x5];\n \tu8 log_hash_size[0x8];\n-\tu8 ste_format[0x8];\n+\tu8 ste_format_0[0x8];\n \tu8 table_type[0x8];\n-\tu8 reserved_at_d0[0x10];\n-\tu8 match_definer_id[0x20];\n+\tu8 ste_format_1[0x8];\n+\tu8 reserved_at_d8[0x8];\n+\tu8 match_definer_0[0x20];\n \tu8 stc_id[0x20];\n \tu8 ste_table_base_id[0x20];\n \tu8 ste_table_offset[0x20];\n \tu8 reserved_at_160[0x8];\n \tu8 miss_flow_table_id[0x18];\n-\tu8 reserved_at_180[0x280];\n+\tu8 match_definer_1[0x20];\n+\tu8 reserved_at_1a0[0x260];\n };\n \n struct mlx5_ifc_alias_context_bits {\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c\nindex e311be780b..a8d1cf0322 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c\n@@ -259,17 +259,26 @@ mlx5dr_cmd_rtc_create(struct ibv_context *ctx,\n \t\t attr, obj_type, MLX5_GENERAL_OBJ_TYPE_RTC);\n \n \tattr = MLX5_ADDR_OF(create_rtc_in, in, rtc);\n-\tMLX5_SET(rtc, attr, ste_format, rtc_attr->is_jumbo ?\n+\tMLX5_SET(rtc, attr, ste_format_0, rtc_attr->is_frst_jumbo ?\n \t\tMLX5_IFC_RTC_STE_FORMAT_11DW :\n \t\tMLX5_IFC_RTC_STE_FORMAT_8DW);\n+\n+\tif (rtc_attr->is_scnd_range) {\n+\t\tMLX5_SET(rtc, attr, ste_format_1, MLX5_IFC_RTC_STE_FORMAT_RANGE);\n+\t\tMLX5_SET(rtc, attr, num_match_ste, 2);\n+\t}\n+\n \tMLX5_SET(rtc, attr, pd, rtc_attr->pd);\n+\tMLX5_SET(rtc, attr, update_method, rtc_attr->fw_gen_wqe);\n \tMLX5_SET(rtc, attr, update_index_mode, rtc_attr->update_index_mode);\n \tMLX5_SET(rtc, attr, access_index_mode, rtc_attr->access_index_mode);\n \tMLX5_SET(rtc, attr, num_hash_definer, rtc_attr->num_hash_definer);\n \tMLX5_SET(rtc, attr, log_depth, rtc_attr->log_depth);\n \tMLX5_SET(rtc, attr, log_hash_size, rtc_attr->log_size);\n \tMLX5_SET(rtc, attr, table_type, rtc_attr->table_type);\n-\tMLX5_SET(rtc, attr, match_definer_id, rtc_attr->definer_id);\n+\tMLX5_SET(rtc, attr, num_hash_definer, rtc_attr->num_hash_definer);\n+\tMLX5_SET(rtc, attr, match_definer_0, rtc_attr->match_definer_0);\n+\tMLX5_SET(rtc, attr, match_definer_1, rtc_attr->match_definer_1);\n \tMLX5_SET(rtc, attr, stc_id, rtc_attr->stc_base);\n \tMLX5_SET(rtc, attr, ste_table_base_id, rtc_attr->ste_base);\n \tMLX5_SET(rtc, attr, ste_table_offset, rtc_attr->ste_offset);\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h\nindex a42218ba74..e062cb8171 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h\n@@ -23,8 +23,8 @@ struct mlx5dr_cmd_ft_modify_attr {\n };\n \n struct mlx5dr_cmd_fg_attr {\n-\tuint32_t\ttable_id;\n-\tuint32_t\ttable_type;\n+\tuint32_t table_id;\n+\tuint32_t table_type;\n };\n \n struct mlx5dr_cmd_forward_tbl {\n@@ -40,14 +40,17 @@ struct mlx5dr_cmd_rtc_create_attr {\n \tuint32_t ste_base;\n \tuint32_t ste_offset;\n \tuint32_t miss_ft_id;\n+\tbool fw_gen_wqe;\n \tuint8_t update_index_mode;\n \tuint8_t access_index_mode;\n \tuint8_t num_hash_definer;\n \tuint8_t log_depth;\n \tuint8_t log_size;\n \tuint8_t table_type;\n-\tuint8_t definer_id;\n-\tbool is_jumbo;\n+\tuint8_t match_definer_0;\n+\tuint8_t match_definer_1;\n+\tbool is_frst_jumbo;\n+\tbool is_scnd_range;\n };\n \n struct mlx5dr_cmd_alias_obj_create_attr {\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c\nindex 913bb9d447..101a12d361 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_matcher.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c\n@@ -413,6 +413,8 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher,\n \tstruct mlx5dr_pool *ste_pool, *stc_pool;\n \tstruct mlx5dr_devx_obj *devx_obj;\n \tstruct mlx5dr_pool_chunk *ste;\n+\tuint8_t first_definer_id;\n+\tbool is_jumbo;\n \tint ret;\n \n \tswitch (rtc_type) {\n@@ -426,12 +428,15 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher,\n \t\trtc_attr.log_depth = attr->table.sz_col_log;\n \t\trtc_attr.miss_ft_id = matcher->end_ft->id;\n \n+\t\tis_jumbo = mlx5dr_definer_is_jumbo(matcher->mt->definer);\n+\t\tfirst_definer_id = mlx5dr_definer_get_id(matcher->mt->definer);\n+\n \t\tif (attr->insert_mode == MLX5DR_MATCHER_INSERT_BY_HASH) {\n \t\t\t/* The usual Hash Table */\n \t\t\trtc_attr.update_index_mode = MLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH;\n \t\t\t/* The first match template is used since all share the same definer */\n-\t\t\trtc_attr.definer_id = mlx5dr_definer_get_id(matcher->mt->definer);\n-\t\t\trtc_attr.is_jumbo = mlx5dr_definer_is_jumbo(matcher->mt->definer);\n+\t\t\trtc_attr.match_definer_0 = first_definer_id;\n+\t\t\trtc_attr.is_frst_jumbo = is_jumbo;\n \t\t} else if (attr->insert_mode == MLX5DR_MATCHER_INSERT_BY_INDEX) {\n \t\t\trtc_attr.update_index_mode = MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET;\n \t\t\trtc_attr.num_hash_definer = 1;\n@@ -439,12 +444,12 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher,\n \t\t\tif (attr->distribute_mode == MLX5DR_MATCHER_DISTRIBUTE_BY_HASH) {\n \t\t\t\t/* Hash Split Table */\n \t\t\t\trtc_attr.access_index_mode = MLX5_IFC_RTC_STE_ACCESS_MODE_BY_HASH;\n-\t\t\t\trtc_attr.definer_id = mlx5dr_definer_get_id(matcher->mt->definer);\n-\t\t\t\trtc_attr.is_jumbo = mlx5dr_definer_is_jumbo(matcher->mt->definer);\n+\t\t\t\trtc_attr.match_definer_0 = first_definer_id;\n+\t\t\t\trtc_attr.is_frst_jumbo = is_jumbo;\n \t\t\t} else if (attr->distribute_mode == MLX5DR_MATCHER_DISTRIBUTE_BY_LINEAR) {\n \t\t\t\t/* Linear Lookup Table */\n \t\t\t\trtc_attr.access_index_mode = MLX5_IFC_RTC_STE_ACCESS_MODE_LINEAR;\n-\t\t\t\trtc_attr.definer_id = ctx->caps->linear_match_definer;\n+\t\t\t\trtc_attr.match_definer_0 = ctx->caps->linear_match_definer;\n \t\t\t}\n \t\t}\n \n@@ -468,8 +473,8 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher,\n \t\trtc_attr.log_depth = 0;\n \t\trtc_attr.update_index_mode = MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET;\n \t\t/* The action STEs use the default always hit definer */\n-\t\trtc_attr.definer_id = ctx->caps->trivial_match_definer;\n-\t\trtc_attr.is_jumbo = false;\n+\t\trtc_attr.match_definer_0 = ctx->caps->trivial_match_definer;\n+\t\trtc_attr.is_frst_jumbo = false;\n \t\trtc_attr.miss_ft_id = 0;\n \t\tbreak;\n \n", "prefixes": [ "v1", "05/16" ] }