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GET /api/patches/122726/?format=api
{ "id": 122726, "url": "http://patchwork.dpdk.org/api/patches/122726/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230131093346.1261066-7-valex@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230131093346.1261066-7-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230131093346.1261066-7-valex@nvidia.com", "date": "2023-01-31T09:33:35", "name": "[v1,06/16] net/mlx5/hws: add send FW match STE using gen WQE", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7db6c064cb2aa4f23146bf871dff9f588bda0a4e", "submitter": { "id": 2858, "url": "http://patchwork.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230131093346.1261066-7-valex@nvidia.com/mbox/", "series": [ { "id": 26709, "url": "http://patchwork.dpdk.org/api/series/26709/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=26709", "date": "2023-01-31T09:33:29", "name": "net/mlx5/hws: support range and partial hash matching", "version": 1, "mbox": "http://patchwork.dpdk.org/series/26709/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/122726/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/122726/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3665341B8D;\n\tTue, 31 Jan 2023 10:35:10 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B059942D42;\n\tTue, 31 Jan 2023 10:34:42 +0100 (CET)", "from NAM12-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam12on2041.outbound.protection.outlook.com [40.107.237.41])\n by mails.dpdk.org (Postfix) with ESMTP id 15BCC42D0C\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n \"Matan Azrad\" <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v1 06/16] net/mlx5/hws: add send FW match STE using gen WQE", "Date": "Tue, 31 Jan 2023 11:33:35 +0200", "Message-ID": "<20230131093346.1261066-7-valex@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230131093346.1261066-1-valex@nvidia.com>", "References": "<20230131093346.1261066-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT115:EE_|PH8PR12MB6986:EE_", "X-MS-Office365-Filtering-Correlation-Id": "92621266-4598-4be2-0e08-08db036e5e97", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n AAT20Z8MP0/nyMfQWPvTjrYai+pxhvJPzJKvbyA30iTVw5l+JXnD8WyGfmwO7x0FXgsIfXlLyxEJeN+CSkYbD9xNCOD+B5tIRHSlIaMCK1VO8pM8sGDvaCDiNOymk5ZY2ShrSd43DsusfBZ/ND6qROJzi0srpKWBZOltoj8HZWiit1M9eWCxv/eDkwgjieBjqoLCwCRo/Rx/Jj9K56SDGt7ipP0pjnlzRUJVgeZC5xGSyQvC5O8wM7wt49v0BUP2NO/g0K9Ckocji4UjKYybQy0Y9UzDhra0QXNFiFgVY9OvdoFlaUe2pklgRBZQN6R7HBRfAMMeyh7ARWaeKP4SKxsznV79fEzfXZMSYWpXFH62FBlIgVgeCw9HW4q0AqPSzfh6QM+Xx//KGAm6lYJCkcAjN83I8uYZ/Cfd41DSO9gIPDEhY3LMNVNh3u1vCnT72FhvIOvSSobbHJygO38yO7QNzMDZ1Jry4pxOjZic0xwO33wL076gfBL1WTwO/Q8wJkDvULNT+Fz1UJDeM3OCSMwprDsKjpD9Ovtj6zdXDvLoalNRZCMHlCwEA9VrEltYf95KXhbUQHyz9RLwn7C5xqsbhQ7ty4Vn0ZW2dmaKFWOKCyOz9F+2M4nrcfEA7H/OAg/9CqZNqCEBavtRqBYXHsfCwVrHm9wIvKKgm0v0O90CMzMDOcst53ikHDfsy5ZocZgZqRy6djWTq8TfKz0MPg==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(346002)(39860400002)(396003)(376002)(136003)(451199018)(40470700004)(46966006)(36840700001)(36756003)(70206006)(6636002)(54906003)(316002)(110136005)(82310400005)(8676002)(4326008)(5660300002)(70586007)(41300700001)(8936002)(86362001)(356005)(7636003)(82740400003)(36860700001)(107886003)(6666004)(16526019)(186003)(26005)(1076003)(83380400001)(336012)(426003)(40480700001)(40460700003)(55016003)(2906002)(6286002)(7696005)(47076005)(478600001)(2616005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Jan 2023 09:34:37.0363 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 92621266-4598-4be2-0e08-08db036e5e97", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT115.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH8PR12MB6986", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Send STE WQE function wraps the send WQE command to support WQE\nbuild and FDB abstraction. Sending using FW is different from\nsending from HW since FW returns the completion immediately which\nrequires us to retry on failure and prepare the completion as\npart of the send process.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_send.c | 134 +++++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_send.h | 7 +-\n 2 files changed, 140 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_send.c b/drivers/net/mlx5/hws/mlx5dr_send.c\nindex a507e5f626..a9958df4f2 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_send.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_send.c\n@@ -235,6 +235,140 @@ void mlx5dr_send_ste(struct mlx5dr_send_engine *queue,\n \tsend_attr->fence = fence;\n }\n \n+static\n+int mlx5dr_send_wqe_fw(struct ibv_context *ibv_ctx,\n+\t\t uint32_t pd_num,\n+\t\t struct mlx5dr_send_engine_post_attr *send_attr,\n+\t\t struct mlx5dr_wqe_gta_ctrl_seg *send_wqe_ctrl,\n+\t\t void *send_wqe_match_data,\n+\t\t void *send_wqe_match_tag,\n+\t\t bool is_jumbo,\n+\t\t uint8_t gta_opcode)\n+{\n+\tbool has_match = send_wqe_match_data || send_wqe_match_tag;\n+\tstruct mlx5dr_wqe_gta_data_seg_ste gta_wqe_data0 = {0};\n+\tstruct mlx5dr_wqe_gta_ctrl_seg gta_wqe_ctrl = {0};\n+\tstruct mlx5dr_cmd_generate_wqe_attr attr = {0};\n+\tstruct mlx5dr_wqe_ctrl_seg wqe_ctrl = {0};\n+\tstruct mlx5_cqe64 cqe;\n+\tuint32_t flags = 0;\n+\tint ret;\n+\n+\t/* Set WQE control */\n+\twqe_ctrl.opmod_idx_opcode =\n+\t\trte_cpu_to_be_32((send_attr->opmod << 24) | send_attr->opcode);\n+\twqe_ctrl.qpn_ds =\n+\t\trte_cpu_to_be_32((send_attr->len + sizeof(struct mlx5dr_wqe_ctrl_seg)) / 16);\n+\tflags |= send_attr->notify_hw ? MLX5_WQE_CTRL_CQ_UPDATE : 0;\n+\twqe_ctrl.flags = rte_cpu_to_be_32(flags);\n+\twqe_ctrl.imm = rte_cpu_to_be_32(send_attr->id);\n+\n+\t/* Set GTA WQE CTRL */\n+\tmemcpy(gta_wqe_ctrl.stc_ix, send_wqe_ctrl->stc_ix, sizeof(send_wqe_ctrl->stc_ix));\n+\tgta_wqe_ctrl.op_dirix = htobe32(gta_opcode << 28);\n+\n+\t/* Set GTA match WQE DATA */\n+\tif (has_match) {\n+\t\tif (send_wqe_match_data)\n+\t\t\tmemcpy(>a_wqe_data0, send_wqe_match_data, sizeof(gta_wqe_data0));\n+\t\telse\n+\t\t\tmlx5dr_send_wqe_set_tag(>a_wqe_data0, send_wqe_match_tag, is_jumbo);\n+\n+\t\tgta_wqe_data0.rsvd1_definer = htobe32(send_attr->match_definer_id << 8);\n+\t\tattr.gta_data_0 = (uint8_t *)>a_wqe_data0;\n+\t}\n+\n+\tattr.pdn = pd_num;\n+\tattr.wqe_ctrl = (uint8_t *)&wqe_ctrl;\n+\tattr.gta_ctrl = (uint8_t *)>a_wqe_ctrl;\n+\n+send_wqe:\n+\tret = mlx5dr_cmd_generate_wqe(ibv_ctx, &attr, &cqe);\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to write WQE using command\");\n+\t\treturn ret;\n+\t}\n+\n+\tif ((mlx5dv_get_cqe_opcode(&cqe) == MLX5_CQE_REQ) &&\n+\t (rte_be_to_cpu_32(cqe.byte_cnt) >> 31 == 0)) {\n+\t\t*send_attr->used_id = send_attr->id;\n+\t\treturn 0;\n+\t}\n+\n+\t/* Retry if rule failed */\n+\tif (send_attr->retry_id) {\n+\t\twqe_ctrl.imm = rte_cpu_to_be_32(send_attr->retry_id);\n+\t\tsend_attr->id = send_attr->retry_id;\n+\t\tsend_attr->retry_id = 0;\n+\t\tgoto send_wqe;\n+\t}\n+\n+\treturn -1;\n+}\n+\n+void mlx5dr_send_stes_fw(struct mlx5dr_send_engine *queue,\n+\t\t\t struct mlx5dr_send_ste_attr *ste_attr)\n+{\n+\tstruct mlx5dr_send_engine_post_attr *send_attr = &ste_attr->send_attr;\n+\tstruct mlx5dr_rule *rule = send_attr->rule;\n+\tstruct ibv_context *ibv_ctx;\n+\tstruct mlx5dr_context *ctx;\n+\tuint16_t queue_id;\n+\tuint32_t pdn;\n+\tint ret;\n+\n+\tctx = rule->matcher->tbl->ctx;\n+\tqueue_id = queue - ctx->send_queue;\n+\tibv_ctx = ctx->ibv_ctx;\n+\tpdn = ctx->pd_num;\n+\n+\t/* Writing through FW can't HW fence, therefore we drain the queue */\n+\tif (send_attr->fence)\n+\t\tmlx5dr_send_queue_action(ctx,\n+\t\t\t\t\t queue_id,\n+\t\t\t\t\t MLX5DR_SEND_QUEUE_ACTION_DRAIN_SYNC);\n+\n+\tif (ste_attr->rtc_1) {\n+\t\tsend_attr->id = ste_attr->rtc_1;\n+\t\tsend_attr->used_id = ste_attr->used_id_rtc_1;\n+\t\tsend_attr->retry_id = ste_attr->retry_rtc_1;\n+\t\tret = mlx5dr_send_wqe_fw(ibv_ctx, pdn, send_attr,\n+\t\t\t\t\t ste_attr->wqe_ctrl,\n+\t\t\t\t\t ste_attr->wqe_data,\n+\t\t\t\t\t ste_attr->wqe_tag,\n+\t\t\t\t\t ste_attr->wqe_tag_is_jumbo,\n+\t\t\t\t\t ste_attr->gta_opcode);\n+\t\tif (ret)\n+\t\t\tgoto fail_rule;\n+\t}\n+\n+\tif (ste_attr->rtc_0) {\n+\t\tsend_attr->id = ste_attr->rtc_0;\n+\t\tsend_attr->used_id = ste_attr->used_id_rtc_0;\n+\t\tsend_attr->retry_id = ste_attr->retry_rtc_0;\n+\t\tret = mlx5dr_send_wqe_fw(ibv_ctx, pdn, send_attr,\n+\t\t\t\t\t ste_attr->wqe_ctrl,\n+\t\t\t\t\t ste_attr->wqe_data,\n+\t\t\t\t\t ste_attr->wqe_tag,\n+\t\t\t\t\t ste_attr->wqe_tag_is_jumbo,\n+\t\t\t\t\t ste_attr->gta_opcode);\n+\t\tif (ret)\n+\t\t\tgoto fail_rule;\n+\t}\n+\n+\t/* Increase the status, this only works on good flow as the enum\n+\t * is arrange it away creating -> created -> deleting -> deleted\n+\t */\n+\trule->status++;\n+\tmlx5dr_send_engine_gen_comp(queue, send_attr->user_data, RTE_FLOW_OP_SUCCESS);\n+\treturn;\n+\n+fail_rule:\n+\trule->status = !rule->rtc_0 && !rule->rtc_1 ?\n+\t\tMLX5DR_RULE_STATUS_FAILED : MLX5DR_RULE_STATUS_FAILING;\n+\tmlx5dr_send_engine_gen_comp(queue, send_attr->user_data, RTE_FLOW_OP_ERROR);\n+}\n+\n static void mlx5dr_send_engine_retry_post_send(struct mlx5dr_send_engine *queue,\n \t\t\t\t\t struct mlx5dr_send_ring_priv *priv,\n \t\t\t\t\t uint16_t wqe_cnt)\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_send.h b/drivers/net/mlx5/hws/mlx5dr_send.h\nindex fcddcc6366..1e845b1c7a 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_send.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_send.h\n@@ -52,7 +52,8 @@ struct mlx5dr_wqe_gta_ctrl_seg {\n \n struct mlx5dr_wqe_gta_data_seg_ste {\n \t__be32 rsvd0_ctr_id;\n-\t__be32 rsvd1[4];\n+\t__be32 rsvd1_definer;\n+\t__be32 rsvd2[3];\n \t__be32 action[3];\n \t__be32 tag[8];\n };\n@@ -159,6 +160,7 @@ struct mlx5dr_send_engine_post_attr {\n \tuint8_t opmod;\n \tuint8_t notify_hw;\n \tuint8_t fence;\n+\tuint8_t match_definer_id;\n \tsize_t len;\n \tstruct mlx5dr_rule *rule;\n \tuint32_t id;\n@@ -238,6 +240,9 @@ void mlx5dr_send_engine_post_end(struct mlx5dr_send_engine_post_ctrl *ctrl,\n void mlx5dr_send_ste(struct mlx5dr_send_engine *queue,\n \t\t struct mlx5dr_send_ste_attr *ste_attr);\n \n+void mlx5dr_send_stes_fw(struct mlx5dr_send_engine *queue,\n+\t\t\t struct mlx5dr_send_ste_attr *ste_attr);\n+\n void mlx5dr_send_engine_flush_queue(struct mlx5dr_send_engine *queue);\n \n static inline bool mlx5dr_send_engine_empty(struct mlx5dr_send_engine *queue)\n", "prefixes": [ "v1", "06/16" ] }