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GET /api/patches/122783/?format=api
{ "id": 122783, "url": "http://patchwork.dpdk.org/api/patches/122783/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230201072815.1329101-6-valex@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201072815.1329101-6-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201072815.1329101-6-valex@nvidia.com", "date": "2023-02-01T07:28:04", "name": "[v2,05/16] net/mlx5/hws: align RTC create command with PRM format", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "5a1ed27738269314034a53f5ac234080359a002b", "submitter": { "id": 2858, "url": "http://patchwork.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230201072815.1329101-6-valex@nvidia.com/mbox/", "series": [ { "id": 26726, "url": "http://patchwork.dpdk.org/api/series/26726/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=26726", "date": "2023-02-01T07:28:01", "name": "net/mlx5/hws: support range and partial hash matching", "version": 2, "mbox": "http://patchwork.dpdk.org/series/26726/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/122783/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/122783/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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net/mlx5/hws: align RTC create command with PRM format", "Date": "Wed, 1 Feb 2023 09:28:04 +0200", "Message-ID": "<20230201072815.1329101-6-valex@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230201072815.1329101-1-valex@nvidia.com>", "References": "<20230131093346.1261066-1-valex@nvidia.com>\n <20230201072815.1329101-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT109:EE_|MN0PR12MB5884:EE_", "X-MS-Office365-Filtering-Correlation-Id": "25c81572-e8e3-484c-fe5b-08db0425fdf9", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", 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SFS:(13230025)(4636009)(396003)(39860400002)(136003)(376002)(346002)(451199018)(36840700001)(46966006)(40470700004)(5660300002)(2906002)(8936002)(41300700001)(4326008)(70206006)(83380400001)(70586007)(8676002)(16526019)(82310400005)(36756003)(7696005)(40480700001)(110136005)(40460700003)(478600001)(6286002)(186003)(6666004)(107886003)(26005)(1076003)(55016003)(426003)(47076005)(86362001)(336012)(2616005)(6636002)(356005)(54906003)(82740400003)(7636003)(36860700001)(316002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Feb 2023 07:29:02.2346 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 25c81572-e8e3-484c-fe5b-08db0425fdf9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT109.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB5884", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Rename rtc params create for new format.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 16 ++++++++++------\n drivers/net/mlx5/hws/mlx5dr_cmd.c | 13 +++++++++++--\n drivers/net/mlx5/hws/mlx5dr_cmd.h | 11 +++++++----\n drivers/net/mlx5/hws/mlx5dr_matcher.c | 19 ++++++++++++-------\n 4 files changed, 40 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 140534ea46..298cc48b06 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -3237,6 +3237,7 @@ enum mlx5_ifc_rtc_access_mode {\n enum mlx5_ifc_rtc_ste_format {\n \tMLX5_IFC_RTC_STE_FORMAT_8DW = 0x4,\n \tMLX5_IFC_RTC_STE_FORMAT_11DW = 0x5,\n+\tMLX5_IFC_RTC_STE_FORMAT_RANGE = 0x7,\n };\n \n enum mlx5_ifc_rtc_reparse_mode {\n@@ -3251,24 +3252,27 @@ struct mlx5_ifc_rtc_bits {\n \tu8 reserved_at_40[0x40];\n \tu8 update_index_mode[0x2];\n \tu8 reparse_mode[0x2];\n-\tu8 reserved_at_84[0x4];\n+\tu8 num_match_ste[0x4];\n \tu8 pd[0x18];\n \tu8 reserved_at_a0[0x9];\n \tu8 access_index_mode[0x3];\n \tu8 num_hash_definer[0x4];\n-\tu8 reserved_at_b0[0x3];\n+\tu8 update_method[0x1];\n+\tu8 reserved_at_b1[0x2];\n \tu8 log_depth[0x5];\n \tu8 log_hash_size[0x8];\n-\tu8 ste_format[0x8];\n+\tu8 ste_format_0[0x8];\n \tu8 table_type[0x8];\n-\tu8 reserved_at_d0[0x10];\n-\tu8 match_definer_id[0x20];\n+\tu8 ste_format_1[0x8];\n+\tu8 reserved_at_d8[0x8];\n+\tu8 match_definer_0[0x20];\n \tu8 stc_id[0x20];\n \tu8 ste_table_base_id[0x20];\n \tu8 ste_table_offset[0x20];\n \tu8 reserved_at_160[0x8];\n \tu8 miss_flow_table_id[0x18];\n-\tu8 reserved_at_180[0x280];\n+\tu8 match_definer_1[0x20];\n+\tu8 reserved_at_1a0[0x260];\n };\n \n struct mlx5_ifc_alias_context_bits {\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c\nindex b0cef5e944..3578fe4b69 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c\n@@ -259,17 +259,26 @@ mlx5dr_cmd_rtc_create(struct ibv_context *ctx,\n \t\t attr, obj_type, MLX5_GENERAL_OBJ_TYPE_RTC);\n \n \tattr = MLX5_ADDR_OF(create_rtc_in, in, rtc);\n-\tMLX5_SET(rtc, attr, ste_format, rtc_attr->is_jumbo ?\n+\tMLX5_SET(rtc, attr, ste_format_0, rtc_attr->is_frst_jumbo ?\n \t\tMLX5_IFC_RTC_STE_FORMAT_11DW :\n \t\tMLX5_IFC_RTC_STE_FORMAT_8DW);\n+\n+\tif (rtc_attr->is_scnd_range) {\n+\t\tMLX5_SET(rtc, attr, ste_format_1, MLX5_IFC_RTC_STE_FORMAT_RANGE);\n+\t\tMLX5_SET(rtc, attr, num_match_ste, 2);\n+\t}\n+\n \tMLX5_SET(rtc, attr, pd, rtc_attr->pd);\n+\tMLX5_SET(rtc, attr, update_method, rtc_attr->fw_gen_wqe);\n \tMLX5_SET(rtc, attr, update_index_mode, rtc_attr->update_index_mode);\n \tMLX5_SET(rtc, attr, access_index_mode, rtc_attr->access_index_mode);\n \tMLX5_SET(rtc, attr, num_hash_definer, rtc_attr->num_hash_definer);\n \tMLX5_SET(rtc, attr, log_depth, rtc_attr->log_depth);\n \tMLX5_SET(rtc, attr, log_hash_size, rtc_attr->log_size);\n \tMLX5_SET(rtc, attr, table_type, rtc_attr->table_type);\n-\tMLX5_SET(rtc, attr, match_definer_id, rtc_attr->definer_id);\n+\tMLX5_SET(rtc, attr, num_hash_definer, rtc_attr->num_hash_definer);\n+\tMLX5_SET(rtc, attr, match_definer_0, rtc_attr->match_definer_0);\n+\tMLX5_SET(rtc, attr, match_definer_1, rtc_attr->match_definer_1);\n \tMLX5_SET(rtc, attr, stc_id, rtc_attr->stc_base);\n \tMLX5_SET(rtc, attr, ste_table_base_id, rtc_attr->ste_base);\n \tMLX5_SET(rtc, attr, ste_table_offset, rtc_attr->ste_offset);\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h\nindex 36295e0c76..0fc65aad49 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_cmd.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h\n@@ -23,8 +23,8 @@ struct mlx5dr_cmd_ft_modify_attr {\n };\n \n struct mlx5dr_cmd_fg_attr {\n-\tuint32_t\ttable_id;\n-\tuint32_t\ttable_type;\n+\tuint32_t table_id;\n+\tuint32_t table_type;\n };\n \n struct mlx5dr_cmd_forward_tbl {\n@@ -40,14 +40,17 @@ struct mlx5dr_cmd_rtc_create_attr {\n \tuint32_t ste_base;\n \tuint32_t ste_offset;\n \tuint32_t miss_ft_id;\n+\tbool fw_gen_wqe;\n \tuint8_t update_index_mode;\n \tuint8_t access_index_mode;\n \tuint8_t num_hash_definer;\n \tuint8_t log_depth;\n \tuint8_t log_size;\n \tuint8_t table_type;\n-\tuint8_t definer_id;\n-\tbool is_jumbo;\n+\tuint8_t match_definer_0;\n+\tuint8_t match_definer_1;\n+\tbool is_frst_jumbo;\n+\tbool is_scnd_range;\n };\n \n struct mlx5dr_cmd_alias_obj_create_attr {\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c\nindex 913bb9d447..101a12d361 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_matcher.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c\n@@ -413,6 +413,8 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher,\n \tstruct mlx5dr_pool *ste_pool, *stc_pool;\n \tstruct mlx5dr_devx_obj *devx_obj;\n \tstruct mlx5dr_pool_chunk *ste;\n+\tuint8_t first_definer_id;\n+\tbool is_jumbo;\n \tint ret;\n \n \tswitch (rtc_type) {\n@@ -426,12 +428,15 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher,\n \t\trtc_attr.log_depth = attr->table.sz_col_log;\n \t\trtc_attr.miss_ft_id = matcher->end_ft->id;\n \n+\t\tis_jumbo = mlx5dr_definer_is_jumbo(matcher->mt->definer);\n+\t\tfirst_definer_id = mlx5dr_definer_get_id(matcher->mt->definer);\n+\n \t\tif (attr->insert_mode == MLX5DR_MATCHER_INSERT_BY_HASH) {\n \t\t\t/* The usual Hash Table */\n \t\t\trtc_attr.update_index_mode = MLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH;\n \t\t\t/* The first match template is used since all share the same definer */\n-\t\t\trtc_attr.definer_id = mlx5dr_definer_get_id(matcher->mt->definer);\n-\t\t\trtc_attr.is_jumbo = mlx5dr_definer_is_jumbo(matcher->mt->definer);\n+\t\t\trtc_attr.match_definer_0 = first_definer_id;\n+\t\t\trtc_attr.is_frst_jumbo = is_jumbo;\n \t\t} else if (attr->insert_mode == MLX5DR_MATCHER_INSERT_BY_INDEX) {\n \t\t\trtc_attr.update_index_mode = MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET;\n \t\t\trtc_attr.num_hash_definer = 1;\n@@ -439,12 +444,12 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher,\n \t\t\tif (attr->distribute_mode == MLX5DR_MATCHER_DISTRIBUTE_BY_HASH) {\n \t\t\t\t/* Hash Split Table */\n \t\t\t\trtc_attr.access_index_mode = MLX5_IFC_RTC_STE_ACCESS_MODE_BY_HASH;\n-\t\t\t\trtc_attr.definer_id = mlx5dr_definer_get_id(matcher->mt->definer);\n-\t\t\t\trtc_attr.is_jumbo = mlx5dr_definer_is_jumbo(matcher->mt->definer);\n+\t\t\t\trtc_attr.match_definer_0 = first_definer_id;\n+\t\t\t\trtc_attr.is_frst_jumbo = is_jumbo;\n \t\t\t} else if (attr->distribute_mode == MLX5DR_MATCHER_DISTRIBUTE_BY_LINEAR) {\n \t\t\t\t/* Linear Lookup Table */\n \t\t\t\trtc_attr.access_index_mode = MLX5_IFC_RTC_STE_ACCESS_MODE_LINEAR;\n-\t\t\t\trtc_attr.definer_id = ctx->caps->linear_match_definer;\n+\t\t\t\trtc_attr.match_definer_0 = ctx->caps->linear_match_definer;\n \t\t\t}\n \t\t}\n \n@@ -468,8 +473,8 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher,\n \t\trtc_attr.log_depth = 0;\n \t\trtc_attr.update_index_mode = MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET;\n \t\t/* The action STEs use the default always hit definer */\n-\t\trtc_attr.definer_id = ctx->caps->trivial_match_definer;\n-\t\trtc_attr.is_jumbo = false;\n+\t\trtc_attr.match_definer_0 = ctx->caps->trivial_match_definer;\n+\t\trtc_attr.is_frst_jumbo = false;\n \t\trtc_attr.miss_ft_id = 0;\n \t\tbreak;\n \n", "prefixes": [ "v2", "05/16" ] }