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GET /api/patches/122788/?format=api
{ "id": 122788, "url": "http://patchwork.dpdk.org/api/patches/122788/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230201072815.1329101-10-valex@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201072815.1329101-10-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201072815.1329101-10-valex@nvidia.com", "date": "2023-02-01T07:28:08", "name": "[v2,09/16] net/mlx5/hws: support range match", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "4b49e868de077e55a40adbb60b2e22bf72babf2a", "submitter": { "id": 2858, "url": "http://patchwork.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230201072815.1329101-10-valex@nvidia.com/mbox/", "series": [ { "id": 26726, "url": "http://patchwork.dpdk.org/api/series/26726/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=26726", "date": "2023-02-01T07:28:01", "name": "net/mlx5/hws: support range and partial hash matching", "version": 2, "mbox": "http://patchwork.dpdk.org/series/26726/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/122788/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/122788/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 244F241B9B;\n\tWed, 1 Feb 2023 08:30:13 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A156342D6C;\n\tWed, 1 Feb 2023 08:29:17 +0100 (CET)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2058.outbound.protection.outlook.com [40.107.223.58])\n by mails.dpdk.org (Postfix) with ESMTP id 0CB6642D48\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n \"Matan Azrad\" <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v2 09/16] net/mlx5/hws: support range match", "Date": "Wed, 1 Feb 2023 09:28:08 +0200", "Message-ID": "<20230201072815.1329101-10-valex@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230201072815.1329101-1-valex@nvidia.com>", "References": "<20230131093346.1261066-1-valex@nvidia.com>\n <20230201072815.1329101-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT023:EE_|PH0PR12MB8126:EE_", "X-MS-Office365-Filtering-Correlation-Id": "7eeed73c-92de-443f-5669-08db042604d4", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n WzZaDO5F8Av2qx9X3ICuiMzs/5DYTVjYNTZW0piBGWSU1FGb4Zng2TxOzxe/NdgdjOlbYeLyXS6/qkKC7XqzJCZFzaKS6fQ+0JdbEj21LOCB+2p/x49ThP487r8q9pO9U2nEXeZGceirBB3xJW6r/rl6W4vd6osrWMGODS9JrGNZ9YWkyho4k0sRZVqe6wFpuNVvG5NHxgqNX9wXLafdeQr4Mf0SWxB2b7H9lG6UtPqbiMh0haJa8IAoAAJ1O8ZhKOV3uLf+0x/zO0sKTYBG/+R3QsB5LhsZPnfN8C+odqhjOhLHgVjhKKTxpY6+cg1X6/F49kpK/xQ3kwzO/5AbnfA+yvn5bS60NtWCwsSh/0Uc3Gftir8D2evUrznBl8DlOQY7ZsZaVvVC9Dh7pdFPoUZtkN5BvkXcG56/thEu19ISi2rJhobvRt/d1XhAav5+qEv87bgBy4GuHKhlP+Q+Dtk+a9YJe3ch/9UAopOap/pn7gn0LbO5qUZVdknh9xnhGUkVkS1C6i1Q0rJix1c58xV8UXiRAUMA57rOvLdMUwOzXU3Bo3llVhjcMfxdtLqAB8npQ6QZnsLH965JP6/oFLD8KRap0s7QwYHz8leVbs+ENFC5oZr31F6vJyqpX1NZCPFTZOF9toTcow3PrNtyOckkWHe1WJBDazEZszAM2oZuAcmhJXqt9FZQHJiVEWFWe5GwY6LU4AlNFea0xs4Zfw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(39860400002)(396003)(136003)(376002)(346002)(451199018)(46966006)(40470700004)(36840700001)(186003)(16526019)(5660300002)(6636002)(110136005)(26005)(54906003)(2616005)(6286002)(86362001)(40480700001)(55016003)(478600001)(2906002)(40460700003)(7696005)(36756003)(6666004)(107886003)(1076003)(36860700001)(4326008)(356005)(70586007)(7636003)(82740400003)(82310400005)(426003)(336012)(83380400001)(316002)(70206006)(47076005)(8676002)(8936002)(41300700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Feb 2023 07:29:13.7319 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7eeed73c-92de-443f-5669-08db042604d4", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT023.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB8126", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Support range matching over selected items and range\nis not supported over all the items. The range match\nis done using:\nitem->last.field - maximum value\nitem->mask.field - bitmask\nitem->spec.field - minimum value\n\nWhen items are processed if item last and mask fields are\nnon zero range matching will be done over these fields.\nThere are two field setter, field copy (fc) and field copy\nrange (fcr).\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 73 +++++++++++++++++++++++++--\n drivers/net/mlx5/hws/mlx5dr_definer.h | 5 +-\n 2 files changed, 72 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 6b98eb8c96..c268f94ad3 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -123,6 +123,7 @@ struct mlx5dr_definer_conv_data {\n \tX(SET,\t\tipv4_next_proto,\tv->next_proto_id,\trte_ipv4_hdr) \\\n \tX(SET,\t\tipv4_version,\t\tSTE_IPV4,\t\trte_ipv4_hdr) \\\n \tX(SET_BE16,\tipv4_frag,\t\tv->fragment_offset,\trte_ipv4_hdr) \\\n+\tX(SET_BE16,\tipv4_len,\t\tv->total_length,\trte_ipv4_hdr) \\\n \tX(SET_BE16,\tipv6_payload_len,\tv->hdr.payload_len,\trte_flow_item_ipv6) \\\n \tX(SET,\t\tipv6_proto,\t\tv->hdr.proto,\t\trte_flow_item_ipv6) \\\n \tX(SET,\t\tipv6_hop_limits,\tv->hdr.hop_limits,\trte_flow_item_ipv6) \\\n@@ -516,6 +517,7 @@ mlx5dr_definer_conv_item_ipv4(struct mlx5dr_definer_conv_data *cd,\n \t\t\t int item_idx)\n {\n \tconst struct rte_ipv4_hdr *m = item->mask;\n+\tconst struct rte_ipv4_hdr *l = item->last;\n \tstruct mlx5dr_definer_fc *fc;\n \tbool inner = cd->tunnel;\n \n@@ -533,8 +535,8 @@ mlx5dr_definer_conv_item_ipv4(struct mlx5dr_definer_conv_data *cd,\n \tif (!m)\n \t\treturn 0;\n \n-\tif (m->total_length || m->packet_id ||\n-\t m->hdr_checksum) {\n+\tif (m->packet_id || m->hdr_checksum ||\n+\t (l && (l->next_proto_id || l->type_of_service))) {\n \t\trte_errno = ENOTSUP;\n \t\treturn rte_errno;\n \t}\n@@ -553,9 +555,18 @@ mlx5dr_definer_conv_item_ipv4(struct mlx5dr_definer_conv_data *cd,\n \t\tDR_CALC_SET(fc, eth_l3, protocol_next_header, inner);\n \t}\n \n+\tif (m->total_length) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(IP_LEN, inner)];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->is_range = l && l->total_length;\n+\t\tfc->tag_set = &mlx5dr_definer_ipv4_len_set;\n+\t\tDR_CALC_SET(fc, eth_l3, ipv4_total_length, inner);\n+\t}\n+\n \tif (m->dst_addr) {\n \t\tfc = &cd->fc[DR_CALC_FNAME(IPV4_DST, inner)];\n \t\tfc->item_idx = item_idx;\n+\t\tfc->is_range = l && l->dst_addr;\n \t\tfc->tag_set = &mlx5dr_definer_ipv4_dst_addr_set;\n \t\tDR_CALC_SET(fc, ipv4_src_dest, destination_address, inner);\n \t}\n@@ -563,6 +574,7 @@ mlx5dr_definer_conv_item_ipv4(struct mlx5dr_definer_conv_data *cd,\n \tif (m->src_addr) {\n \t\tfc = &cd->fc[DR_CALC_FNAME(IPV4_SRC, inner)];\n \t\tfc->item_idx = item_idx;\n+\t\tfc->is_range = l && l->src_addr;\n \t\tfc->tag_set = &mlx5dr_definer_ipv4_src_addr_set;\n \t\tDR_CALC_SET(fc, ipv4_src_dest, source_address, inner);\n \t}\n@@ -570,6 +582,7 @@ mlx5dr_definer_conv_item_ipv4(struct mlx5dr_definer_conv_data *cd,\n \tif (m->ihl) {\n \t\tfc = &cd->fc[DR_CALC_FNAME(IPV4_IHL, inner)];\n \t\tfc->item_idx = item_idx;\n+\t\tfc->is_range = l && l->ihl;\n \t\tfc->tag_set = &mlx5dr_definer_ipv4_ihl_set;\n \t\tDR_CALC_SET(fc, eth_l3, ihl, inner);\n \t}\n@@ -577,6 +590,7 @@ mlx5dr_definer_conv_item_ipv4(struct mlx5dr_definer_conv_data *cd,\n \tif (m->time_to_live) {\n \t\tfc = &cd->fc[DR_CALC_FNAME(IP_TTL, inner)];\n \t\tfc->item_idx = item_idx;\n+\t\tfc->is_range = l && l->time_to_live;\n \t\tfc->tag_set = &mlx5dr_definer_ipv4_time_to_live_set;\n \t\tDR_CALC_SET(fc, eth_l3, time_to_live_hop_limit, inner);\n \t}\n@@ -597,6 +611,7 @@ mlx5dr_definer_conv_item_ipv6(struct mlx5dr_definer_conv_data *cd,\n \t\t\t int item_idx)\n {\n \tconst struct rte_flow_item_ipv6 *m = item->mask;\n+\tconst struct rte_flow_item_ipv6 *l = item->last;\n \tstruct mlx5dr_definer_fc *fc;\n \tbool inner = cd->tunnel;\n \n@@ -616,7 +631,10 @@ mlx5dr_definer_conv_item_ipv6(struct mlx5dr_definer_conv_data *cd,\n \n \tif (m->has_hop_ext || m->has_route_ext || m->has_auth_ext ||\n \t m->has_esp_ext || m->has_dest_ext || m->has_mobil_ext ||\n-\t m->has_hip_ext || m->has_shim6_ext) {\n+\t m->has_hip_ext || m->has_shim6_ext ||\n+\t (l && (l->has_frag_ext || l->hdr.vtc_flow || l->hdr.proto ||\n+\t\t !is_mem_zero(l->hdr.src_addr, 16) ||\n+\t\t !is_mem_zero(l->hdr.dst_addr, 16)))) {\n \t\trte_errno = ENOTSUP;\n \t\treturn rte_errno;\n \t}\n@@ -643,8 +661,9 @@ mlx5dr_definer_conv_item_ipv6(struct mlx5dr_definer_conv_data *cd,\n \t}\n \n \tif (m->hdr.payload_len) {\n-\t\tfc = &cd->fc[DR_CALC_FNAME(IPV6_PAYLOAD_LEN, inner)];\n+\t\tfc = &cd->fc[DR_CALC_FNAME(IP_LEN, inner)];\n \t\tfc->item_idx = item_idx;\n+\t\tfc->is_range = l && l->hdr.payload_len;\n \t\tfc->tag_set = &mlx5dr_definer_ipv6_payload_len_set;\n \t\tDR_CALC_SET(fc, eth_l3, ipv6_payload_length, inner);\n \t}\n@@ -659,6 +678,7 @@ mlx5dr_definer_conv_item_ipv6(struct mlx5dr_definer_conv_data *cd,\n \tif (m->hdr.hop_limits) {\n \t\tfc = &cd->fc[DR_CALC_FNAME(IP_TTL, inner)];\n \t\tfc->item_idx = item_idx;\n+\t\tfc->is_range = l && l->hdr.hop_limits;\n \t\tfc->tag_set = &mlx5dr_definer_ipv6_hop_limits_set;\n \t\tDR_CALC_SET(fc, eth_l3, time_to_live_hop_limit, inner);\n \t}\n@@ -728,6 +748,7 @@ mlx5dr_definer_conv_item_udp(struct mlx5dr_definer_conv_data *cd,\n \t\t\t int item_idx)\n {\n \tconst struct rte_flow_item_udp *m = item->mask;\n+\tconst struct rte_flow_item_udp *l = item->last;\n \tstruct mlx5dr_definer_fc *fc;\n \tbool inner = cd->tunnel;\n \n@@ -751,6 +772,7 @@ mlx5dr_definer_conv_item_udp(struct mlx5dr_definer_conv_data *cd,\n \tif (m->hdr.src_port) {\n \t\tfc = &cd->fc[DR_CALC_FNAME(L4_SPORT, inner)];\n \t\tfc->item_idx = item_idx;\n+\t\tfc->is_range = l && l->hdr.src_port;\n \t\tfc->tag_set = &mlx5dr_definer_udp_src_port_set;\n \t\tDR_CALC_SET(fc, eth_l4, source_port, inner);\n \t}\n@@ -758,6 +780,7 @@ mlx5dr_definer_conv_item_udp(struct mlx5dr_definer_conv_data *cd,\n \tif (m->hdr.dst_port) {\n \t\tfc = &cd->fc[DR_CALC_FNAME(L4_DPORT, inner)];\n \t\tfc->item_idx = item_idx;\n+\t\tfc->is_range = l && l->hdr.dst_port;\n \t\tfc->tag_set = &mlx5dr_definer_udp_dst_port_set;\n \t\tDR_CALC_SET(fc, eth_l4, destination_port, inner);\n \t}\n@@ -771,6 +794,7 @@ mlx5dr_definer_conv_item_tcp(struct mlx5dr_definer_conv_data *cd,\n \t\t\t int item_idx)\n {\n \tconst struct rte_flow_item_tcp *m = item->mask;\n+\tconst struct rte_flow_item_tcp *l = item->last;\n \tstruct mlx5dr_definer_fc *fc;\n \tbool inner = cd->tunnel;\n \n@@ -786,9 +810,16 @@ mlx5dr_definer_conv_item_tcp(struct mlx5dr_definer_conv_data *cd,\n \tif (!m)\n \t\treturn 0;\n \n+\tif (m->hdr.sent_seq || m->hdr.recv_ack || m->hdr.data_off ||\n+\t m->hdr.rx_win || m->hdr.cksum || m->hdr.tcp_urp) {\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n \tif (m->hdr.tcp_flags) {\n \t\tfc = &cd->fc[DR_CALC_FNAME(TCP_FLAGS, inner)];\n \t\tfc->item_idx = item_idx;\n+\t\tfc->is_range = l && l->hdr.tcp_flags;\n \t\tfc->tag_set = &mlx5dr_definer_tcp_flags_set;\n \t\tDR_CALC_SET(fc, eth_l4, tcp_flags, inner);\n \t}\n@@ -796,6 +827,7 @@ mlx5dr_definer_conv_item_tcp(struct mlx5dr_definer_conv_data *cd,\n \tif (m->hdr.src_port) {\n \t\tfc = &cd->fc[DR_CALC_FNAME(L4_SPORT, inner)];\n \t\tfc->item_idx = item_idx;\n+\t\tfc->is_range = l && l->hdr.src_port;\n \t\tfc->tag_set = &mlx5dr_definer_tcp_src_port_set;\n \t\tDR_CALC_SET(fc, eth_l4, source_port, inner);\n \t}\n@@ -803,6 +835,7 @@ mlx5dr_definer_conv_item_tcp(struct mlx5dr_definer_conv_data *cd,\n \tif (m->hdr.dst_port) {\n \t\tfc = &cd->fc[DR_CALC_FNAME(L4_DPORT, inner)];\n \t\tfc->item_idx = item_idx;\n+\t\tfc->is_range = l && l->hdr.dst_port;\n \t\tfc->tag_set = &mlx5dr_definer_tcp_dst_port_set;\n \t\tDR_CALC_SET(fc, eth_l4, destination_port, inner);\n \t}\n@@ -1108,6 +1141,7 @@ mlx5dr_definer_conv_item_tag(struct mlx5dr_definer_conv_data *cd,\n {\n \tconst struct rte_flow_item_tag *m = item->mask;\n \tconst struct rte_flow_item_tag *v = item->spec;\n+\tconst struct rte_flow_item_tag *l = item->last;\n \tstruct mlx5dr_definer_fc *fc;\n \tint reg;\n \n@@ -1130,7 +1164,9 @@ mlx5dr_definer_conv_item_tag(struct mlx5dr_definer_conv_data *cd,\n \t\treturn rte_errno;\n \n \tfc->item_idx = item_idx;\n+\tfc->is_range = l && l->index;\n \tfc->tag_set = &mlx5dr_definer_tag_set;\n+\n \treturn 0;\n }\n \n@@ -1140,6 +1176,7 @@ mlx5dr_definer_conv_item_metadata(struct mlx5dr_definer_conv_data *cd,\n \t\t\t\t int item_idx)\n {\n \tconst struct rte_flow_item_meta *m = item->mask;\n+\tconst struct rte_flow_item_meta *l = item->last;\n \tstruct mlx5dr_definer_fc *fc;\n \tint reg;\n \n@@ -1158,7 +1195,9 @@ mlx5dr_definer_conv_item_metadata(struct mlx5dr_definer_conv_data *cd,\n \t\treturn rte_errno;\n \n \tfc->item_idx = item_idx;\n+\tfc->is_range = l && l->data;\n \tfc->tag_set = &mlx5dr_definer_metadata_set;\n+\n \treturn 0;\n }\n \n@@ -1465,6 +1504,28 @@ mlx5dr_definer_conv_item_meter_color(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_check_item_range_supp(struct rte_flow_item *item)\n+{\n+\tif (!item->last)\n+\t\treturn 0;\n+\n+\tswitch ((int)item->type) {\n+\tcase RTE_FLOW_ITEM_TYPE_IPV4:\n+\tcase RTE_FLOW_ITEM_TYPE_IPV6:\n+\tcase RTE_FLOW_ITEM_TYPE_UDP:\n+\tcase RTE_FLOW_ITEM_TYPE_TCP:\n+\tcase RTE_FLOW_ITEM_TYPE_TAG:\n+\tcase RTE_FLOW_ITEM_TYPE_META:\n+\tcase MLX5_RTE_FLOW_ITEM_TYPE_TAG:\n+\t\treturn 0;\n+\tdefault:\n+\t\tDR_LOG(ERR, \"Range not supported over item type %d\", item->type);\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+}\n+\n static int\n mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\t\tstruct mlx5dr_match_template *mt,\n@@ -1487,6 +1548,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \tfor (i = 0; items->type != RTE_FLOW_ITEM_TYPE_END; i++, items++) {\n \t\tcd.tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);\n \n+\t\tret = mlx5dr_definer_check_item_range_supp(items);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n \t\tswitch ((int)items->type) {\n \t\tcase RTE_FLOW_ITEM_TYPE_ETH:\n \t\t\tret = mlx5dr_definer_conv_item_eth(&cd, items, i);\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex d52c6b0627..bab4baae4a 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -38,8 +38,8 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_IP_VERSION_I,\n \tMLX5DR_DEFINER_FNAME_IP_FRAG_O,\n \tMLX5DR_DEFINER_FNAME_IP_FRAG_I,\n-\tMLX5DR_DEFINER_FNAME_IPV6_PAYLOAD_LEN_O,\n-\tMLX5DR_DEFINER_FNAME_IPV6_PAYLOAD_LEN_I,\n+\tMLX5DR_DEFINER_FNAME_IP_LEN_O,\n+\tMLX5DR_DEFINER_FNAME_IP_LEN_I,\n \tMLX5DR_DEFINER_FNAME_IP_TOS_O,\n \tMLX5DR_DEFINER_FNAME_IP_TOS_I,\n \tMLX5DR_DEFINER_FNAME_IPV6_FLOW_LABEL_O,\n@@ -116,6 +116,7 @@ enum mlx5dr_definer_type {\n \n struct mlx5dr_definer_fc {\n \tuint8_t item_idx;\n+\tuint8_t is_range;\n \tuint32_t byte_off;\n \tint bit_off;\n \tuint32_t bit_mask;\n", "prefixes": [ "v2", "09/16" ] }