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GET /api/patches/123057/?format=api
{ "id": 123057, "url": "http://patchwork.dpdk.org/api/patches/123057/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230205134154.408984-4-yongquanx@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230205134154.408984-4-yongquanx@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230205134154.408984-4-yongquanx@nvidia.com", "date": "2023-02-05T13:41:54", "name": "[v3,3/3] net/mlx5/hws: add ICMPv6 ID and sequence match support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "ca5617fb98e9b8f8705a998854482127fe49a7ae", "submitter": { "id": 2910, "url": "http://patchwork.dpdk.org/api/people/2910/?format=api", "name": "Leo Xu", "email": "yongquanx@nvidia.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230205134154.408984-4-yongquanx@nvidia.com/mbox/", "series": [ { "id": 26794, "url": "http://patchwork.dpdk.org/api/series/26794/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=26794", "date": "2023-02-05T13:41:51", "name": "support match icmpv6 ID and sequence", "version": 3, "mbox": "http://patchwork.dpdk.org/series/26794/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/123057/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/123057/checks/", "tags": {}, "related": [], "headers": { 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b=ET3Pmte/kvcrjxTNWMclztZNTN/oooJO/Wi8AKGutFdxwUgWVI/gSWDPGdewDq+6z0KCqGO96+NrfNEPdqEkPXah7PYM3+6eSYFeZvmm7AEm+fhZ4vPosWcL+LLcICetfmKc6J2cFX/fI7moLtoPsreZCPJFZEgMlGZ83wMGJkkL42zHWVn57RH3NNUDA6SAu7GH3hVQs3nbDlCVVqs9n0d6tgltgvaAayP0Yr3aHWNUYqXBW9OLexV3AFfkYLGDlhK9PJzPyZxHYL2fPoLIKMxL4xRW+hN2LhjhHoneaH8Mn+m9NPJnRd3+OjEKLzS2XYb+SjFRuPAsFdVAjSHhiw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Leo Xu <yongquanx@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "Subject": "[PATCH v3 3/3] net/mlx5/hws: add ICMPv6 ID and sequence match support", "Date": "Sun, 5 Feb 2023 15:41:54 +0200", "Message-ID": "<20230205134154.408984-4-yongquanx@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230205134154.408984-1-yongquanx@nvidia.com>", "References": "<20221220074403.1015411-1-yongquanx@nvidia.com>\n <20230205134154.408984-1-yongquanx@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1PEPF00001A60:EE_|SN7PR12MB7953:EE_", "X-MS-Office365-Filtering-Correlation-Id": "32e4ab7c-4002-490b-4820-08db077ee369", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n T6ixwEcuFL8D95ihy12PinSHaPGjgzxuwjTrBKcrwCAwuB1osrEjEgFBAF7lsCcf2wZcRyfIMUf9GJhcLScPL3ON4ZyAdqzQHEsR7tJC4ZSYPUwM4iEeZWj/L5maX6i9MGh9ZamWuhJSCeqO64nYWFtparrI1qPTqFIlVRVrriccjQJS8EwBAKYJoBx1cuDrhcwSVEzRFY2rQ9UsMnWO915cELeaGgTSQzxb0slJRm3BXz24SJsqWjGCJcx1LSwdhe1EdLdoYKcSeoqDD8BNSWmOfv9v9OP7mLzCAyKuz5QqJTim+UoaFvSBtjgONLbcbwd1qS//2rCFIG6SPXuzCwB1rapi1CwEy9PW4cy7dtlVymrBKZcC0yHv5FDEQkVwKuaUvRvj8DMeLmhHWvjHLd4tTDwCBMmGYonxrF+rILRTxozPAIc3fmI5GfEkkWzHFwBzNpRhFlC29Zzwi5Rp6VgDD/tfS3p74LVQKQi5CmBToAZMXp8kBZorPyc9Kz1vSRs1SrJ1C1Nna1GYrydcrL2/GaSUlaWl643+Cnhvs4EyOd3Wkltrrbeb5IYZRFrdkK6je8PsnBwo7BDiJ8w1gi3BWg0d2YAU0gUD7MebNjD5SNmM29JAszKd6pA8cl95FmmX1vsB3/XccJLQaWiXGARqKeM6Ct3ynuJ7ycNA/g3auE0p0jVHcn8KtlFw3mHOpxwh1Cl1iIjSxT2zJtFFtw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(136003)(376002)(396003)(346002)(39860400002)(451199018)(40470700004)(36840700001)(46966006)(82310400005)(40460700003)(1076003)(55016003)(40480700001)(6666004)(107886003)(478600001)(2616005)(26005)(186003)(16526019)(6286002)(4326008)(8676002)(70586007)(70206006)(6916009)(7696005)(316002)(7636003)(54906003)(82740400003)(36756003)(86362001)(356005)(47076005)(426003)(83380400001)(336012)(36860700001)(5660300002)(41300700001)(8936002)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 Feb 2023 13:42:56.4096 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 32e4ab7c-4002-490b-4820-08db077ee369", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1PEPF00001A60.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB7953", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch adds ICMPv6 ID and sequence match support for HWS.\nSince type and code of ICMPv6 echo is already specified by ITEM type:\n RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST\n RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY\nmlx5 pmd will set appropriate type and code automatically:\n Echo request: type(128), code(0)\n Echo reply: type(129), code(0)\ntype and code provided by application will be ignored\n\nSigned-off-by: Leo Xu <yongquanx@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 88 +++++++++++++++++++++++++++\n 1 file changed, 88 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 6b98eb8c96..d56e85631d 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -368,6 +368,47 @@ mlx5dr_definer_icmp6_dw1_set(struct mlx5dr_definer_fc *fc,\n \tDR_SET(tag, icmp_dw1, fc->byte_off, fc->bit_off, fc->bit_mask);\n }\n \n+static void\n+mlx5dr_definer_icmp6_echo_dw1_mask_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t\t __rte_unused const void *item_spec,\n+\t\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_icmp6 spec = {0xFF, 0xFF, 0x0};\n+\tmlx5dr_definer_icmp6_dw1_set(fc, &spec, tag);\n+}\n+\n+static void\n+mlx5dr_definer_icmp6_echo_request_dw1_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t\t\t __rte_unused const void *item_spec,\n+\t\t\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_icmp6 spec = {RTE_ICMP6_ECHO_REQUEST, 0, 0};\n+\tmlx5dr_definer_icmp6_dw1_set(fc, &spec, tag);\n+}\n+\n+static void\n+mlx5dr_definer_icmp6_echo_reply_dw1_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t\t\t__rte_unused const void *item_spec,\n+\t\t\t\t\tuint8_t *tag)\n+{\n+\tconst struct rte_flow_item_icmp6 spec = {RTE_ICMP6_ECHO_REPLY, 0, 0};\n+\tmlx5dr_definer_icmp6_dw1_set(fc, &spec, tag);\n+}\n+\n+static void\n+mlx5dr_definer_icmp6_echo_dw2_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t\t const void *item_spec,\n+\t\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_icmp6_echo *v = item_spec;\n+\trte_be32_t dw2;\n+\n+\tdw2 = (rte_be_to_cpu_16(v->hdr.identifier) << __mlx5_dw_bit_off(header_icmp, ident)) |\n+\t (rte_be_to_cpu_16(v->hdr.sequence) << __mlx5_dw_bit_off(header_icmp, seq_nb));\n+\n+\tDR_SET(tag, dw2, fc->byte_off, fc->bit_off, fc->bit_mask);\n+}\n+\n static void\n mlx5dr_definer_ipv6_flow_label_set(struct mlx5dr_definer_fc *fc,\n \t\t\t\t const void *item_spec,\n@@ -1441,6 +1482,48 @@ mlx5dr_definer_conv_item_icmp6(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_conv_item_icmp6_echo(struct mlx5dr_definer_conv_data *cd,\n+\t\t\t\t struct rte_flow_item *item,\n+\t\t\t\t int item_idx)\n+{\n+\tconst struct rte_flow_item_icmp6_echo *m = item->mask;\n+\tstruct mlx5dr_definer_fc *fc;\n+\tbool inner = cd->tunnel;\n+\n+\tif (!cd->relaxed) {\n+\t\t/* Overwrite match on L4 type ICMP6 */\n+\t\tfc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_icmp_protocol_set;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\tDR_CALC_SET(fc, eth_l2, l4_type, inner);\n+\n+\t\t/* Set fixed type and code for icmp6 echo request/reply */\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_ICMP_DW1];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_icmp6_echo_dw1_mask_set;\n+\t\tif (item->type == RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST)\n+\t\t\tfc->tag_set = &mlx5dr_definer_icmp6_echo_request_dw1_set;\n+\t\telse /* RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY */\n+\t\t\tfc->tag_set = &mlx5dr_definer_icmp6_echo_reply_dw1_set;\n+\t\tDR_CALC_SET_HDR(fc, tcp_icmp, icmp_dw1);\n+\t}\n+\n+\tif (!m)\n+\t\treturn 0;\n+\n+\t/* Set identifier & sequence into icmp_dw2 */\n+\tif (m->hdr.identifier || m->hdr.sequence) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_ICMP_DW2];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_icmp6_echo_dw2_set;\n+\t\tDR_CALC_SET_HDR(fc, tcp_icmp, icmp_dw2);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n mlx5dr_definer_conv_item_meter_color(struct mlx5dr_definer_conv_data *cd,\n \t\t\t struct rte_flow_item *item,\n@@ -1577,6 +1660,11 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\tret = mlx5dr_definer_conv_item_icmp6(&cd, items, i);\n \t\t\titem_flags |= MLX5_FLOW_LAYER_ICMP6;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST:\n+\t\tcase RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY:\n+\t\t\tret = mlx5dr_definer_conv_item_icmp6_echo(&cd, items, i);\n+\t\t\titem_flags |= MLX5_FLOW_LAYER_ICMP6;\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_METER_COLOR:\n \t\t\tret = mlx5dr_definer_conv_item_meter_color(&cd, items, i);\n \t\t\titem_flags |= MLX5_FLOW_ITEM_METER_COLOR;\n", "prefixes": [ "v3", "3/3" ] }